The eMMC reads and writes are performed in 512-byte sectors units. These addresses are logical since the actual physical location in NAND is different and dynamic. Therefore, the 512-byte sector address used by the eMMC can be referred to as a Logical Block Address or LBA. If this sector data is modified, it would not be practical to erase the entire NAND block where data is stored and then program all pages back with updated data. This large read-modify-write operation would create a performance penalty as well as unnecessary and significant wear on NAND area where the data did not change and did not need to be re-programmed. To address this issue, managed NAND storage devices do not use a fixed mapping of logical to physical block address. Instead, a logical to physical address mapping scheme is used to enable smaller writes to NAND while balancing block wear. This mapping is done with an address translation table that translates the logical address to a physical address location in flash. When the data of one or more logical sector addresses is modified, the NAND page where these sectors are mapped is read then updated and programmed back to a new page that is in an erased state. The address translation table is then updated to map these logical sector addresses to the new, updated NAND page address. This improves write performance since only the NAND pages that require updating are programmed to a new location. Programing is limited to NAND page size units. This scheme also allows for the write load to be balanced across the entire device by allocating a physical NAND blocks with the lowest erase count for new page writes. This scheme is known as dynamic wear-leveling.