NAND Flash has a limit to the total number of program-erase cycles. Once this limit is reached, the device is in an end-of-life state. At this point, the media has degraded to a level where it is no longer reliable. Endurance can vary, based on the configuration of the NAND cells. For a given NAND flash generation, Single Level Cell configuration provides the greatest margin against errors and as a result, has the highest endurance. Additional bits can be added by dividing the cell into more energy levels. Such is the case for MLC, TLC, and QLC configurations. While this increases the device storage density, it reduces the overall endurance. In general, the more bits that are stored in a cell, the lower the endurance. Reliability can be improved with stronger error control and more robust management algorithms. To achieve maximum device life, wear leveling algorithms are implemented to ensure that the NAND wear is spread evenly across the entire media.