UCC27282 Datasheet

I TEXAS INSTRUMENTS TIT
HS
LO
HB
HO
75V
VSS
LI
HI
EN
7V
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCC27282
SNVSAQ5A –NOVEMBER 2018–REVISED JANUARY 2020
UCC27282 120-V Half-Bridge Driver
with Cross Conduction Protection and Low Switching Losses
1
1 Features
1• Drives two N-channel MOSFETs in high-side low-
side configuration
• 5-V typical under voltage lockout
• Input interlock
• Enable/disable functionality in DRC package
• 16-ns typical propagation delay
• 12-ns rise, 10-ns fall time with 1.8-nF load
• 1-ns typical delay matching
• Absolute Maximum Negative Voltage Handling on
Inputs (–5 V)
• Absolute Maximum Negative Voltage Handling on
HS (–14 V)
• 3.5-A sink, 2.5-A Source output currents
• Absolute maximum boot voltage 120 V
• Low current (7-µA) consumption when disabled
• Integrated bootstrap diode
• Specified from –40°C to 140°C junction
temperature
2 Applications
• Telecom and merchant power supplies
• Motor drives and power tools
• Auxiliary inverters
• Half-bridge and full-bridge converters
• Active-clamp forward converters
• High voltage synchronous-buck converters
• Class-D audio amplifiers
Simplified Application Diagram
3 Description
The UCC27282 is a robust N-channel MOSFET
driver with a maximum switch node (HS) voltage
rating of 100 V. It allows for two N-channel MOSFETs
to be controlled in half-bridge or synchronous buck
configuration based topologies. Its 3.5-A peak sink
current and 2.5-A peak source current along with low
pull-up and pull-down resistance allows the
UCC27282 to drive large power MOSFETs with
minimum switching losses during the transition of the
MOSFET Miller plateau. Since the inputs are
independent of the supply voltage, UCC27282 can be
used in conjunction with both analog and digital
controllers.
The input pins as well as the HS pin are able to
tolerate significant negative voltage, which improves
system robustness. Input interlock further improves
robustness and system reliability in high noise
applications. The enable and disable functionality
provides additional system flexibility by reducing
power consumption by the driver and responds to
fault events within the system. 5-V UVLO allows
systems to operate at lower bias voltages, which is
necessary in many high frequency applications and
improves system efficiency in certain operating
modes. Small propagation delay and delay matching
specifications minimize the dead-time requirement
which further improves efficiency.
Under voltage lockout (UVLO) is provided for both the
high-side and low-side driver stages forcing the
outputs low if the VDD voltage is below the specified
threshold. An integrated bootstrap diode eliminates
the need for an external discrete diode in many
applications, which saves board space and reduces
system cost. UCC27282 is offered in a small package
enabling high density designs.
Device Information(1)
PART NUMBER PACKAGE (SIZE)
UCC27282 SON10 (3 mm x 3 mm)
SOIC8 (6 mm x 5mm))
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Switching Characteristics.......................................... 6
6.7 Timing Diagrams....................................................... 7
6.8 Typical Characteristics.............................................. 7
7 Detailed Description............................................ 13
7.1 Overview ................................................................. 13
7.2 Functional Block Diagram....................................... 13
7.3 Feature Description................................................. 14
7.4 Device Functional Modes........................................ 16
8 Application and Implementation ........................ 17
8.1 Application Information............................................ 17
8.2 Typical Application ................................................. 18
9 Power Supply Recommendations...................... 26
10 Layout................................................................... 27
10.1 Layout Guidelines ................................................. 27
10.2 Layout Example .................................................... 27
11 Device and Documentation Support ................. 28
11.1 Receiving Notification of Documentation Updates 28
11.2 Community Resources.......................................... 28
11.3 Trademarks........................................................... 28
11.4 Electrostatic Discharge Caution............................ 28
11.5 Glossary................................................................ 28
12 Mechanical, Packaging, and Orderable
Information ........................................................... 28
4 Revision History
Changes from Original (November 2018) to Revision A Page
• Added SOIC 8-Pin D package to the Device Information table. ........................................................................................... 1
• Added SOIC 8-Pin D package image and updated the Pin Functions table.......................................................................... 3
*9 TEXAS INSTRUMENTS
1VDD 8 LO
2HB 7 VSS
3HO 6 LI
4HS 5 HI
Not to scale
1VDD 10 LO
2NC 9 VSS
3HB 8 LI
4HO 7 HI
5HS 6 EN
Not to scale
Thermal
Pad
3
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5 Pin Configuration and Functions
DRC Package
10-Pin VSON With Exposed Thermal Pad
Top View
D Package
8-Pin SOIC
Top View
(1) P = Power, G = Ground, I = Input, O = Output, I/O = Input/Output
Pin Functions
PIN I/O(1) DESCRIPTION
Name D DRC
EN n/a 6 I Enable input. When this pin is pulled high, it will enable the driver. If left floating or pulled low, it will
disable the driver. 1 nF filter capacitor is recommended for high-noise systems.
HB 2 3 P
High-side bootstrap supply. The bootstrap diode is on-chip but the external bootstrap capacitor is
required. Connect positive side of the bootstrap capacitor to this pin. Typical recommended value of
HB bypass capacitor is 0.1 μF, This value primarily depends on the gate charge of the high-side
MOSFET. When using external boot diode, connect cathode of the diode to this pin.
HI 5 7 I High-side input.
HO 3 4 O High-side output. Connect to the gate of the high-side power MOSFET or one end of external gate
resistor, when used.
HS 4 5 P High-side source connection. Connect to source of high-side power MOSFET. Connect negative
side of bootstrap capacitor to this pin.
LI 6 8 I Low-side input
LO 8 10 O Low-side output. Connect to the gate of the low-side power MOSFET or one end of external gate
resistor, when used.
NC n/a 2 — Not connected internally.
VDD 1 1 P Positive supply to the low-side gate driver. Decouple this pin to VSS. Typical decoupling capacitor
value is 1 μF. When using an external boot diode, connect the anode to this pin.
VSS 7 9 G Negative supply terminal for the device which is generally the system ground.
Thermal
pad n/a - — Connect to a large thermal mass trace (generally IC ground plane) to improve thermal performance.
This can only be electrically connected to VSS.
l TEXAS INSTRUMENTS
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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to Vss. Currents are positive into, negative out of the specified terminal.
(3) Values are verified by characterization only.
6 Specifications
6.1 Absolute Maximum Ratings
All voltages are with respect to Vss(1)(2)
MIN MAX UNIT
VDD Supply voltage –0.3 20 V
VEN, VHI, VLI Input voltages on EN, HI and LI –5 20 V
VLO Output voltage on LO DC –0.3 VDD + 0.3 V
Pulses < 100 ns(3) –2 VDD + 0.3
VHO Output voltage on HO DC VHS – 0.3 VHB + 0.3 V
Pulses < 100 ns(3) VHS – 2 VHB + 0.3
VHS Voltage on HS DC –10 100 V
Pulses < 100 ns(3) –14 100
VHB Voltage on HB –0.3 120 V
VHB-HS Voltage on HB with respect to HS –0.3 20 V
TJOperating junction temperature –40 150 °C
Lead temperature (soldering, 10 sec.) 300 °C
Tstg Storage temperature –65 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) Pins HS, HB and HO are rated at 500V HBM
(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings
VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)(2) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(3) ±1500
(1) VHB-HS < 16V (Voltage on HB with respect to HS must be less than 16V)
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDD Supply voltage 5.5 12 16 V
VEN, VHI, VLI Input Voltage 0 VDD+0.3
VLO Low side output voltage 0 VDD+0.3
VHO High side output voltage VHS VHB+0.3
VHS Voltage on HS(1) –8 100 V
Voltage on HS (Pulses < 100 ns)(1) –12 100
VHB Voltage on HB VHS + 5.5 VHS+16 V
Vsr Voltage slew rate on HS 50 V/ns
TJOperating junction temperature –40 140 °C
l TEXAS INSTRUMENTS
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(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.4 Thermal Information
THERMAL METRIC(1)
UCC27282
UNITD DRC
8 PINS 10 PINS
RθJA Junction-to-ambient thermal resistance 118.3 47.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 53.6 50.3 °C/W
RθJB Junction-to-board thermal resistance 63.1 21.3 °C/W
ψJT Junction-to-top characterization parameter 10.7 1.0 °C/W
ψJB Junction-to-board characterization parameter 62.1 21.2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a 4.4 °C/W
(1) Parameter not tested in production
6.5 Electrical Characteristics
VDD = VHB = VEN =12 V, VHS = VSS = 0 V, No load on LO or HO, TJ= –40°C to +140°C, (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENTS
IDD VDD quiescent current VLI = VHI = 0 0.3 0.4 mA
IDDO VDD operating current f = 500 kHz, CLOAD = 0 2.2 4.5 mA
IHB HB quiescent current VLI = VHI = 0 V 0.2 0.4 mA
IHBO HB operating current f = 500 kHz, CLOAD = 0 2.5 4 mA
IHBS HB to VSS quiescent current VHS = VHB = 110 V 2.0 50 μA
IHBSO HB to VSS operating current(1) f = 500 kHz, CLOAD = 0 0.1 mA
IDD_DIS IDD when driver is disabled VEN = 0 7.0 μA
INPUT
VHIT Input rising threshold 1.9 2.1 2.4 V
VLIT Input falling threshold 0.9 1.1 1.3 V
VIHYS Input voltage Hysteresis 1.0 V
RIN Input pulldown resistance 100 250 350 kΩ
ENABLE
VEN Voltage threshold on EN pin to enable the driver 1.54 2.0 V
VDIS Voltage threshold on EN pin to disable the driver 0.7 1.21 V
VENHYS Enable pin Hysteresis 0.3 V
REN EN pin internal pull-down resistor 250 kΩ
TEN Time to enable the driver once the EN pin is
pulled high VEN = 2V 18 μs
TDIS Time to disable the driver once the EN pin is
pulled low VEN = 0V 1.5 μs
UNDERVOLTAGE LOCKOUT PROTECTION (UVLO)
VDDR VDD rising threshold 4.7 5.0 5.4 V
VDDF VDD falling threshold 4.2 4.5 4.9 V
VDDHYS VDD threshold hysteresis 0.5 V
VHBR HB rising threshold with respect to HS pin 3.3 3.7 4.4 V
VHBF HB falling threshold with respect to HS pin 3.0 3.3 4.1 V
VHBHYS HB threshold hysteresis 0.3 V
BOOTSTRAP DIODE
VFLow-current forward voltage IVDD-HB = 100 μA 0.55 0.85 V
VFI High-current forward voltage IVDD-HB = 80 mA 0.88 1.0 V
RDDynamic resistance, ΔVF/ΔI IVDD-HB = 100 mA and 80 mA 1.5 2.5 Ω
l TEXAS INSTRUMENTS
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Electrical Characteristics (continued)
VDD = VHB = VEN =12 V, VHS = VSS = 0 V, No load on LO or HO, TJ= –40°C to +140°C, (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LO GATE DRIVER
VLOL Low level output voltage ILO = 100 mA 0.085 0.4 V
VLOH High level output voltage ILO = -100 mA, VLOH = VDD – VLO 0.13 0.42 V
Peak pullup current (1) VLO = 0 V 2.5 A
Peak pulldown current (1) VLO = 12 V 3.5 A
HO GATE DRIVER
VHOL Low level output voltage IHO = 100 mA 0.1 0.4 V
VHOH High level output voltage IHO = –100 mA, VHOH = VHB- VHO 0.13 0.42 V
Peak pullup current (1) VHO = 0 V 2.5 A
Peak pulldown current (1) VHO = 12 V 3.5 A
(1) Parameter not tested in production
6.6 Switching Characteristics
VDD = VHB = 12 V, VHS = VSS = 0 V, No load on LO or HO, TJ= –40°C to +140°C, (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PROPAGATION DELAYS
tDLFF VLI falling to VLO falling See Timing Diagrams 16 30 ns
tDHFF VHI falling to VHO falling See Timing Diagrams 16 30 ns
tDLRR VLI rising to VLO rising See Timing Diagrams 16 30 ns
tDHRR VHI rising to VHO rising See Timing Diagrams 16 30 ns
DELAY MATCHING
tMON From LO being ON to HO being OFF See Timing Diagrams 1 7 ns
tMOFF From LO being OFF to HO being ON See Timing Diagrams 1 7 ns
OUTPUT RISE AND FALL TIME
tRLO, HO rise time CLOAD = 1800 pF, 10% to 90% 12 ns
tFLO, HO fall time CLOAD = 1800 pF, 90% to 10% 10 ns
tRLO, HO (3 V to 9 V) rise time CLOAD = 0.1 μF, 30% to 70% 0.33 0.6 μs
tFLO, HO (3 V to 9 V) fall time CLOAD = 0.1 μF, 70% to 30% 0.23 0.6 μs
MISCELLANEOUS
TPW,min Minimum input pulse width that changes the output 20 ns
Bootstrap diode turnoff time(1) IF= 20 mA, IREV = 0.5 A 50 ns
*9 TEXAS INSTRUMENTS Tm 022
Temperature (°C)
VDD Quiescent Current (mA)
-40 -20 0 20 40 60 80 100 120 140
0.1
0.12
0.14
0.16
0.18
0.2
0.22
0.24
0.26
0.28
0.3
IDDQ
5.5V
12V
16V
Temperature (°C)
HB Quiescent Current (mA)
-40 -20 0 20 40 60 80 100 120 140
0.02
0.06
0.1
0.14
0.18
0.22
IHBQ
5.5V
12V
16V
7
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6.7 Timing Diagrams
6.8 Typical Characteristics
Unless otherwise specified VVDD=VHB = 12 V, VHS=VVSS = 0 V, No load on outputs
VHI = VLI = 0 V
Figure 1. VDD Quiescent Current
VHI = VLI = 0 V
Figure 2. HB Quiescent Current
l TEXAS INSTRUMENTS 222 HA5
Temperature (°C)
Input Rising Threshold (V)
-40 -20 0 20 40 60 80 100 120 140
2.165
2.17
2.175
2.18
2.185
2.19
2.195
2.2
2.205
2.21
2.215
2.22
IN_R
5.5V
12V
16V
Temperature (°C)
Input Falling Threshold (V)
-40 -20 0 20 40 60 80 100 120 140
1.105
1.11
1.115
1.12
1.125
1.13
1.135
1.14
1.145
IN_F
5.5V
12V
16V
Temperature (°C)
IDD_DIS (PA)
-40 -20 0 20 40 60 80 100 120 140
0
2
4
6
8
10
12
14
IDD_
5.5V
12V
16V
Temperature (°C)
IHBS (PA)
-40 -20 0 20 40 60 80 100 120 140
0
2
4
6
8
10
12
14
16
18
20
IHBS
Frequency (kHz)
IDDO (mA)
1 2 3 4 5 67 10 20 30 50 70100 200 500 1000
0
1
2
3
4
5
6
IDDO
-40°C
25°°C
140°°C
Frequency (kHz)
IHBO (mA)
1 2 3 4 5 67 10 20 30 50 70100 200 500 1000
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
IHBO
-40°C
25°C
140°C
8
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Typical Characteristics (continued)
Unless otherwise specified VVDD=VHB = 12 V, VHS=VVSS = 0 V, No load on outputs
CL= 0 F VDD =VHB= 12V
Figure 3. VDD Operating Current
CL= 0 F VDD =VHB= 12V
Figure 4. HB Operating Current
CL= 0 F VEN = 0 V
Figure 5. VDD Current When Disabled
VHB=VHS=100V
Figure 6. HB to VSS Quiescent Current
Figure 7. Input Rising Threshold Figure 8. Input Falling Threshold
l TEXAS INSTRUMENTS 280 1 75 u:
Temperature (°C)
Disable Delay (Ps)
-40 -20 0 20 40 60 80 100 120 140
1.6
1.65
1.7
1.75
1.8
1.85
1.9
1.95
2
2.05
2.1
2.15
2.2
T_Di
5.5V
12V
16V
Temperature (°C)
VDD UVLO (V)
-40 -20 0 20 40 60 80 100 120 140
4.2
4.4
4.6
4.8
5
5.2
VDDU
Rise
Fall
Temperature (°C)
Disable Threshold (V)
-40 -20 0 20 40 60 80 100 120 140
0.9
0.95
1
1.05
1.1
1.15
1.2
1.25
1.3
1.35
Dis_
5.5V
12V
16V
Temperature (°C)
Enable Delay (Ps)
-40 -20 0 20 40 60 80 100 120 140
15
20
25
30
35
40
45
50
55
60
65
70
T_EN
5.5V
12V
16V
Temperature (°C)
Input Resistance (k:)
-40 -20 0 20 40 60 80 100 120 140
230
240
250
260
270
280
R_IN
Temperature (°C)
Enable Threshold (V)
-40 -20 0 20 40 60 80 100 120 140
1.2
1.25
1.3
1.35
1.4
1.45
1.5
1.55
1.6
1.65
1.7
1.75
EN_T
5.5V
12V
16V
9
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Typical Characteristics (continued)
Unless otherwise specified VVDD=VHB = 12 V, VHS=VVSS = 0 V, No load on outputs
Figure 9. Input Pull-down Resistor Figure 10. Enable Threshold
Figure 11. Disable Threshold Figure 12. Enable Delay
Figure 13. Disable Delay Figure 14. VDD UVLO Threshold
l TEXAS INSTRUMENTS out. 021 015:
Temperature (°C)
Output Voltage (V)
-40 -20 0 20 40 60 80 100 120 140
0.1
0.11
0.12
0.13
0.14
0.15
0.16
0.17
0.18
0.19
0.2
0.21
V_LO
5.5V
12V
16V
Temperature (°C)
Output Voltage (V)
-40 -20 0 20 40 60 80 100 120 140
0.085
0.09
0.095
0.1
0.105
0.11
0.115
0.12
0.125
0.13
0.135
0.14
0.145
0.15
0.155
UCC2V_HO
5.5V
12V
16V
Temperature (°C)
Diode Dynamic Resistance (:)
-40 -20 0 20 40 60 80 100 120 140
1.2
1.25
1.3
1.35
1.4
1.45
1.5
1.55
1.6
1.65
1.7
1.75
1.8
R_Dy
Temperature (°C)
Output Voltage (V)
-40 -20 0 20 40 60 80 100 120 140
0.065
0.07
0.075
0.08
0.085
0.09
0.095
0.1
0.105
0.11
0.115
0.12
0.125
0.13
0.135
V_LO
5.5V
12V
16V
Temperature (°C)
HB UVLO (V)
-40 -20 0 20 40 60 80 100 120 140
3
3.2
3.4
3.6
3.8
4
HBUV
Rise
Fall
Temperature (°C)
Diode Forward Voltage (V)
-40 -20 0 20 40 60 80 100 120 140
0.25
0.3
0.35
0.4
0.45
0.5
0.55
0.6
0.65
0.7
0.75
0.8
0.85
0.9
0.95
1
Vf
100uA
80mA
10
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Typical Characteristics (continued)
Unless otherwise specified VVDD=VHB = 12 V, VHS=VVSS = 0 V, No load on outputs
Figure 15. HB UVLO Threshold Figure 16. Boot Diode Forward Voltage Drop
Figure 17. Boot Diode Dynamic Resistance
IO=100mA
Figure 18. LO Low Output Voltage (VLOL)
IO=-100mA
Figure 19. LO High Output Voltage (VLOH)
IO=100mA
Figure 20. HO Low Output Voltage (VHOL)
l TEXAS INSTRUMENTS
Temperature (°C)
HO Fall Time (ns)
-40 -20 0 20 40 60 80 100 120 140
7.2
7.4
7.6
7.8
8
8.2
8.4
8.6
8.8
9
HO_F
5.5V
12V
16V
Temperature (°C)
Time (Ps)
-40 -20 0 20 40 60 80 100 120 140
0.2
0.22
0.24
0.26
0.28
0.3
0.32
0.34
0.36
0.38
0.4
LO_R
Rise
Fall
Temperature (°C)
LO Fall Time (ns)
-40 -20 0 20 40 60 80 100 120 140
8
8.2
8.4
8.6
8.8
9
9.2
9.4
9.6
9.8
10
10.2
LO_F
5.5V
12V
16V
Temperature (°C)
HO Rise Time (ns)
-40 -20 0 20 40 60 80 100 120 140
6
9
12
15
18
HO_R
5.5V
12V
16V
Temperature (°C)
Output Voltage (V)
-40 -20 0 20 40 60 80 100 120 140
0.09
0.1
0.11
0.12
0.13
0.14
0.15
0.16
0.17
0.18
0.19
V_HO
5.5V
12V
16V
Temperature (°C)
LO Rise Time (ns)
-40 -20 0 20 40 60 80 100 120 140
9.5
10
10.5
11
11.5
12
12.5
13
13.5
14
14.5
15
LO_R
5.5V
12V
16V
11
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Typical Characteristics (continued)
Unless otherwise specified VVDD=VHB = 12 V, VHS=VVSS = 0 V, No load on outputs
IO=-100mA
Figure 21. HO High Output Voltage (VHOH)
CL=1800pF
Figure 22. LO Rise Time
CL=1800pF
Figure 23. LO Fall Time
CL=1800pF
Figure 24. HO Rise Time
CL=1800pF
Figure 25. HO Fall Time
CL=100nF
Figure 26. LO Rise & Fall Time
l TEXAS INSTRUMENTS ua: 205
Temperature (°C)
Time (ns)
-40 -20 0 20 40 60 80 100 120 140
14.5
15
15.5
16
16.5
17
17.5
18
18.5
19
TDLF
5.5V
12V
16V
Temperature (°C)
Time (ns)
-40 -20 0 20 40 60 80 100 120 140
14
14.5
15
15.5
16
16.5
17
17.5
18
18.5
19
19.5
20
20.5
TDHF
5.5V
12V
16V
Temperature (°C)
Time (ns)
-40 -20 0 20 40 60 80 100 120 140
15
15.5
16
16.5
17
17.5
18
18.5
19
19.5
20
TDLR
5.5V
12V
16V
Temperature (°C)
Time (Ps)
-40 -20 0 20 40 60 80 100 120 140
0.175
0.2
0.225
0.25
0.275
0.3
0.325
0.35
0.375
0.4
0.425
0.45
HO_R
Rise
Fall
Temperature (°C)
Time (ns)
-40 -20 0 20 40 60 80 100 120 140
14.5
15
15.5
16
16.5
17
17.5
18
18.5
19
19.5
20
TDHR
5.5V
12V
16V
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Typical Characteristics (continued)
Unless otherwise specified VVDD=VHB = 12 V, VHS=VVSS = 0 V, No load on outputs
CL=100nF
Figure 27. HO Rise & Fall Time
CL=No Load
Figure 28. HO Rising Propagation Delay (TDHRR)
CL= No Load
Figure 29. HO Falling Propagation Delay (TDHFF)
CL= No Load
Figure 30. LO Rising Propagation Delay (TDLRR)
CL= No Load
Figure 31. LO Falling Propagation Delay (TDLFF)
LEVEL
SHIFT
UVLO
UVLO
HI
LI
VDD
HB
HO
HS
LO
VSS
Copyright © 2018, Texas Instruments Incorporated
Interlock Logic
EN
DRIVER
STAGE
DRIVER
STAGE
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7 Detailed Description
7.1 Overview
The UCC27282 is a high-voltage gate driver designed to drive both the high-side and the low-side N-channel
FETs in a synchronous buck or a half-bridge configurations. The two outputs are independently controlled with
two TTL-compatible input signals. The device can also work with CMOS type control signals at its inputs as long
as signals meet turn-on and turn-off threshold specifications of the UCC27282. The floating high-side driver is
capable of working with HS voltage up to 100 V with respect to VSS. A 100 V bootstrap diode is integrated in the
UCC27282 device to charge high-side gate drive bootstrap capacitor. A robust level shifter operates at high
speed while consuming low power and provides clean level transitions from the control logic to the high-side gate
driver. Undervoltage lockout (UVLO) is provided on both the low-side and the high-side power rails. EN pin is
provided (in DRC packaged parts) to enable or disable the driver. The driver also has input interlock functionality,
which shuts off both the outputs when the two inputs overlap.
7.2 Functional Block Diagram
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7.3 Feature Description
7.3.1 Enable
The device in DRC package has an enable (EN) pin. The outputs will be active only if the EN pin voltage is
above the threshold voltage. Outputs will be held low if EN pin is left floating or pulled-down to ground. An
internal 250 kΩresistor connects EN pin to VSS pin. Thus, leaving the EN pin floating disables the device.
Externally pulling EN pin to ground shall also disable the device. If the EN pin is not used, then it is
recommended to connect it to VDD pin. If a pull-up resistor needs to be used then a strong pull-up resistor is
recommended. For 12V supply voltage, a 10kΩpull-up is suggested. In noise prone application, a small filter
capacitor, 1nF, should be connected from the EN pin to VSS pin as close to the device as possible. An analog or
a digital controller output pin could be connected to EN pin to enable or disable the device. Built-in hysteresis
helps prevent any nuisance tripping or chattering of the outputs.
7.3.2 Start-up and UVLO
Both the high-side and the low-side driver stages include UVLO protection circuitry which monitors the supply
voltage (VDD) and the bootstrap capacitor voltage (VHB–HS). The UVLO circuit inhibits each output until sufficient
supply voltage is available to turn on the external MOSFETs. The built-in UVLO hysteresis prevents chattering
during supply voltage variations. When the supply voltage is applied to the VDD pin of the device, both the
outputs are held low until VDD exceeds the UVLO threshold, typically 5 V. Any UVLO condition on the bootstrap
capacitor (VHB–HS) disables only the high- side output (HO).
Table 1. VDD UVLO Logic Operation
Condition (VHB-HS > VHBR and VEN > Enable Threshold) HI LI HO LO
VDD-VSS < VDDR during device start-up
H L L L
L H L L
H H L L
L L L L
VDD-VSS < VDDR – VDDH after device start-up
H L L L
L H L L
H H L L
L L L L
Table 2. HB UVLO Logic Operation
Condition (VDD > VDDR and VEN > Enable Threshold) HI LI HO LO
VHB-HS < VHBR during device start-up
H L L L
L H L H
H H L L
L L L L
VHB-HS < VHBR – VHBH after device start-up
H L L L
L H L H
H H L L
L L L L
7.3.3 Input Stages and Interlock
The two inputs operate independently, with an exception that both outputs will be pulled low when both inputs
are high or overlap. The independence allows for full control of two outputs compared to the gate drivers that
have a single input. The device has input interlock or cross-conduction protection. Whenever both the inputs are
high, the internal logic turns both the outputs off. Once the device is in shoot-through mode, when one of the
inputs goes low, the outputs follow the input logic. There is no other fixed time de-glitch filter implemented in the
device and therefore propagation delay and delay matching are not sacrificed. In other words, there is no built-in
dead-time due to the interlock feature. Any noise on the input that could cause the output to shoot-through will be
HI
LI
LO
HO
Time
Interlock
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filtered by this feature and the system stays protected. Because the inputs are independent of supply voltage,
they can be connected to outputs of either digital controller or analog controller. Inputs can accept wide slew rate
signals and input can withstand negative voltage to increase the robustness. Small filter at the inputs of the driver
further improves system robustness in noise prone applications. The inputs have internal pull down resistors with
typical value of 250 kΩ. Thus, when the inputs are floating, the outputs are held low.
Figure 32. Interlock or Input Shoot-through Protection
7.3.4 Level Shifter
The level shift circuit is the interface from the high-side input, which is a VSS referenced signal, to the high-side
driver stage which is referenced to the switch node (HS pin). The level shift allows control of the HO output which
is referenced to the HS pin. The delay introduced by the level shifter is kept as low as possible and therefore the
device provides excellent propagation delay characteristic and delay matching with the low-side driver output.
Low delay matching allows power stages to operate with less dead time. The reduction in dead-time is very
important in applications where high efficiency is required.
7.3.5 Output Stage
The output stages are the interface from level shifter output to the power MOSFETs in the power train. High slew
rate, low resistance, and high peak current capability of both outputs allow for efficient switching of the power
MOSFETs. The low-side output stage is referenced to VSS and the high-side is referenced to HS. The device
output stages are robust to handle harsh environment, such as –2 V transient for 100 ns. The device can also
sustain positive transients on the outputs. The device output stages feature a pull-up structure which delivers the
highest peak source current when it is most needed, during the Miller plateau region of the power switch turn on
transition. The output pull-up and pull-down structure of the device is totem pole NMOS-PMOS structure.
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(1) HO is measured with respect to HS
(2) LO is measured with respect to VSS
7.3.6 Negative Voltage Transients
In most applications, the body diode of the external low-side power MOSFET clamps the HS node to ground. In
some situations, board capacitances and inductances can cause the HS node to transiently swing several volts
below ground, before the body diode of the external low-side MOSFET clamps this swing. When used in
conjunction with the UCC27282, the HS node can swing below ground as long as specifications are not violated
and conditions mentioned in this section are followed.
HS must always be at a lower potential than HO. Pulling HO more negative than specified conditions can
activate parasitic transistors which may result in excessive current flow from the HB supply. This may result in
damage to the device. The same relationship is true with LO and VSS. If necessary, a Schottky diode can be
placed externally between HO and HS or LO and VSS to protect the device from this type of transient. The diode
must be placed as close to the device pins as possible in order to be effective.
Ensure that the HB to HS operating voltage is 16 V or less. Hence, if the HS pin transient voltage is –5 V, then
VDD (and thus HB) is ideally limited to 11 V to keep the HB to HS voltage below 16 V. Generally when HS
swings negative, HB follows HS instantaneously and therefore the HB to HS voltage does not significantly
overshoot.
Low ESR bypass capacitors from HB to HS and from VDD to VSS are essential for proper operation of the gate
driver device. The capacitor should be located at the leads of the device to minimize series inductance. The peak
currents from LO and HO can be quite large. Any series inductances with the bypass capacitor causes voltage
ringing at the leads of the device which must be avoided for reliable operation.
Based on application board design and other operating parameters, along with HS pin, other pins such as inputs,
HI and LI, might also transiently swing below ground. To accommodate such operating conditions UCC27282
input pins are capable of handling absolute maximum of -5V. As explained earlier, based on the layout and other
design constraints, some times the outputs, HO and LO, might also see transient voltages for short durations.
Therefore, UCC27282 gate drivers can also handle -2 V 100 ns transients on output pins, HO and LO.
7.4 Device Functional Modes
When the device is enabled, the device operates in normal mode and UVLO mode. See Start-up and UVLO for
more information on UVLO operation mode. In normal mode when the VDD and VHB–HS are above UVLO
threshold, the output stage is dependent on the states of the EN, HI and LI pins. The output HO and LO will be
low if input state is floating.
Table 3. Input/Output Logic in Normal Mode of Operation
EN HI LI HO (1) LO (2)
L
H H L L
L H L L
H L L L
L L L L
H
H H L L
L H L H
H L H L
L L L L
H
Floating L L L
Floating H L H
L Floating L L
H Floating H L
Floating Floating Floating L L
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
Most electronic devices and applications are becoming more and more power hungry. These applications are
also reducing in overall size. One way to achieve both high power and low size is to improve the efficiency and
distribute the power loss optimally. Most of these applications employ power MOSFETs and they are being
switched at higher and higher frequencies. To operate power MOSFETs at high switching frequencies and to
reduce associated switching losses, a powerful gate driver is employed between the PWM output of controller
and the gates of the power semiconductor devices, such as power MOSFETs, IGBTs, SiC FETs, and GaN FETs.
Many of these applications require proper UVLO protection so that power semiconductor devices are turned ON
and OFF optimally. Also, gate drivers are indispensable when it is impossible for the PWM controller to directly
drive the gates of the switching devices. With the advent of digital power, this situation is often encountered
because the PWM signal from the digital controller is often a 3.3-V logic signal which cannot effectively turn on a
power switch. A level-shift circuit is needed to boost the 3.3-V signal to the gate-drive voltage (such as 12 V or 5
V) in order to fully turn-on the power device, minimize conduction losses, and minimize the switching losses.
Traditional buffer drive circuits based on NPN/PNP bipolar transistors in totem-pole arrangement prove
inadequate with digital power because they lack level-shifting capability and under voltage lockout protection.
Gate drivers effectively combine both the level-shifting and buffer-drive functions. Gate drivers also solve other
problems such as minimizing the effect of high-frequency switching noise (by placing the high-current driver
device physically close to the power switch), driving gate-drive transformers and controlling floating power device
gates. This helps reduce power dissipation and thermal stress in controllers by moving gate charge power losses
from the controller IC to the gate driver.
UCC27282 gate drivers offer high voltage (100 V), small delays (16 ns), and good driving capability (2.5 A/3.5 A)
in a single device. The floating high-side driver is capable of operating with switch node voltages up to 100 V.
This allows for N-channel MOSFETs control in half-bridge, full-bridge, synchronous buck, synchronous boost,
and active clamp topologies. UCC27282 gate driver IC also has built-in bootstrap diode to help power supply
designers optimize PWB area and to help reduce bill of material cost in most applications. The driver has an
enable/disable functionality to be used in applications where driver needs to be enabled or disabled based on
fault condition in other parts of the circuit. Interlock functionality of the device is very useful in applications where
overall reliability of the system is of utmost criteria and redundant protection is desired. Each channel is
controlled by its respective input pins (HI and LI), allowing flexibility to control ON and OFF state of the output.
Both the outputs are forced OFF when the two inputs overlap.
Switching power devices such as MOSFETs have two main loss components; switching losses and conduction
losses. Conduction loss is dominated by current through the device and ON resistance of the device. Switching
losses are dominated by gate charge of the switching device, gate voltage of the switching device, and switching
frequency. Applications where operating switching frequency is very high, the switching losses start to
significantly impact overall system efficiency. In such applications, to reduce the switching losses it becomes
essential to reduce the gate voltage. The gate voltage is determined by the supply voltage the gate driver ICs,
therefore, the gate driver IC needs to operate at lower supply voltage in such applications. UCC27282 gate driver
has typical UVLO level of 5V and therefore, they are perfectly suitable for such applications. There is enough
UVLO hysteresis provided to avoid any chattering or nuisance tripping which improves system robustness.
l TEXAS INSTRUMENTS 4 gillE 47 ; g 1 L" E I I \F'?‘ 1‘”—I L * MJEL l 7 : 7 7 7 97v
¿VHB = VDD FVDH FVHBL
= :7 V 1 V (4.4 V 0.37 V); = 1.97 V
PWM
CONTROLLER
CONTROL
DRIVE
LO
7 V
VDD
DRIVE
HI
UCC27282
HB
HO
HS
LO
HI
LI
75 V
ISOLATION
AND
FEEDBACK
SECONDARY
SIDE
CIRCUIT
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EN
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8.2 Typical Application
Figure 33. Typical Application
8.2.1 Design Requirements
Table below lists the system parameters. UCC27282 needs to operate satisfactorily in conjunction with them.
Table 4. Design Requirements
Parameter Value
MOSFET CSD19535KTT
Maximum Bus/Input Voltage, Vin 75V
Operating Bias Votage, VDD 7V
Switching Frequency, Fsw 300kHz
Total Gate Charge of FET at given VDD, QG52nC
MOSFET Internal Gate Resistance,
RGFET_Int 1.4
Maximum Duty Cycle, DMax 0.5
Gate Driver UCC27282
8.2.2 Detailed Design Procedure
8.2.2.1 Select Bootstrap and VDD Capacitor
The bootstrap capacitor must maintain the VHB-HS voltage above the UVLO threshold for normal operation.
Calculate the maximum allowable drop across the bootstrap capacitor, ΔVHB, with Equation 1.
where
• VDD is the supply voltage of gate driver device
• VDH is the bootstrap diode forward voltage drop
• VHBL is the HB falling threshold ( VHBR(max) – VHBH) (1)
l TEXAS INSTRUMENTS Q (D— (‘— 2 52 nC + 0.083 nC + 1.33 nC : 53.41 HC 2711 nF AVHB P :7V >< 0.4ma+="" 6v="">< 0.4ma="" :5.2mw="" 12mg="vHE" x1"bs="">< d="82V">< sopax="" 05:2‘05mw="">
P
IHBS = V
HB × IHBS × D = 82 V × 50 µA × 0.5 = 2.05 mW
P
QC = :VDD × IDD ;+ :VDD F VDH ; × IHB
= 7 V × 0.4 mA + 6 V × 0.4 mA = 5.2 mW
CBOOT :min ;= QTOTAL
¿VHB
= 53.41 nC
1.97 V = 27.11 nF
QTOTAL = QG+ IHBS ×lDMAX
fSW p+lIHB
fSW p
= 52 nC + 0.083 nC + 1.33 nC = 53.41 nC
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In this example the allowed voltage drop across bootstrap capacitor is 1.97 V.
It is generally recommended that ripple voltage on both the bootstrap capacitor and VDD capacitor should be
minimized as much as possible. Many of commercial, industrial, and automotive applications use ripple value of
0.5 V.
Use Equation 2 to estimate the total charge needed per switching cycle from bootstrap capacitor.
where
• QGis the total MOSFET gate charge
• IHBS is the HB to VSS leakage current from datasheet
• DMax is the converter maximum duty cycle
• IHB is the HB quiescent current from the datasheet (2)
The caculated total charge is 53.41 nC.
Next, use Equation 3 to estimate the minimum bootstrap capacitor value.
(3)
The calculated value of minimum bootstrap capacitor is 27.11 nF. It should be noted that, this value of
capacitance is needed at full bias voltage. In practice, the value of the bootstrap capacitor must be greater than
calculated value to allow for situations where the power stage may skip pulse due to various transient conditions.
It is recommended to use a 100-nF bootstrap capacitor in this example. It is also recommenced to include
enough margin and place the bootstrap capacitor as close to the HB and HS pins as possible. Also place a small
size, 0402, low value, 1000 pF, capacitor to filter high frequency noise, in parallel with main bypass capacitor.
For this application, choose a CBOOT capacitor that has the following specifications: 0.1 µF, 25 V, X7R
As a general rule the local VDD bypass capacitor must be greater than the value of bootstrap capacitor value
(generally 10 times the bootstrap capacitor value). For this application choose a CVDD capacitor with the following
specifications: 1 µF , 25 V, X7R
CVDD capacitor is placed across VDD and VSS pin of the gate driver. Similar to bootstrap capacitors, place a
small size and low value capacitor in parallel with the main bypass capacitor. For this application, choose 0402,
1000 pF, capacitance in parallel with main bypass capacitor to filter high frequency noise.
The bootstrap and bias capacitors must be ceramic types with X7R dielectric or better. Choose a capacitor with a
voltage rating at least twice the maximum voltage that it will be exposed to. Choose this value because most
ceramic capacitors lose significant capacitance when biased. This value also improves the long term reliability of
the system.
8.2.2.2 Estimate Driver Power Losses
The total power loss in gate driver device such as the UCC27282 is the summation of the power loss in different
functional blocks of the gate driver device. These power loss components are explained in this section.
1. Equation 4 describes how quiescent currents (IDD and IHB) affect the static power losses, PQC.
(4)
it is not shown here, but for better approximation, add no load operating current, IDDO and IHBO in above
equation.
2. Equation 5 shows how high-side to low-side leakage current (IHBS) affects level-shifter losses (PIHBS).
where
• D is the high-side MOSFET duty cycle
• VHB is the sum of input voltage and voltage across bootstrap capacitor. (5)
l TEXAS INSTRUMENTS R P :2 X 7V X 52nC X 300kHz X 0.74: 0.16W PLS VHB QP fSW
P
MAX =kT
JFT
Ao
REJA
P
LS = V
HB × QP× fSW
P
QG = 2 × VDD × QG× fSW ×RGD _R
RGD _R+ RGATE + RGFET :int ;
= 2 × 7 V × 52 nC × 300 kHz × 0.74 = 0.16 W
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3. Equation 6 shows how MOSFETs gate charge (QG) affects the dynamic losses, PQG.
where
• QGis the total MOSFET gate charge
• fSW is the switching frequency
• RGD_R is the average value of pullup and pulldown resistor
• RGATE is the external gate drive resistor
• RGFET(int) is the power MOSFETs internal gate resistor (6)
Assume there is no external gate resistor in this example. The average value of maximum pull-up and pull
down resistance of the driver output section is approximately 4 Ω. Substitute the application values to
calculate the dynamic loss due to gate charge, which is 160 mW here.
4. Equation 7 shows how parasitic level-shifter charge (QP) on each switching cycle affects dynamic losses,
(PLS) during high-side switching.
(7)
For this example and simplicity, it is assumed that value of parasitic charge QPis 1 nC. Substituting values
results in 24.6 mW as level shifter dynamic loss. This estimate is very high for level shifter dynamic losses.
The sum of all the losses is 191.85 mW as a total gate driver loss. As shown in this example, in most
applications the dynamic loss due to gate charge dominates the total power loss in gate driver device. For gate
drivers that include bootstrap diode, one should also estimate losses in bootstrap diode. Diode forward
conduction loss is computed as product of average forward voltage drop and average forward current.
Equation 8 estimates the maximum allowable power loss of the device for a given ambient temperature.
where
• PMAX is the maximum allowed power dissipation in the gate driver device
• TJis the recommended maximum operating junction temperature
• TAis hte ambient temperature of the gate driver device
• RθJA is the junction-to-ambient thermal resistance (8)
To better estimate the junction temperature of the gate driver device in the application, it is recommended to first
accurately measure the case temperature and then determine the power dissipation in a given application. Then
use ψJT to calculate junction temperature. After estimating junction temperature and measuring ambient
temperature in the application, calculate θJA(effective). Then, if design parameters (such as the value of an external
gate resistor or power MOSFET) change during the development of the project, use θJA(effective) to estimate how
these changes affect junction temperature of the gate driver device.
For detailed information regarding the thermal information table, please refer to the Semiconductor and Device
Package Thermal Metrics application report.
8.2.2.3 Selecting External Gate Resistor
In high-frequency switching power supply applications where high-current gate drivers such as the UCC27282
are used, parasitic inductances, parasitic capacitances and high-current loops can cause noise and ringing on
the gate of power MOSFETs. Often external gate resistors are used to damp this ringing and noise. In some
applications the gate charge, which is load on gate driver device, is significantly larger than gate driver peak
output current capability. In such applications external gate resistors can limit the peak output current of the gate
driver. it is recommended that there should be provision of external gate resistor whenever the layout or
application permits.
Use Equation 9 to calculate the driver high-side pull-up current.
l TEXAS INSTRUMENTS V + RGFET( t)
IOLL =
VDD
RLOL + RGATE+ RGFET:int;
IOHL =
VDD
RLOH + RGATE+ RGFET:int;
IOLH =
VDD FVDH
RHOL + RGATE+ RGFET:int;
IOHH =
VDD FVDH
RHOH + RGATE+ RGFET:int;
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where
• IOHH is the high-side, peak pull-up current
• VDH is the bootstrap diode forward voltage drop
• RHOH is the gate driver internal high-side pull-up resistor. Value either directly provided in datasheet or can be
calculated from test conditions (RHOH = VHOH/IHO)
• RGATE is the external gate resistance connected between driver output and power MOSFET gate
• RGFET(int) is the MOSFET internal gate resistance provided by MOSFET datasheet (9)
Use Equation 10 to calculate the driver high-side sink current.
where
• RHOL is the gate driver internal high-side pull-down resistance (10)
Use Equation 11 to calculate the driver low-side source current.
where
• RLOH is the gate driver internal low-side pull-up resistance (11)
Use Equation 12 to calculate the driver low-side sink current.
where
• RLOL is the gate driver internal low-side pull-down resistance (12)
Typical peak pull up and pull down current of the device is 2.5 A and 3.5 A respectively. These equations help
reduce the peak current if needed. To establish different rise time value compared to fall time value, external
gate resistor can be anti-paralleled with diode-resistor combination as shown in Figure 33. Generally selecting an
optimal value or configuration of external gate resistor is an iterative process. For additional information on
selecting external gate resistor please refer to External Gate Resistor Design Guide for Gate Drivers
8.2.2.4 Delays and Pulse Width
The total delay encountered in the PWM, driver and power stage need to be considered for a number of reasons,
primarily delay in current limit response. Also to be considered are differences in delays between the drivers
which can lead to various concerns depending on the topology. The synchronous buck topology switching
requires careful selection of dead-time between the high-side and low-side switches to avoid cross conduction as
well as excessive body diode conduction.
Bridge topologies can be affected by a volt-second imbalance on the transformer if there is imbalance in the
high-side and low-side pulse widths in any operating condition. The UCC27282 device has maximum
propagation delay, across process, and temperature variation, of 30 ns and delay matching of 7 ns, which is one
of the best in the industry.
Narrow input pulse width performance is an important consideration in gate driver devices, because output may
not follow input signals satisfactorily when input pulse widths are very narrow. Although there may be relatively
wide steady state PWM output signals from controller, very narrow pulses may be encountered under following
operating conditions.
• soft-start period
• large load transients
• short circuit conditions
l TEXAS INSTRUMENTS mm ‘ ‘ \mun sow 200v , my mm Mun m M» 5mm .owmuv assom WWW-mu smmh mm 115m mm mm 2123a «(my mum WWW-mu nwmxh mm 1mm xswn um uzm loom Human [ rm mom noon) vows
HI (2V/div)
BW=1GHz
LI (2V/div)
BW=1GHz
HO (5V/div)
BW=1GHz
LO (5V/div)
BW=1GHz
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These narrow pulses appear as an input signal to the gate driver device and the gate driver device need to
respond properly to these narrow signals.
Figure 34 shows that the UCC27282 device produces reliable output pulse even when the input pulses are very
narrow and bias voltages are very low. The propagation delay and delay matching do not get affected when the
input pulse width is very narrow.
Figure 34. Input and Output Pulse Width
8.2.2.5 External Bootstrap Diode
The UCC27282 incorporates the bootstrap diode necessary to generate the high-side bias for HO to work
satisfactorily. The characteristics of this diode are important to achieve efficient, reliable operation. The
characteristics to consider are forward voltage drop and dynamic resistance. Generally, low forward voltage drop
diodes are preferred for low power loss during charging of the bootstrap capacitor. The device has a boot diode
forward voltage drop rated at 0.85 V and dynamic resistance of 1.5 Ωfor reliable charge transfer to the bootstrap
capacitor. The dynamic characteristics to consider are diode recovery time and stored charge. Diode recovery
times that are specified without operating conditions, can be misleading. Diode recovery times at no forward
current (IF) can be noticeably less than with forward current applied. The UCC27282 boot diode recovery is
specified as 50 ns at IF= 20 mA, IREV = 0.5 A. Dynamic impedance of UCC27282 bootstrap diode naturally limits
the peak forward current and prevents any damage if repetitive peak forward current pulses exist in the system
for most applications.
In applications where switching frequencies are very high, for example in excess of 1 MHz, and the low-side
minimum pulse widths are very small, the diode peak forward current could be very high and peak reverse
current could also be very high, specifically if high bootstrap capacitor value has been chosen. In such
applications it might be advisable to use external Schottkey diode as bootstrap diode. It is safe to at least make a
provision for such diode on the board if possible.
8.2.2.6 VDD and Input Filter
Some switching power supply applications are extremely noisy. Noise may come from ground bouncing and
ringing at the inputs, (which are the HI and LI pins of the gate driver device). To mitigate such situations, the
UCC27282 offers both negative input voltage handling capability and wide input threshold hysteresis. If these
features are not enough, then the application might need an input filter. Small filter such as 10-Ωresistor and 47-
pF capacitor might be sufficient to filter noise at the inputs of the gate driver device. This RC filter would
introduce delay and therefore need to be considered carefully. High frequency noise on bias supply can cause
problems in performance of the gate driver device. To filter this noise it is recommended to use 1-Ωresistor in
series with VDD pin as shown in Figure 33. This resistor also acts as a current limiting element. In the event of
short circuit on the bias rail, this resistor opens up and prevents further damage. This resistor can also be helpful
in debugging the design during development phase.
l TEXAS INSTRUMENTS
23
UCC27282
www.ti.com
SNVSAQ5A –NOVEMBER 2018–REVISED JANUARY 2020
Product Folder Links: UCC27282
Submit Documentation FeedbackCopyright © 2018–2020, Texas Instruments Incorporated
8.2.2.7 Transient Protection
As mentioned in previous sections, high power high switching frequency power supplies are inherently noisy.
High dV/dt and dI/dt in the circuit can cause negative voltage on different pins such as HO, LO, and HS. The
device tolerates negative voltage on all of these pins as mentioned in specification tables. If parasitic elements of
the circuit cause very large negative swings, circuit might require additional protection. In such cases fast acting
and low leakage type Schottky diode should be used. This diode must be placed as close to the gate driver
device pin as possible for it to be effective in clamping excessive negative voltage on the gate driver device pin.
Sometimes a small resistor, (for example 2 Ω, in series with HS pin) is also effective in improving performance
reliability. To avoid the possibility of driver device damage due to over-voltage on its output pins or supply pins,
low leakage Zener diode can be used. A 15-V Zener diode is often sufficient to clamp the voltage below the
maximum recommended value of 16 V.
8.2.3 Application Curves
To minimize the switching losses in power supplies, turn-ON and turn-OFF of the power MOSFETs need to be
as fast as possible. Higher the drive current capability of the driver, faster the switching. Therefore, the
UCC27282 is designed with high drive current capability and low resistance of the output stages. One of the
common way to test the drive capability of the gate driver device , is to test it under heavy load. Rise time and
fall time of the outputs would provide idea of drive capability of the gate driver device. There must not be any
resistance in this test circuit. Figure 35 and Figure 36 shows rise time and fall time of HO respectively of
UCC27282. Figure 37 and Figure 38 shows rise time and fall time of LO respectively of UCC27282. For accuracy
purpose, the VDD and HB pin of the gate driver device were connected together. HS and VSS pins are also
connected together for this test.
Peak current capability can be estimated using the fastest dV/dt along the rise and fall curve of the plot. This
method is also useful in comparing performance of two or more gate driver devices.
As explained in Delays and Pulse Width, propagation delay plays an important role in reliable operation of many
applications. Figure 39 and Figure 40
Figure 40 shows propagation delay and delay matching of UCC27282. In many switching power supply
applications input signals to the gate driver have large amplitude high frequency noise. If there is no filter
employed at the input, then there is a possibility of false signal passing through the gate driver and causing
shoot-through on the output. UCC27282 prevents such shoot-through. If two inputs are high at the same time,
UCC27282 shuts both the outputs off. Figure 41 shows interlock feature of UCC27282 and Figure 42 shows
input negative voltage handling capability of UCC27282.
VDD = VHB = 6 V, HS =
VSS CLOAD = 10
nF Ch4 = HO
Figure 35. HO Rise Time
VDD = VHB=6 V, HS =
VSS CLOAD = 10
nF Ch4 = HO
Figure 36. HO Fall Time
l TEXAS INSTRUMENTS
24
UCC27282
SNVSAQ5A –NOVEMBER 2018–REVISED JANUARY 2020
www.ti.com
Product Folder Links: UCC27282
Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated
VDD = VHB = 6 V, HS = VSS CLOAD = 10 nF Ch4 =
LO
Figure 37. LO Rise Time
VDD = VHB = 6 V, HS =
VSS CLOAD = 10 nF Ch4 = LO
Figure 38. LO Fall Time
VDD = 6 V CLOAD = 2
nF Ch1 = HI Ch2 = LI Ch3 = HO Ch4
= LO
Figure 39. Propagation Delay and Delay Matching
VDD = 6
VCLOAD = 2 nF Ch1 = HI Ch2 = LI Ch3 = HO Ch4
= LO
Figure 40. Propagation Delay and Delay Matching
l TEXAS INSTRUMENTS unfla‘mnufl '“ 1""
HI (2V/div)
LI (2V/div)
HO (5V/div)
LO (5V/div)
25
UCC27282
www.ti.com
SNVSAQ5A –NOVEMBER 2018–REVISED JANUARY 2020
Product Folder Links: UCC27282
Submit Documentation FeedbackCopyright © 2018–2020, Texas Instruments Incorporated
VDD = VHB = 12 V, HS = VSS CLOAD = 0 nF
Figure 41. Input Shoot-through Protection or Interlock
VDD = 10 V Vin =
100 V CL= 1
nF Ch1 = HI Ch2 = LI Ch3 = HO
Ch4 = LO
Figure 42. Input Negative Voltage
l TEXAS INSTRUMENTS
26
UCC27282
SNVSAQ5A –NOVEMBER 2018–REVISED JANUARY 2020
www.ti.com
Product Folder Links: UCC27282
Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated
9 Power Supply Recommendations
The recommended bias supply voltage range for UCC27282 is from 5.5 V to 16 V. The lower end of this range is
governed by the internal under voltage-lockout (UVLO) protection feature, 5 V typical, of the VDD supply circuit
block. The upper end of this range is driven by the 16-V recomended maximum voltage rating of the VDD. It is
recommended that voltage on VDD pin should be lower than maximum recommended voltage. In some transient
condition it is not possible to keep this voltage below recommended maximum level and therefore absolute
maximum voltage rating of the UCC27282 is 20 V.
The UVLO protection feature also involves a hysteresis function. This means that once the device is operating in
normal mode, if the VDD voltage drops, the device continues to operate in normal mode as far as the voltage
drop do not exceeds the hysteresis specification, VDDHYS. If the voltage drop is more than hysteresis
specification, the device shuts down. Therefore, while operating at or near the 5.5-V range, the voltage ripple on
the auxiliary power supply output should be smaller than the hysteresis specification of UCC27282 to avoid
triggering device shutdown.
A local bypass capacitor should be placed between the VDD and GND pins. This capacitor should be located as
close to the device as possible. A low ESR, ceramic surface mount capacitor is recommended. It is
recommended to use two capacitors across VDD and GND: a low capacitance ceramic surface-mount capacitor
for high frequency filtering placed very close to VDD and GND pin, and another high capacitance value surface-
mount capacitor for device bias requirements. In a similar manner, the current pulses delivered by the HO pin are
sourced from the HB pin. Therefore, two capacitors across the HB to HS are recommended. One low value small
size capacitor for high frequency filtering and another one high capacitance value capacitor to deliver HO pulses.
UCC27282 has enable/disable functionality through EN pin. Therefore, signal at the EN pin should be as clean
as possible. If EN pin is not used, then it is recommended to connect the pin to VDD pin. If EN pin is pulled up
through a resistor, then the pull-up resistor needs to be strong. In noise prone applications, it is recommended to
filter the EN pin with small capacitor, such as X7R 0402 1nF.
In power supplies where noise is very dominant and there is space on the PWB (Printed Wiring Board), it is
recommended to place a small RC filter at the inputs. This allows for improving the overall performance of the
design. In such applications. it is also recommended to have a place holder for power MOSFET external gate
resistor. This resistor allows the control of not only the drive capability but also the slew rate on HS, which
impacts the performance of the high-side circuit. If diode is used across the external gate resistor, it is
recommended to use a resistor in series with the diode, which provides further control of fall time.
In power supply applications such as motor drives, there exist lot of transients through-out the system. This
sometime causes over voltage and under voltage spikes on almost all pins of the gate driver device. To increase
the robustness of the design, it is recommended that the clamp diode should be used on HO and LO pins. If user
does not wish to use power MOSFET parasitic diode, external clamp diode on HS pin is recommended, which
needs to be high voltage high current type (same rating as MOSFET) and very fast acting. The leakage of these
diodes across the temperature needs to be minimal.
In power supply applications where it is almost certain that there is excessive negative HS voltage, it is
recommended to place a small resistor between the HS pin and the switch node. This resistance helps limit
current into the driver device up to some extent. This resistor will impact the high side drive capability and
therefore needs to be considered carefully.
l TEXAS INSTRUMENTS vss P‘ane p and 50an MOSFET
Input Filters
(Top Layer)
VDD Capacitors
(Top Layer)
To High Side MOSFET
VSS Plane
(Top and Bottom Layer)
Input PWMs
Boot Diode & Capacitor
(Bottom Layer)
To Low Side
MOSFET
27
UCC27282
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SNVSAQ5A –NOVEMBER 2018–REVISED JANUARY 2020
Product Folder Links: UCC27282
Submit Documentation FeedbackCopyright © 2018–2020, Texas Instruments Incorporated
10 Layout
10.1 Layout Guidelines
To achieve optimum performance of high-side and low-side gate drivers, one must consider following printed
wiring board (PWB) layout guidelines.
• Low ESR/ESL capacitors must be connected close to the device between VDD and VSS pins and between
HB and HS pins to support high peak currents drawn from VDD and HB pins during the turn-on of the
external MOSFETs.
• To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor and a
good quality ceramic capacitor must be connected between the high side MOSFET drain and ground (VSS).
• In order to avoid large negative transients on the switch node (HS) pin, the parasitic inductances between the
source of the high-side MOSFET and the source of the low-side MOSFET (synchronous rectifier) must be
minimized.
• Overlapping of HS plane and ground (VSS) plane should be minimized as much as possible so that coupling
of switching noise into the ground plane is minimized.
• Thermal pad should be connected to large heavy copper plane to improve the thermal performance of the
device. Generally it is connected to the ground plane which is the same as VSS of the device. It is
recommended to connect this pad to the VSS pin only.
• Grounding considerations:
– The first priority in designing grounding connections is to confine the high peak currents that charge and
discharge the MOSFET gates to a minimal physical area. This confinement decreases the loop inductance
and minimize noise issues on the gate terminals of the MOSFETs. Place the gate driver as close to the
MOSFETs as possible.
– The second consideration is the high current path that includes the bootstrap capacitor, the bootstrap
diode, the local ground referenced bypass capacitor, and the low-side MOSFET body diode. The
bootstrap capacitor is recharged on a cycle-by-cycle basis through the bootstrap diode from the ground
referenced VDD bypass capacitor. The recharging occurs in a short time interval and involves high peak
current. Minimizing this loop length and area on the circuit board is important to ensure reliable operation.
10.2 Layout Example
Figure 43. Layout Example
l TEXAS INSTRUMENTS Am
28
UCC27282
SNVSAQ5A –NOVEMBER 2018–REVISED JANUARY 2020
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Product Folder Links: UCC27282
Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated
11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.2 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.5 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
UCC27282D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 U282
UCC27282DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 U282
UCC27282DRCR ACTIVE VSON DRC 10 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 U27282
UCC27282DRCT ACTIVE VSON DRC 10 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 U27282
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF UCC27282 :
•Automotive: UCC27282-Q1
NOTE: Qualified Version Definitions:
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
l TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “K0 '«Pi» Reel Diame|er AD Dimension designed to accommodate the componeni width ED Dimension deSigned to eccemmodaie me componeni iengm KO Dlmenslun designed to accommodate the eomponeni thickness 7 w Overeii Widlh loe earner cape i p1 Piich between successive cawiy ceniers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D D SprockeiHules ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pockel Quadrams
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
UCC27282DR SOIC D 8 2500 330.0 12.5 6.4 5.2 2.1 8.0 12.0 Q1
UCC27282DRCR VSON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
UCC27282DRCT VSON DRC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 7-Jul-2021
Pack Materials-Page 1
l TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
UCC27282DR SOIC D 8 2500 340.5 336.1 25.0
UCC27282DRCR VSON DRC 10 3000 367.0 367.0 35.0
UCC27282DRCT VSON DRC 10 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 7-Jul-2021
Pack Materials-Page 2
‘J
www.ti.com
PACKAGE OUTLINE
C
.228-.244 TYP
[5.80-6.19]
.069 MAX
[1.75]
6X .050
[1.27]
8X .012-.020
[0.31-0.51]
2X
.150
[3.81]
.005-.010 TYP
[0.13-0.25]
0 - 8 .004-.010
[0.11-0.25]
.010
[0.25]
.016-.050
[0.41-1.27]
4X (0 -15 )
A
.189-.197
[4.81-5.00]
NOTE 3
B .150-.157
[3.81-3.98]
NOTE 4
4X (0 -15 )
(.041)
[1.04]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
18
.010 [0.25] C A B
5
4
PIN 1 ID AREA
SEATING PLANE
.004 [0.1] C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
Yl“‘+
www.ti.com
EXAMPLE BOARD LAYOUT
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
(.213)
[5.4]
6X (.050 )
[1.27]
8X (.061 )
[1.55]
8X (.024)
[0.6]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED
METAL
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED
METAL
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SYMM
1
45
8
SEE
DETAILS
SYMM
www.ti.com
EXAMPLE STENCIL DESIGN
8X (.061 )
[1.55]
8X (.024)
[0.6]
6X (.050 )
[1.27] (.213)
[5.4]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
SYMM
SYMM
1
45
8
www.ti.com
GENERIC PACKAGE VIEW
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
VSON - 1 mm max heightDRC 10
PLASTIC SMALL OUTLINE - NO LEAD
3 x 3, 0.5 mm pitch
4226193/A
--I vfi g C C C C C r1 C I WW‘iTiqu C A 33933
www.ti.com
PACKAGE OUTLINE
C
10X 0.30
0.18
2.4 0.1
2X
2
1.65 0.1
8X 0.5
1.0
0.8
10X 0.5
0.3
0.05
0.00
A3.1
2.9 B
3.1
2.9
(0.2) TYP
4X (0.25)
2X (0.5)
VSON - 1 mm max heightDRC0010J
PLASTIC SMALL OUTLINE - NO LEAD
4218878/B 07/2018
PIN 1 INDEX AREA
SEATING PLANE
0.08 C
1
56
10
(OPTIONAL)
PIN 1 ID 0.1 C A B
0.05 C
THERMAL PAD
EXPOSED
SYMM
SYMM
11
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
10X (0.24)
(2.4)
(2.8)
8X (0.5)
(1.65)
( 0.2) VIA
TYP
(0.575)
(0.95)
10X (0.6)
(R0.05) TYP
(3.4)
(0.25)
(0.5)
VSON - 1 mm max heightDRC0010J
PLASTIC SMALL OUTLINE - NO LEAD
4218878/B 07/2018
SYMM
1
56
10
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
11
SYMM
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
SOLDER MASK
OPENING
SOLDER MASK
METAL UNDER
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
(PREFERRED)
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(R0.05) TYP
10X (0.24)
10X (0.6)
2X (1.5)
2X
(1.06)
(2.8)
(0.63)
8X (0.5)
(0.5)
4X (0.34)
4X (0.25)
(1.53)
VSON - 1 mm max heightDRC0010J
PLASTIC SMALL OUTLINE - NO LEAD
4218878/B 07/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
80% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
SYMM
1
56
10
EXPOSED METAL
TYP
11
SYMM
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