Use Ferroelectric Memory to Enhance Reliability of Automotive Applications

By Stephen Evanczuk

Contributed By Digi-Key's North American Editors

Non-volatile memory (NVM) plays a key role in nearly every embedded system design, but many designs have increasingly stringent non-volatile memory requirements in terms of data write and access speed, data retention, and low power. This is increasingly the case in automotive applications where designers are looking to build in more advanced features such as advanced driver assistance systems (ADAS) that are mission critical.

To ensure safe and reliable operation of these systems, designers need to take a closer look at advanced ferroelectric random access memory (F-RAM) as a low-power automotive grade NVM option that is reliable, low power, and faster than current NVM solutions.

This article discusses key characteristics of F-RAM technology and describes how developers can use two F-RAM solutions from Cypress Semiconductor to enhance the reliability of ADAS, and use ADAS as a proxy for F-RAM use in other mission-critical applications.

Automotive NVM requirements

Automotive safety applications epitomize the industry trend for the integration of more advanced sensors with higher resolution and faster update rates. Automotive subsystems such as ADAS, electronic control units (ECUs), and event data recorders (EDRs) continue to evolve, relying on deep pools of data collected from a wide array of sensors. Any loss of data or even slow access to the data can compromise system safety, the vehicle, and its passengers.

In ADAS designs, for example, the time needed to write to electrically erasable programmable read-only memory (EEPROM) can inject a potentially disastrous lag in the automatic maneuvers designed to avoid sensed hazards. In EDR designs, slow write performance can cause critical sensor data to be lost if power fails during a vehicular accident, likely eliminating the very data needed to understand the root cause of the accident.

F-RAM NVM characteristics

Memory devices built with F-RAM technology provide an effective NVM alternative that can meet the increasing demand and performance requirements for reliable data storage and high-speed access. The devices are fabricated from lead-zirconate-titanate (Pb[ZrxTi1−x]O3), otherwise known simply as PZT. PZT possesses the unique characteristic where the metal vacancy (cation) embedded within the PZT crystal will attain one of two possible polarization states, up or down, following the direction of the applied electric field (Figure 1).

Diagram of F-RAM technology takes advantages of two equally stable energy statesFigure 1: F-RAM technology takes advantages of two equally stable energy states exhibited by PZT materials when subjected to an electric field. (Image source: Cypress Semiconductor)

Because both are equal low-energy states, the cation will remain fixed in its most recent polarization state when the electric field is removed (Figure 2). Upon application of a positive or negative electric field, the cation will once again quickly transition to the appropriate polarization state following a characteristic hysteresis loop similar to that found in ferromagnetic materials.

Graph of PZT materials follow a characteristic hysteresis loopFigure 2: PZT materials follow a characteristic hysteresis loop when switching between two stable polarization states in response to an applied electric field. (Image source: WikiMedia Commons/ CC-BY-SA-3.0)

The characteristics of F-RAM technology translate directly into a number of benefits for NVM devices fabricated with this technology. Because both PZT energy states are equally stable, the cation will remain in its last position for decades or possibly centuries, resulting in unprecedented data retention rates in PZT-based F-RAM NVM devices. Also, because this technology is based on cation position rather than the charge-storage mechanisms of other NVM technologies, F-RAM devices are inherently radiation tolerant and are immune to single event upsets from ionizing radiation.

Beyond its advantages for long-term storage, F-RAM technology enhances the dynamic performance of NVM devices. The state transition is very fast and requires little energy, overcoming a fundamental limitation associated with the use of EEPROM or flash memory in mission-critical applications. EEPROM and flash devices require a significant “soak time” associated with data buffering during their relatively slow write cycles. This extra delay in the write cycle results in a period where data can be at risk and completely lost if power fails before the operation completes with the final read status check (Figure 3).

Diagram of extended soak time (red highlight) during EEPROM or flash write operationsFigure 3: The need for an extended soak time (red highlight) during EEPROM or flash write operations translates into a significant period of time where data remains at risk compared to F-RAM devices. (Image source: Cypress Semiconductor)

To account for slower write cycles in EEPROM or flash memory, developers hoping to mitigate the effects of power failures have needed to add large capacitors or batteries along with appropriate voltage regulators to maintain NVM supply voltage long enough to complete write operations. In contrast, F-RAMs such as the Cypress Semiconductor Excelon-Auto devices operate at bus speed during write operations, greatly reducing the loss of critical data and eliminating the need for supplemental power sources in the design.

Automotive grade F-RAM devices

Functionally similar to serial EEPROMs and serial flash memories, Excelon™-Auto F-RAM devices are designed to meet requirements of mission-critical applications for reliable, high-performance NVM. Automotive systems designers can use these AEC-Q100-qualified devices to replace other memory types, choosing from the CY15V102QN for 1.71 to 1.89 volt supplies, or the CY15B102QN for 1.8 to 3.6 volt supplies. Both are 2 megabit (Mbit) devices, logically organized as 256 Kbits x 8.

Across their -40°C to +125°C operating temperature range, the Excelon F-RAMs have a data retention rate well beyond that available with other NVM technologies. For example, the CY15x102QN can retain data for an estimated 121 years while operating at 85°C. As data retention is inversely proportional to temperature, if forced to operate at the higher end of typical engine temperatures, for example 95°C, the F-RAMs have an estimated 35 year data retention rate.

With respect to reliability, the F-RAMs have a read/write cycle endurance of 1013, which is about seven orders of magnitude greater than a typical EEPROM or flash memory. As a result, developers using these F-RAM devices do not need to implement techniques such as wear leveling which distributes writes across sectors to account for limited write cycles associated with other NVM technologies.

Simplified design with F-RAM

In a typical design, developers can use these devices to directly replace or complement other types of NVM devices such as NOR flash. In an ADAS design, for example, developers might combine a NOR flash used to store firmware with an Excelon F-RAM able to reliably handle multiple data streams from the many automotive subsystems that provide input to ADAS applications (Figure 4).

Diagram of Excelon F-RAM devices for storing critical data combined with NOR flash devicesFigure 4: Automotive ADAS developers can combine Excelon F-RAM devices for storing critical data with NOR flash devices commonly used to store firmware or configuration data in microcontroller (MCU)-based designs. (Image source: Cypress Semiconductor)

Developers can easily drop Excelon F-RAMs into a design by simply connecting them to the host processor’s serial peripheral interface (SPI) bus. Designed to operate as an SPI slave device, the CY15x102QN F-RAMs can support SPI clock rates up to 50 megahertz (MHz). In a typical hardware configuration, developers connect the F-RAM’s serial in (SI) and serial out (SO) to the SPI master’s Master Out Slave In (MOSI) and Master In Slave Out (MISO) lines, respectively. Connections to the respective serial clock (SCK) and chip select (/CS) lines complete the hardware interface. Developers can combine multiple devices to share the host’s SPI bus (Figure 5).

Diagram of shared SPI bus connected to a host processorFigure 5: Developers can use a shared SPI bus to connect a host processor with one or more CY15x102QN F-RAMs. (Image source: Cypress Semiconductor)

For MCUs without SPI capabilities, the CY15x102QN devices support a simple alternative for emulating the SPI hardware interface by using the microcontroller’s general purpose IO (GPIO) to connect to the F-RAM. Developers can implement this interface using only three GPIO by using the same pin for the F-RAM’s SI and SO data lines (Figure 6).

Diagram of SPI protocol to access a Cypress CY15x102QN serial F-RAMFigure 6: For a microcontroller without native SPI capability, developers can simply use the microcontroller’s general purpose IO to emulate the SPI protocol to access a CY15x102QN serial F-RAM. (Image source: Cypress Semiconductor)

In the standard SPI protocol, a master initiates a transaction by pulling /CS low. After its /CS goes low, the F-RAM interprets the next byte as an opcode. For example, a write operation follows the SPI standard write opcode (02h) with the three byte address and data bytes (Figure 7).

Diagram of Cypress CY15x102QN F-RAM devicesFigure 7: Cypress CY15x102QN F-RAM devices support standard SPI opcodes and protocols, enabling developers to easily perform zero-delay writes by sending the write opcode (02h), address, and data in sequence. (Image source: Cypress Semiconductor)

For the 2 Mbit CY15x102QN F-RAMs, the address is a three byte sequence, with the upper six bits ignored. Cypress recommends setting these upper six bits to zero to permit an easy transition to higher capacity F-RAM devices in the future.

A read operation follows the same protocol. After receiving the standard read opcode (03h) and address, the F-RAM device transmits data bytes sequentially on SO, automatically incrementing the memory address while /CS remains low and clock signals continue. Consequently, developers can perform a bulk read simply by keeping /CS low and continuing to issue SCK clock signals until the required number of data bytes are read.

The CY15x102QN F-RAMs also support a fast read feature compatible with serial flash memory. Following the fast read opcode (0Bh) and address, the SPI host sends a dummy byte to emulate flash read latency. After receiving the dummy byte, the F-RAM responds with the requested data. Fast read operations can also perform bulk reads using the same mechanism as standard reads.

Write protection

Along with SPI interface control logic, the CY15x102QN F-RAMs provide additional mechanisms to identify the device and to write protect the F-RAM array.

Developers can issue SPI opcodes to access a CY15x102QN device’s read-only unique ID and device ID which provide information such as the manufacturer, memory density, and part revision. Developers can also set an eight byte read/write serial number register to associate an F-RAM with a particular system or configuration.

For F-RAM protection, the device provides both software and hardware mechanisms. For data protection during manufacturing, a dedicated 256 byte special sector is designed to maintain data integrity through as many as three standard reflow soldering cycles. For protection during normal operations, the device uses a write-enable latch (WEL) to protect the F-RAM array from inadvertent writes. At power up, the WEL is cleared by default, requiring the developer to issue the write-enable (WREN) opcode (06h) before performing write operations.

In the device status register, a pair of block protection (BP) bits, BP0 and BP1, allow developers to protect memory across the full address range (BP1=1, BP0=1), in only the upper half of memory (BP1=1, BP0=0), or in only the upper quarter of memory (BP1=0, BP0=1).

Developers can use the hardware write protect pin (/WP) to prevent software from modifying the BP bits during normal operations. Here, developers set the write protect enable (WPEN) bit in the status register and send the /WP pin low to lock the status register.

Power management

In normal operations, the energy efficiency inherent in F-RAM technology typically results in current consumption for the CY15V102QN (VDD 1.71 to 1.89 volts) at only 5.0 milliamps (mA) for operations at the maximum 50 MHz clock rate. Developers can reduce the clock frequency for further power savings, dropping current consumptions to about 0.4 mA at 1 MHz for the CY15V102QN. Current consumption with CY15B102QN (VDD 1.8 to 3.6 volts) is only slightly higher at 6.0 mA at 50 MHz and 0.5 mA at 1 MHz.

For extended periods of inactivity, developers significantly reduce power consumption by using SPI opcodes to set the CY15x102QN devices in three low-power modes:

  • Standby mode with typical current consumption at 2.7 microamps (μA) for the CY15V102QN or 3.2 μA for the CY15B102QN
  • Deep power down mode at 1.1 μA for the CY15V102QN or 1.3 μA for the CY15B102QN
  • Hibernate mode at 0.1 μA for either of the two parts

The CY15x102QN devices automatically switch to standby mode whenever the SPI host sets /CS high at the end of an opcode sequence. To switch the device to deep power down or hibernate modes, the SPI host uses the SPI opcode protocol. Specifically, the SPI host switches to one of the two lowest power modes by first setting /CS low, then sending a special opcode for deep power down (BAh) or hibernate (B9h), and finally setting /CS high (Figure 8).

Diagram of Cypress CY15x102QN F-RAM devices automatically enter standby modeFigure 8: While CY15x102QN F-RAM devices automatically enter standby mode after an opcode sequence, developers can put them into even lower power modes such as deep power down (DPD) mode using the normal SPI opcode procedure. (Image source: Cypress Semiconductor)

When the SPI host sets /CS high after sending the appropriate low-power opcode, the CY15x102QN F-RAM enters the requested low-power mode within about 3 μs.

From standby mode, the Cypress F-RAMs immediately return to active mode when /CS goes low to initiate the next opcode sequence. From deep power down or hibernate mode, the F-RAMs also return to active mode after /CS goes low, but with a short delay of about 10 μs for deep power down mode, or 450 μs from hibernate mode.


The need for reliable, fast, low-power, high-performance NVM has become increasingly important across a broad array of applications that depend on data from a growing array of sensors. In mission-critical areas such as automotive ADAS applications, the loss of data can significantly degrade safety mechanisms designed to protect the vehicle and its occupants.

Using F-RAM devices from Cypress Semiconductor, developers can easily add NVM that is able to store critical data reliably for decades without sacrificing performance or low-power requirements.

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About this author

Stephen Evanczuk

Stephen Evanczuk has more than 20 years of experience writing for and about the electronics industry on a wide range of topics including hardware, software, systems, and applications including the IoT. He received his Ph.D. in neuroscience on neuronal networks and worked in the aerospace industry on massively distributed secure systems and algorithm acceleration methods. Currently, when he's not writing articles on technology and engineering, he's working on applications of deep learning to recognition and recommendation systems.

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Digi-Key's North American Editors