CISC MCU Architecture Promises Code Density and Performance Advantages

By Maury Wright

Contributed By Electronic Products

Renesas Electronics has begun to significantly expand the members of its RX microcontroller (MCU) family, introducing one series targeted at connectivity applications and another targeted at motor control applications. The CISC architecture was initially announced a couple years back and then followed up last year with the first product, the RX610. With the new RX62T, RX62N, and RX621 families on the market, let’s take a look at the architecture and the advantages that Renesas claims in areas such as code density and performance.

The RX is based on an enhanced Harvard architecture that is combined with five internal buses and one external bus to optimize the flow of instructions and data. In general, a Harvard design is one in which instructions and data flow into the CPU via separate dedicated buses. In the case of the RX, the CPU can actually fetch both instructions and data from either on-chip flash or SRAM through dedicated buses.

The other internal buses are independent of the code and data paths. The architecture includes multiple DMA controllers, and in fact, a DMA operation can commence simultaneously with the CPU, accessing code and data from flash or SRAM. The architecture also includes a DMA controller that can simultaneously handle transfers between peripherals connected to the external bus.

One key to performance in the RX is the flash memory. In many applications today, integrated flash functions as the primary code-storage memory. But in many cases, flash memory read cycles are not sufficiently fast for zero-wait-state memory access – especially given the escalating clock rates in the MCU segment.

Slower flash either results in performance hit or requires some other way to mitigate the performance penalty. Some MCU companies have turned to what they call a memory accelerator for flash access. Memory accelerator is really a fancy term for cache, and cache hit rates aren’t perfect, so such MCUs will suffer through wait states. Renesas claims its integrated flash can natively support zero-wait-state access at clock speeds up to 100 MHz and deliver 1.65 DMIPs (Dhrystone MIPs) per MHz.

Renesas claims several other performance advantages for the RX family. The MCUs include both a floating-point unit (FPU) to accelerate math operations and a multiply-accumulate unit (MAC) for DSP operations. Moreover, the floating-point instructions can operate directly on data stored in the general-purpose registers, whereas some FPUs require that data be moved to dedicated floating-point registers.

Moving on to code density, the size of the code effects memory requirements and ultimately, system cost. CISC architectures in general offer an advantage to RISC architectures. One of the tenets of RISC is simple instructions that do not accomplish as much as typical CISC instructions. For example, RISC processors generally use load/store instructions to read or write data to and from registers. Arithmetic and logic instructions only operate on data that is in the register.

Again, some companies have attempted to mitigate the code density issue with RISC processors. ARM, for example, has the Thumb instruction set that replaces 32-bit instructions with 16-bit versions of the most commonly used instructions. Such steps certainly can reduce code size but don’t match the CISC alternative. The RX, for example, includes a mix of 8-, 16-, and 32-bit instructions that can be mixed and matched to the task at hand.

In March, Renesas began to significantly expand RX availability. The RX62N and RX621 families integrate communications capabilities and target applications such as home appliances, communications gateways, and point-of-sale terminals. Both series integrate USB and CAN support, and the RX62N series adds Ethernet support. The company offers a range of products in both series with varying amounts of flash and SRAM.

The RX62T family targets motor control applications. All of the RX family members include A/D converters on chip, but the RX62T adds dual 12-bit A/D converters with three programmable gain amplifiers and three window comparators. Target applications include solar inverters, washing machines, and power-factor controllers. Integrated timers will allow the RX62T family to simultaneously control two three-phase motors.

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About this author

Maury Wright

Maury Wright is an electronics engineer turned technology journalist and industry consultant with broad experience in technology areas ranging from microprocessors to digital media to wireless to power management. Wright worked at EDN Magazine for 22 years, serving as editor-in-chief and editorial director for five years. Wright also served as editor of EE Times' Digital Home and Power Management websites.

Currently, Wright is working as a consultant for a number of technology companies and writing under his own byline for the Intel Embedded Community website and for LEDs Magazine.

Wright has won numerous industry awards, including ASBPE national wards for EDN's 50th Anniversary Issue and a similar award for the EDN Prying Eyes department. Wright is an expert in the area of digital media and the connected home, having covered the wired and wireless service-provider and in-home networks extensively. This expertise extends from processors and ASSPs all the way up through the end application. Wright graduated from Auburn University in 1978 with a BSEE and a curriculum emphasis on digital design and development with early microprocessors.

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Electronic Products

Electronic Products magazine and serves engineers and engineering managers responsible for designing electronic equipment and systems.