MG2040 Datasheet by ON Semiconductor

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M62040, SZMGZO40 F 0N Semiconductor® www.0nsemi.com w o 1
© Semiconductor Components Industries, LLC, 2014
October, 2017 Rev. 5
1Publication Order Number:
MG2040/D
MG2040, SZMG2040
ESD Protection Diodes
Low Capacitance ESD Protection for
High Speed Video Interface
The MG2040 ESD protection diode is designed specifically to
protect HDMI and Display Port with full functionality ESD protection
and back drive current protection for VCC line. Ultralow capacitance
and low ESD clamping voltage make this device an ideal solution for
protecting voltage sensitive high speed data lines. The flowthrough
style package allows for easy PCB layout and matched trace lengths
necessary to maintain consistent impedance for the high speed TMDS
lines.
Features
Full Function HDMI / Display Port Solution
Single Connect, Flow through Routing for TMDS Lines
Low Capacitance (0.35 pF Typical, I/O to GND)
Protection for the Following IEC Standards:
IEC 6100042 Level 4 (±8 kV Contact)
UL Flammability Rating of 94 V0
SZ Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AECQ101 Qualified and
PPAP Capable
This is a PbFree Device
Typical Applications
HDMI
Display Port
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating Symbol Value Unit
Operating Junction Temperature Range TJ55 to +125 °C
Storage Temperature Range Tstg 55 to +150 °C
Lead Solder Temperature
Maximum (10 Seconds)
TL260 °C
IEC 6100042 Contact (ESD)
IEC 6100042 Air (ESD)
ESD
ESD
±15
±15
kV
kV
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
See Application Note AND8308/D for further description of
survivability specs.
MARKING
DIAGRAM
Device Package Shipping
ORDERING INFORMATION
UDFN18
CASE 517CP
www.onsemi.com
MG2040MUTAG UDFN18
(PbFree)
3000 / Tape &
Reel
For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
(Note: Microdot may be in either location)
2040MG
G
2040 = Specific Device Code
M = Date Code
G= PbFree Package
1
18
SZMG2040MUTAG UDFN18
(PbFree)
3000 / Tape &
Reel
DDDDDDD 33333333333
MG2040, SZMG2040
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2
1
2
3
4
5
6
7
8
9
10
11
18
17
16
15
14
13
12
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
GND
GND
GND
GND
GND
GND
Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 Pin 9 Pin 10 Pin 11 Pin 13 Pin 15 Pin 17
Center Pins, Pin 12, 14, 16, 18
Note: Common GND – Only Minimum of 1 GND connection required
Figure 1. Pin Schematic
Figure 2. Pin Configuration
=
Note: Pins 12, 14, 16, 18 and center pins are connected internally as a common ground.
Only minimum of one pin needs to be connected to ground for functionality of all pins.
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ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified)
Parameter Symbol Conditions Min Typ Max Unit
Reverse Working Voltage VRWM I/O Pin to GND (Note 1) 5.0 V
Breakdown Voltage VBR IT = 1 mA, I/O Pin to GND 5.5 V
Reverse Leakage Current IRVRWM = 5 V, I/O Pin to GND 1.0 mA
Clamping Voltage (Note 1) VCIPP = 1 A, I/O Pin to GND (8 x 20 ms pulse) 10 V
Clamping Voltage (Note 2) VCIEC6100042, ±8 kV Contact See Figures 3 and 4 V
Clamping Voltage
TLP (Note 3)
See Figures 8 through 11
VCIPP = 8 A
IPP = 16 A
IPP = 8 A
IPP = 16 A
11.4
15.3
4.6
8.1
Junction Capacitance CJVR = 0 V, f = 1 MHz between I/O Pins 0.15 0.20 pF
VR = 0 V, f = 1 MHz between I/O Pins and GND 0.35 0.42
Junction Capacitance
Difference
DCJVR = 0 V, f = 1 MHz between I/O Pins 0.02 pF
VR = 0 V, f = 1 MHz between I/O Pins and GND 0.04
1. Surge current waveform per Figure 7.
2. For test procedure see Figures 5 and 6 and application note AND8307/D.
3. ANSI/ESD STM5.5.1 Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns.
Figure 3. IEC6100042 +8 KV Contact
Clamping Voltage
Figure 4. IEC6100042 8 KV Contact
Clamping Voltage
TIME (ns) TIME (ns)
VOLTAGE (V)
VOLTAGE (V)
10
0
10
20
30
40
50
60
70
80
90
20 0 20 40 60 80 100 120 140
50
40
30
20
10
0
20 0 20 40 60 80 100 120 140
Tes EIEIEIEI |:I|:||:I|:| EIEIEI El E El 3 30 a O El 0 O
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IEC 6100042 Spec.
Level
Test Volt-
age (kV)
First Peak
Current
(A)
Current at
30 ns (A)
Current at
60 ns (A)
1 2 7.5 4 2
2 4 15 8 4
3 6 22.5 12 6
4 8 30 16 8
Ipeak
90%
10%
IEC6100042 Waveform
100%
I @ 30 ns
I @ 60 ns
tP = 0.7 ns to 1 ns
Figure 5. IEC6100042 Spec
Figure 6. Diagram of ESD Clamping Voltage Test Setup
50 W
Cable
Device
Under
Test Oscilloscope
ESD Gun
50 W
The following is taken from Application Note
AND8308/D Interpretation of Datasheet Parameters
for ESD Devices.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC6100042 waveform. Since the
IEC6100042 was written as a pass/fail spec for larger
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
Figure 7. 8 x 20 ms Pulse Waveform
100
90
80
70
60
50
40
30
20
10
0020406080
t, TIME (ms)
% OF PEAK PULSE CURRENT
tP
tr
PULSE WIDTH (tP) IS DEFINED
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms
PEAK VALUE IRSM @ 8 ms
HALF VALUE IRSM/2 @ 20 ms
from e 101) ns long ree . ngular pulse from e charged ion line. A simplified schematic of a (ypicul TLP system is shown in Figure llle TLP l—V curves of ESD pmleciion devices accurately demunslmie lhe pruduci's ESD capabilily because Ihe llls of amps cllnem levels and under 100 ns lime scale mulch ihose (If an ESD eveni. This is illllsiraled in Figure 11 where an 8 kV [EC ()ll)l)l)—4—Z current waveform is compared wilh TLP current puls at 8 A and 16A. A TLP I—V curve shows ihe voltage at which the device mms on as well as how well lhe device clumps voltage over a range of currem levels. 35 30 25 20 15 Current(A) 10 720 0 20 40 l Figure 10. Simp 7‘ IECS kV —TLP 8A —TLP 16A 60 80 100 1 20 Time (n5) www.cnsemi.com 5 l”—
MG2040, SZMG2040
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5
Figure 8. Positive TLP IV Curve Figure 9. Negative TLP IV Curve
CURRENT (A)
VOLTAGE (V)
CURRENT (A)
VOLTAGE (V)
0
2
4
6
8
10
12
14
16
18
20
22
0 2 4 6 8 10 12 14 16 18
22
20
18
16
14
12
10
8
6
4
2
0181614121086420
Transmission Line Pulse (TLP) Measurement
Transmission Line Pulse (TLP) provides current versus
voltage (IV) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 10. TLP IV curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 11 where an 8 kV IEC 6100042
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP IV curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels.
Figure 10. Simplified Schematic of a Typical TLP
System
DUT
LS
÷
Oscilloscope
Attenuator
10 MW
VC
VM
IM
50 W Coax
Cable
50 W Coax
Cable
Figure 11. Comparison Between 8 kV IEC 6100042 and 8 A and 16 A TLP Waveforms
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With MG2040Without ESD
Figure 12. HDMI1.4 Eye Diagram with and without MG2040. 3.4 Gb/s, 400 mVPP
Figure 13. MG2040 Insertion Loss
10
8
6
4
2
0
2
4
1.E+06 1.E+07 1.E+08 1.E+09 1.E+10
FREQUENCY (Hz)
S21 INSERTION LOSS (dB)
MG2040
IOGND
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MG2040, SZMG2040
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7
Figure 14. HDMI Layout Diagram
5V
D2+
HPD (and HEC_DAT – HDMI1.4)
GND
SDA
D1+
D1
GND
MG2040
HDMI TypeA
Connector
Black = Top layer
Red = other layer
GND
CEC
GND
N/C (or HEC_DAT – HDMI1.4)
CLK+
CLK
GND
D0+
D2
SCL
D0
SIDE VIEW I: BOTTOM VIEW :w‘ [e \‘ n J {3+ DETAILC '1 m n n '1 €39 + O O
MG2040, SZMG2040
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8
PACKAGE DIMENSIONS
UDFN18, 5.5 x 1.5, 0.5P/0.75P
CASE 517CP
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.10 AND 0.20 MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. EXPOSED ENDS OF TERMINALS ARE
ELECTRICALLY ACTIVE.
DIM MIN MAX
MILLIMETERS
A0.45 0.55
A1 0.00 0.05
A3 0.13 REF
b0.15 0.25
D5.50 BSC
D2 0.35 0.45
E1.50 BSC
eA 0.50 BSC
L0.20 0.40
0.10 C
D
E
B
A
2X
2X
NOTE 4
A
A1
(A3)
0.10 C
PIN ONE
REFERENCE
0.10 C
0.05 C
CSEATING
PLANE
BOTTOM VIEW
b
eB
18X
0.10 B
0.05
AC
C
L
SIDE VIEW
TOP VIEW
NOTE 3
111
1218
3X
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
DETAIL C
DIMENSION: MILLIMETERS
RECOMMENDED
DETAIL A
OPTIONAL
CONSTRUCTION
DETAIL B
MOLD CMPDEXPOSED Cu
OPTIONAL
CONSTRUCTION
DETAIL B
0.50
1.80
0.50
0.50
PITCH
eB 0.75 BSC
3X
0.30
17X
E2 0.35 0.45
eA
M
M
D2
E2 NOTE 5
END VIEW
0.75
PITCH 18X
0.50
D3
DETAIL C
D3
D3
DETAIL A
0.13
6X
0.13
6X
NOTE: CENTER PADS OPTIONAL
1
1.50
PITCH
eC
eC 1.50 BSC
LL2
L2 0.10 REF
0.45
0.10 REF
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