HEF4517B Datasheet by NXP USA Inc.

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1. General description
The HEF4517B consists of two identical, independent 64-bit static shift registers. Each
register has separate clock (nCP), data input (nD), parallel input-enable/output-enable
(nPE/OE) and four 3-state outputs of the 16th, 32nd, 48th, and 64th bit positions (nQ16 to
nQ64). Data at the nD input is entered into the first bit on the LOW-to-HIGH transition of
the clock, regardless of the state of nPE/OE.
When nPE/OE is LOW, the outputs are enabled and it is in the 64-bit serial mode.
When nPE/OE is HIGH, the outputs are disabled (high-impedance OFF-state), the 64-bit
shift register is divided into four 16-bit shift registers with nD, nQ16, nQ32 and nQ48 as
data inputs of the 1st, 17th, 33rd, and 49th bit respectively. Schmitt-trigger action in the
clock input makes the circuit highly tolerant of slower clock rise and fall times.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
2. Features and benefits
Tolerant of slow clock rise and fall times
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from 40 C to +85 C
Complies with JEDEC standard JESD 13-B
3. Ordering information
HEF4517B
Dual 64-bit static shift register
Rev. 7 — 11 November 2011 Product data sheet
Table 1. Ordering information
All types operate from
40
C to +85
C
Type number Package
Name Description Version
HEF4517BP DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
HEF4517BT SO16 plastic small outline package; 16 leads; body width 7.5 mm SOT162-1
11111
HEF4517B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 11 November 2011 2 of 16
NXP Semiconductors HEF4517B
Dual 64-bit static shift register
4. Functional diagram
Fig 1. Functional diagram
001aae694
64-BIT STATIC SHIFT REGISTER
1Q64
1Q48
1Q32
1Q16
1D
7
2
5
6
1
4
3
1CP
INPUT/3-STATE-OUTPUT CIRCUITRY
1PE/OE
64-BIT STATIC SHIFT REGISTER
2Q64
2Q48
2Q32
2Q16
2D
9
14
11
10
15
12
13
2CP
INPUT/3-STATE-OUTPUT CIRCUITRY
2PE/OE
F F F F F F F EMFMF mmflw y Hy?» F F F F F F F FFEMF mmflfi % r; J Hy»:
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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
HEF4517B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 11 November 2011 3 of 16
NXP Semiconductors HEF4517B
Dual 64-bit static shift register
Fig 2. Logic diagram
1D
1CP
1PE/OE
D
CP
O
FF 1 FF 16 FF 17 FF 32 FF 33 FF 48 FF 49 FF 64
D
CP
O
D
CP
O D
CP
O
1Q16
D
CP
O D
CP
O
1Q32
D
CP
O D
CP
O
1Q48 1Q64
2Q16 2Q32 2Q48 2Q64
2D
2CP
2PE/OE
001aae696
D
CP
O
FF 1 FF 16 FF 17 FF 32 FF 33 FF 48 FF 49 FF 64
D
CP
O
D
CP
O D
CP
OD
CP
O D
CP
OD
CP
O D
CP
O
7 33333333 EEEEEEEE 7
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Product data sheet Rev. 7 — 11 November 2011 4 of 16
NXP Semiconductors HEF4517B
Dual 64-bit static shift register
5. Pinning information
5.1 Pinning
5.2 Pin description
Fig 3. Pin configuration
HEF4517B
1Q16 VDD
1Q48 2Q16
1PE/OE 2Q48
1CP 2PE/OE
1Q64 2CP
1Q32 2Q64
1D 2Q32
VSS 2D
001aae695
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
Table 2. Pin description
Symbol Pin Description
1Q16, 2Q16 1, 15 3-state input/output
1Q48, 2Q48 2, 14 3-state input/output
1PE/OE, 2PE/OE 3, 13 parallel input-enable/output-enable input
1CP, 2CP 4, 12 clock input
1Q64, 2Q64 5, 11 3-state input/output
1Q32, 2Q32 6, 10 3-state input/output
1D, 2D 7, 9 data input
VSS 8 ground supply voltage
VDD 16 supply voltage
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Product data sheet Rev. 7 — 11 November 2011 5 of 16
NXP Semiconductors HEF4517B
Dual 64-bit static shift register
6. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance state;
= positive-going transition; = negative-going transition.
7. Limiting values
[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C.
[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
Table 3. Function table[1]
Inputs Inputs/outputs Mode
nCP nD nPE/OE nQ16 nQ32 nQ48 nQ64
data entered
into 1st bit L content of
16th bit
displayed
content of
32nd bit
displayed
content of
48th bit
displayed
content of
64th bit
displayed
One 64-bit shift register. The
content of the shift register is
shifted over one stage
data entered
into 1st bit H data at nQ16
entered into
17th bit
data at nQ32
entered into
33rd bit
data at nQ48
entered into
49th bit
remains in ‘Z’
state Four 16-bit shift register. The
content of the shift registers is
shifted over one stage
X L no change no change no change no change no change
XHZZZZno change
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDD supply voltage 0.5 +18 V
IIK input clamping current VI<0.5 V or VI>V
DD + 0.5 V - 10 mA
VIinput voltage 0.5 VDD + 0.5 V
IOK output clamping current VO<0.5 V or VO>V
DD + 0.5 V - 10 mA
II/O input/output current - 10 mA
IDD supply current - 50 mA
Tstg storage temperature 65 +150 C
Tamb ambient temperature 40 +85 C
Ptot total power dissipation DIP16 package [1] -750mW
SO16 package [2] -500mW
P power dissipation per output - 100 mW
HEF4517B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 11 November 2011 6 of 16
NXP Semiconductors HEF4517B
Dual 64-bit static shift register
8. Recommended operating conditions
9. Static characteristics
Table 5. Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
VDD supply voltage 3 - 15 V
VIinput voltage 0 - VDD V
Tamb ambient temperature in free air 40 - +85 C
t/V input transition rise and fall rate VDD = 5 V - - 3.75 s/V
VDD = 10 V - - 0.5 s/V
VDD = 15 V - - 0.08 s/V
Table 6. Static characteristics
VSS = 0 V; VI = VSS or VDD unless otherwise specified.
Symbol Parameter Conditions VDD Tamb = 40 C Tamb = 25 C Tamb = 85 CUnit
Min Max Min Max Min Max
VIH HIGH-level input voltage IO < 1 A 5 V 3.5-3.5-3.5-V
10 V 7.0-7.0-7.0-V
15 V 11.0 - 11.0 - 11.0 - V
VIL LOW-level input voltage IO < 1 A 5 V -1.5-1.5-1.5V
10 V - 3.0 - 3.0 - 3.0 V
15 V - 4.0 - 4.0 - 4.0 V
VOH HIGH-level output voltage IO < 1 A 5 V 4.95 - 4.95 - 4.95 - V
10 V 9.95 - 9.95 - 9.95 - V
15 V 14.95 - 14.95 - 14.95 - V
VOL LOW-level output voltage IO < 1 A 5 V - 0.05 - 0.05 - 0.05 V
10 V - 0.05 - 0.05 - 0.05 V
15 V - 0.05 - 0.05 - 0.05 V
IOH HIGH-level output current VO = 2.5 V 5 V - 1.7 - 1.4 - 1.1 mA
VO = 4.6 V 5 V - 0.52 - 0.44 - 0.36 mA
VO = 9.5 V 10 V - 1.3 - 1.1 - 0.9 mA
VO = 13.5 V 15 V - 3.6 - 3.0 - 2.4 mA
IOL LOW-level output current VO = 0.4 V 5 V 0.52 - 0.44 - 0.36 - mA
VO = 0.5 V 10 V 1.3 - 1.1 - 0.9 - mA
VO = 1.5 V 15 V 3.6 - 3.0 - 2.4 - mA
IIinput leakage current 15 V - 0.3 - 0.3 - 1.0 A
IDD supply current IO = 0 A 5 V - 50 - 50 - 375 A
10 V - 100 - 100 - 750 A
15 V - 200 - 200 - 1500 A
CIinput capacitance - - - - 7.5 - - pF
see Figure 8 Figure 4 Figure 4 Figure 5 Figure 5 Figure 5 Figure 5 Figure 6 Figure 7 Figure 7 Figure 7 Figure 7
HEF4517B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 11 November 2011 7 of 16
NXP Semiconductors HEF4517B
Dual 64-bit static shift register
10. Dynamic characteristics
[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).
Table 7. Dynamic characteristics
VSS = 0 V; Tamb = 25
C; for test circuit see Figure 8; unless otherwise specified.
Symbol Parameter Conditions VDD Extrapolation formula Min Typ Max Unit
tPHL HIGH to LOW
propagation delay nCP to nQn;
see Figure 4 5 V [1] 193 ns + (0.55 ns/pF)CL- 220 440 ns
10 V 74 ns + (0.23 ns/pF)CL-85170ns
15 V 52 ns + (0.16 ns/pF)CL-60120ns
tPLH LOW to HIGH
propagation delay nCP to nQn;
see Figure 4 5 V [1] 163 ns + (0.55 ns/pF)CL- 190 380 ns
10 V 64 ns + (0.23 ns/pF)CL-75150ns
15 V 42 ns + (0.16 ns/pF)CL-50100ns
tPHZ HIGH to OFF-state
propagation delay nPE/OE to nQn;
see Figure 5 5 V - 40 80 ns
10 V - 30 60 ns
15 V - 25 50 ns
tPZH OFF-state to HIGH
propagation delay nPE/OE to nQn;
see Figure 5 5 V - 45 90 ns
10 V - 25 50 ns
15 V - 20 40 ns
tPLZ LOW to OFF-state
propagation delay nPE/OE to nQn;
see Figure 5 5 V - 50 100 ns
10 V - 30 60 ns
15 V - 25 50 ns
tPZL OFF-state to LOW
propagation delay nPE/OE to nQn;
see Figure 5 5 V - 60 120 ns
10 V - 30 60 ns
15 V - 25 50 ns
tttransition time nQn;
see Figure 6 5 V [1] 10 ns + (1.00 ns/pF)CL-60120ns
10 V 9 ns + (0.42 ns/pF)CL-3060ns
15 V 6 ns + (0.28 ns/pF)CL-2040ns
tsu set-up time nQn, nD to nCP;
see Figure 7 5 V 30 10 - ns
10 V 25 5 - ns
15 V 20 5 - ns
thhold time nQn, nD to nCP;
see Figure 7 5 V 45 15 - ns
10 V 30 10 - ns
15 V 25 10 - ns
tWpulse width nQn, nD to nCP;
see Figure 7 5 V - 95 190 ns
10 V - 40 80 ns
15 V - 30 60 ns
fmax maximum
frequency see Figure 7 5 V 25- MHz
10 V 6 12 - MHz
15 V 8 16 - MHz
%
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Product data sheet Rev. 7 — 11 November 2011 8 of 16
NXP Semiconductors HEF4517B
Dual 64-bit static shift register
11. Waveforms
Table 8. Dynamic power dissipation PD
PD can be calculated from the formulas shown. VSS = 0 V; tr = tf
20 ns; Tamb = 25
C.
Symbol Parameter VDD Typical formula for PD (W) where:
PDdynamic power
dissipation 5 V PD = 7000 fi + (fo CL) VDD2fi = input frequency in MHz,
fo = output frequency in MHz,
CL = output load capacitance in pF,
VDD = supply voltage in V,
(fo CL) = sum of the outputs.
10 V PD = 28000 fi + (fo CL) VDD2
15 V PD = 70000 fi + (fo CL) VDD2
Measurement points are given in Table 9
The logic levels VOH and VOL are typical voltage output levels that occur with the output load.
Fig 4. Propagation delays for nCP to nQn
Table 9. Measurement points
Input Output
VMVMVXVY
0.5VI0.5VDD 0.1VDD 0.9VDD
1% fl JV V a 3 L , M a TA , g % :wj
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Product data sheet Rev. 7 — 11 November 2011 9 of 16
NXP Semiconductors HEF4517B
Dual 64-bit static shift register
Measurement points are given in Table 9
The logic levels VOH and VOL are typical voltage output levels that occur with the output load.
Fig 5. Enable and disable times and 3-state propagation delays
001aaj913
tPLZ
tPHZ
outputs
disabled
outputs
enabled
VY
VX
outputs
enabled
nQn output
LOW-to-OFF
OFF-to-LOW
nQn output
HIGH-to-OFF
OFF-to-HIGH
nPE/OE input
VI
VDD
VM
VOL
VOH
0 V
GND
tPZL
tPZH
VM
VM
The logic levels VOH and VOL are typical voltage output levels that occur with the output load.
Fig 6. Transition times for nQn
001aaj916
90 %
10 %
VOH
tttt
VOL
nQn output
The shading indicates where the data (nQn and nD) is permitted to change for predictable output changes.
Measurement points are given in Table 9
The logic levels VOH and VOL are typical voltage output levels that occur with the output load.
Fig 7. Waveforms showing minimum clock pulse width and maximum frequency and set-up and hold times for
nQn (as data input) or nD to nCP
001aae697
tsu
1/fmax
th
nCP input
VI
0 V
VI
0 V
nQn, nD input
VM
VM
tW
ifliifs
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Product data sheet Rev. 7 — 11 November 2011 10 of 16
NXP Semiconductors HEF4517B
Dual 64-bit static shift register
a. Input waveforms
b. Test circuit
Test data is given in Table 10.
Definitions for test circuit:
DUT = Device Under Test;
RL = Load resistance;
CL = Load capacitance including jig and probe capacitance;
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
Fig 8. Test circuit for switching times
V
M
V
M
t
W
t
W
10 %
90 %
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
90 %
10 %
t
f
t
r
t
r
t
f
001aaj781
001aaj915
VEXT
VDD
VIVO
DUT
CL
RT
RL
G
Table 10. Test data
Supply
voltage Input Load VEXT
VItr, tfCLRLtPLH, tPHL tPLZ, tPZL tPHZ, tPZH
5Vto15V V
DD 20 ns 50 pF 1 kopen 2VDD GND
VWV mmflfihfififl LARAUHA‘LLJULLAU E©W
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Product data sheet Rev. 7 — 11 November 2011 11 of 16
NXP Semiconductors HEF4517B
Dual 64-bit static shift register
12. Package outline
Fig 9. Package outline SOT38-4 (DIP16)
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT38-4 95-01-14
03-02-13
MH
c
(e )
1
ME
A
L
seating plane
A1
wM
b1
b2
e
D
A2
Z
16
1
9
8
E
pin 1 index
b
0 5 10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
UNIT A
max. 12 b1(1) (1) (1)
b2cD E e M Z
H
L
mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
min. A
max. bmax.
w
ME
e1
1.73
1.30 0.53
0.38 0.36
0.23 19.50
18.55 6.48
6.20 3.60
3.05 0.2542.54 7.62 8.25
7.80 10.0
8.3 0.764.2 0.51 3.2
inches 0.068
0.051 0.021
0.015 0.014
0.009
1.25
0.85
0.049
0.033 0.77
0.73 0.26
0.24 0.14
0.12 0.010.1 0.3 0.32
0.31 0.39
0.33 0.030.17 0.02 0.13
DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4
Er©
HEF4517B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 11 November 2011 12 of 16
NXP Semiconductors HEF4517B
Dual 64-bit static shift register
Fig 10. Package outline SOT162-1 (SO16)
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZ
ywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
2.65 0.3
0.1 2.45
2.25 0.49
0.36 0.32
0.23 10.5
10.1 7.6
7.4 1.27 10.65
10.00 1.1
1.0 0.9
0.4 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.1
0.4
SOT162-1
8
16
wM
bp
D
detail X
Z
e
9
1
y
0.25
075E03 MS-013
pin 1 index
0.1 0.012
0.004 0.096
0.089 0.019
0.014 0.013
0.009 0.41
0.40 0.30
0.29 0.05
1.4
0.055
0.419
0.394 0.043
0.039 0.035
0.016
0.01
0.25
0.01 0.004
0.043
0.016
0.01
X
θ
A
A1
A2
HE
Lp
Q
E
c
L
vMA
(A )
3
A
0 5 10 mm
scale
SO16: plastic small outline package; 16 leads; body width 7.5 mm SOT162-1
99-12-27
03-02-19
Table 6 Figure 8
HEF4517B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 11 November 2011 13 of 16
NXP Semiconductors HEF4517B
Dual 64-bit static shift register
13. Revision history
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
HEF4517B v.7 20111111 Product data sheet - HEF4517B v.6
Modifications: Section Applications removed
Table 6: IOH minimum values changed to maximum
Figure 8: added “DUT = Device Under Test”
HEF4517B v.6 20091210 Product data sheet - HEF4517B v.5
HEF4517B v.5 20090728 Product data sheet - HEF4517B v.4
HEF4517B v.4 20090406 Product data sheet - HEF4517B_CNV v.3
HEF4517B_CNV v.3 19950101 Product specification - HEF4517B_CNV v.2
HEF4517B_CNV v.2 19950101 Product specification - -
HEF4517B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 11 November 2011 14 of 16
NXP Semiconductors HEF4517B
Dual 64-bit static shift register
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[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
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Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
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Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
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HEF4517B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 11 November 2011 15 of 16
NXP Semiconductors HEF4517B
Dual 64-bit static shift register
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
14.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
15. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors HEF4517B
Dual 64-bit static shift register
© NXP B.V. 2011. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 11 November 2011
Document identifier: HEF4517B
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
16. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6 Functional description . . . . . . . . . . . . . . . . . . . 5
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
8 Recommended operating conditions. . . . . . . . 6
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11
13 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 13
14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14
14.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14
14.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
14.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
14.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
15 Contact information. . . . . . . . . . . . . . . . . . . . . 15
16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

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