40MX,42MX FPGA Family Datasheet

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Q Microsemi Power Matters."
DS2316
Datasheet
40MX and 42MX FPGA
C Microsemi Power Matters:
5172136. 16.0 8/17
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Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of
its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the
application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have
been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any
performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all
performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not
rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer's responsibility to
independently determine suitability of any products and to test and verify the same. The information provided by Microsemi
hereunder is provided “as is, where is” and with all faults, and the entire risk associated with such information is entirely
with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP
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document or to any products and services at any time without notice.
About Microsemi
Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor and system solutions for
aerospace & defense, communications, data center and industrial markets. Products include high-performance and
radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products;
timing and synchronization devices and precise time solutions, setting the world's standard for time; voice processing
devices; RF solutions; discrete components; enterprise storage and communication solutions, security technologies and
scalable anti-tamper products; Ethernet solutions; Power-over-Ethernet ICs and midspans; as well as custom design
capabilities and services. Microsemi is headquartered in Aliso Viejo, California, and has approximately 4,800 employees
globally. Learn more at www.microsemi.com.
0 Microsemi Power Matters.-
DS2316 Datasheet Revision 16.0 iii
Contents
1 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Revision 16.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Revision 15.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 Revision 14.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.4 Revision 13.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.5 Revision 12.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.6 Revision 11.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.7 Revision 10.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.8 Revision 9.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.9 Revision 6.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 40MX and 42MX FPGA Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1.1 High Capacity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1.2 High Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1.3 HiRel Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1.4 Ease of Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2 Product Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.3 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.4 Plastic Device Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.5 Ceramic Device Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.6 Temperature Grade Offerings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.7 Speed Grade Offerings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 40MX and 42MX FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 MX Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2.1 Logic Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2.2 Dual-Port SRAM Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2.3 Routing Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2.4 Clock Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2.5 MultiPlex I/O Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3.1 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3.2 User Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3.3 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3.4 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3.5 Power-Up/Down in Mixed-Voltage Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3.6 Transient Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3.7 Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4.1 General Power Equation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4.2 Static Power Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4.3 Active Power Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4.4 Equivalent Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4.5 CEQ Values for Microsemi MX FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4.6 Test Circuitry and Silicon Explorer II Probe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.4.7 Design Consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4.8 IEEE Standard 1149.1 Boundary Scan Test (BST) Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4.9 JTAG Mode Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
O Microsemi Power Maners:
DS2316 Datasheet Revision 16.0 iv
3.4.10 TRST Pin and TAP Controller Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.4.11 Boundary Scan Description Language (BSDL) File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.5 Development Tool Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.6 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.6.1 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.6.2 User Guides and Manuals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.6.3 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.7 5.0 V Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.7.1 5 V TTL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.8 3.3 V Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.8.1 3.3 V LVTTL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.9 Mixed 5.0 V / 3.3 V Operating Conditions (for 42MX Devices Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.9.1 Mixed 5.0V/3.3V Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.9.2 Output Drive Characteristics for 5.0 V PCI Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.9.3 Output Drive Characteristics for 3.3 V PCI Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.9.4 Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.9.5 Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.10 Timing Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.10.1 Parameter Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.10.2 Sequential Module Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.10.3 Sequential Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.10.4 Decode Module Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.10.5 SRAM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.10.6 Dual-Port SRAM Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.10.7 Predictable Performance: Tight Delay Distributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.11 Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.11.1 Critical Nets and Typical Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.11.2 Long Tracks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.11.3 Timing Derating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.11.4 Temperature and Voltage Derating Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.11.5 PCI System Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.11.6 PCI Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.12 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
4 Package Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
0 Microsemi Power Matters.-
DS2316 Datasheet Revision 15.0 v
Tables
Table 1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Table 2 Plastic Device Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3 Ceramic Device Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 4 Temperature Grade Offerings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 5 Speed Grade Offerings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 6 Voltage Support of MX Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 7 Fixed Capacitance Values for MX FPGAs (pF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 8 Device Configuration Options for Probe Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 9 Test Access Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 10 Supported BST Public Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 11 Boundary Scan Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 12 Absolute Maximum Ratings for 40MX Devices* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 13 Absolute Maximum Ratings for 42MX Devices* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 14 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 15 5V TTL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 16 Absolute Maximum Ratings for 40MX Devices* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 17 Absolute Maximum Ratings for 42MX Devices* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 18 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 19 3.3V LVTTL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 20 Absolute Maximum Ratings* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 21 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 22 Mixed 5.0V/3.3V Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 23 DC Specification (5.0 V PCI Signaling) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 24 AC Specifications (5.0V PCI Signaling)* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 25 DC Specification (3.3 V PCI Signaling) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 26 AC Specifications for (3.3 V PCI Signaling)* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 27 Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 28 42MX Temperature and Voltage Derating Factors (Normalized to TJ = 25°C, VCCA = 5.0 V) . . . 40
Table 29 40MX Temperature and Voltage Derating Factors(Normalized to TJ = 25°C, VCC = 5.0 V) . . . . . 41
Table 30 42MX Temperature and Voltage Derating Factors(Normalized to TJ = 25°C, VCCA = 3.3 V) . . . . 41
Table 31 40MX Temperature and Voltage Derating Factors (Normalized to TJ = 25°C, VCC = 3.3 V) . . . . 42
Table 32 Clock Specification for 33 MHz PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 33 Timing Parameters for 33 MHz PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 34 A40MX02 Timing Characteristics (Nominal 5.0 V Operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 35 A40MX02 Timing Characteristics (Nominal 3.3 V Operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 36 A40MX04 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C) . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 37 A40MX04 Timing Characteristics (Nominal 3.3 V Operation)
(Worst-Case Commercial Conditions, VCC = 3.0 V, TJ = 70°C) . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 38 A42MX09 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70°C) . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 39 A42MX09 Timing Characteristics (Nominal 3.3 V Operation)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, TJ = 70°C) . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 40 A42MX16 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70°C) . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 41 A42MX16 Timing Characteristics (Nominal 3.3 V Operation)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, TJ = 70°C) . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 42 A42MX24 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70°C) . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 43 A42MX24 Timing Characteristics (Nominal 3.3 V Operation)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, TJ = 70°C) . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 44 A42MX36 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70°C) . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 45 A42MX36 Timing Characteristics (Nominal 3.3 V Operation)
O Microsemi Power Maners:
DS2316 Datasheet Revision 15.0 vi
(Worst-Case Commercial Conditions, VCCA = 3.0 V, TJ = 70°C) . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 46 Configuration of Unused I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 47 PL44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 48 PL68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 49 PL84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 50 PQ 100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 51 PQ144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 52 PQ160 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 53 PQ208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 54 PQ240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table 55 VQ80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 56 VQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 57 TQ176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 58 CQ208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Table 59 CQ256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 60 BG272 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 61 PG132 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 62 CQ172 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
0 Microsemi Power Matters.-
DS2316 Datasheet Revision 16.0 vii
Figures
Figure 1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2 42MX C-Module Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 3 42MX C-Module Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4 42MX S-Module Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5 A42MX24 and A42MX36 D-Module Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6 A42MX36 Dual-Port SRAM Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 7 MX Routing Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 8 Clock Networks of 42MX Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 9 Quadrant Clock Network of A42MX36 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 10 42MX I/O Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 11 PCI Output Structure of A42MX24 and A42MX36 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 12 Silicon Explorer II Setup with 40MX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 13 Silicon Explorer II Setup with 42MX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 14 42MX IEEE 1149.1 Boundary Scan Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 15 Device Selection Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 16 Typical Output Drive Characteristics (Based Upon Measured Data) . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 17 40MX Timing Model* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 18 42MX Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 19 42MX Timing Model (Logic Functions Using Quadrant Clocks) . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 20 42MX Timing Model (SRAM Functions) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 21 Output Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 22 AC Test Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 23 Input Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 24 Module Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 25 Flip-Flops and Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 26 Input Buffer Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 27 Output Buffer Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 28 Decode Module Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 29 SRAM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 30 42MX SRAM Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 31 42MX SRAM Synchronous Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 32 42MX SRAM Asynchronous Read Operation—Type 1 (Read Address Controlled) . . . . . . . . . . . . 38
Figure 33 42MX SRAM Asynchronous Read Operation—Type 2 (Write Address Controlled) . . . . . . . . . . . . 39
Figure 34 42MX Junction Temperature and Voltage Derating Curves
(Normalized to TJ = 25°C, VCCA = 5.0 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 35 40MX Junction Temperature and Voltage Derating Curves
(Normalized to TJ = 25°C, VCC = 5.0 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 36 42MX Junction Temperature and Voltage Derating Curves
(Normalized to TJ = 25°C, VCCA = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 37 40MX Junction Temperature and Voltage Derating Curves
(Normalized to TJ = 25°C, VCC = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 38 PL44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 39 PL68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 40 PL84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 41 PQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 42 PQ144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 43 PQ160 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 44 PQ208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 45 PQ240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 46 VQ80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 47 VQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 48 TQ176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 49 CQ208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Figure 50 CQ256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
O Microsemi Power Maners:
DS2316 Datasheet Revision 16.0 viii
Figure 51 BG272 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Figure 52 PG132 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Figure 53 CQ172 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
0 Microsemi Power Matters.-
Revision History
DS2316 Datasheet Revision 16.0 1
1 Revision History
The revision history describes the changes that were implemented in the document. The changes are
listed by revision, starting with the most current publication.
1.1 Revision 16.0
Table 4, page 7 is edited in this revision to add the temperature grade, “I” for the column A42MX09 and
row PQFP144
1.2 Revision 15.0
The following is a summary of the changes in revision 15.0 (Published in December 2016) of this
document.
Table 15, page 23 is edited to add the footnote, VIH(Min) is 2.4V for A42MX36 family. This applies
only to VCCI of 5V and is not applicable to VCCI of 3.3V
Table 22, page 27 is edited to add the footnote, VIH(Min) is 2.4V for A42MX36 family. This applies
only to VCCI of 5V and is not applicable to VCCI of 3.3V
Table 23, page 27 is edited to add the footnote, VIH(Min) is 2.4V for A42MX36 family. This applies
only to VCCI of 5V and is not applicable to VCCI of 3.3V
1.3 Revision 14.0
The following is a summary of the changes in revision 14.0 of this document.
Added CQFP package information for A42MX16 device in Product Profile, page 3 and Ceramic
Device Resources, page 6 (SAR 79522).
Added Military (M) and MIL-STD-883 Class B (B) grades for CPGA 132 Package and added
Commercial (C), Military (M), and MIL-STD-883 Class B (B) grades for CQFP 172 Package in
Temperature Grade Offerings, page 7 (SAR 79519)
Changed Silicon Sculptor II to Silicon Sculptor in Programming, page 15 (SAR 38754)
Added Figure 53, page 160 CQ172 package (SAR 79522).
1.4 Revision 13.0
The following is a summary of the changes in revision 13.0 of this document.
Added Figure 42, page 99 PQ144 Package for A42MX09 device (SAR 69776)
Added Figure 52, page 155 PQ132 Package for A42MX09 device (SAR 69776)
1.5 Revision 12.0
The following is a summary of the changes in revision 12.0 of this document.
Added information on power-up behavior for A42MX24 and A42MX36 devices to the Power Supply,
page 15 (SAR 42096
Corrected the inadvertent mistake in the naming of the PL68 pin assignment table (SARs 48999,
49793)
1.6 Revision 11.0
The following is a summary of the changes in revision 11.0 of this document.
The FuseLock logo and accompanying text was removed from the User Security, page 14. This
marking is no longer used on Microsemi devices (PCN 0915)
•The Development Tool Support, page 21 was updated (SAR 38512)
1.7 Revision 10.0
The following is a summary of the changes in revision 10.0 of this document.
O Microsemi Power Maners:
Revision History
DS2316 Datasheet Revision 16.0 2
Ordering Information, page 5 was updated to include lead-free package ordering codes (SAR
21968)
•The User Security, page 14 was revised to clarify that although no existing security measures can
give an absolute guarantee, Microsemi FPGAs implement the best security available in the industry
(SAR 34673)
•The Transient Current, page 15 is new (SAR 36930).
Package names were revised according to standards established in Package Mechanical Drawings
(SAR 34774)
1.8 Revision 9.0
The following is a summary of the changes in revision 9.0 of this document
•In Table 20, page 25, the limits in VI were changed from -0.5 to VCCI + 0.5 to -0.5 to VCCA + 0.5
In Table 22, page 27, VOH was changed from 3.7 to 2.4 for the min in industrial and military. VIH had VCCI
and that was changed to VCCA
1.9 Revision 6.0
The following is a summary of the changes in revision 6.0 of this document.
•The Ease of Integration, page 3 was updated
•The Temperature Grade Offerings, page 7 is new
•The Speed Grade Offerings, page 7 is new
•The General Description, page 8 was updated
•The MultiPlex I/O Modules, page 13 was updated
•The User Security, page 14 was updated
Table 6, page 15 was updated
•The Power Dissipation, page 16 was updated.
•The Static Power Component, page 16 was updated
•The Equivalent Capacitance, page 17 was updated
Figure 13, page 19 was updated
Table 10, page 20 was updated.
Figure 14, page 20 was updated.
Table 11, page 21 was updated.
G Micmsemi. Power Matters:
40MX and 42MX FPGA Families
DS2316 Datasheet Revision 16.0 3
2 40MX and 42MX FPGA Families
2.1 Features
The following sections list out various features of the 40MX and 42MX FPGA family devices.
2.1.1 High Capacity
Single-Chip ASIC Alternative
3,000 to 54,000 System Gates
Up to 2.5 kbits Configurable Dual-Port SRAM
Fast Wide-Decode Circuitry
Up to 202 User-Programmable I/O Pins
2.1.2 High Performance
5.6 ns Clock-to-Out
250 MHz Performance
5 ns Dual-Port SRAM Access
100 MHz FIFOs
7.5 ns 35-Bit Address Decode
2.1.3 HiRel Features
Commercial, Industrial, Automotive, and Military Temperature Plastic Packages
Commercial, Military Temperature, and MIL-STD-883 Ceramic Packages
QML Certification
Ceramic Devices Available to DSCC SMD
2.1.4 Ease of Integration
Mixed-Voltage Operation (5.0 V or 3.3 V for core and
I/Os), with PCI-Compliant I/Os
Up to 100% Resource Utilization and 100% Pin Locking
Deterministic, User-Controllable Timing
Unique In-System Diagnostic and Verification Capability with Silicon Explorer II
Low Power Consumption
IEEE Standard 1149.1 (JTAG) Boundary Scan Testing
2.2 Product Profile
The following table gives the features of the products.
Table 1 • Product profile
Device A40MX02 A40MX04 A42MX09 A42MX16 A42MX24 A42MX36
Capacity
System Gates
SRAM Bits 3,000 6,000 14,000 24,000 36,000 54,000
2,560
Logic Modules
Sequential
Combinatorial
Decode 295 547 348
336 624
608 954
912
24
1,230
1,184
24
Clock-to-Out 9.5 ns 9.5 ns 5.6 ns 6.1 ns 6.1 ns 6.3 ns
SRAM Modules
(64x4 or 32x8) 10
Dedicated Flip-Flops 348 624 954 1,230
G Micmsemi. Power Matters:
40MX and 42MX FPGA Families
DS2316 Datasheet Revision 16.0 4
Maximum Flip-Flops 147 273 516 928 1,410 1,822
Clocks 112226
User I/O (maximum) 57 69 104 140 176 202
PCI Yes Yes
Boundary Scan Test
(BST) Yes Yes
Packages (by pin
count)
PLCC
PQFP
VQFP
TQFP
CQFP
PBGA
CPGA
44, 68
100
80
44, 68, 84
100
80
84
100, 144,
160
100
176
132
84
100, 160,
208
100
176
172
84
160, 208
176
208, 240
208, 256
272
Table 1 • Product profile (continued)
Device A40MX02 A40MX04 A42MX09 A42MX16 A42MX24 A42MX36
0 Microsemi. eeeeeeeeee .-
40MX and 42MX FPGA Families
DS2316 Datasheet Revision 16.0 5
2.3 Ordering Information
The following figure shows ordering information.All the following tables show plastic and ceramic device
resources, temperature and speed grade offerings.
Figure 1 • Ordering Information
_
Part Number
Speed Grade
Package Type
Package Lead Count
Lead-Free Packaging
Blank = Standard Packaging
G = RoHS Compliant Packaging
Blank = Commercial (0 to +70°C)
Application (Temperature Range)
PL = Plastic Leaded Chip Carrier
CQ =Ceramic Quad Flat Pack
BG = Plastic Ball Grid Array
VQ = Very Thin (1.0 mm) Quad Flat Pack
TQ = Thin (1.4 mm) Quad Flat Pack
PQ = Plastic Quad Flat Pack
Blank = Standard Speed
–1 = Approximately 15% Faster than Standard
–2 = Approximately 25% Faster than Standard
–3 = Approximately 35% Faster than Standard
–F = Approximately 40% Slower than Standard
A40MX02 = 3,000 System Gates
A40MX04 = 6,000 System Gates
A42MX09 = 14,000 System Gates
A42MX16 = 24,000 System Gates
A42MX24 = 36,000 System Gates
A42MX36 = 54,000 System Gates
A42MX16 1PQ 100
GES
I = Industrial (–40 to +85°C)
M = Military (–55 to +125°C)
B = MIL-STD-883
PG =Ceramic Pin Grid Array
A = Automotive (–40 to +125°C)
G Microsemi. Power Matters:
40MX and 42MX FPGA Families
DS2316 Datasheet Revision 16.0 6
2.4 Plastic Device Resources
Note: Package Definitions: PLCC = Plastic Leaded Chip Carrier, PQFP = Plastic Quad Flat Pack,
TQFP = Thin Quad Flat Pack, VQFP = Very Thin Quad Flat Pack, PBGA = Plastic Ball Grid Array
2.5 Ceramic Device Resources
Note: Package Definitions: CQFP = Ceramic Quad Flat Pack
Table 2 • Plastic Device Resources
Device
User I/Os
PLCC
44-Pin PLCC
68-Pin PLCC
84-Pin
PQFP
100-
Pin
PQFP
144-
Pin
PQFP
160-
Pin
PQFP
208-
Pin
PQFP
240-
Pin VQFP
80-Pin
VQFP
100-
Pin
TQFP
176-
Pin
PBGA
272-
Pin
A40MX02 34 57 57 57
A40MX04 34 57 69 69 69
A42MX09 72 83 95 101 83 104
A42MX16 72 83 125 140 83 140
A42MX24 72 125 176 150
A42MX36 176 202 202
Table 3 • Ceramic Device Resources
Device
User I/Os
CPGA 132-Pin CQFP 172-Pin CQFP 208-Pin CQFP 256-Pin
A42MX09 95
A42MX16 131
A42MX36 176 202
G Microsemi. Power Matters:
40MX and 42MX FPGA Families
DS2316 Datasheet Revision 16.0 7
2.6 Temperature Grade Offerings
Note: C = Commercial
I = Industrial
A = Automotive
M = Military
B = MIL-STD-883 Class B
2.7 Speed Grade Offerings
Note: See the 40MX and 42MX Automotive Family FPGAs datasheet for details on automotive-grade MX
offerings.
Contact your local Microsemi Sales representative for device availability.
Table 4 • Temperature Grade Offerings
Package A40MX02 A40MX04 A42MX09 A42MX16 A42MX24 A42MX36
PLCC 44 C, I, M C, I, M
PLCC 68 C, I, A, M C, I, M
PLCC 84 C, I, A, M C, I, A, M C, I, M C, I, M
PQFP 100 C, I, A, M C, I, A, M C, I, A, M C, I, M
PQFP 144 C, I
PQFP 160 C, I, A, M C, I, M C, I, A, M
PQFP 208 C, I, A, M C, I, A, M C, I, A, M
PQFP 240 C, I, A, M
VQFP 80 C, I, A, M C, I, A, M
VQFP 100 C, I, A, M C, I, A, M
TQFP 176 C, I, A, M C, I, A, M C, I, A, M
PBGA 272 C, I, M
CQFP 172 C, M, B
CQFP 208 C, M, B
CQFP 256 C, M, B
CPGA 132 C, M, B
Table 5 • Speed Grade Offerings
– F Std –1 2 –3
CP P P PP
IPPPP
AP
MPP
BPP
0 Microsemi Power Matters.-
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 8
3 40MX and 42MX FPGAs
3.1 General Description
Microsemi's 40MX and 42MX families offer a cost-effective design solution at 5V. The MX devices are
single-chip solutions and provide high performance while shortening the system design and development
cycle. MX devices can integrate and consolidate logic implemented in multiple programmable array
logics (PALs), complex programmable logic devices (CPLDs), and FPGAs. Example applications include
high-speed controllers and address decoding, peripheral bus interfaces, digital signal processor (DSP),
and co-processor functions.
The MX device architecture is based on Microsemi’s patented antifuse technology implemented in a
0.45µm triple-metal CMOS process. With capacities ranging from 3,000 to 54,000 system gates,
the MX devices provide performance up to 250 MHz, are live on power-up and have one-fifth the standby
power consumption of comparable FPGAs. MX FPGAs provide up to 202 user I/Os and are available in a
wide variety of packages and speed grades.
A42MX24 and A42MX36 devices also feature multiPlex I/Os, which support mixed-voltage systems,
enable programmable peripheral component interconnect (PCI), deliver high-performance operation at
both 5.0V and 3.3V, and provide a low-power mode. The devices are fully compliant with the PCI local
bus specification
(version 2.1). They deliver 200 MHz on-chip operation and 6.1 ns clock-to-output performance.
The 42MX24 and 42MX36 devices include system-level features such as
IEEE Standard 1149.1 (JTAG) Boundary Scan Testing and fast wide-decode modules. In addition, the
A42MX36 device offers dual-port SRAM for implementing fast first in first out (FIFOs), last in first out
(LIFOs), and temporary data storage. The storage elements can efficiently address applications requiring
wide data path manipulation and can perform transformation functions such as those required for
telecommunications, networking, and DSP.
All MX devices are fully tested over automotive and military temperature ranges. In addition, the largest
member of the family, the A42MX36, is available in both CQ208 and CQ256 ceramic packages screened
to MIL-STD-883 levels. For easy prototyping and conversion from plastic to ceramic, the CQ208 and
PQ208 devices are pin-compatible.
3.2 MX Architectural Overview
The MX devices are composed of fine-grained building blocks that enable fast, efficient logic designs. All
devices within these families are composed of logic modules, I/O modules, routing resources and clock
networks, which are the building blocks for fast logic designs. In addition, the A42MX36 device contains
embedded dual-port SRAM modules, which are optimized for high-speed data path functions such as
FIFOs, LIFOs and scratch pad memory. A42MX24 and A42MX36 also contain wide-decode modules.
3.2.1 Logic Modules
The 40MX logic module is an eight-input, one-output logic circuit designed to implement a wide range of
logic functions with efficient use of interconnect routing resources.(see the following figures).
The logic module can implement the four basic logic functions (NAND, AND, OR and NOR) in gates of
two, three, or four inputs. The logic module can also implement a variety of D-latches, exclusivity
functions, AND-ORs and OR-ANDs. No dedicated hard-wired latches or flip-flops are required in the
array; latches and flip-flops can be constructed from logic modules whenever required in the application.
0 Microsemi. eeeeeeeeee .-
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 9
Figure 2 • 42MX C-Module Implementation
The 42MX devices contain three types of logic modules: combinatorial (C-modules),
sequential (S-modules) and decode (D-modules). The following figure illustrates the combinatorial logic
module. The S-module, shown in Figure 4, page 10, implements the same combinatorial logic function
as the C-module while adding a sequential element. The sequential element can be configured as either
a D-flip-flop or a transparent latch. The S-module register can be bypassed so that it implements purely
combinatorial logic.
Figure 3 • 42MX C-Module Implementation
D00
D01
D10
D11
S0
S1
Y
A0
B0
A1
B1
G Microsemi. Power Menus:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 10
Figure 4 • 42MX S-Module Implementation
A42MX24 and A42MX36 devices contain D-modules, which are arranged around the periphery of the
device. D-modules contain wide-decode circuitry, providing a fast, wide-input AND function similar to that
found in CPLD architectures (Figure 5, page 11). The D-module allows A42MX24 and A42MX36 devices
to perform wide-decode functions at speeds comparable to CPLDs and PALs. The output of the
D-module has a programmable inverter for active HIGH or LOW assertion. The D-module output is
hardwired to an output pin, and can also be fed back into the array to be incorporated into other logic.
3.2.2 Dual-Port SRAM Modules
The A42MX36 device contains dual-port SRAM modules that have been optimized for synchronous or
asynchronous applications. The SRAM modules are arranged in 256-bit blocks that can be configured as
32x8 or 64x4. SRAM modules can be cascaded together to form memory spaces of user-definable width
and depth. A block diagram of the A42MX36 dual-port SRAM block is shown in Figure 6, page 11.
The A42MX36 SRAM modules are true dual-port structures containing independent read and write ports.
Each SRAM module contains six bits of read and write addressing (RDAD[5:0] and WRAD[5:0],
respectively) for 64x4-bit blocks. When configured in byte mode, the highest order address bits (RDAD5
and WRAD5) are not used. The read and write ports of the SRAM block contain independent clocks
(RCLK and WCLK) with programmable polarities offering active HIGH or LOW implementation. The
SRAM block contains eight data inputs (WD[7:0]), and eight outputs (RD[7:0]), which are connected to
segmented vertical routing tracks.
The A42MX36 dual-port SRAM blocks provide an optimal solution for high-speed buffered applications
requiring FIFO and LIFO queues. The ACTgen Macro Builder within Microsemi's designer software
provides capability to quickly design memory functions with the SRAM blocks. Unused SRAM blocks can
be used to implement registers for other user logic within the design.
CLR
Up to 7-Input Function Plus D-Type Flip-Flop with Clear
Up to 4-Input Function Plus Latch with Clear
D0
D1 S
YDQ
GATE
CLR
OUT
Up to 8-Input Function (Same as C-Module)
D00
D01
D10
D11
S1
S0
YOUT
Up to 7-Input Function Plus Latch
D00
D01
D10
D11
S1 S0
YOUT
GATE
DQ
D00
D01
D10
D11
S1
S0
YDQ OUT
O Micmsemi. Power Matters. i? Lm l _r i C
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 11
Figure 5 • A42MX24 and A42MX36 D-Module Implementation
Figure 6 • A42MX36 Dual-Port SRAM Block
3.2.3 Routing Structure
The MX architecture uses vertical and horizontal routing tracks to interconnect the various logic and I/O
modules. These routing tracks are metal interconnects that may be continuous or split into segments.
Varying segment lengths allow the interconnect of over 90% of design tracks to occur with only two
antifuse connections. Segments can be joined together at the ends using antifuses to increase their
lengths up to the full length of the track. All interconnects can be accomplished with a maximum of four
antifuses.
3.2.3.1 Horizontal Routing
Horizontal routing tracks span the whole row length or are divided into multiple segments and are located
in between the rows of modules. Any segment that spans more than one-third of the row length is
considered a long horizontal segment. A typical channel is shown in Figure 7, page 12. Within horizontal
routing, dedicated routing tracks are used for global clock networks and for power and ground tie-off
tracks. Non-dedicated tracks are used for signal nets.
3.2.3.2 Vertical Routing
Another set of routing tracks run vertically through the module. There are three types of vertical tracks:
input, output, and long. Long tracks span the column length of the module, and can be divided into
multiple segments. Each segment in an input track is dedicated to the input of a particular module; each
segment in an output track is dedicated to the output of a particular module. Long segments are
uncommitted and can be assigned during routing.
Each output segment spans four channels (two above and two below), except near the top and bottom of
the array, where edge effects occur. Long vertical tracks contain either one or two segments. An example
of vertical routing tracks and segments is shown in Figure 7, page 12.
7 Inputs
Hard-Wire to I/
O
Feedback to Array
P
rogrammable
I
nverter
SRAM Module
32 x 8 or 64 x 4
(256 Bits)
Read
Port
Logic
Write
Port
Logic
RD[7:0]
Routing Tracks
Latches
Read
Logic
[5:0] RDAD[5:0]
REN
RCLK
Latches
WD[7:0]
Latches
WRAD[5:0]
Write
Logic
MODE
BLKEN
WEN
WCLK
[5:0]
[7:0]
0 Microsemi. Power Menus:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 12
3.2.3.3 Antifuse Structures
An antifuse is a “normally open” structure. The use of antifuses to implement a programmable logic
device results in highly testable structures as well as efficient programming algorithms. There are no
pre-existing connections; temporary connections can be made using pass transistors. These temporary
connections can isolate individual antifuses to be programmed and individual circuit structures to be
tested, which can be done before and after programming. For instance, all metal tracks can be tested for
continuity and shorts between adjacent tracks, and the functionality of all logic modules can be verified.
Figure 7 • MX Routing Structure
3.2.4 Clock Networks
The 40MX devices have one global clock distribution network (CLK). A signal can be put on the CLK
network by being routed through the CLKBUF buffer.
In 42MX devices, there are two low-skew, high-fanout clock distribution networks, referred to as CLKA
and CLKB. Each network has a clock module (CLKMOD) that can select the source of the clock signal
from any of the following (Figure 8, page 13):
Externally from the CLKA pad, using CLKBUF buffer
Externally from the CLKB pad, using CLKBUF buffer
Internally from the CLKINTA input, using CLKINT buffer
Internally from the CLKINTB input, using CLKINT buffer
The clock modules are located in the top row of I/O modules. Clock drivers and a dedicated horizontal
clock track are located in each horizontal routing channel.
Clock input pads in both 40MX and 42MX devices can also be used as normal I/Os, bypassing the clock
networks.
The A42MX36 device has four additional register control resources, called quadrant clock networks
(Figure 9, page 13). Each quadrant clock provides a local, high-fanout resource to the contiguous logic
modules within its quadrant of the device. Quadrant clock signals can originate from specific I/O pins or
from the internal array and can be used as a secondary register clock, register clear, or output enable.
S
egmented
H
orizontal
R
outing Logic
Module
s
Antifus
es
Vertical Routing Tracks
3 D? O Micmsemi. eeeeeeeeee .- 2 5h fiah ;+
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 13
Figure 8 • Clock Networks of 42MX Devices
Figure 9 • Quadrant Clock Network of A42MX36 Devices
Note: *QCLK1IN, QCLK2IN, QCLK3IN, and QCLK4IN are internally-generated signals.
3.2.5 MultiPlex I/O Modules
42MX devices feature Multiplex I/Os and support 5.0 V, 3.3 V, and mixed 3.3 V/5.0 V operations.
The MultiPlex I/O modules provide the interface between the device pins and the logic array. Figure 10,
page 14 is a block diagram of the 42MX I/O module. A variety of user functions, determined by a library
macro selection, can be implemented in the module. (See the Antifuse Macro Library Guide for more
information.) All 42MX I/O modules contain tristate buffers, with input and output latches that can be
configured for input, output, or bidirectional operation.
All 42MX devices contain flexible I/O structures, where each output pin has a dedicated output-enable
control (Figure 10, page 14). The I/O module can be used to latch input or output data, or both, providing
fast set-up time. In addition, the Designer software tools can build a D-type flip-flop using a C-module
combined with an I/O module to register input and output signals. See the Antifuse Macro Library Guide
for more details.
A42MX24 and A42MX36 devices also offer selectable PCI output drives, enabling 100% compliance with
version 2.1 of the PCI specification. For low-power systems, all inputs and outputs are turned off to
reduce current consumption to below 500 A.
To achieve 5.0 V or 3.3 V PCI-compliant output drives on A42MX24 and A42MX36 devices, a chip-wide
PCI fuse is programmed via the Device Selection Wizard in the Designer software (Figure 11, page 14).
When the PCI fuse is not programmed, the output drive is standard.
CLKB
CLKA
From
Pads
Clock
Drivers
CLKMOD
CLKINB
CLKINA
S0
S1 Intern
al
Signa
l
CLKO(1
7)
CLKO(1
6)
CLKO(1
5)
CLKO(
2)
CLKO(
1)
Clock Tracks
Quad
Clock
Modul
QCLKA
Q
CLKB
*QCLK1IN
S0 S1
QCLK1
Quad
Clock
Modul
*QCLK2IN
S0 S1
QCLK2
Quad
Clock
Modul
QCLK
C
QCLK
D
*QCLK3I
N
S0S1
QCLK3
Quad
Clock
Modul *QCLK4I
N
S0S1
QCLK4
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 14
Designer software development tools provide a design library of I/O macro functions that can implement
all I/O configurations supported by the MX FPGAs.
Figure 10 • 42MX I/O Module
Note: *Can be configured as a Latch or D Flip-Flop (Using C-Module)
Figure 11 • PCI Output Structure of A42MX24 and A42MX36 Devices
3.3 Other Architectural Features
The following sections cover other architectural features of 40MX and 42MX FPGAs.
3.3.1 Performance
MX devices can operate with internal clock frequencies of 250 MHz, enabling fast execution of complex
logic functions. MX devices are live on power-up and do not require auxiliary configuration devices and
thus are an optimal platform to integrate the functionality contained in multiple programmable logic
devices. In addition, designs that previously would have required a gate array to meet performance can
be integrated into an MX device with improvements in cost and time-to-market. Using
timing-driven place-and-route (TDPR) tools, designers can achieve highly deterministic device
performance.
3.3.2 User Security
Microsemi FuseLock provides robust security against design theft. Special security fuses are hidden in
the fabric of the device and protect against unauthorized users attempting to access the programming
and/or probe interfaces. It is virtually impossible to identify or bypass these fuses without damaging the
device, making Microsemi antifuse FPGAs protected with the highest level of security available from both
invasive and noninvasive attacks.
Special security fuses in 40MX devices include the Probe Fuse and Program Fuse. The former disables
the probing circuitry while the latter prohibits further programming of all fuses, including the Probe Fuse.
In 42MX devices, there is the Security Fuse which, when programmed, both disables the probing circuitry
and prohibits further programming of the device.
QD
From Array
o Array
G/CLK*
QD
PA
Signal
PCI Enable
PCI
Fuse
Drive
STD
Output
G Micmsemi. Power Matters:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 15
3.3.3 Programming
Device programming is supported through the Silicon Sculptor series of programmers. Silicon Sculptor is
a compact, robust, single-site and multi-site device programmer for the PC. With standalone software,
Silicon Sculptor is designed to allow concurrent programming of multiple units from the same PC.
Silicon Sculptor programs devices independently to achieve the fastest programming times possible.
After being programmed, each fuse is verified to insure that it has been programmed correctly.
Furthermore, at the end of programming, there are integrity tests that are run to ensure no extra fuses
have been programmed. Not only does it test fuses (both programmed and non-programmed), Silicon
Sculptor also allows self-test to verify its own hardware extensively.
The procedure for programming an MX device using Silicon Sculptor is as follows:
1. Load the *.AFM file
2. Select the device to be programmed
3. Begin programming
When the design is ready to go to production, Microsemi offers device volume-programming services
either through distribution partners or via In-House Programming from the factory.
For more details on programming MX devices, see the AC225: Programming Antifuse Devices
application note and the Silicon Sculptor 3 Programmers User Guide.
3.3.4 Power Supply
MX devices are designed to operate in both 5.0V and 3.3V environments. In particular, 42MX devices
can operate in mixed 5.0 V/3.3 V systems. The following table describes the voltage support of MX
devices.
For A42MX24 and A42MX36 devices the VCCA supply has to be monotonic during power up in order for
the POR to issue reset to the JTAG state machine correctly. For more information, see the AC291: 42MX
Family Devices Power-Up Behavior.
3.3.5 Power-Up/Down in Mixed-Voltage Mode
When powering up 42MX in mixed voltage mode (VCCA = 5.0 V and VCCI = 3.3 V), VCCA must be
greater than or equal to VCCI throughout the power-up sequence. If VCCI exceeds VCCA during
power-up, one of two things will happen:
The input protection diode on the I/Os will be forward biased
The I/Os will be at logical High
In either case, ICC rises to high levels. For power-down, any sequence with VCCA and VCCI can be
implemented.
3.3.6 Transient Current
Due to the simultaneous random logic switching activity during power-up, a transient current may appear
on the core supply (VCC). Customers must use a regulator for the VCC supply that can source a
minimum of 100 mA for transient current during power-up. Failure to provide enough power can prevent
the system from powering up properly and result in functional failure. However, there are no reliability
concerns, since transient current is distributed across the die instead of confined to a localized spot.
Table 6 • Voltage Support of MX Devices
Device VCC VCCA VCCI Maximum Input Tolerance Nominal Output Voltage
40MX 5.0 V 5.5 V 5.0 V
3.3 V 3.6 V 3.3 V
42MX 5.0 V 5.0 V 5.5 V 5.0 V
3.3 V 3.3 V 3.6 V 3.3 V
5.0 V 3.3 V 5.5 V 3.3 V
O Microsemi Power Maners:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 16
Since the transient current is not due to I/O switching, its value and duration are independent of the
VCCI.
3.3.7 Low Power Mode
42MX devices have been designed with a low power mode. This feature, activated with setting the
special LP pin to HIGH for a period longer than 800 ns, is particularly useful for battery-operated systems
where battery life is a primary concern. In this mode, the core of the device is turned off and the device
consumes minimal power with low standby current. In addition, all input buffers are turned off, and all
outputs and bidirectional buffers are tristated. Since the core of the device is turned off, the states of the
registers are lost. The device must be re-initialized when exiting low power mode. I/Os can be driven
during LP mode, and clock pins should be driven HIGH or LOW and should not float to avoid drawing
current. To exit LP mode, the LP pin must be pulled LOW for over
200 µs to allow for charge pumps to power up, and device initialization will begin.
3.4 Power Dissipation
The general power consumption of MX devices is made up of static and dynamic power and can be
expressed with the following equation.
3.4.1 General Power Equation
EQ 1
where:
ICCstandby is the current flowing when no inputs or outputs are changing.
ICCactive is the current flowing due to CMOS switching.
IOL, IOH are TTL sink/source currents.
VOL, VOH are TTL level output voltages.
N equals the number of outputs driving TTL loads to VOL.
M equals the number of outputs driving TTL loads to VOH.
Accurate values for N and M are difficult to determine because they depend on the family type, on design
details, and on the system I/O. The power can be divided into two components: static and active.
3.4.2 Static Power Component
The static power due to standby current is typically a small component of the overall power consumption.
Standby power is calculated for commercial, worst-case conditions. The static power dissipation by TTL
loads depends on the number of outputs driving, and on the DC load current. For instance, a 32-bit bus
sinking 4mA at 0.33V will generate 42mW with all outputs driving LOW, and 140mW with all outputs
driving HIGH. The actual dissipation will average somewhere in between, as I/Os switch states with time.
3.4.3 Active Power Component
Power dissipation in CMOS devices is usually dominated by the dynamic power dissipation.
Dynamic power consumption is frequency-dependent and is a function of the logic and the external I/O.
Active power dissipation results from charging internal chip capacitances of the interconnect,
unprogrammed antifuses, module inputs, and module outputs, plus external capacitances due to PC
board traces and load device inputs. An additional component of the active power dissipation is the totem
pole current in the CMOS transistor pairs. The net effect can be associated with an equivalent
capacitance that can be combined with frequency and voltage to represent active power dissipation.
The power dissipated by a CMOS circuit can be expressed by the equation:
EQ 2
P ICCs dbytan ICCactive+
VCCI IOLVOLNIOH
VCCI VOH
M++=
Power WCEQVCCA2F1=
O Microsemi Power Maners:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 17
where:
•C
EQ = Equivalent capacitance expressed in picofarads (pF)
VCCA = Power supply in volts (V)
F = Switching frequency in megahertz (MHz)
3.4.4 Equivalent Capacitance
Equivalent capacitance is calculated by measuring ICCactive at a specified frequency and voltage for
each circuit component of interest. Measurements have been made over a range of frequencies at a
fixed value of VCC. Equivalent capacitance is frequency-independent, so the results can be used over a
wide range of operating conditions. Equivalent capacitance values are shown below.
3.4.5 CEQ Values for Microsemi MX FPGAs
Modules (CEQM)3.5
Input Buffers (CEQI)6.9
Output Buffers (CEQO)18.2
Routed Array Clock Buffer Loads (CEQCR)1.4
To calculate the active power dissipated from the complete design, the switching frequency of each part
of the logic must be known. The equation below shows a piece-wise linear summation over all
components.
EQ 3
where:
m = Number of logic modules switching at frequency fm
n = Number of input buffers switching at frequency fn
p = Number of output buffers switching at frequency fp
q1 = Number of clock loads on the first routed array clock
q2 = Number of clock loads on the second routed array clock
r1 = Fixed capacitance due to first routed array clock
r2 = Fixed capacitance due to second routed array clock
CEQM = Equivalent capacitance of logic modules in pF
CEQI = Equivalent capacitance of input buffers in pF
CEQO = Equivalent capacitance of output buffers in pF
CEQCR = Equivalent capacitance of routed array clock in pF
CL = Output load capacitance in pF
fm = Average logic module switching rate in MHz
fn = Average input buffer switching rate in MHz
fp = Average output buffer switching rate in MHz
fq1 = Average first routed array clock rate in MHz
Power VCCA2mC
EQMfm

modules nCEQIfn

inputs pCEQO CL
+
fp

outputs
0.5q1CEQCRfq1

routed Clk1 r1fq1

routed Clk1
0.5q2CEQCRfq2

routed Clk2 r2fq2

routed Clk2 2
++ +
++
+
=
0 Micmsemi. eeeeeeeeee .-
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 18
fq2 = Average second routed array clock rate in MHz)
3.4.6 Test Circuitry and Silicon Explorer II Probe
MX devices contain probing circuitry that provides built-in access to every node in a design, via the use of
Silicon Explorer II. Silicon Explorer II is an integrated hardware and software solution that, in conjunction
with the Designer software, allows users to examine any of the internal nets of the device while it is
operating in a prototyping or a production system. The user can probe into an MX device without
changing the placement and routing of the design and without using any additional resources. Silicon
Explorer II's noninvasive method does not alter timing or loading effects, thus shortening the debug cycle
and providing a true representation of the device under actual functional situations.
Silicon Explorer II samples data at 100 MHz (asynchronous) or 66 MHz (synchronous). Silicon Explorer II
attaches to a PC's standard COM port, turning the PC into a fully functional 18-channel logic analyzer.
Silicon Explorer II allows designers to complete the design verification process at their desks and
reduces verification time from several hours per cycle to a few seconds.
Silicon Explorer II is used to control the MODE, DCLK, SDI and SDO pins in MX devices to select the
desired nets for debugging. The user simply assigns the selected internal nets in the Silicon Explorer II
software to the PRA/PRB output pins for observation. Probing functionality is activated when the MODE
pin is held HIGH.
Figure 12, page 18 illustrates the interconnection between Silicon Explorer II and 40MX devices, while
Figure 13, page 19 illustrates the interconnection between Silicon Explorer II and 42MX devices
To allow for probing capabilities, the security fuses must not be programmed. (See User Security,
page 14 for the security fuses of 40MX and 42MX devices). Table 8, page 19 summarizes the possible
device configurations for probing.
PRA and PRB pins are dual-purpose pins. When the “Reserve Probe Pin” is checked in the Designer
software, PRA and PRB pins are reserved as dedicated outputs for probing. If PRA and PRB pins are
required as user I/Os to achieve successful layout and “Reserve Probe Pin” is checked, the layout tool
will override the option and place user I/Os on PRA and PRB pins.
Figure 12 • Silicon Explorer II Setup with 40MX
Table 7 • Fixed Capacitance Values for MX FPGAs (pF)
Device Type r1 routed_Clk1 r2 routed_Clk2
A40MX02 41.4 N/A
A40MX04 68.6 N/A
A42MX09 118 118
A42MX16 165 165
A42MX24 185 185
A42MX36 220 220
40MX
Silicon
Explorer II
PRA
PRB
SDO
DCLK
SDI
MODE
Serial Connection
to Windows PC
16 Logic Analyzer Channels
G Micmsemi. Power Matters:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 19
Figure 13 • Silicon Explorer II Setup with 42MX
3.4.7 Design Consideration
It is recommended to use a series 70 termination resistor on every probe connector (SDI, SDO,
MODE, DCLK, PRA and PRB). The 70 series termination is used to prevent data transmission
corruption during probing and reading back the checksum.
3.4.8 IEEE Standard 1149.1 Boundary Scan Test (BST) Circuitry
42MX24 and 42MX36 devices are compatible with IEEE Standard 1149.1 (informally known as Joint
Testing Action Group Standard or JTAG), which defines a set of hardware architecture and mechanisms
for cost-effective board-level testing. The basic MX boundary-scan logic circuit is composed of the TAP
(test access port), TAP controller, test data registers and instruction register (Figure 14, page 20). This
circuit supports all mandatory IEEE 1149.1 instructions (EXTEST, SAMPLE/PRELOAD and BYPASS)
and some optional instructions. Table 9, page 20 describes the ports that control JTAG testing, while
Table 10, page 20 describes the test instructions supported by these MX devices.
Each test section is accessed through the TAP, which has four associated pins: TCK (test clock input),
TDI and TDO (test data input and output), and TMS (test mode selector).
The TAP controller is a four-bit state machine. The '1's and '0's represent the values that must be present
at TMS at a rising edge of TCK for the given state transition to occur. IR and DR indicate that the
instruction register or the data register is operating in that state.
The TAP controller receives two control inputs (TMS and TCK) and generates control and clock signals
for the rest of the test logic architecture. On power-up, the TAP controller enters the Test-Logic-Reset
state. To guarantee a reset of the controller from any of the possible states, TMS must remain high for
five TCK cycles.
42MX24 and 42MX36 devices support three types of test data registers: bypass, device identification,
and boundary scan. The bypass register is selected when no other register needs to be accessed in a
device. This speeds up test data transfer to other devices in a test data path. The 32-bit device
identification register is a shift register with four fields (lowest significant byte (LSB), ID number, part
number and version). The boundary-scan register observes and controls the state of each I/O pin.
Table 8 • Device Configuration Options for Probe Capability
Security Fuse(s) Programmed Mode PRA, PRB1
1. Avoid using SDI, SDO, DCLK, PRA and PRB pins as input or bidirectional ports.Since
these pins are active during probing, input signals will not pass through these pins and may
cause contention.
SDI, SDO, DCLK1
No LOW User I/Os2
2. If no user signal is assigned to these pins, they will behave as unused I/Os in this mode.
See the Pin Descriptions, page 85 for information on unused I/O pins
User I/Os2
No HIGH Probe Circuit Outputs Probe Circuit Inputs
Yes Probe Circuit Secured Probe Circuit Secured
42MX
Silicon
Explorer II
PRA
PRB
SDO
DCLK
SDI
MODE
Serial Connection
to Windows PC
16 Logic Analyzer Channels
G Microsemi. eeeeeeeeee .-
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 20
Each I/O cell has three boundary-scan register cells, each with a serial-in, serial-out, parallel-in, and
parallel-out pin. The serial pins are used to serially connect all the boundary-scan register cells in a
device into a boundary-scan register chain, which starts at the TDI pin and ends at the TDO pin. The
parallel ports are connected to the internal core logic tile and the input, output and control ports of an I/O
buffer to capture and load data into the register to control or observe the logic state of each I/O.
Figure 14 • 42MX IEEE 1149.1 Boundary Scan Circuitry
Table 9 • Test Access Port Descriptions
Port Description
TMS
(Test Mode Select) Serial input for the test logic control bits. Data is captured on the rising edge of the test logic
clock (TCK).
TCK
(Test Clock Input) Dedicated test logic clock used serially to shift test instruction, test data, and control inputs
on the rising edge of the clock, and serially to shift the output data on the falling edge of the
clock. The maximum clock frequency for TCK is 20 MHz.
TDI
(Test Data Input) Serial input for instruction and test data. Data is captured on the rising edge of the test logic
clock.
TDO
(Test Data Output) Serial output for test instruction and data from the test logic. TDO is set to an inactive drive
state (high impedance) when data scanning is not in progress.
Table 10 • Supported BST Public Instructions
Instruction IR Code
(IR2.IR0) Instruction
Type Description
EXTEST 000 Mandatory Allows the external circuitry and board-level interconnections to be
tested by forcing a test pattern at the output pins and capturing test
results at the input pins.
SAMPLE/PRELOAD 001 Mandatory Allows a snapshot of the signals at the device pins to be captured
and examined during operation
HIGH Z 101 Optional Tristates all I/Os to allow external signals to drive pins.
See the IEEE Standard 1149.1 specification.
CLAMP 110 Optional Allows state of signals driven from component pins to be determined
from the Boundary-Scan Register. See the IEEE Standard 1149.1
specification for details.
BYPASS 111 Mandatory Enables the bypass register between the TDI and TDO pins. The
test data passes through the selected device to adjacent devices in
the test chain.
Boundary Scan Register
Instruction
Decode
Control Logic
TAP Controller
Instruction
Register
Bypass
Register
TMS
TCK
TDI
Output
MUX TDO
JTAG
JTAG
RESENE Ems 17 Reserve JAG I— HESEN: Um xesrese« I— Reset/E prune O Microsemi Power Matters.
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 21
3.4.9 JTAG Mode Activation
The JTAG test logic circuit is activated in the Designer software by selecting Tools > Device Selection.
This brings up the Device Selection dialog box as shown in the following figure. The JTAG test logic
circuit can be enabled by clicking the “Reserve JTAG Pins” check box. The following table explains the
pins' behavior in either mode.
Figure 15 • Device Selection Wizard
3.4.10 TRST Pin and TAP Controller Reset
An active reset (TRST) pin is not supported; however, MX devices contain power-on circuitry that resets
the boundary scan circuitry upon power-up. Also, the TMS pin is equipped with an internal pull-up
resistor. This allows the TAP controller to remain in or return to the Test-Logic-Reset state when there is
no input or when a logical 1 is on the TMS pin. To reset the controller, TMS must be HIGH for at least five
TCK cycles.
3.4.11 Boundary Scan Description Language (BSDL) File
Conforming to the IEEE Standard 1149.1 requires that the operation of the various JTAG components be
documented. The BSDL file provides the standard format to describe the JTAG components that can be
used by automatic test equipment software. The file includes the instructions that are supported,
instruction bit pattern, and the boundary-scan chain order. For an in-depth discussion on BSDL files, see
the BSDL Files Format Description application note.
BSDL files are grouped into two categories - generic and device-specific. The generic files assign all user
I/Os as inouts. Device-specific files assign user I/Os as inputs, outputs or inouts.
Generic files for MX devices are available on the Microsemi SoC Product Group's website:
http://www.microsemi.com/soc/techdocs/models/bsdl.html.
3.5 Development Tool Support
The MX family of FPGAs is fully supported by Libero® integrated design environment (IDE). Libero IDE is
a design management environment, seamlessly integrating design tools while guiding the user through
the design flow, managing all design and log files, and passing necessary design data among tools.
Libero IDE allows users to integrate both schematic and HDL synthesis into a single flow and verify the
entire design in a single environment. Libero IDE includes SynplifyPro from Synopsys, ModelSim® HDL
Simulator from Mentor Graphics® and Viewdraw.
Libero IDE includes place-and-route and provides a comprehensive suite of backend support tools for
FPGA development, including timing-driven place-and-route, and a world-class integrated static timing
analyzer and constraints editor.
Table 11 • Boundary Scan Pin Configuration and Functionality
Reserve JTAG Checked Unchecked
TCK BST input; must be terminated to logical HIGH or LOW to avoid floating User I/O
TDI, TMS BST input; may float or be tied to HIGH User I/O
TDO BST output; may float or be connected to TDI of another device User I/O
G Micmsemi. Power Matters:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 22
Additionally, the back-annotation flow is compatible with all the major simulators and the simulation
results can be cross-probed with Silicon Explorer II, Microsemi’s integrated verification and logic analysis
tool. Another tool included in the Libero software is the SmartGen macro builder, which easily creates
popular and commonly used logic functions for implementation into your schematic or HDL design.
Microsemi’s Libero software is compatible with the most popular FPGA design entry and verification tools
from companies such as Mentor Graphics, Synopsys, and Cadence design systems.
See the Libero IDE web content at www.microsemi.com/soc/products/software/libero/default.aspx for
further information on licensing and current operating system support.
3.6 Related Documents
The following sections give the list of related documents which can be refered for this datasheet.
3.6.1 Application Notes
AC278: BSDL Files Format Description
AC225: Programming Antifuse Devices
AC168: Implementation of Security in Microsemi Antifuse FPGAs
3.6.2 User Guides and Manuals
Antifuse Macro Library Guide
Silicon Sculptor Programmers User Guide
3.6.3 Miscellaneous
Libero IDE Flow Diagram
3.7 5.0 V Operating Conditions
The following tables show 5.0 V operating conditions.
Note: *Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability. Devices should not be operated outside the recommended operating conditions.
Table 12 • Absolute Maximum Ratings for 40MX Devices*
Symbol Parameter Limits Units
VCC DC Supply Voltage –0.5 to +7.0 V
VI Input Voltage –0.5 to VCC+0.5 V
VO Output Voltage –0.5 to VCC+0.5 V
tSTG Storage Temperature –65 to +150 °C
Table 13 • Absolute Maximum Ratings for 42MX Devices*
Symbol Parameter Limits Units
VCCI DC Supply Voltage for I/Os –0.5 to +7.0 V
VCCA DC Supply Voltage for Array –0.5 to +7.0 V
VI Input Voltage –0.5 to VCCI+0.5 V
VO Output Voltage –0.5 to VCCI+0.5 V
tSTG Storage Temperature –65 to +150 °C
C} Microsemi. Power Matters:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 23
Note: *Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability. Devices should not be operated outside the recommended operating conditions.
Note: * Ambient temperature (TA) is used for commercial and industrial grades; case temperature (TC) is used
for military grades.
3.7.1 5 V TTL Electrical Specifications
The following tables show 5 V TTL electrical specifications.
Table 14 • Recommended Operating Conditions
Parameter Commercial Industrial Military Units
Temperature Range* 0 to +70 –40 to +85 –55 to +125 °C
VCC (40MX) 4.75 to 5.25 4.5 to 5.5 4.5 to 5.5 V
VCCA (42MX) 4.75 to 5.25 4.5 to 5.5 4.5 to 5.5 V
VCCI (42MX) 4.75 to 5.25 4.5 to 5.5 4.5 to 5.5 V
Table 15 • 5V TTL Electrical Specifications
Symbol Parameter
Commercial Commercial -F Industrial Military
UnitsMin. Max. Min. Max. Min. Max. Min. Max.
VOH1IOH = –10 mA 2.4 2.4 V
IOH = –4 mA 3.7 3.7 V
VOL1IOL = 10 mA 0.5 0.5 V
IOL = 6 mA 0.4 0.4 V
VIL –0.3 0.8 –0.3 0.8 –0.3 0.8 –0.3 0.8 V
VIH (40MX) 2.0 VCC + 0.3 2.0 VCC + 0.3 2.0 VCC + 0.3 2.0 VCC + 0.3 V
VIH (42MX)22.0 VCCI +
0.3 2.0 VCCI +
0.3 2.0 VCCI +
0.3 2.0 VCCI + 0.3 V
IIL VIN = 0.5 V –10 –10 –10 –10 µA
IIH VIN = 2.7 V –10 –10 –10 –10 µA
Input Transition
Time, TR and TF
500 500 500 500 ns
CIO I/O
Capacitance 10 10 10 10 pF
Standby
Current, ICC3A40MX02,
A40MX04 3251025mA
A42MX09 5 25 25 25 mA
A42MX16 6 25 25 25 mA
A42MX24,
A42MX36 20 25 25 25 mA
Low power
mode Standby
Current
42MX devices
only 0.5 ICC – 5.0 ICC – 5.0 ICC – 5.0 mA
IIO, I/O source
sink current Can be derived from the IBIS model
(http://www.microsemi.com/soc/techdocs/models/ibis.html)
G Microsemi. Power Matters:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 24
3.8 3.3 V Operating Conditions
The following table shows 3.3 V operating conditions.
Note: *Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability. Devices should not be operated outside the recommended operating conditions.
Note: *Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability. Devices should not be operated outside the recommended operating conditions.
Note: *Ambient temperature (TA) is used for commercial and industrial grades; case temperature (TC) is used
for military grades.
All the following tables show various specifications and operating conditions of 40MX and 42MX FPGAs.
1. Only one output tested at a time. VCC/VCCI = Min.
2. VIH(Min) is 2.4V for A42MX36 family. This applies only to VCCI of 5V and is not applicable to VCCI of 3.3V
3. All outputs unloaded. All inputs = VCC/VCCI or GND
Table 16 • Absolute Maximum Ratings for 40MX Devices*
Symbol Parameter Limits Units
VCC DC Supply Voltage –0.5 to +7.0 V
VI Input Voltage –0.5 to VCC + 0.5 V
VO Output Voltage –0.5 to VCC + 0.5 V
tSTG Storage Temperature –65 to + 150 °C
Table 17 • Absolute Maximum Ratings for 42MX Devices*
Symbol Parameter Limits Units
VCCI DC Supply Voltage for I/Os –0.5 to +7.0 V
VCCA DC Supply Voltage for Array –0.5 to +7.0 V
VI Input Voltage –0.5 to VCCI+0.5 V
VO Output Voltage –0.5 to VCCI+0.5 V
tSTG Storage Temperature –65 to +150 °C
Table 18 • Recommended Operating Conditions
Parameter Commercial Industrial Military Units
Temperature Range* 0 to +70 –40 to +85 –55 to +125 °C
VCC (40MX) 3.0 to 3.6 3.0 to 3.6 3.0 to 3.6 V
VCCA (42MX) 3.0 to 3.6 3.0 to 3.6 3.0 to 3.6 V
VCCI (42MX) 3.0 to 3.6 3.0 to 3.6 3.0 to 3.6 V
C} Microsemi. Power Matters:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 25
3.8.1 3.3 V LVTTL Electrical Specifications
3.9 Mixed 5.0 V / 3.3 V Operating Conditions (for 42MX
Devices Only)
Note: *Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. Exposure to absolute maximum rated conditions for extended periods may affect device
Table 19 • 3.3V LVTTL Electrical Specifications
Symbol Parameter
Commercial Commercial -F Industrial Military
UnitsMin. Max. Min. Max. Min. Max. Min. Max.
VOH1
1. Only one output tested at a time. VCC/VCCI = Min.
IOH = –4 mA 2.15 2.15 2.4 2.4 V
VOL1IOL = 6 mA 0.4 0.4 0.48 0.48 V
VIL –0.3 0.8 –0.3 0.8 –0.3 0.8 –0.3 0.8 V
VIH (40MX) 2.0 VCC + 0.3 2.0 VCC + 0.3 2.0 VCC + 0.3 2.0 VCC + 0.3 V
VIH (42MX) 2.0 VCCI + 0.3 2.0 VCCI + 0.3 2.0 VCCI + 0.3 2.0 VCCI + 0.3 V
IIL –10 –10 –10 –10 µA
IIH –10 –10 –10 –10 µA
Input Transition
Time, TR and TF
500 500 500 500 ns
CIO I/O
Capacitance 10 10 10 10 pF
Standby
Current, ICC2
2. All outputs unloaded. All inputs = VCC/VCCI or GND.
A40MX02,
A40MX04 3251025mA
A42MX09 5 25 25 25 mA
A42MX16 6 25 25 25 mA
A42MX24,
A42MX36 15 25 25 25 mA
Low-Power
Mode Standby
Current
42MX
devices only 0.5 ICC - 5.0 ICC - 5.0 ICC - 5.0 mA
IIO, I/O source
sink current Can be derived from the IBIS model (http://www.microsemi.com/soc/techdocs/models/ibis.html)
Table 20 • Absolute Maximum Ratings*
Symbol Parameter Limits Units
VCCI DC Supply Voltage for I/Os –0.5 to +7.0 V
VCCA DC Supply Voltage for Array –0.5 to +7.0 V
VI Input Voltage –0.5 to VCCA +0.5 V
VO Output Voltage –0.5 to VCCI + 0.5 V
tSTG Storage Temperature –65 to +150 °C
G Micmsemi. Power Matters:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 26
reliability. Devices should not be operated outside the recommended operating conditions.
Note: *Ambient temperature (TA) is used for commercial and industrial grades; case temperature (TC) is used
for military grades.
Table 21 • Recommended Operating Conditions
Parameter Commercial Industrial Military Units
Temperature Range* 0 to +70 –40 to +85 –55 to +125 °C
VCCA 4.75 to 5.25 4.5 to 5.5 4.5 to 5.5 V
VCCI 3.14 to 3.47 3.0 to 3.6 3.0 to 3.6 V
G Microsemi. Power Matters:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 27
3.9.1 Mixed 5.0V/3.3V Electrical Specifications
3.9.2 Output Drive Characteristics for 5.0 V PCI Signaling
MX PCI device I/O drivers were designed specifically for high-performance PCI systems. Figure 16,
page 30 shows the typical output drive characteristics of the MX devices. MX output drivers are
compliant with the PCI Local Bus Specification.
Table 22 • Mixed 5.0V/3.3V Electrical Specifications
Symbol Parameter
Commercial Commercial –F Industrial Military
UnitsMin. Max. Min. Max. Min. Max. Min. Max.
VOH1
1. Only one output tested at a time. VCCI = min.
IOH = –10 mA 2.4 2.4 V
IOH = –4 mA 2.4 2.4 V
VOL1IOL = 10 mA 0.5 0.5 V
IOL = 6 mA 0.4 0.4 V
VIL –0.3 0.8 –0.3 0.8 –0.3 0.8 –0.3 0.8 V
VIH2
2. VIH(Min) is 2.4V for A42MX36 family. This applies only to VCCI of 5V and is not applicable to VCCI of 3.3V
2.0 VCCA + 0.3 2.0 VCCA + 0.3 2.0 VCCA + 0.3 2.0 VCCA + 0.3 V
IL VIN = 0.5 V –10 –10 –10 –10 µA
IH VIN = 2.7 V –10 –10 –10 –10 µA
Input Transition
Time, TR and TF
500 500 500 500 ns
CIO I/O Capacitance 10 10 10 10 pF
Standby Current,
ICC3
3. All outputs unloaded. All inputs = VCCI or GND
A42MX09 5 25 25 25 mA
A42MX16 6 25 25 25 mA
A42MX24,
A42MX36 20 25 25 25 mA
Low Power Mode
Standby Current 0.5 ICC – 5.0 ICC – 5.0 ICC – 5.0 mA
IIO I/O source sink
current Can be derived from the IBIS model (http://www.microsemi.com/soc/techdocs/models/ibis.html)
Table 23 • DC Specification (5.0 V PCI Signaling)1
Symbol Parameter
PCI MX
UnitsCondition Min. Max. Min. Max.
VCCI Supply Voltage for I/Os 4.75 5.25 4.75 5.252V
VIH3Input High Voltage 2.0 VCC + 0.5 2.0 VCCI + 0.3 V
VIL Input Low Voltage –0.5 0.8 –0.3 0.8 V
IIH Input High Leakage Current VIN = 2.7 V 70 10 µA
IIL Input Low Leakage Current VIN=0.5 V –70 –10 µA
VOH Output High Voltage IOUT = –2 mA
IOUT = –6 mA 2.4 3.84 V
VOL Output Low Voltage IOUT = 3 mA, 6 mA 0.55 0.33 V
G Micmsemi. Power Matters: m
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 28
Note: *PCI Local Bus Specification, Version 2.1, Section 4.2.1.2.
CIN Input Pin Capacitance 10 10 pF
CCLK CLK Pin Capacitance 5 12 10 pF
LPIN Pin Inductance 20 < 8 nH4nH
1. PCI Local Bus Specification, Version 2.1, Section 4.2.1.1.
2. Maximum rating for VCCI is –0.5 V to 7.0 V
3. VIH(Min) is 2.4V for A42MX36 family. This applies only to VCCI of 5V and is not applicable to VCCI of 3.3V.
4. Dependent upon the chosen package. PCI recommends QFP and BGA packaging to reduce pin inductance and
capacitance.
Table 24 • AC Specifications (5.0V PCI Signaling)*
Symbol Parameter Condition
PCI MX
UnitsMin. Max. Min. Max.
ICL Low Clamp Current –5 < VIN –1 –25 + (VIN +1) /0.015 –60 –10 mA
Slew (r) Output Rise Slew Rate 0.4 V to 2.4 V load 1 5 1.8 2.8 V/ns
Slew (f) Output Fall Slew Rate 2.4 V to 0.4 V load 1 5 2.8 4.3 V/ns
Table 23 • DC Specification (5.0 V PCI Signaling)1 (continued)
Symbol Parameter
PCI MX
UnitsCondition Min. Max. Min. Max.
G Microsemi. Power Matters: vx
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 29
3.9.3 Output Drive Characteristics for 3.3 V PCI Signaling
Note: *PCI Local Bus Specification, Version 2.1, Section 4.2.2.2.
Table 25 DC Specification (3.3 V PCI Signaling)1
1. PCI Local Bus Specification, Version 2.1, Section 4.2.2.1.
Symbol Parameter Condition
PCI MX
UnitsMin. Max. Min. Max.
VCCI Supply Voltage for I/Os 3.0 3.6 3.0 3.62
2. Maximum rating for VCCI is–0.5 V to 7.0V.
V
VIH Input High Voltage 0.5 VCC + 0.5 0.5 VCCI + 0.3 V
VIL Input Low Voltage –0.5 0.8 –0.3 0.8 V
IIH Input High Leakage Current VIN = 2.7 V 70 10 µA
IIL Input Leakage Current –70 –10 µA
VOH Output High Voltage IOUT = –2 mA 0.9 3.3 V
VOL Output Low Voltage IOUT = 3 mA,
6mA 0.1 0.1 VCCI V
CIN Input Pin Capacitance 10 10 pF
CCLK CLK Pin Capacitance 5 12 10 pF
LPIN Pin Inductance 20 < 8 nH3
3. Dependent upon the chosen package. PCI recommends QFP and BGA packaging to reduce pin inductance and
capacitance.
nH
Table 26 • AC Specifications for (3.3 V PCI Signaling)*
Symbol Parameter Condition PCI MX Units
Min. Max. Min. Max.
ICL Low Clamp Current –5 < VIN –1 –25 + (VIN +1) /0.015 –60 –10 mA
Slew (r) Output Rise Slew Rate 0.2 V to 0.6 V load 1 4 1.8 2.8 V/ns
Slew (f) Output Fall Slew Rate 0.6 V to 0.2 V load 1 4 2.8 4.0 V/ns
O Micmsemi. Power Matters:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 30
Figure 16 • Typical Output Drive Characteristics (Based Upon Measured Data)
3.9.4 Junction Temperature (TJ)
The temperature variable in the Designer software refers to the junction temperature, not the ambient
temperature. This is an important distinction because the heat generated from dynamic power
consumption is usually hotter than the ambient temperature. The following equation can be used to
calculate junction temperature.
EQ 4
where:
•T
a = Ambient Temperature
T = Temperature gradient between junction (silicon) and ambient
T = ja * P (2)
•P = Power
ja = Junction to ambient of package. ja numbers are located in Table 27, page 31.
3.9.5 Package Thermal Characteristics
The device junction-to-case thermal characteristic is jc, and the junction-to-ambient air characteristic is
ja. The thermal characteristics for ja are shown with two different air flow rates.
The maximum junction temperature is 150C.
Maximum power dissipation for commercial- and industrial-grade devices is a function of ja.
0123456
MX PCI IOL
MX PCI IOH
PCI IOL Maximum
PCI IOL Minimum
PCI IOH Minimum
PCI IOH Maximum
Voltage Out (V)
–0.20
–0.15
–0.10
–0.05
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
Current (A)
Junction Temperature TT+a1=
G Microsemi. Power Matters: l)
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 31
A sample calculation of the absolute maximum power dissipation allowed for a TQ176 package at
commercial temperature and still air is given in the following equation
EQ 5
The maximum power dissipation for military-grade devices is a function of
jc. A sample calculation of the
absolute maximum power dissipation allowed for CQFP 208-pin package at military temperature and still
air is given in the following equation
EQ 6
Table 27 • Package Thermal Characteristics
Plastic Packages Pin Count jc
ja
UnitsStill Air 1.0 m/s
200 ft/min. 2.5 m/s
500 ft/min.
Plastic Quad Flat Pack 100 12.0 27.8 23.4 21.2 °C/W
Plastic Quad Flat Pack 144 10.0 26.2 22.8 21.1 °C/W
Plastic Quad Flat Pack 160 10.0 26.2 22.8 21.1 °C/W
Plastic Quad Flat Pack 208 8.0 26.1 22.5 20.8 °C/W
Plastic Quad Flat Pack 240 8.5 25.6 22.3 20.8 °C/W
Plastic Leaded Chip Carrier 44 16.0 20.0 24.5 22.0 °C/W
Plastic Leaded Chip Carrier 68 13.0 25.0 21.0 19.4 °C/W
Plastic Leaded Chip Carrier 84 12.0 22.5 18.9 17.6 °C/W
Thin Plastic Quad Flat Pack 176 11.0 24.7 19.9 18.0 °C/W
Very Thin Plastic Quad Flat
Pack 80 12.0 38.2 31.9 29.4 °C/W
Very Thin Plastic Quad Flat
Pack 100 10.0 35.3 29.4 27.1 °C/W
Plastic Ball Grid Array 272 3.0 18.3 14.9 13.9 °C/W
Ceramic Packages
Ceramic Pin Grid Array 132 4.8 25.0 20.6 18.7 °C/W
Ceramic Quad Flat Pack 208 2.0 22.0 19.8 18.0 °C/W
Ceramic Quad Flat Pack 256 2.0 20.0 16.5 15.0 °C/W
MaximumPowerAllowed Max junction temp CMax ambient temp C
ja CW
-----------------------------------------------------------------------------------------------------------------------------------------------------150C70C
28CW
-----------------------------------2.86W===
MaximumPowerAllowed Max junction temp CMax ambient temp C
jc CW
-----------------------------------------------------------------------------------------------------------------------------------------------------150C125C
6.3CW
--------------------------------------3.97W===
O Micmsemi. Power Matters:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 32
3.10 Timing Models
The following figures show various timing models.
Figure 17 • 40MX Timing Model*
Note: Values are shown for 40MX –3 speed grade devices at 5.0 V worst-case commercial conditions.
Figure 18 • 42MX Timing Model
Note: 1. Input module predicted routing delay
Note: 2. Values are shown for A42MX09 –3 speed grade devices at 5.0 V worst-case commercial conditions.
Output DelayInput Delay
Logic Module
Internal Delays
t
DLH
= 3.32 ns
t
ENHZ
= 7.92 ns
t
RD1
= 1.28 ns
t
RD2
= 1.80 ns
t
RD4
= 2.33 ns
t
RD8
= 4.93 ns
I/O Module
t
PD
= 1.24 ns
t
CO
= 1.24 ns
t
IRD1
= 2.09 ns
t
IRD4
= 3.64 ns
t
IRD8
= 5.73 ns
t
INYL
= 0.62 ns t
IRD2
= 2.59 ns
I/O Module
F
MAX
= 180 MHz
tCKH
= 4.55 ns FO = 128
Array
Clock
Predicted
Routing
Delays
Array
Clocks
Comb.
Logic
Include
DQ
FO = 32
Output DelaysInternal DelaysInput Delays
I/O Module
DQ
Combinatorial
Logic Module
Sequential
Logic Module
I/O Module
I/O Module
DQ
Predicted
Routing
Delays
G
G
t
RD1
= 0.7 ns
t
RD2
= 1.9 ns
t
RD4
= 1.4 ns
t
RD8
= 2.3 ns
t
OUTH
= 0.00 ns
t
OUTSU
= 0.3 ns
t
GLH
= 2.6 ns
t
DLH
= 2.5 ns
t
DLH
= 2.5 ns
t
ENHZ
= 4.9 ns
t
RD1
= 0.70 ns
t
LCO
= 5.2 ns (light loads, pad-to-pad)
tCO = 1.3 ns
t
SUD
= 0.3 ns
t
HD
= 0.00 ns
t
PD
=1.2 ns
t
IRD1
= 2.0 ns
1
t
INYL
= 0.8 ns
tI
NH
= 0.0 ns
t
INSU
= 0.3 ns
t
INGL
= 1.3 ns
F
MAX
= 296 MHz
t
CKH
= 2.70 ns
O Micmsemi. Power Matters:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 33
Figure 19 • 42MX Timing Model (Logic Functions Using Quadrant Clocks)
Note: 1. Load-dependent
Note: 2. Values are shown for A42MX36 –3 speed grade devices at 5.0 V worst-case commercial conditions
t
SUD
= 3.0 ns
t
HD
= 0.0 ns
FMAX=180 MHz
t
CKH
=3.03 ns
1
Quadrant
Clocks
t
CO
= 1.3 ns
t
RD1
= 0.9 ns
Sequential
Logic Module
t
LH
= 0.00 ns
t
LSU
= 0.5 ns
t
GHL
= 2.9 ns
t
ENHZ
= 5.3 ns
t
DLH
= 2.6 ns
t
RDD
= 0.3 ns
t
PDD
= 1.6 ns
t
INH
= 0.0 ns
t
INSU
= 0.5 ns
t
INGO
= 1.4 ns
t
RD1
= 0.9 ns
t
RD2
= 1.3 ns
t
RD4
= 2.0 ns
t
DLH
= 2.6 ns
t
PD
=1.3 ns
t
INPY
= 1.0 ns t
IRD1
= 2.0 ns
I/O Module
Combinatorial
Module
I/O Module
Decode
Module
Comb.
Logic
Include
DQDQ
G
G
DQ
I/O Module
Input Delays Internal Delays Output Delays
Predicted
Routing
Delays
eeeeeeeeeeee
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 34
Figure 20 • 42MX Timing Model (SRAM Functions)
Note: Values are shown for A42MX36 –3 speed grade devices at 5.0 V worst-case commercial conditions.
3.10.1 Parameter Measurement
The following figures show parameter measurement details.
Figure 21 • Output Buffer Delays
t
INPY
= 1 .0 ns
Input Delays
I/O Module
DQ
Array
Clocks
GI/O Module
DQ
G
WD [7:0]
WRAD [5:0]
BLKEN
WEN
WCLK
RD [7:0]
RDAD [5:0]
REN
RCLK
Predicted
Routing
Delays
t
GHL
= 2.9 ns
t
LSU
= 0.5 ns
t
LH
= 0.0 ns
t
DLH
= 2.6 ns
t
ADSU
= 1.6 ns
t
ADH
= 0.0 ns
t
RENSU
= 0.6 ns
t
RCO
= 3.4 ns
t
ADSU
= 1.6 ns
t
ADH
= 0.0 ns
t
WENSU
= 2.7 ns
t
BENS
= 2.8 ns
t
RD1
= 0.9 ns
F
MAX
= 167 MHz
t
IRD1
= 2.0 ns
t
INSU
= 0.5 ns
t
INH
= 0.0 ns
t
INGO
= 1.4 ns
To AC test loads (shown below)
PAD
D
E
TRIBUFF
In 50%
PAD 1.5 V
50%
1.5 V
E50%
PAD 1.5 V
50%
10%
E50%
PAD
GND 1.5 V
50%
90%
t
ENZL
t
ENLZ
t
ENZH
t
ENHZ
t
DLH
t
DHL
VOL
VOH VCCI
VOL
VOH
O Microsemi. >—_‘ 4. I I -{> m: eeeeeeeeee . J W
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 35
Figure 22 • AC Test Loads
Figure 23 • Input Buffer Delays
Figure 24 • Module Delays
35 pF
Load 1
(Used to measure propagation delay)
To the output under test
To the output under test
Load 2
(Used to measure rising/falling edges)
VCCI GND
35 pF
R to VCCI for tPLZ / tPZL
R to GND for tPHZ / tPZH
R =1 k
PA D Y
INBUF
PAD 3 V 0 V
1.5 V
Y
GND 50%
1.5 V
50%
t
INYL
t
INYH
VCCI
S
A
BY
S, A or B
Y
50%
t
PLH
Y
50%
50% 50%
50% 50%
t
PHL
PHL
t
PLH
O Micmsemj Power Matters. +I I4— X X I4 +I I<—>I I<— —="">| l—| l—I l—I l— +I I<—><—>I |<—>| |<- -="">| X I<—>I
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 36
3.10.2 Sequential Module Timing Characteristics
The following figure shows sequential module timing characteristics.
Figure 25 • Flip-Flops and Latches
Note: *D represents all data functions involving A, B, and S for multiplexed flip-flops.
3.10.3 Sequential Timing Characteristics
The following figures show sequential timing characteristics.
Figure 26 • Input Buffer Latches
t
WCLKA
t
WASYN
t
HD
t
SUENA
t
SUD
t
RS
t
A
t
WCLK1
t
CO
t
HENA
D*
G, CLK
E
Q
PRE, CLR
(Positive Edge-Triggered)
D
E
CLK CLR
PRE Y
G
PA D
PA D
CLK
DATA
G
CLK
t
INH
t
INSU
INSU
t
SU EXT
t
HEXT
IBDL
DATA
O Micmsemj Power Matters.
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 37
Figure 27 • Output Buffer Latches
3.10.4 Decode Module Timing
The following figure shows decode module timing.
Figure 28 • Decode Module Timing
3.10.5 SRAM Timing Characteristics
The following figure shows SRAM timing characteristics.
Figure 29 • SRAM Timing Characteristics
D
G
tOUTSU
tOUTH
PAD
OBDLHS
D
G
A–G, H
Y
tPLH
50%
tPHL
Y
A
B
C
D
E
F
GH
WRAD [5:0]
BLKEN
WEN
WCLK
RDAD [5:0]
LEW
REN
RCLK
RD [7:0]
WD [7:0]
Write Port Read Port
RAM Array
32x8 or 64x4
(256 Bits)
0 Microsemi. Power Matters. <——>
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 38
3.10.6 Dual-Port SRAM Timing Waveforms
The following figures show dual-port SRAM timing waveforms.
Figure 30 • 42MX SRAM Write Operation
Note: Identical timing for falling edge clock
Figure 31 • 42MX SRAM Synchronous Read Operation
Note: Identical timing for falling edge clock
Figure 32 • 42MX SRAM Asynchronous Read Operation—Type 1 (Read Address Controlled)
WCLK
WD[7:0]
WRAD[5:0]
WEN
BLKEN Valid
Valid
t
RCKHL
t
RCKHL
t
WENSU
t
BENSU
t
WENH
t
BENH
t
ADSU
t
ADH
RCLK
REN
RDAD[5:0]
RD[7:0] Old Data
Valid
tRCKHL
tCKHL
tRENH
tRCO
tADH
tDOH
tADSU
New Data
tRENSU
RDAD[5:0]
RD[7:0] Data 1
tRDADV
tDOH
ADDR2ADDR1
Data 2
tRPD
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DS2316 Datasheet Revision 16.0 39
Figure 33 • 42MX SRAM Asynchronous Read Operation—Type 2 (Write Address Controlled)
3.10.7 Predictable Performance: Tight Delay Distributions
Propagation delay between logic modules depends on the resistive and capacitive loading of the routing
tracks, the interconnect elements, and the module inputs being driven. Propagation delay increases as
the length of routing tracks, the number of interconnect elements, or the number of inputs increases.
From a design perspective, the propagation delay can be statistically correlated or modeled by the fanout
(number of loads) driven by a module. Higher fanout usually requires some paths to have longer routing
tracks.
The MX FPGAs deliver a tight fanout delay distribution, which is achieved in two ways: by decreasing the
delay of the interconnect elements and by decreasing the number of interconnect elements per path.
Microsemi’s patented antifuse offers a very low resistive/capacitive interconnect. The antifuses,
fabricated in 0.45 µm lithography, offer nominal levels of 100 resistance and 7.0 fF capacitance per
antifuse.
MX fanout distribution is also tight due to the low number of antifuses required for each interconnect
path. The proprietary architecture limits the number of antifuses per path to a maximum of four, with
90 percent of interconnects using only two antifuses.
3.11 Timing Characteristics
Device timing characteristics fall into three categories: family-dependent, device-dependent, and design-
dependent. The input and output buffer characteristics are common to all MX devices. Internal routing
delays are device-dependent; actual delays are not determined until after place-and-route of the user's
design is complete. Delay values may then be determined by using the Designer software utility or by
performing simulation with post-layout delays.
3.11.1 Critical Nets and Typical Nets
Propagation delays are expressed only for typical nets, which are used for initial design performance
evaluation. Critical net delays can then be applied to the most timing critical paths. Critical nets are
determined by net property assignment in Microsemi's Designer software prior to placement and routing.
Up to 6% of the nets in a design may be designated as critical.
WEN
WD[7:0]
WCLK
RD[7:0] Old Data
Valid
tWENH
tRPD
tWENSU
New Data
tDOH
tADSU
WRAD[5:0]
BLKEN
tADH
G Micmsemi. Power Matters: +++++++
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 40
3.11.2 Long Tracks
Some nets in the design use long tracks, which are special routing resources that span multiple rows,
columns, or modules. Long tracks employ three and sometimes four antifuse connections, which
increase capacitance and resistance, resulting in longer net delays for macros connected to long tracks.
Typically, up to 6 percent of nets in a fully utilized device require long tracks.
Long tracks add approximately a 3 ns to a 6 ns delay, which is represented statistically in higher fanout
(FO=8) routing delays in the data sheet specifications section, shown in Table 34, page 43.
3.11.3 Timing Derating
MX devices are manufactured with a CMOS process. Therefore, device performance varies according to
temperature, voltage, and process changes. Minimum timing parameters reflect maximum operating
voltage, minimum operating temperature and best-case processing. Maximum timing parameters reflect
minimum operating voltage, maximum operating temperature and worst-case processing.
3.11.4 Temperature and Voltage Derating Factors
The following tables and figures show temperature and voltage derating factors for 40MX and 42MX
FPGAs.
Figure 34 • 42MX Junction Temperature and Voltage Derating Curves
(Normalized to TJ = 25°C, VCCA = 5.0 V)
Table 28 • 42MX Temperature and Voltage Derating Factors (Normalized to TJ =
25°C, VCCA = 5.0 V)
42MX Voltage
Temperature
–55°C –40°C 0°C 25°C 70°C 85°C 125°C
4.50 0.93 0.95 1.05 1.09 1.25 1.29 1.41
4.75 0.88 0.90 1.00 1.03 1.18 1.22 1.34
5.00 0.85 0.87 0.96 1.00 1.15 1.18 1.29
5.25 0.84 0.86 0.95 0.97 1.12 1.14 1.28
5.50 0.83 0.85 0.94 0.96 1.10 1.13 1.26
0.60
0.70
0.80
0.90
1.00
1.10
1.20
1.30
1.40
1.50
4.50 4.75 5.00 5.25 5.50
Voltage (V)
Derating Factor
–55°C
–40°C
0°C
25°C
70°C
85°C
125°C
G Micmsemi. Power Matters: +++++++
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 41
Note: This derating factor applies to all routing and propagation delays
Figure 35 • 40MX Junction Temperature and Voltage Derating Curves (Normalized to TJ = 25°C, VCC = 5.0 V)
Note: This derating factor applies to all routing and propagation delays
Table 29 • 40MX Temperature and Voltage Derating Factors(Normalized to TJ =
25°C, VCC = 5.0 V)
40MX Voltage
Temperature
–55°C –40°C 0°C 25°C 70°C 85°C 125°C
4.50 0.89 0.93 1.02 1.09 1.25 1.31 1.45
4.75 0.84 0.88 0.97 1.03 1.18 1.24 1.37
5.00 0.82 0.85 0.94 1.00 1.15 1.20 1.33
5.25 0.80 0.82 0.91 0.97 1.12 1.16 1.29
5.50 0.79 0.82 0.90 0.96 1.10 1.15 1.28
Table 30 • 42MX Temperature and Voltage Derating Factors(Normalized to TJ =
25°C, VCCA = 3.3 V)
42MX Voltage
Temperature
–55°C –40°C 0°C 25°C 70°C 85°C 125°C
3.00 0.97 1.00 1.10 1.15 1.32 1.36 1.45
3.30 0.84 0.87 0.96 1.00 1.15 1.18 1.26
3.60 0.81 0.84 0.92 0.96 1.10 1.13 1.21
Factor
0.60
0.70
0.80
0.90
1.00
1.10
1.20
1.30
1.40
1.50
4.50 4.75 5.00 5.25 5.50
Voltage (V)
Derating
–55°C
–40°C
0°C
25°C
70°C
85°C
125°C
O Micmsemi. Power Matters.-
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 42
Figure 36 • 42MX Junction Temperature and Voltage Derating Curves
(Normalized to TJ = 25°C, VCCA = 3.3 V)
Note: This derating factor applies to all routing and propagation delays
Figure 37 • 40MX Junction Temperature and Voltage Derating Curves (Normalized to TJ = 25°C, VCC = 3.3 V)
Note: This derating factor applies to all routing and propagation delays
Table 31 40MX Temperature and Voltage Derating Factors (Normalized to TJ =
25°C, VCC = 3.3 V)
40MX Voltage
Temperature
–55°C –40°C 0°C 25°C 70°C 85°C 125°C
3.00 1.08 1.12 1.21 1.26 1.50 1.64 2.00
3.30 0.86 0.89 0.96 1.00 1.19 1.30 1.59
3.60 0.83 0.85 0.92 0.96 1.14 1.25 1.53
0.40
0.50
0.60
0.70
0.80
0.90
1.00
1.10
1.20
1.30
1.40
1.50
1.60
Voltage (V)
Derating Factor
3.00 3.30 3.60
55°C
40°C
0°C
25°C
70°C
85°C
125°C
3.00 3.30 3.60
Voltage (V)
Derating Factor
0.60
0.80
1.00
1.20
1.40
1.60
1.80
2.00
2.20
55˚C
40˚C
0˚C
25˚C
70˚C
85˚C
125˚C
C} Microsemi. Power Matters:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 43
3.11.5 PCI System Timing Specification
The following tables list the critical PCI timing parameters and the corresponding timing parameters for
the MX PCI-compliant devices.
3.11.6 PCI Models
Microsemi provides synthesizable VHDL(VHSIC Hardware Description Language) and Verilog-HDL
models for a PCI Target interface, a PCI Target and Target+DMA Master interface. Contact the Microsemi
sales representative for more details.
3.11.6.1 Timing Characteristics
The following tables list the timing characteristics.
Table 32 • Clock Specification for 33 MHz PCI
Symbol Parameter
PCI A42MX24 A42MX36
UnitsMin. Max. Min. Max. Min. Max.
tCYC CLK Cycle Time 30 4.0 4.0 ns
tHIGH CLK High Time 11 1.9 1.9 ns
tLOW CLK Low Time 11 1.9 1.9 ns
Table 33 • Timing Parameters for 33 MHz PCI
Symbol Parameter
PCI A42MX24 A42MX36
UnitsMin. Max. Min. Max. Min. Max.
tVAL CLK to Signal Valid—Bused Signals 2 11 2.0 9.0 2.0 9.0 ns
tVAL(PTP) CLK to Signal Valid—Point-to-Point 2 212 2.0 9.0 2.0 9.0 ns
tON Float to Active 2 2.0 4.0 2.0 4.0 ns
tOFF Active to Float 28 8.31
1. TOFF is system dependent. MX PCI devices have 7.4 ns turn-off time, reflection is typically an additional 10 ns.
8.31ns
tSU Input Set-Up Time to CLK—Bused Signals 7 1.5 1.5 ns
tSU(PTP) Input Set-Up Time to CLK—Point-to-Point 10, 122
2. REQ# and GNT# are point-to-point signals and have different output valid delay and input setup times than do
bussed signals. GNT# has a setup of 10; REW# has a setup of 12.
1.5 1.5 ns
tHInput Hold to CLK 0 0 0 ns
Table 34 • A40MX02 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C)
Parameter / Description
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Logic Module Propagation Delays
tPD1 Single Module 1.2 1.4 1.6 1.9 2.7 ns
tPD2 Dual-Module Macros 2.7 3.1 3.5 4.1 5.7 ns
tCO Sequential Clock-to-Q 1.2 1.4 1.6 1.9 2.7 ns
tGO Latch G-to-Q 1.2 1.4 1.6 1.9 2.7 ns
tRS Flip-Flop (Latch) Reset-to-Q 1.2 1.4 1.6 1.9 2.7 ns
Logic Module Predicted Routing Delays1
C: Microsemi. Power Matters:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 44
tRD1 FO = 1 Routing Delay 1.3 1.5 1.7 2.0 2.8 ns
tRD2 FO = 2 Routing Delay 1.8 2.1 2.4 2.8 3.9 ns
tRD3 FO = 3 Routing Delay 2.3 2.7 3.0 3.6 5.0 ns
tRD4 FO = 4 Routing Delay 2.9 3.3 3.7 4.4 6.1 ns
tRD8 FO = 8 Routing Delay 4.9 5.7 6.5 7.6 10.6 ns
Logic Module Sequential Timing2
tSUD Flip-Flop (Latch)
Data Input Set-Up 3.1 3.5 4.0 4.7 6.6 ns
tHD3Flip-Flop (Latch)
Data Input Hold 0.0 0.0 0.0 0.0 0.0 ns
tSUEN
A
Flip-Flop (Latch)
Enable Set-Up 3.1 3.5 4.0 4.7 6.6 ns
tHENA Flip-Flop (Latch) Enable
Hold 0.0 0.0 0.0 0.0 0.0 ns
tWCL
KA
Flip-Flop (Latch)
Clock Active Pulse Width 3.3 3.8 4.3 5.0 7.0 ns
tWAS
YN
Flip-Flop (Latch)
Asynchronous Pulse Width 3.3 3.8 4.3 5.0 7.0 ns
tAFlip-Flop Clock Input Period 4.8 5.6 6.3 7.5 10.4 ns
fMAX Flip-Flop (Latch) Clock
Frequency (FO = 128) 181 168 154 134 80 MHz
Input Module Propagation Delays
tINYH Pad-to-Y HIGH 0.7 0.8 0.9 1.1 1.5 ns
tINYL Pad-to-Y LOW 0.6 0.7 0.8 1.0 1.3 ns
Input Module Predicted Routing Delays1
tIRD1 FO = 1 Routing Delay 2.1 2.4 2.2 3.2 4.5 ns
tIRD2 FO = 2 Routing Delay 2.6 3.0 3.4 4.0 5.6 ns
tIRD3 FO = 3 Routing Delay 3.1 3.6 4.1 4.8 6.7 ns
tIRD4 FO = 4 Routing Delay 3.6 4.2 4.8 5.6 7.8 ns
tIRD8 FO = 8 Routing Delay 5.7 6.6 7.5 8.8 12.4 ns
Global Clock Network
tCKH Input Low to HIGH FO = 16
FO = 128 4.6
4.6 5.3
5.3 6.0
6.0 7.0
7.0 9.8
9.8 ns
tCKL Input High to LOW FO = 16
FO = 128 4.8
4.8 5.6
5.6 6.3
6.3 7.4
7.4 10.4
10.4 ns
tPWH Minimum Pulse
Width HIGH FO = 16
FO = 128 2.2
2.4 2.6
2.7 2.9
3.1 3.4
3.6 4.8
5.1 ns
tPWL Minimum Pulse
Width LOW FO = 16
FO = 128 2.2
2.4 2.6
2.7 2.9
3.01 3.4
3.6 4.8
5.1 ns
Table 34 • A40MX02 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C) (continued)
Parameter / Description
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
G Microsemi. Power Matters:
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DS2316 Datasheet Revision 16.0 45
tCKS
W
Maximum Skew FO = 16
FO = 128 0.4
0.5 0.5
0.6 0.5
0.7 0.6
0.8 0.8
1.2 ns
tPMinimum Period FO = 16
FO = 128 4.7
4.8 5.4
5.6 6.1
6.3 7.2
7.5 10.0
10.4 ns
fMAX Maximum
Frequency FO = 16
FO = 128 188
181 175
168 160
154 139
134 83
80 MHz
TTL Output Module Timing4
tDLH Data-to-Pad HIGH 3.3 3.8 4.3 5.1 7.2 ns
tDHL Data-to-Pad LOW 4.0 4.6 5.2 6.1 8.6 ns
tENZH Enable Pad Z to HIGH 3.7 4.3 4.9 5.8 8.0 ns
tENZL Enable Pad Z to LOW 4.7 5.4 6.1 7.2 10.1 ns
tENHZ Enable Pad HIGH to Z 7.9 9.1 10.4 12.2 17.1 ns
tENLZ Enable Pad LOW to Z 5.9 6.8 7.7 9.0 12.6 ns
dTLH Delta LOW to
HIGH 0.02 0.02 0.03 0.03 0.04 ns/pF
dTHL Delta HIGH to
LOW 0.03 0.03 0.03 0.04 0.06 ns/pF
CMOS Output Module Timing4
tDLH Data-to-Pad HIGH 3.9 4.5 5.1 6.05 8.5 ns
tDHL Data-to-Pad LOW 3.4 3.9 4.4 5.2 7.3 ns
tENZH Enable Pad Z to HIGH 3.4 3.9 4.4 5.2 7.3 ns
tENZL Enable Pad Z to LOW 4.9 5.6 6.4 7.5 10.5 ns
tENHZ Enable Pad HIGH to Z 7.9 9.1 10.4 12.2 17.0 ns
tENLZ Enable Pad LOW to Z 5.9 6.8 7.7 9.0 12.6 ns
dTLH Delta LOW to
HIGH 0.03 0.04 0.04 0.05 0.07 ns/pF
dTHL Delta HIGH to
LOW 0.02 0.02 0.03 0.03 0.04 ns/pF
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check
the hold time for this macro.
4. Delays based on 35pF loading
Table 35 A40MX02 Timing Characteristics (Nominal 3.3 V Operation)
(Worst-Case Commercial Conditions, VCC = 3.0 V, TJ = 70°C)
Parameter / Description
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Logic Module Propagation Delays
tPD1 Single Module 1.7 2.0 2.3 2.7 3.7 ns
Table 34 • A40MX02 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C) (continued)
Parameter / Description
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
C: Microsemi. Power Matters:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 46
tPD2 Dual-Module Macros 3.7 4.3 4.9 5.7 8.0 ns
tCO Sequential Clock-to-Q 1.7 2.0 2.3 2.7 3.7 ns
tGO Latch G-to-Q 1.7 2.0 2.3 2.7 3.7 ns
tRS Flip-Flop (Latch) Reset-to-Q 1.7 2.0 2.3 2.7 3.7 ns
Logic Module Predicted Routing Delays1
tRD1 FO = 1 Routing Delay 2.0 2.2 2.5 3.0 4.2 ns
tRD2 FO = 2 Routing Delay 2.7 3.1 3.5 4.1 5.7 ns
tRD3 FO = 3 Routing Delay 3.4 3.9 4.4 5.2 7.3 ns
tRD4 FO = 4 Routing Delay 4.2 4.8 5.4 6.3 8.9 ns
tRD8 FO = 8 Routing Delay 7.1 8.2 9.2 10.9 15.2 ns
Logic Module Sequential Timing2
tSUD Flip-Flop (Latch)
Data Input Set-Up 4.3 4.9 5.6 6.6 9.2 ns
tHD3Flip-Flop (Latch)
Data Input Hold 0.0 0.0 0.0 0.0 0.0 ns
tSUENA Flip-Flop (Latch) Enable
Set-Up 4.3 4.9 5.6 6.6 9.2 ns
tHENA Flip-Flop (Latch) Enable
Hold 0.0 0.0 0.0 0.0 0.0 ns
tWCLKA Flip-Flop (Latch)
Clock Active Pulse Width 4.6 5.3 6.0 7.0 9.8 ns
tWASYN Flip-Flop (Latch)
Asynchronous Pulse Width 4.6 5.3 6.0 7.0 9.8 ns
tAFlip-Flop Clock Input Period 6.8 7.8 8.9 10.4 14.6 ns
fMAX Flip-Flop (Latch) Clock
Frequency (FO = 128) 109 101 92 80 48 MHz
Input Module Propagation Delays
tINYH Pad-to-Y HIGH 1.0 1.1 1.3 1.5 2.1 ns
tINYL Pad-to-Y LOW 0.9 1.0 1.1 1.3 1.9 ns
Input Module Predicted Routing Delays1
tIRD1 FO = 1 Routing Delay 2.9 3.4 3.8 4.5 6.3 ns
tIRD2 FO = 2 Routing Delay 3.6 4.2 4.8 5.6 7.8 ns
tIRD3 FO = 3 Routing Delay 4.4 5.0 5.7 6.7 9.4 ns
tIRD4 FO = 4 Routing Delay 5.1 5.9 6.7 7.8 11.0 ns
tIRD8 FO = 8 Routing Delay 8.0 9.26 10.5 12.6 17.3 ns
Global Clock Network
tCKH Input LOW to
HIGH FO = 16
FO =
128
6.4
6.4 7.4
7.4 8.3
8.3 9.8
9.8 13.7
13.7 ns
Table 35 A40MX02 Timing Characteristics (Nominal 3.3 V Operation)
(Worst-Case Commercial Conditions, VCC = 3.0 V, TJ = 70°C) (continued)
Parameter / Description
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
G Microsemi. Power Matters:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 47
tCKL Input HIGH to
LOW FO = 16
FO =
128
6.7
6.7 7.8
7.8 8.8
8.8 10.4
10.4 14.5
14.5 ns
tPWH Minimum Pulse
Width HIGH FO = 16
FO =
128
3.1
3.3 3.6
3.8 4.1
4.3 4.8
5.1 6.7
7.1 ns
tPWL Minimum Pulse
Width LOW FO = 16
FO =
128
3.1
3.3 3.6
3.8 4.1
4.3 4.8
5.1 6.7
7.1 ns
tCKSW Maximum Skew FO = 16
FO =
128
0.6
0.8 0.6
0.9 0.7
1.0 0.8
1.2 1.2
1.6 ns
tPMinimum Period FO = 16
FO =
128
6.5
6.8 7.5
7.8 8.5
8.9 10.1
10.4 14.1
14.6 ns
fMAX Maximum
Frequency FO = 16
FO =
128
113
109 105
101 96
92 83
80 50
48 MHz
TTL Output Module Timing4
tDLH Data-to-Pad
HIGH 4.7 5.4 6.1 7.2 10.0 ns
tDHL Data-to-Pad LOW 5.6 6.4 7.3 8.6 12.0 ns
tENZH Enable Pad Z to HIGH 5.2 6.0 6.8 8.1 11.3 ns
tENZL Enable Pad Z to LOW 6.6 7.6 8.6 10.1 14.1 ns
tENHZ Enable Pad HIGH to Z 11.1 12.8 14.5 17.1 23.9 ns
tENLZ Enable Pad LOW to Z 8.2 9.5 10.7 12.6 17.7 ns
dTLH Delta LOW to
HIGH 0.03 0.03 0.04 0.04 0.06 ns/pF
dTHL Delta HIGH to
LOW 0.04 0.04 0.05 0.06 0.08 ns/pF
Table 35 A40MX02 Timing Characteristics (Nominal 3.3 V Operation)
(Worst-Case Commercial Conditions, VCC = 3.0 V, TJ = 70°C) (continued)
Parameter / Description
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
G Microsemi. Power Matters:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 48
CMOS Output Module Timing4
tDLH Data-to-Pad
HIGH 5.5 6.4 7.2 8.5 11.9 ns
tDHL Data-to-Pad LOW 4.8 5.5 6.2 7.3 10.2 ns
tENZH Enable Pad Z to HIGH 4.7 5.5 6.2 7.3 10.2 ns
tENZL Enable Pad Z to LOW 6.8 7.9 8.9 10.5 14.7 ns
tENHZ Enable Pad HIGH to Z 11.1 12.8 14.5 17.1 23.9 ns
tENLZ Enable Pad LOW to Z 8.2 9.5 10.7 12.6 17.7 ns
dTLH Delta LOW to
HIGH 0.05 0.05 0.06 0.07 0.10 ns/pF
dTHL Delta HIGH to
LOW 0.03 0.03 0.04 0.04 0.06 ns/pF
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check
the hold time for this macro
4. Delays based on 35 pF loading
Table 36 • A40MX04 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C)
Parameter / Description
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Logic Module Propagation Delays
tPD1 Single Module 1.2 1.4 1.6 1.9 2.7 ns
tPD2 Dual-Module Macros 2.3 3.1 3.5 4.1 5.7 ns
tCO Sequential Clock-to-Q 1.2 1.4 1.6 1.9 2.7 ns
tGO Latch G-to-Q 1.2 1.4 1.6 1.9 2.7 ns
tRS Flip-Flop (Latch) Reset-to-Q 1.2 1.4 1.6 1.9 2.7 ns
Logic Module Predicted Routing Delays1
tRD1 FO = 1 Routing Delay 1.2 1.6 1.8 2.1 3.0 ns
tRD2 FO = 2 Routing Delay 1.9 2.2 2.5 2.9 4.1 ns
tRD3 FO = 3 Routing Delay 2.4 2.8 3.2 3.7 5.2 ns
tRD4 FO = 4 Routing Delay 2.9 3.4 3.9 4.5 6.3 ns
tRD8 FO = 8 Routing Delay 5.0 5.8 6.6 7.8 10.9 ns
Logic Module Sequential Timing2
tSUD Flip-Flop (Latch)
Data Input Set-Up 3.1 3.5 4.0 4.7 6.6 ns
tHD3Flip-Flop (Latch)
Data Input Hold 0.0 0.0 0.0 0.0 0.0 ns
Table 35 A40MX02 Timing Characteristics (Nominal 3.3 V Operation)
(Worst-Case Commercial Conditions, VCC = 3.0 V, TJ = 70°C) (continued)
Parameter / Description
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
G Microsemi. Power Matters:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 49
tSUENA Flip-Flop (Latch)
Enable Set-Up 3.1 3.5 4.0 4.7 6.6 ns
tHENA Flip-Flop (Latch)
Enable Hold 0.0 0.0 0.0 0.0 0.0 ns
tWCLKA Flip-Flop (Latch)
Clock Active Pulse Width 3.3 3.8 4.3 5.0 7.0 ns
tWASYN Flip-Flop (Latch)
Asynchronous Pulse Width 3.3 3.8 4.3 5.0 7.0 ns
tAFlip-Flop Clock Input Period 4.8 5.6 6.3 7.5 10.4 ns
fMAX Flip-Flop (Latch)
Clock Frequency
(FO = 128)
181 167 154 134 80 MHz
Input Module Propagation Delays
tINYH Pad-to-Y HIGH 0.7 0.8 0.9 1.1 1.5 ns
tINYL Pad-to-Y LOW 0.6 0.7 0.8 1.0 1.3 ns
Input Module Predicted Routing Delays1
tIRD1 FO = 1 Routing Delay 2.1 2.4 2.2 3.2 4.5 ns
tIRD2 FO = 2 Routing Delay 2.6 3.0 3.4 4.0 5.6 ns
tIRD3 FO = 3 Routing Delay 3.1 3.6 4.1 4.8 6.7 ns
tIRD4 FO = 4 Routing Delay 3.6 4.2 4.8 5.6 7.8 ns
tIRD8 FO = 8 Routing Delay 5.7 6.6 7.5 8.8 12.4 ns
Global Clock Network
tCKH Input Low to HIGH FO = 16
FO = 128 4.6
4.6 5.3
5.3 6.0
6.0 7.0
7.0 9.8
9.8 ns
tCKL Input High to LOW FO = 16
FO = 128 4.8
4.8 5.6
5.6 6.3
6.3 7.4
7.4 10.4
10.4 ns
tPWH Minimum Pulse
Width HIGH FO = 16
FO = 128 2.2
2.4 2.6
2.7 2.9
3.1 3.4
3.6 4.8
5.1 ns
tPWL Minimum Pulse
Width LOW FO = 16
FO = 128 2.2
2.4 2.6
2.7 2.9
3.01 3.4
3.6 4.8
5.1 ns
tCKSW Maximum Skew FO = 16
FO = 128 0.4
0.5 0.5
0.6 0.5
0.7 0.6
0.8 0.8
1.2 ns
tPMinimum Period FO = 16
FO = 128 4.7
4.8 5.4
5.6 6.1
6.3 7.2
7.5 10.0
10.4 ns
fMAX Maximum
Frequency FO = 16
FO = 128 188
181 175
168 160
154 139
134 83
80 MHz
TTL Output Module Timing4
tDLH Data-to-Pad HIGH 3.3 3.8 4.3 5.1 7.2 ns
tDHL Data-to-Pad LOW 4.0 4.6 5.2 6.1 8.6 ns
tENZH Enable Pad Z to HIGH 3.7 4.3 4.9 5.8 8.0 ns
Table 36 • A40MX04 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C) (continued)
Parameter / Description
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
G Micmsemi. Power Matters:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 50
tENZL Enable Pad Z to LOW 4.7 5.4 6.1 7.2 10.1 ns
tENHZ Enable Pad HIGH to Z 7.9 9.1 10.4 12.2 17.1 ns
tENLZ Enable Pad LOW to Z 5.9 6.8 7.7 9.0 12.6 ns
dTLH Delta LOW to
HIGH 0.02 0.02 0.03 0.03 0.04 ns/pF
dTHL Delta HIGH to
LOW 0.03 0.03 0.03 0.04 0.06 ns/pF
Table 36 • A40MX04 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C) (continued)
Parameter / Description
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
C: Microsemi. Power Matters:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 51
CMOS Output Module Timing1
tDLH Data-to-Pad HIGH 3.9 4.5 5.1 6.05 8.5 ns
tDHL Data-to-Pad LOW 3.4 3.9 4.4 5.2 7.3 ns
tENZH Enable Pad Z to HIGH 3.4 3.9 4.4 5.2 7.3 ns
tENZL Enable Pad Z to LOW 4.9 5.6 6.4 7.5 10.5 ns
tENHZ Enable Pad HIGH to Z 7.9 9.1 10.4 12.2 17.0 ns
tENLZ Enable Pad LOW to Z 5.9 6.8 7.7 9.0 12.6 ns
dTLH Delta LOW to
HIGH 0.03 0.04 0.04 0.05 0.07 ns/pF
dTHL Delta HIGH to
LOW 0.02 0.02 0.03 0.03 0.04 ns/pF
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer utility from the Designer software to check the
hold time for this macro.
4. Delays based on 35 pF loading
Table 37 • A40MX04 Timing Characteristics (Nominal 3.3 V Operation)
(Worst-Case Commercial Conditions, VCC = 3.0 V, TJ = 70°C)
Parameter / Description
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Logic Module Propagation Delays
tPD1 Single Module 1.7 2.0 2.3 2.7 3.7 ns
tPD2 Dual-Module Macros 3.7 4.3 4.9 5.7 8.0 ns
tCO Sequential Clock-to-Q 1.7 2.0 2.3 2.7 3.7 ns
tGO Latch G-to-Q 1.7 2.0 2.3 2.7 3.7 ns
tRS Flip-Flop (Latch) Reset-to-Q 1.7 2.0 2.3 2.7 3.7 ns
Logic Module Predicted Routing Delays1
tRD1 FO = 1 Routing Delay 1.9 2.2 2.5 3.0 4.2 ns
tRD2 FO = 2 Routing Delay 2.7 3.1 3.5 4.1 5.7 ns
tRD3 FO = 3 Routing Delay 3.4 3.9 4.4 5.2 7.3 ns
tRD4 FO = 4 Routing Delay 4.1 4.8 5.4 6.3 8.9 ns
tRD8 FO = 8 Routing Delay 7.1 8.1 9.2 10.9 15.2 ns
Logic Module Sequential Timing2
tSUD Flip-Flop (Latch)
Data Input Set-Up 4.3 5.0 5.6 6.6 9.2 ns
tHD3Flip-Flop (Latch) Data Input Hold 0.0 0.0 0.0 0.0 0.0 ns
tSUENA Flip-Flop (Latch) Enable Set-Up 4.3 5.0 5.6 6.6 9.2 ns
Table 36 • A40MX04 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C) (continued)
Parameter / Description
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
G Microsemi. Power Matters:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 52
tHENA Flip-Flop (Latch) Enable Hold 0.0 0.0 0.0 0.0 0.0 ns
tWCLKA Flip-Flop (Latch)
Clock Active Pulse Width 4.6 5.3 5.6 7.0 9.8 ns
tWASYN Flip-Flop (Latch)
Asynchronous Pulse Width 4.6 5.3 5.6 7.0 9.8 ns
tAFlip-Flop Clock Input Period 6.8 7.8 8.9 10.4 14.6 ns
fMAX Flip-Flop (Latch) Clock
Frequency
(FO = 128)
109 101 92 80 48 MHz
Input Module Propagation Delays
tINYH Pad-to-Y HIGH 1.0 1.1 1.3 1.5 2.1 ns
tINYL Pad-to-Y LOW 0.9 1.0 1.1 1.3 1.9 ns
Table 37 • A40MX04 Timing Characteristics (Nominal 3.3 V Operation)
(Worst-Case Commercial Conditions, VCC = 3.0 V, TJ = 70°C) (continued)
Parameter / Description
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
G Microsemi. Power Matters:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 53
Input Module Predicted Routing Delays1
tIRD1 FO = 1 Routing Delay 2.9 3.3 3.8 4.5 6.3 ns
tIRD2 FO = 2 Routing Delay 3.6 4.2 4.8 5.6 7.8 ns
tIRD3 FO = 3 Routing Delay 4.4 5.0 5.7 6.7 9.4 ns
tIRD4 FO = 4 Routing Delay 5.1 5.9 6.7 7.8 11.0 ns
tIRD8 FO = 8 Routing
Delay 8.0 9.3 10.5 12.4 17.2 ns
Global Clock Network
tCKH Input LOW to HIGH FO = 16
FO = 128 6.4
6.4 7.4
7.4 8.4
8.4 9.9
9.9 13.8
13.8 ns
tCKL Input HIGH to LOW FO = 16
FO = 128 6.8
6.8 7.8
7.8 8.9
8.9 10.4
10.4 14.6
14.6 ns
tPWH Minimum Pulse
Width HIGH FO = 16
FO = 128 3.1
3.3 3.6
3.8 4.1
4.3 4.8
5.1 6.7
7.1 ns
tPWL Minimum Pulse
Width LOW FO = 16
FO = 128 3.1
3.3 3.6
3.8 4.1
4.3 4.8
5.1 6.7
7.1 ns
tCKSW Maximum Skew FO = 16
FO = 128 0.6
0.8 0.6
0.9 0.7
1.0 0.8
1.2 1.2
1.6 ns
tPMinimum Period FO = 16
FO = 128 6.5
6.8 7.5
7.8 8.5
8.9 10.1
10.4 14.1
14.6 ns
fMAX Maximum
Frequency FO = 16
FO = 128 113
109 105
101 96
92 83
80 50
48 MHz
TTL Output Module Timing4
tDLH Data-to-Pad HIGH 4.7 5.4 6.1 7.2 10.0 ns
tDHL Data-to-Pad LOW 5.6 6.4 7.3 8.6 12.0 ns
tENZH Enable Pad Z to HIGH 5.2 6.0 6.9 8.1 11.3 ns
tENZL Enable Pad Z to LOW 6.6 7.6 8.6 10.1 14.1 ns
tENHZ Enable Pad HIGH to Z 11.1 12.8 14.5 17.1 23.9 ns
tENLZ Enable Pad LOW to Z 8.2 9.5 10.7 12.6 17.7 ns
dTLH Delta LOW to HIGH 0.03 0.03 0.04 0.04 0.06 ns/pF
dTHL Delta HIGH to LOW 0.04 0.04 0.05 0.06 0.08 ns/pF
Table 37 • A40MX04 Timing Characteristics (Nominal 3.3 V Operation)
(Worst-Case Commercial Conditions, VCC = 3.0 V, TJ = 70°C) (continued)
Parameter / Description
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
C: Microsemi. Power Matters:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 54
CMOS Output Module Timing4
tDLH Data-to-Pad HIGH 5.5 6.4 7.2 8.5 11.9 ns
tDHL Data-to-Pad LOW 4.8 5.5 6.2 7.3 10.2 ns
tENZH Enable Pad Z to HIGH 4.7 5.5 6.2 7.3 10.2 ns
tENZL Enable Pad Z to LOW 6.8 7.9 8.9 10.5 14.7 ns
tENHZ Enable Pad HIGH to Z 11.1 12.8 14.5 17.1 23.9 ns
tENLZ Enable Pad LOW to Z 8.2 9.5 10.7 12.6 17.7 ns
dTLH Delta LOW to HIGH 0.05 0.05 0.06 0.07 0.10 ns/pF
dTHL Delta HIGH to LOW 0.03 0.03 0.04 0.04 0.06 ns/pF
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check the hold
time for this macro.
4. Delays based on 35 pF loading.
Table 38 • A42MX09 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70°C)
Parameter / Description
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Logic Module Propagation Delays1
tPD1 Single Module 1.2 1.3 1.5 1.8 2.5 ns
tCO Sequential Clock-to-Q 1.3 1.4 1.6 1.9 2.7 ns
tGO Latch G-to-Q 1.2 1.4 1.6 1.8 2.6 ns
tRS Flip-Flop (Latch) Reset-to-Q 1.2 1.6 1.8 2.1 2.9 ns
Logic Module Predicted Routing Delays2
tRD1 FO = 1 Routing Delay 0.7 0.8 0.9 1.0 1.4 ns
tRD2 FO = 2 Routing Delay 0.9 1.0 1.2 1.4 1.9 ns
tRD3 FO = 3 Routing Delay 1.2 1.3 1.5 1.7 2.4 ns
tRD4 FO = 4 Routing Delay 1.4 1.5 1.7 2.0 2.9 ns
tRD8 FO = 8 Routing Delay 2.3 2.6 2.9 3.4 4.8 ns
Logic Module Sequential Timing3, 4
tSUD Flip-Flop (Latch)
Data Input Set-Up 0.3 0.4 0.4 0.5 0.7 ns
tHD Flip-Flop (Latch) Data Input Hold 0.0 0.0 0.0 0.0 0.0 ns
tSUENA Flip-Flop (Latch) Enable Set-Up 0.4 0.5 0.5 0.6 0.8 ns
tHENA Flip-Flop (Latch) Enable Hold 0.0 0.0 0.0 0.0 0.0 ns
tWCLKA Flip-Flop (Latch) Clock Active
Pulse Width 3.4 3.8 4.3 5.0 7.0 ns
Table 37 • A40MX04 Timing Characteristics (Nominal 3.3 V Operation)
(Worst-Case Commercial Conditions, VCC = 3.0 V, TJ = 70°C) (continued)
Parameter / Description
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
G Micmsemi. Power Matters:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 55
tWASYN Flip-Flop (Latch) Asynchronous
Pulse Width 4.5 4.9 5.6 6.6 9.2 ns
tAFlip-Flop Clock Input Period 3.5 3.8 4.3 5.1 7.1 ns
tINH Input Buffer Latch Hold 0.0 0.0 0.0 0.0 0.0 ns
tINSU Input Buffer Latch Set-Up 0.3 0.3 0.4 0.4 0.6 ns
tOUTH Output Buffer Latch Hold 0.0 0.0 0.0 0.0 0.0 ns
tOUTSU Output Buffer Latch Set-Up 0.3 0.3 0.4 0.4 0.6 ns
fMAX Flip-Flop (Latch) Clock Frequency 268 244 224 195 117 MHz
Table 38 • A42MX09 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70°C) (continued)
Parameter / Description
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
G Microsemi. Power Matters:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 56
Input Module Propagation Delays
tINYH Pad-to-Y HIGH 1.0 1.2 1.3 1.6 2.2 ns
tINYL Pad-to-Y LOW 0.8 0.9 1.0 1.2 1.7 ns
tINGH G to Y HIGH 1.3 1.4 1.6 1.9 2.7 ns
tINGL G to Y LOW 1.3 1.4 1.6 1.9 2.7 ns
Input Module Predicted Routing Delays2
tIRD1 FO = 1 Routing Delay 2.0 2.2 2.5 3.0 4.2 ns
tIRD2 FO = 2 Routing Delay 2.3 2.5 2.9 3.4 4.7 ns
tIRD3 FO = 3 Routing Delay 2.5 2.8 3.2 3.7 5.2 ns
tIRD4 FO = 4 Routing Delay 2.8 3.1 3.5 4.1 5.7 ns
tIRD8 FO = 8 Routing Delay 3.7 4.1 4.7 5.5 7.7 ns
Global Clock Network
tCKH Input LOW to HIGH FO = 32
FO = 256 2.4
2.7 2.7
3.0 3.0
3.4 3.6
4.0 5.0
5.5 ns
ns
tCKL Input HIGH to LOW FO = 32
FO = 256 3.5
3.9 3.9
4.3 4.4
4.9 5.2
5.7 7.3
8.0 ns
ns
tPWH Minimum Pulse
Width HIGH FO = 32
FO = 256 1.2
1.3 1.4
1.5 1.5
1.7 1.8
2.0 2.5
2.7 ns
ns
tPWL Minimum Pulse
Width LOW FO = 32
FO = 256 1.2
1.3 1.4
1.5 1.5
1.7 1.8
2.0 2.5
2.7 ns
ns
tCKSW Maximum Skew FO = 32
FO = 256 0.3
0.3 0.3
0.3 0.4
0.4 0.5
0.5 0.6
0.6 ns
ns
tSUEXT Input Latch
External Set-Up FO = 32
FO = 256 0.0
0.0 0.0
0.0 0.0
0.0 0.0
0.0 0.0
0.0 ns
ns
tHEXT Input Latch
External Hold FO = 32
FO = 256 2.3
2.2 2.6
2.4 3.0
3.3 3.5
3.9 4.9
5.5 ns
ns
tPMinimum Period FO = 32
FO = 256 3.4
3.7 3.7
4.1 4.0
4.5 4.7
5.2 7.8
8.6 ns
ns
fMAX Maximum Frequency FO = 32
FO = 256 296
268 269
244 247
224 215
195 129
117 MHz
MHz
Table 38 • A42MX09 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70°C) (continued)
Parameter / Description
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
G Microsemi. Power Matters:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 57
TTL Output Module Timing5
tDLH Data-to-Pad HIGH 2.5 2.7 3.1 3.6 5.1 ns
tDHL Data-to-Pad LOW 2.9 3.2 3.6 4.3 6.0 ns
tENZH Enable Pad Z to HIGH 2.6 2.9 3.3 3.9 5.5 ns
tENZL Enable Pad Z to LOW 2.9 3.2 3.7 4.3 6.1 ns
tENHZ Enable Pad HIGH to Z 4.9 5.4 6.2 7.3 10.2 ns
tENLZ Enable Pad LOW to Z 5.3 5.9 6.7 7.9 11.1 ns
tGLH G-to-Pad HIGH 2.6 2.9 3.3 3.8 5.3 ns
tGHL G-to-Pad LOW 2.6 2.9 3.3 3.8 5.3 ns
tLSU I/O Latch Set-Up 0.5 0.5 0.6 0.7 1.0 ns
tLH I/O Latch Hold 0.0 0.0 0.0 0.0 0.0 ns
tLCO I/O Latch Clock-to-Out
(Pad-to-Pad), 64 Clock Loading 5.2 5.8 6.6 7.7 10.8 ns
tACO Array Clock-to-Out
(Pad-to-Pad), 64 Clock Loading 7.4 8.2 9.3 10.9 15.3 ns
dTLH Capacity Loading, LOW to HIGH 0.03 0.03 0.03 0.04 0.06 ns/pF
dTHL Capacity Loading, HIGH to LOW 0.04 0.04 0.04 0.05 0.07 ns/pF
Table 38 • A42MX09 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70°C) (continued)
Parameter / Description
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
G Microsemi. Power Matters:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 58
CMOS Output Module Timing5
tDLH Data-to-Pad HIGH 2.4 2.7 3.1 3.6 5.1 ns
tDHL Data-to-Pad LOW 2.9 3.2 3.6 4.3 6.0 ns
tENZH Enable Pad Z to HIGH 2.7 2.9 3.3 3.9 5.5 ns
tENZL Enable Pad Z to LOW 2.9 3.2 3.7 4.3 6.1 ns
tENHZ Enable Pad HIGH to Z 4.9 5.4 6.2 7.3 10.2 ns
tENLZ Enable Pad LOW to Z 5.3 5.9 6.7 7.9 11.1 ns
tGLH G-to-Pad HIGH 4.2 4.6 5.2 6.1 8.6 ns
tGHL G-to-Pad LOW 4.2 4.6 5.2 6.1 8.6 ns
tLSU I/O Latch Set-Up 0.5 0.5 0.6 0.7 1.0 ns
tLH I/O Latch Hold 0.0 0.0 0.0 0.0 0.0 ns
tLCO I/O Latch Clock-to-Out
(Pad-to-Pad), 64 Clock Loading 5.2 5.8 6.6 7.7 10.8 ns
tACO Array Clock-to-Out (
Pad-to-Pad), 64 Clock Loading 7.4 8.2 9.3 10.9 15.3 ns
dTLH Capacity Loading, LOW to HIGH 0.03 0.03 0.03 0.04 0.06 ns/pF
dTHL Capacity Loading, HIGH to LOW 0.04 0.04 0.04 0.05 0.07 ns/pF
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External
setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD
signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading
Table 39 • A42MX09 Timing Characteristics (Nominal 3.3 V Operation)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, TJ = 70°C)
Parameter / Description
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Logic Module Propagation Delays1
tPD1 Single Module 1.6 1.8 2.1 2.5 3.5 ns
tCO Sequential Clock-to-Q 1.8 2.0 2.3 2.7 3.8 ns
tGO Latch G-to-Q 1.7 1.9 2.1 2.5 3.5 ns
tRS Flip-Flop (Latch) Reset-to-Q 2.0 2.2 2.5 2.9 4.1 ns
Logic Module Predicted Routing Delays2
tRD1 FO = 1 Routing Delay 1.0 1.1 1.2 1.4 2.0 ns
tRD2 FO = 2 Routing Delay 1.3 1.4 1.6 1.9 2.7 ns
tRD3 FO = 3 Routing Delay 1.6 1.8 2.0 2.4 3.3 ns
Table 38 • A42MX09 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70°C) (continued)
Parameter / Description
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
G Microsemi. Power Matters:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 59
tRD4 FO = 4 Routing Delay 1.9 2.1 2.4 2.9 4.0 ns
tRD8 FO = 8 Routing Delay 3.2 3.6 4.1 4.8 6.7 ns
Logic Module Sequential Timing 3, 4
tSUD Flip-Flop (Latch) Data Input Set-Up 0.5 0.5 0.6 0.7 0.9 ns
tHD Flip-Flop (Latch) Data Input Hold 0.0 0.0 0.0 0.0 0.0 ns
tSUENA Flip-Flop (Latch) Enable Set-Up 0.6 0.6 0.7 0.8 1.2 ns
tHENA Flip-Flop (Latch) Enable Hold 0.0 0.0 0.0 0.0 0.0 ns
tWCLKA Flip-Flop (Latch)
Clock Active Pulse Width 4.7 5.3 6.0 7.0 9.8 ns
tWASYN Flip-Flop (Latch)
Asynchronous Pulse Width 6.2 6.9 7.8 9.2 12.9 ns
tAFlip-Flop Clock Input Period 5.0 5.6 6.2 7.1 9.9 ns
tINH Input Buffer Latch Hold 0.0 0.0 0.0 0.0 0.0 ns
tINSU Input Buffer Latch Set-Up 0.3 0.3 0.3 0.4 0.6 ns
tOUTH Output Buffer Latch Hold 0.0 0.0 0.0 0.0 0.0 ns
tOUTSU Output Buffer Latch Set-Up 0.3 0.3 0.3 0.4 0.6 ns
fMAX Flip-Flop (Latch) Clock Frequency 161 146 135 117 70 MHz
Table 39 • A42MX09 Timing Characteristics (Nominal 3.3 V Operation)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, TJ = 70°C) (continued)
Parameter / Description
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
G Microsemi. Power Matters:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 60
Input Module Propagation Delays
tINYH Pad-to-Y HIGH 1.5 1.6 1.8 2.17 3.0 ns
tINYL Pad-to-Y LOW 1.2 1.3 1.4 1.7 2.4 ns
tINGH G to Y HIGH 1.8 2.0 2.3 2.7 3.7 ns
tINGL G to Y LOW 1.8 2.0 2.3 2.7 3.7 ns
Input Module Predicted Routing Delays2
tIRD1 FO = 1 Routing Delay 2.8 3.2 3.6 4.2 5.9 ns
tIRD2 FO = 2 Routing Delay 3.2 3.5 4.0 4.7 6.6 ns
tIRD3 FO = 3 Routing Delay 3.5 3.9 4.4 5.2 7.3 ns
tIRD4 FO = 4 Routing Delay 3.9 4.3 4.9 5.7 8.0 ns
tIRD8 FO = 8 Routing Delay 5.2 5.8 6.6 7.7 10.8 ns
Global Clock Network
tCKH Input LOW to HIGH FO = 32
FO = 256 4.1
4.5 4.5
5.0 5.1
5.6 6.0
6.7 8.4
9.3 ns
ns
tCKL Input HIGH to LOW FO = 32
FO = 256 5.0
5.4 5.5
6.0 6.2
6.8 7.3
8.0 10.2
11.2 ns
ns
tPWH Minimum Pulse Width
HIGH FO = 32
FO = 256 1.7
1.9 1.9
2.1 2.1
2.3 2.5
2.7 3.5
3.8 ns
ns
tPWL Minimum Pulse Width
LOW FO = 32
FO = 256 1.7
1.9 1.9
2.1 2.1
2.3 2.5
2.7 3.5
3.8 ns
ns
tCKSW Maximum Skew FO = 32
FO = 256 0.4
0.4 0.5
0.5 0.5
0.5 0.6
0.6 0.9
0.9 ns
ns
tSUEXT Input Latch External
Set-Up FO = 32
FO = 256 0.0
0.0 0.0
0.0 0.0
0.0 0.0
0.0 0.0
0.0 ns
ns
tHEXT Input Latch External
Hold FO = 32
FO = 256 3.3
3.7 3.7
4.1 4.2
4.6 4.9
5.5 6.9
7.6 ns
ns
tPMinimum Period FO = 32
FO = 256 5.6
6.1 6.2
6.8 6.7
7.4 7.8
8.5 12.9
14.2 ns
ns
fMAX Maximum Frequency FO = 32
FO = 256 177
161 161
146 148
135 129
117 77
70 MHz
MHz
Table 39 • A42MX09 Timing Characteristics (Nominal 3.3 V Operation)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, TJ = 70°C) (continued)
Parameter / Description
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
G Microsemi. Power Matters:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 61
TTL Output Module Timing5
tDLH Data-to-Pad HIGH 3.4 3.8 4.3 5.1 7.1 ns
tDHL Data-to-Pad LOW 4.0 4.5 5.1 6.1 8.3 ns
tENZH Enable Pad Z to HIGH 3.7 4.1 4.6 5.5 7.6 ns
tENZL Enable Pad Z to LOW 4.1 4.5 5.1 6.1 8.5 ns
tENHZ Enable Pad HIGH to Z 6.9 7.6 8.6 10.2 14.2 ns
tENLZ Enable Pad LOW to Z 7.5 8.3 9.4 11.1 15.5 ns
tGLH G-to-Pad HIGH 5.8 6.5 7.3 8.6 12.0 ns
tGHL G-to-Pad LOW 5.8 6.5 7.3 8.6 12.0 ns
tLSU I/O Latch Set-Up 0.7 0.8 0.9 1.0 1.4 ns
tLH I/O Latch Hold 0.0 0.0 0.0 0.0 0.0 ns
tLCO I/O Latch Clock-to-Out
(Pad-to-Pad), 64 Clock Loading 8.7 9.7 10.9 12.9 18.0 ns
tACO Array Clock-to-Out
(Pad-to-Pad),64 Clock Loading 12.2 13.5 15.4 18.1 25.3 ns
dTLH Capacity Loading, LOW to HIGH 0.00 0.00 0.00 0.10 0.01 ns/pF
dTHL Capacity Loading, HIGH to LOW 0.09 0.10 0.10 0.10 0.10 ns/pF
Table 39 • A42MX09 Timing Characteristics (Nominal 3.3 V Operation)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, TJ = 70°C) (continued)
Parameter / Description
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
G Microsemi. Power Matters:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 62
CMOS Output Module Timing5
tDLH Data-to-Pad HIGH 3.4 3.8 5.5 6.4 9.0 ns
tDHL Data-to-Pad LOW 4.1 4.5 4.2 5.0 7.0 ns
tENZH Enable Pad Z to HIGH 3.7 4.1 4.6 5.5 7.6 ns
tENZL Enable Pad Z to LOW 4.1 4.5 5.1 6.1 8.5 ns
tENHZ Enable Pad HIGH to Z 6.9 7.6 8.6 10.2 14.2 ns
tENLZ Enable Pad LOW to Z 7.5 8.3 9.4 11.1 15.5 ns
tGLH G-to-Pad HIGH 5.8 6.5 7.3 8.6 12.0 ns
tGHL G-to-Pad LOW 5.8 6.5 7.3 8.6 12.0 ns
tLSU I/O Latch Set-Up 0.7 0.8 0.9 1.0 1.4 ns
tLH I/O Latch Hold 0.0 0.0 0.0 0.0 0.0 ns
tLCO I/O Latch Clock-to-Out
(Pad-to-Pad), 64 Clock Loading 8.7 9.7 10.9 12.9 18.0 ns
tACO Array Clock-to-Out
(Pad-to-Pad),
64 Clock Loading
12.2 13.5 15.4 18.1 25.3 ns
dTLH Capacity Loading, LOW to HIGH 0.04 0.04 0.05 0.06 0.08 ns/pF
dTHL Capacity Loading, HIGH to LOW 0.05 0.05 0.06 0.07 0.10 ns/pF
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External
setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external
PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
Table 40 A42MX16 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70°C)
Parameter / Description
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Logic Module Propagation Delays1
tPD1 Single Module 1.4 1.5 1.7 2.0 2.8 ns
tCO Sequential Clock-to-Q 1.4 1.6 1.8 2.1 3.0 ns
tGO Latch G-to-Q 1.4 1.5 1.7 2.0 2.8 ns
tRS Flip-Flop (Latch) Reset-to-Q 1.6 1.7 2.0 2.3 3.3 ns
Logic Module Predicted Routing Delays2
tRD1 FO = 1 Routing Delay 0.8 0.9 1.0 1.2 1.6 ns
tRD2 FO = 2 Routing Delay 1.0 1.2 1.3 1.5 2.1 ns
Table 39 • A42MX09 Timing Characteristics (Nominal 3.3 V Operation)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, TJ = 70°C) (continued)
Parameter / Description
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
C: Microsemi. Power Matters:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 63
tRD3 FO = 3 Routing Delay 1.3 1.4 1.6 1.9 2.7 ns
tRD4 FO = 4 Routing Delay 1.6 1.7 2.0 2.3 3.2 ns
tRD8 FO = 8 Routing Delay 2.6 2.9 3.2 3.8 5.3 ns
Logic Module Sequential Timing3,4
tSUD Flip-Flop (Latch)
Data Input Set-Up 0.3 0.4 0.4 0.5 0.7 ns
tHD Flip-Flop (Latch) Data Input Hold 0.0 0.0 0.0 0.0 0.0 ns
tSUENA Flip-Flop (Latch) Enable Set-Up 0.7 0.8 0.9 1.0 1.4 ns
tHENA Flip-Flop (Latch) Enable Hold 0.0 0.0 0.0 0.0 0.0 ns
tWCLKA Flip-Flop (Latch)
Clock Active Pulse Width 3.4 3.8 4.3 5.0 7.1 ns
tWASYN Flip-Flop (Latch)
Asynchronous Pulse Width 4.5 5.0 5.6 6.6 9.2 ns
tAFlip-Flop Clock Input Period 6.8 7.6 8.6 10.1 14.1 ns
tINH Input Buffer Latch Hold 0.0 0.0 0.0 0.0 0.0 ns
tINSU Input Buffer Latch Set-Up 0.5 0.5 0.6 0.7 1.0 ns
tOUTH Output Buffer Latch Hold 0.0 0.0 0.0 0.0 0.0 ns
tOUTSU Output Buffer Latch Set-Up 0.5 0.5 0.6 0.7 1.0 ns
fMAX Flip-Flop (Latch) Clock
Frequency 215 195 179 156 94 MHz
Input Module Propagation Delays
tINYH Pad-to-Y HIGH 1.1 1.2 1.3 1.6 2.2 ns
tINYL Pad-to-Y LOW 0.8 0.9 1.0 1.2 1.7 ns
tINGH G to Y HIGH 1.4 1.6 1.8 2.1 2.9 ns
tINGL G to Y LOW 1.4 1.6 1.8 2.1 2.9 ns
Input Module Predicted Routing Delays2
tIRD1 FO = 1 Routing Delay 1.8 2.0 2.3 2.7 4.0 ns
tIRD2 FO = 2 Routing Delay 2.1 2.3 2.6 3.1 4.3 ns
tIRD3 FO = 3 Routing Delay 2.3 2.6 3.0 3.5 4.9 ns
tIRD4 FO = 4 Routing Delay 2.6 3.0 3.3 3.9 5.4 ns
tIRD8 FO = 8 Routing Delay 3.6 4.0 4.6 5.4 7.5 ns
Global Clock Network
tCKH Input LOW to HIGH FO = 32
FO = 384 2.6
2.9 2.9
3.2 3.3
3.6 3.9
4.3 5.4
6.0 ns
ns
tCKL Input HIGH to LOW FO = 32
FO = 384 3.8
4.5 4.2
5.0 4.8
5.6 5.6
6.6 7.8
9.2 ns
ns
tPWH Minimum Pulse
Width HIGH FO = 32
FO = 384 3.2
3.7 3.5
4.1 4.0
4.6 4.7
5.4 6.6
7.6 ns
ns
Table 40 A42MX16 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70°C) (continued)
Parameter / Description
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
G Micmsemi. Power Matters:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 64
tPWL Minimum Pulse
Width LOW FO = 32
FO = 384 3.2
3.7 3.5
4.1 4.0
4.6 4.7
5.4 6.6
7.6 ns
ns
tCKSW Maximum Skew FO = 32
FO = 384 0.3
0.3 0.4
0.4 0.4
0.4 0.5
0.5 0.7
0.7 ns
ns
tSUEXT Input Latch External
Set-Up FO = 32
FO = 384 0.0
0.0 0.0
0.0 0.0
0.0 0.0
0.0 0.0
0.0 ns
ns
tHEXT Input Latch External
Hold FO = 32
FO = 384 2.8
3.2 3.1
3.5 5.5
4.0 4.1
4.7 5.7
6.6 ns
ns
tPMinimum Period FO = 32
FO = 384 4.2
4.6 4.67
5.1 5.1
5.6 5.8
6.4 9.7
10.7 ns
ns
fMAX Maximum Frequency FO = 32
FO = 384 237
215 215
195 198
179 172
156 103
94 MHz
MHz
Table 40 A42MX16 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70°C) (continued)
Parameter / Description
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
G Microsemi. Power Matters:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 65
TTL Output Module Timing4
tDLH Data-to-Pad HIGH 2.5 2.8 3.2 3.7 5.2 ns
tDHL Data-to-Pad LOW 3.0 3.3 3.7 4.4 6.1 ns
tENZH Enable Pad Z to HIGH 2.7 3.0 3.4 4.0 5.6 ns
tENZL Enable Pad Z to LOW 3.0 3.3 3.8 4.4 6.2 ns
tENHZ Enable Pad HIGH to Z 5.4 6.0 6.8 8.0 11.2 ns
tENLZ Enable Pad LOW to Z 5.0 5.6 6.3 7.4 10.4 ns
tGLH G-to-Pad HIGH 2.9 3.2 3.6 4.3 6.0 ns
tGHL G-to-Pad LOW 2.9 3.2 3.6 4.3 6.0 ns
tLCO I/O Latch Clock-to-Out
(Pad-to-Pad), 64 Clock Loading 5.7 6.3 7.1 8.4 11.9 ns
tACO Array Clock-to-Out
(Pad-to-Pad), 64 Clock Loading 8.0 8.9 10.1 11.9 16.7 ns
dTLH Capacitive Loading, LOW to
HIGH 0.03 0.03 0.03 0.04 0.06 ns/pF
dTHL Capacitive Loading, HIGH to
LOW 0.04 0.04 0.04 0.05 0.07 ns/pF
Table 40 A42MX16 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70°C) (continued)
Parameter / Description
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
G Microsemi. Power Matters:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 66
CMOS Output Module Timing5
tDLH Data-to-Pad HIGH 3.2 3.6 4.0 4.7 6.6 ns
tDHL Data-to-Pad LOW 2.5 2.7 3.1 3.6 5.1 ns
tENZH Enable Pad Z to HIGH 2.7 3.0 3.4 4.0 5.6 ns
tENZL Enable Pad Z to LOW 3.0 3.3 3.8 4.4 6.2 ns
tENHZ Enable Pad HIGH to Z 5.4 6.0 6.8 8.0 11.2 ns
tENLZ Enable Pad LOW to Z 5.0 5.6 6.3 7.4 10.4 ns
tGLH G-to-Pad HIGH 5.1 5.6 6.4 7.5 10.5 ns
tGHL G-to-Pad LOW 5.1 5.6 6.4 7.5 10.5 ns
tLCO I/O Latch Clock-to-Out
(Pad-to-Pad), 64 Clock Loading 5.7 6.3 7.1 8.4 11.9 ns
tACO Array Clock-to-Out
(Pad-to-Pad), 64 Clock Loading 8.0 8.9 10.1 11.9 16.7 ns
dTLH Capacitive Loading, LOW to
HIGH 0.03 0.03 0.03 0.04 0.06 ns/pF
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, point and position whichever is
appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External
setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD
signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading
Table 41 • A42MX16 Timing Characteristics (Nominal 3.3 V Operation)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, TJ = 70°C)
Parameter / Description
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Logic Module Propagation Delays1
tPD1 Single Module 1.9 2.1 2.4 2.8 4.0 ns
tCO Sequential Clock-to-Q 2.0 2.2 2.5 3.0 4.2 ns
tGO Latch G-to-Q 1.9 2.1 2.4 2.8 4.0 ns
tRS Flip-Flop (Latch) Reset-to-Q 2.2 2.4 2.8 3.3 4.6 ns
Logic Module Predicted Routing Delays2
tRD1 FO = 1 Routing Delay 1.1 1.2 1.4 1.6 2.3 ns
tRD2 FO = 2 Routing Delay 1.5 1.6 1.8 2.1 3.0 ns
tRD3 FO = 3 Routing Delay 1.8 2.0 2.3 2.7 3.8 ns
tRD4 FO = 4 Routing Delay 2.2 2.4 2.7 3.2 4.5 ns
tRD8 FO = 8 Routing Delay 3.6 4.0 4.5 5.3 7.5 ns
Table 40 A42MX16 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70°C) (continued)
Parameter / Description
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
C: Microsemi. Power Matters:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 67
Logic Module Sequential Timing3, 4
tSUD Flip-Flop (Latch)
Data Input Set-Up 0.5 0.5 0.6 0.7 0.9 ns
tHD Flip-Flop (Latch) Data Input Hold 0.0 0.0 0.0 0.0 0.0 ns
tSUENA Flip-Flop (Latch) Enable Set-Up 1.0 1.1 1.2 1.4 2.0 ns
tHENA Flip-Flop (Latch) Enable Hold 0.0 0.0 0.0 0.0 0.0 ns
tWCLKA Flip-Flop (Latch)
Clock Active Pulse Width 4.8 5.3 6.0 7.1 9.9 ns
tWASYN Flip-Flop (Latch)
Asynchronous Pulse Width 6.2 6.9 7.9 9.2 12.9 ns
tAFlip-Flop Clock Input Period 9.5 10.6 12.0 14.1 19.8 ns
tINH Input Buffer Latch Hold 0.0 0.0 0.0 0.0 0.0 ns
tINSU Input Buffer Latch Set-Up 0.7 0.8 0.9 1.01 1.4 ns
tOUTH Output Buffer Latch Hold 0.0 0.0 0.0 0.0 0.0 ns
tOUTSU Output Buffer Latch Set-Up 0.7 0.8 0.89 1.01 1.4 ns
fMAX Flip-Flop (Latch) Clock
Frequency 129 117 108 94 56 MHz
Input Module Propagation Delays
tINYH Pad-to-Y HIGH 1.5 1.6 1.9 2.2 3.1 ns
tINYL Pad-to-Y LOW 1.1 1.3 1.4 1.7 2.4 ns
tINGH G to Y HIGH 2.0 2.2 2.5 2.9 4.1 ns
tINGL G to Y LOW 2.0 2.2 2.5 2.9 4.1 ns
Input Module Predicted Routing Delays2
tIRD1 FO = 1 Routing
Delay 2.62.93.23.85.3ns
tIRD2 FO = 2 Routing
Delay 2.93.23.74.36.1ns
tIRD3 FO = 3 Routing
Delay 3.33.64.14.96.8ns
tIRD4 FO = 4 Routing
Delay 3.64.04.65.47.6ns
tIRD8 FO = 8 Routing
Delay 5.1 5.6 6.4 7.5 10.5 ns
Global Clock Network
tCKH Input LOW to HIGH FO = 32
FO = 384 4.4
4.8 4.8
5.3 5.5
6.0 6.5
7.1 9.0
9.9 ns
ns
tCKL Input HIGH to LOW FO = 32
FO = 384 5.3
6.2 5.9
6.9 6.7
7.9 7.8
9.2 11.0
12.9 ns
ns
tPWH Minimum Pulse
Width HIGH FO = 32
FO = 384 5.7
6.6 6.3
7.4 7.1
8.3 8.4
9.8 11.8
13.7 ns
ns
Table 41 • A42MX16 Timing Characteristics (Nominal 3.3 V Operation)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, TJ = 70°C) (continued)
Parameter / Description
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
C: Microsemi. Power Matters:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 68
tPWL Minimum Pulse
Width LOW FO = 32
FO = 384 5.3
6.2 5.9
6.9 6.7
7.9 7.8
9.2 11.0
12.9 ns
ns
tCKSW Maximum Skew FO = 32
FO = 384 0.5
2.2 0.5
2.4 0.6
2.7 0.7
3.2 1.0
4.5 ns
ns
tSUEXT Input Latch External
Set-Up FO = 32
FO = 384 0.0
0.0 0.0
0.0 0.0
0.0 0.0
0.0 0.0
0.0 ns
ns
tHEXT Input Latch External
Hold FO = 32
FO = 384 3.9
4.5 4.3
4.9 4.9
5.6 5.7
6.6 8.0
9.2 ns
ns
tPMinimum Period FO = 32
FO = 384 7.0
7.7 7.8
8.6 8.4
9.3 9.7
10.7 16.2
17.8 ns
ns
fMAX Maximum
Frequency FO = 32
FO = 384 142
129 129
117 119
108 103
94 62
56 MHz
MHz
TTL Output Module Timing5
tDLH Data-to-Pad HIGH 3.5 3.9 4.4 5.2 7.3 ns
tDHL Data-to-Pad LOW 4.1 4.6 5.2 6.1 8.6 ns
tENZH Enable Pad Z to HIGH 3.8 4.2 4.8 5.6 7.8 ns
tENZL Enable Pad Z to LOW 4.2 4.6 5.3 6.2 8.7 ns
tENHZ Enable Pad HIGH to Z 7.6 8.4 9.5 11.2 15.7 ns
tENLZ Enable Pad LOW to Z 7.0 7.8 8.8 10.4 14.5 ns
tGLH G-to-Pad HIGH 4.8 5.3 6.0 7.2 10.0 ns
tGHL G-to-Pad LOW 4.8 5.3 6.0 7.2 10.0 ns
tLCO I/O Latch Clock-to-Out
(Pad-to-Pad), 64 Clock Loading 8.0 8.9 10.1 11.9 16.7 ns
tACO Array Clock-to-Out
(Pad-to-Pad), 64 Clock Loading 11.3 12.5 14.2 16.7 23.3 ns
dTLH Capacitive Loading, LOW to
HIGH 0.04 0.04 0.05 0.06 0.08 ns/pF
dTHL Capacitive Loading, HIGH to
LOW 0.05 0.05 0.06 0.07 0.10 ns/pF
CMOS Output Module Timing5
tDLH Data-to-Pad HIGH 4.5 5.0 5.6 6.6 9.3 ns
tDHL Data-to-Pad LOW 3.4 3.8 4.3 5.1 7.1 ns
tENZH Enable Pad Z to HIGH 3.8 4.2 4.8 5.6 7.8 ns
tENZL Enable Pad Z to LOW 4.2 4.6 5.3 6.2 8.7 ns
tENHZ Enable Pad HIGH to Z 7.6 8.4 9.5 11.2 15.7 ns
tENLZ Enable Pad LOW to Z 7.0 7.8 8.8 10.4 14.5 ns
tGLH G-to-Pad HIGH 7.1 7.9 8.9 10.5 14.7 ns
tGHL G-to-Pad LOW 7.1 7.9 8.9 10.5 14.7 ns
tLCO I/O Latch Clock-to-Out
(Pad-to-Pad), 64 Clock Loading 8.0 8.9 10.1 11.9 16.7 ns
Table 41 • A42MX16 Timing Characteristics (Nominal 3.3 V Operation)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, TJ = 70°C) (continued)
Parameter / Description
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
G Microsemi. Power Matters:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 69
tACO Array Clock-to-Out
(Pad-to-Pad),64 Clock Loading 11.3 12.5 14.2 16.7 23.3 ns
dTLH Capacitive Loading, LOW to
HIGH 0.04 0.04 0.05 0.06 0.08 ns/pF
dTHL Capacitive Loading, HIGH to
LOW 0.05 0.05 0.06 0.07 0.10 ns/pF
1. For dual-module macros use tPD1 + tRD1 + taped, to + tRD1 + taped, or tPD1 + tRD1 + tusk, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing ansalysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External
setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD
signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
Table 42 • A42MX24 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70°C)
Parameter / Description
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Logic Module Combinatorial Functions1
tPD Internal Array Module Delay 1.2 1.3 1.5 1.8 2.5 ns
tPDD Internal Decode Module Delay 1.4 1.6 1.8 2.1 3.0 ns
Logic Module Predicted Routing Delays2
tRD1 FO = 1 Routing Delay 0.8 0.9 1.0 1.2 1.7 ns
tRD2 FO = 2 Routing Delay 1.0 1.2 1.3 1.5 2.1 ns
tRD3 FO = 3 Routing Delay 1.3 1.4 1.6 1.9 2.6 ns
tRD4 FO = 4 Routing Delay 1.5 1.7 1.9 2.2 3.1 ns
tRD5 FO = 8 Routing Delay 2.4 2.7 3.0 3.6 5.0 ns
Logic Module Sequential Timing3, 4
tCO Flip-Flop Clock-to-Output 1.3 1.4 1.6 1.9 2.7 ns
tGO Latch Gate-to-Output 1.2 1.3 1.5 1.8 2.5 ns
tSUD Flip-Flop (Latch) Set-Up Time 0.3 0.4 0.4 0.5 0.7 ns
tHD Flip-Flop (Latch) Hold Time 0.0 0.0 0.0 0.0 0.0 ns
tRO Flip-Flop (Latch) Reset-to-Output 1.4 1.6 1.8 2.1 2.9 ns
tSUENA Flip-Flop (Latch) Enable Set-Up 0.4 0.5 0.5 0.6 0.8 ns
tHENA Flip-Flop (Latch) Enable Hold 0.0 0.0 0.0 0.0 0.0 ns
tWCLKA Flip-Flop (Latch)
Clock Active Pulse Width 3.33.7 4.24.9 6.9 ns
tWASYN Flip-Flop (Latch)
Asynchronous Pulse Width 4.44.8 5.36.5 9.0 ns
Table 41 • A42MX16 Timing Characteristics (Nominal 3.3 V Operation)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, TJ = 70°C) (continued)
Parameter / Description
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
G Micmsemi. Power Matters:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 70
Input Module Propagation Delays
tINPY Input Data Pad-to-Y 1.0 1.1 1.3 1.5 2.1 ns
tINGO Input Latch Gate-to-Output 1.3 1.4 1.6 1.9 2.6 ns
tINH Input Latch Hold 0.0 0.0 0.0 0.0 0.0 ns
tINSU Input Latch Set-Up 0.5 0.5 0.6 0.7 1.0 ns
tILA Latch Active Pulse Width 4.7 5.2 5.9 6.9 9.7 ns
Table 42 • A42MX24 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70°C) (continued)
Parameter / Description
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
G Microsemi. Power Matters:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 71
Input Module Predicted Routing Delays2
tIRD1 FO = 1 Routing Delay 1.8 2.0 2.3 2.7 3.8 ns
tIRD2 FO = 2 Routing Delay 2.1 2.3 2.6 3.1 4.3 ns
tIRD3 FO = 3 Routing Delay 2.3 2.5 2.9 3.4 4.8 ns
tIRD4 FO = 4 Routing Delay 2.5 2.8 3.2 3.7 5.2 ns
tIRD8 FO = 8 Routing Delay 3.4 3.8 4.3 5.1 7.1 ns
Global Clock Network
tCKH Input LOW to HIGH FO = 32
FO = 486 2.6
2.9 2.9
3.2 3.3
3.6 3.9
4.3 5.4
5.9 ns
ns
tCKL Input HIGH to LOW FO = 32
FO = 486 3.7
4.3 4.1
4.7 4.6
5.4 5.4
6.3 7.6
8.8 ns
ns
tPWH Minimum Pulse
Width HIGH FO = 32
FO = 486 2.2
2.4 2.4
2.6 2.7
3.0 3.2
3.5 4.5
4.9 ns
ns
tPWL Minimum Pulse
Width LOW FO = 32
FO = 486 2.2
2.4 2.4
2.6 2.7
3.0 3.2
3.5 4.5
4.9 ns
ns
tCKSW Maximum Skew FO = 32
FO = 486 0.5
0.5 0.6
0.6 0.7
0.7 0.8
0.8 1.1
1.1 ns
ns
tSUEXT Input Latch External
Set-Up FO = 32
FO = 486 0.0
0.0 0.0
0.0 0.0
0.0 0.0
0.0 0.0
0.0 ns
ns
tHEXT Input Latch External
Hold FO = 32
FO = 486 2.8
3.3 3.1
3.7 3.5
4.2 4.1
4.9 5.7
6.9 ns
ns
tPMinimum Period
(1/fMAX)FO = 32
FO = 486 4.7
5.1 5.2
5.7 5.7
6.2 6.5
7.1 10.9
11.9 ns
ns
Table 42 • A42MX24 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70°C) (continued)
Parameter / Description
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
G Microsemi. Power Matters:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 72
TTL Output Module Timing5
tDLH Data-to-Pad HIGH 2.4 2.7 3.1 3.6 5.1 ns
tDHL Data-to-Pad LOW 2.8 3.2 3.6 4.2 5.9 ns
tENZH Enable Pad Z to HIGH 2.5 2.8 3.2 3.8 5.3 ns
tENZL Enable Pad Z to LOW 2.8 3.1 3.5 4.2 5.9 ns
tENHZ Enable Pad HIGH to Z 5.2 5.7 6.5 7.6 10.7 ns
tENLZ Enable Pad LOW to Z 4.8 5.3 6.0 7.1 9.9 ns
tGLH G-to-Pad HIGH 2.9 3.2 3.6 4.3 6.0 ns
tGHL G-to-Pad LOW 2.9 3.2 3.6 4.3 6.0 ns
tLSU I/O Latch Output Set-Up 0.5 0.5 0.6 0.7 1.0 ns
tLH I/O Latch Output Hold 0.0 0.0 0.0 0.0 0.0 ns
tLCO I/O Latch Clock-to-Out
(Pad-to-Pad) 32 I/O 5.6 6.1 6.9 8.1 11.4 ns
tACO Array Latch Clock-to-Out
(Pad-to-Pad) 32 I/O 10.6 11.8 13.4 15.7 22.0 ns
dTLH Capacitive Loading, LOW to HIGH 0.04 0.04 0.04 0.05 0.07 ns/pF
dTHL Capacitive Loading, HIGH to LOW 0.03 0.03 0.03 0.04 0.06 ns/pF
Table 42 • A42MX24 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70°C) (continued)
Parameter / Description
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
G Microsemi. Power Matters:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 73
CMOS Output Module Timing5
tDLH Data-to-Pad HIGH 3.1 3.5 3.9 4.6 6.4 ns
tDHL Data-to-Pad LOW 2.4 2.6 3.0 3.5 4.9 ns
tENZH Enable Pad Z to HIGH 2.5 2.8 3.2 3.8 5.3 ns
tENZL Enable Pad Z to LOW 2.8 3.1 3.5 4.2 5.8 ns
tENHZ Enable Pad HIGH to Z 5.2 5.7 6.5 7.6 10.7 ns
tENLZ Enable Pad LOW to Z 4.8 5.3 6.0 7.1 9.9 ns
tGLH G-to-Pad HIGH 4.9 5.4 6.2 7.2 10.1 ns
tGHL G-to-Pad LOW 4.9 5.4 6.2 7.2 10.1 ns
tLSU I/O Latch Set-Up 0.5 0.5 0.6 0.7 1.0 ns
tLH I/O Latch Hold 0.0 0.0 0.0 0.0 0.0 ns
tLCO I/O Latch Clock-to-Out
(Pad-to-Pad) 32 I/O 5.5 6.1 6.9 8.1 11.3 ns
tACO Array Latch Clock-to-Out
(Pad-to-Pad) 32 I/O 10.6 11.8 13.4 15.7 22.0 ns
dTLH Capacitive Loading, LOW to HIGH 0.04 0.04 0.04 0.05 0.07 ns/pF
dTHL Capacitive Loading, HIGH to LOW 0.03 0.03 0.03 0.04 0.06 ns/pF
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External
setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD
signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading
Table 43 • A42MX24 Timing Characteristics (Nominal 3.3 V Operation)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, TJ = 70°C)
Parameter / Description
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Logic Module Combinatorial Functions1
tPD Internal Array Module Delay 2.0 1.8 2.1 2.5 3.4 ns
tPDD Internal Decode Module Delay 1.1 2.2 2.5 3.0 4.2 ns
Logic Module Predicted Routing Delays2
tRD1 FO = 1 Routing Delay 1.7 1.3 1.4 1.7 2.3 ns
tRD2 FO = 2 Routing Delay 2.0 1.6 1.8 2.1 3.0 ns
tRD3 FO = 3 Routing Delay 1.1 2.0 2.2 2.6 3.7 ns
tRD4 FO = 4 Routing Delay 1.5 2.3 2.6 3.1 4.3 ns
tRD5 FO = 8 Routing Delay 1.8 3.7 4.2 5.0 7.0 ns
Table 42 • A42MX24 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70°C) (continued)
Parameter / Description
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
C} Microsemi. Power Matters:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 74
Logic Module Sequential Timing3, 4
tCO Flip-Flop Clock-to-Output 2.1 2.0 2.3 2.7 3.7 ns
tGO Latch Gate-to-Output 3.4 1.9 2.1 2.5 3.4 ns
tSUD Flip-Flop (Latch) Set-Up Time 0.4 0.5 0.6 0.7 0.9 ns
tHD Flip-Flop (Latch) Hold Time 0.0 0.0 0.0 0.0 0.0 ns
tRO Flip-Flop (Latch) Reset-to-Output 2.0 2.2 2.5 2.9 4.1 ns
tSUENA Flip-Flop (Latch) Enable Set-Up 0.6 0.6 0.7 0.8 1.2 ns
tHENA Flip-Flop (Latch) Enable Hold 0.0 0.0 0.0 0.0 0.0 ns
tWCLKA Flip-Flop (Latch)
Clock Active Pulse Width 4.6 5.2 5.8 6.9 9.6 ns
tWASYN Flip-Flop (Latch)
Asynchronous Pulse Width 6.1 6.8 7.7 9.0 12.6 ns
Input Module Propagation Delays
tINPY Input Data Pad-to-Y 1.4 1.6 1.8 2.2 3.0 ns
tINGO Input Latch Gate-to-Output 1.8 1.9 2.2 2.6 3.6 ns
tINH Input Latch Hold 0.0 0.0 0.0 0.0 0.0 ns
tINSU Input Latch Set-Up 0.7 0.7 0.8 1.0 1.4 ns
tILA Latch Active Pulse Width 6.5 7.3 8.2 9.7 13.5 ns
Table 43 • A42MX24 Timing Characteristics (Nominal 3.3 V Operation)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, TJ = 70°C) (continued)
Parameter / Description
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
G Microsemi. Power Matters:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 75
Input Module Predicted Routing Delays2
tIRD1 FO = 1 Routing Delay 2.6 2.9 3.2 3.8 5.3 ns
tIRD2 FO = 2 Routing Delay 2.9 3.2 3.6 4.3 6.0 ns
tIRD3 FO = 3 Routing Delay 3.2 3.6 4.0 4.8 6.6 ns
tIRD4 FO = 4 Routing Delay 3.5 3.9 4.4 5.2 7.3 ns
tIRD8 FO = 8 Routing Delay 4.8 5.3 6.1 7.1 10.0 ns
Global Clock Network
tCKH Input LOW to HIGH FO = 32
FO = 486 4.4
4.8 4.8
5.3 5.5
6.0 6.5
7.1 9.1
10.0 ns
ns
tCKL Input HIGH to LOW FO = 32
FO = 486 5.1
6.0 5.7
6.6 6.4
7.5 7.6
8.8 10.6
12.4 ns
ns
tPWH Minimum Pulse
Width HIGH FO = 32
FO = 486 3.0
3.3 3.3
3.7 3.8
4.2 4.5
4.9 6.3
6.9 ns
ns
tPWL Minimum Pulse
Width LOW FO = 32
FO = 486 3.0
3.3 3.4
3.7 3.8
4.2 4.5
4.9 6.3
6.9 ns
ns
tCKSW Maximum Skew FO = 32
FO = 486 0.8
0.8 0.8
0.8 1.0
1.0 1.1
1.1 1.6
1.6 ns
ns
tSUEXT Input Latch External
Set-Up FO = 32
FO = 486 0.0
0.0 0.0
0.0 0.0
0.0 0.0
0.0 0.0
0.0 ns
ns
TTL Output Module Timing5
tDLH Data-to-Pad HIGH 3.4 3.8 4.3 5.0 7.1 ns
tDHL Data-to-Pad LOW 4.0 4.4 5.0 5.9 8.3 ns
tENZH Enable Pad Z to HIGH 3.6 4.0 4.5 5.3 7.4 ns
tENZL Enable Pad Z to LOW 3.9 4.4 5.0 5.8 8.2 ns
tENHZ Enable Pad HIGH to Z 7.2 8.0 9.1 10.7 14.9 ns
tENLZ Enable Pad LOW to Z 6.7 7.5 8.5 9.9 13.9 ns
tGLH G-to-Pad HIGH 4.8 5.3 6.0 7.2 10.0 ns
tGHL G-to-Pad LOW 4.8 5.3 6.0 7.2 10.0 ns
tLSU I/O Latch Output Set-Up 0.7 0.7 0.8 1.0 1.4 ns
Table 43 • A42MX24 Timing Characteristics (Nominal 3.3 V Operation)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, TJ = 70°C) (continued)
Parameter / Description
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
G Microsemi. Power Matters:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 76
TTL Output Module Timing5
tLH I/O Latch Output Hold 0.0 0.0 0.0 0.0 0.0 ns
tLCO I/O Latch Clock-to-Out
(Pad-to-Pad) 32 I/O 7.7 8.5 9.6 11.3 15.9 ns
tACO Array Latch Clock-to-Out
(Pad-to-Pad) 32 I/O 14.8 16.5 18.7 22.0 30.8 ns
dTLH Capacitive Loading, LOW to HIGH 0.05 0.05 0.06 0.07 0.10 ns/pF
dTHL Capacitive Loading, HIGH to LOW 0.04 0.04 0.05 0.06 0.08 ns/pF
CMOS Output Module Timing5
tDLH Data-to-Pad HIGH 4.8 5.3 5.5 6.4 9.0 ns
tDHL Data-to-Pad LOW 3.5 3.9 4.1 4.9 6.8 ns
tENZH Enable Pad Z to HIGH 3.6 4.0 4.5 5.3 7.4 ns
tENZL Enable Pad Z to LOW 3.4 4.0 5.0 5.8 8.2 ns
tENHZ Enable Pad HIGH to Z 7.2 8.0 9.0 10.7 14.9 ns
tENLZ Enable Pad LOW to Z 6.7 7.5 8.5 9.9 13.9 ns
tGLH G-to-Pad HIGH 6.8 7.6 8.6 10.1 14.2 ns
tGHL G-to-Pad LOW 6.8 7.6 8.6 10.1 14.2 ns
tLSU I/O Latch Set-Up 0.7 0.7 0.8 1.0 1.4 ns
tLH I/O Latch Hold 0.0 0.0 0.0 0.0 0.0 ns
tLCO I/O Latch Clock-to-Out
(Pad-to-Pad) 32 I/O 7.7 8.5 9.6 11.3 15.9 ns
tACO Array Latch Clock-to-Out
(Pad-to-Pad) 32 I/O 14.8 16.5 18.7 22.0 30.8 ns
dTLH Capacitive Loading, LOW to HIGH 0.05 0.05 0.06 0.07 0.10 ns/pF
dTHL Capacitive Loading, HIGH to LOW 0.04 0.04 0.05 0.06 0.08 ns/pF
tHEXT Input Latch External
Hold FO = 32
FO = 486 3.9
4.6 4.3
5.2 4.9
5.8 5.7
6.9 8.1
9.6 ns
ns
tPMinimum Period
(1/fMAX)FO = 32
FO = 486 7.8
8.6 8.7
9.5 9.5
10.4 10.8
11.9 18.2
19.9 ns
ns
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External
setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD
signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
Table 43 • A42MX24 Timing Characteristics (Nominal 3.3 V Operation)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, TJ = 70°C) (continued)
Parameter / Description
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
C: Microsemi. Power Matters:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 77
Table 44 • A42MX36 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70°C)
Parameter / Description
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Logic Module Combinatorial Functions1
tPD Internal Array Module Delay 1.3 1.5 1.7 2.0 2.7 ns
tPDD Internal Decode Module Delay 1.6 1.8 2.0 2.4 3.3 ns
Logic Module Predicted Routing Delays2
tRD1 FO = 1 Routing Delay 0.9 1.0 1.2 1.4 2.0 ns
tRD2 FO = 2 Routing Delay 1.3 1.4 1.6 1.9 2.7 ns
tRD3 FO =3 Routing Delay 1.6 1.8 2.0 2.4 3.4 ns
tRD4 FO = 4 Routing Delay 2.0 2.2 2.5 2.9 4.1 ns
tRD5 FO = 8 Routing Delay 3.3 3.7 4.2 4.9 6.9 ns
tRDD Decode-to-Output Routing Delay 0.3 0.4 0.4 0.5 0.7 ns
Logic Module Sequential Timing3, 4
tCO Flip-Flop Clock-to-Output 1.3 1.4 1.6 1.9 2.7 ns
tGO Latch Gate-to-Output 1.3 1.4 1.6 1.9 2.7 ns
tSUD Flip-Flop (Latch) Set-Up Time 0.3 0.3 0.4 0.5 0.7 ns
tHD Flip-Flop (Latch) Hold Time 0.0 0.0 0.0 0.0 0.0 ns
tRO Flip-Flop (Latch) Reset-to-Output 1.6 1.7 2.0 2.3 3.2 ns
tSUENA Flip-Flop (Latch) Enable Set-Up 0.7 0.8 0.9 1.0 1.4 ns
tHENA Flip-Flop (Latch) Enable Hold 0.0 0.0 0.0 0.0 0.0 ns
tWCLKA Flip-Flop (Latch) Clock Active
Pulse Width 3.3 3.7 4.2 4.9 6.9 ns
tWASYN Flip-Flop (Latch) Asynchronous
Pulse Width 4.4 4.8 5.5 6.4 9.0 ns
Synchronous SRAM Operations
tRC Read Cycle Time 6.8 7.5 8.5 10.0 14.0 ns
tWC Write Cycle Time 6.8 7.5 8.5 10.0 14.0 ns
tRCKHL Clock HIGH/LOW Time 3.4 3.8 4.3 5.0 7.0 ns
tRCO Data Valid After Clock
HIGH/LOW 3.4 3.8 4.3 5.0 7.0 ns
tADSU Address/Data Set-Up Time 1.6 1.8 2.0 2.4 3.4 ns
Synchronous SRAM Operations
tADH Address/Data Hold Time 0.0 0.0 0.0 0.0 0.0 ns
tRENSU Read Enable Set-Up 0.6 0.7 0.8 0.9 1.3 ns
tRENH Read Enable Hold 3.4 3.8 4.3 5.0 7.0 ns
tWENSU Write Enable Set-Up 2.7 3.0 3.4 4.0 5.6 ns
tWENH Write Enable Hold 0.0 0.0 0.0 0.0 0.0 ns
tBENS Block Enable Set-Up 2.8 3.1 3.5 4.1 5.7 ns
tBENH Block Enable Hold 0.0 0.0 0.0 0.0 0.0 ns
C: Microsemi. Power Matters:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 78
Asynchronous SRAM Operations
tRPD Asynchronous Access Time 8.1 9.0 10.2 12.0 16.8 ns
tRDADV Read Address Valid 8.8 9.8 11.1 13.0 18.2 ns
tADSU Address/Data Set-Up Time 1.6 1.8 2.0 2.4 3.4 ns
tADH Address/Data Hold Time 0.0 0.0 0.0 0.0 0.0 ns
tRENSUA Read Enable Set-Up to Address
Valid 0.6 0.7 0.8 0.9 1.3 ns
tRENHA Read Enable Hold 3.4 3.8 4.3 5.0 7.0 ns
tWENSU Write Enable Set-Up 2.7 3.0 3.4 4.0 5.6 ns
tWENH Write Enable Hold 0.0 0.0 0.0 0.0 0.0 ns
tDOH Data Out Hold Time 1.2 1.3 1.5 1.8 2.5 ns
Input Module Propagation Delays
tINPY Input Data Pad-to-Y 1.0 1.1 1.3 1.5 2.1 ns
tINGO Input Latch Gate-to-Output 1.4 1.6 1.8 2.1 2.9 ns
tINH Input Latch Hold 0.0 0.0 0.0 0.0 0.0 ns
tINSU Input Latch Set-Up 0.5 0.5 0.6 0.7 1.0 ns
tILA Latch Active Pulse Width 4.7 5.2 5.9 6.9 9.7 ns
Input Module Predicted Routing Delays2
tIRD1 FO = 1 Routing
Delay 2.0 2.2 2.5 2.9 4.1 ns
tIRD2 FO = 2 Routing
Delay 2.3 2.6 2.9 3.4 4.8 ns
tIRD3 FO = 3 Routing
Delay 2.6 2.9 3.3 3.9 5.5 ns
tIRD4 FO = 4 Routing
Delay 3.0 3.3 3.8 4.4 6.2 ns
tIRD8 FO = 8 Routing
Delay 4.3 4.8 5.5 6.4 9.0 ns
Global Clock Network
tCKH Input LOW to HIGH FO = 32
FO = 635 2.7
3.0 3.0
3.3 3.4
3.8 4.0
4.4 5.6
6.2 ns
ns
tCKL Input HIGH to LOW FO = 32
FO = 635 3.8
4.9 4.2
5.4 4.8
6.1 5.6
7.2 7.8
10.1 ns
ns
tPWH Minimum Pulse
Width HIGH FO = 32
FO = 635 1.8
2.0 2.0
2.2 2.2
2.5 2.6
2.9 3.6
4.1 ns
ns
tPWL Minimum Pulse
Width LOW FO = 32
FO = 635 1.8
2.0 2.0
2.2 2.2
2.5 2.6
2.9 3.6
4.1 ns
ns
tCKSW Maximum Skew FO = 32
FO = 635 0.8
0.8 0.8
0.8 0.9
0.9 1.0
1.0 1.4
1.4 ns
ns
Table 44 • A42MX36 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70°C) (continued)
Parameter / Description
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
G Microsemi. Power Matters:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 79
tSUEXT Input Latch External
Set-Up FO = 32
FO = 635 0.0
0.0 0.0
0.0 0.0
0.0 0.0
0.0 0.0
0.0 ns
ns
tHEXT Input Latch External
Hold FO = 32
FO = 635 2.8
3.3 3.2
3.7 3.6
4.2 4.2
4.9 5.9
6.9 ns
ns
tPMinimum Period
(1/fMAX)FO = 32
FO = 635 5.5
6.0 6.1
6.6 6.6
7.2 7.6
8.3 12.7
13.8 ns
ns
fMAX Maximum Datapath
Frequency FO = 32
FO = 635 180
166 164
151 151
139 131
121 79
73 MHz
MHz
TTL Output Module Timing5
tDLH Data-to-Pad HIGH 2.6 2.8 3.2 3.8 5.3 ns
tDHL Data-to-Pad LOW 3.0 3.3 3.7 4.4 6.2 ns
tENZH Enable Pad Z to HIGH 2.7 3.0 3.3 3.9 5.5 ns
tENZL Enable Pad Z to LOW 3.0 3.3 3.7 4.3 6.1 ns
tENHZ Enable Pad HIGH to Z 5.3 5.8 6.6 7.8 10.9 ns
Table 44 • A42MX36 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70°C) (continued)
Parameter / Description
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
G Microsemi. Power Matters:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 80
TTL Output Module Timing5
tENLZ Enable Pad LOW to Z 4.9 5.5 6.2 7.3 10.2 ns
tGLH G-to-Pad HIGH 2.9 3.3 3.7 4.4 6.1 ns
tGHL G-to-Pad LOW 2.9 3.3 3.7 4.4 6.1 ns
tLSU I/O Latch Output Set-Up 0.5 0.5 0.6 0.7 1.0 ns
tLH I/O Latch Output Hold 0.0 0.0 0.0 0.0 0.0 ns
tLCO I/O Latch Clock-to-Out
(Pad-to-Pad) 32 I/O 5.7 6.3 7.1 8.4 11.8 ns
tACO Array Latch Clock-to-Out
(Pad-to-Pad) 32 I/O 7.8 8.6 9.8 11.5 16.1 ns
dTLH Capacitive Loading,
LOW to HIGH 0.07 0.08 0.09 0.10 0.14 ns/pF
dTHL Capacitive Loading,
HIGH to LOW 0.07 0.08 0.09 0.10 0.14 ns/pF
Table 44 • A42MX36 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70°C) (continued)
Parameter / Description
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
G Microsemi. Power Matters:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 81
CMOS Output Module Timing5
tDLH Data-to-Pad HIGH 3.5 3.9 4.5 5.2 7.3 ns
tDHL Data-to-Pad LOW 2.5 2.7 3.1 3.6 5.1 ns
tENZH Enable Pad Z to HIGH 2.7 3.0 3.3 3.9 5.5 ns
tENZL Enable Pad Z to LOW 2.9 3.3 3.7 4.3 6.1 ns
tENHZ Enable Pad HIGH to Z 5.3 5.8 6.6 7.8 10.9 ns
tENLZ Enable Pad LOW to Z 4.9 5.5 6.2 7.3 10.2 ns
tGLH G-to-Pad HIGH 5.0 5.6 6.3 7.5 10.4 ns
tGHL G-to-Pad LOW 5.0 5.6 6.3 7.5 10.4 ns
tLSU I/O Latch Set-Up 0.5 0.5 0.6 0.7 1.0 ns
tLH I/O Latch Hold 0.0 0.0 0.0 0.0 0.0 ns
tLCO I/O Latch Clock-to-Out
(Pad-to-Pad) 32 I/O 5.7 6.3 7.1 8.4 11.8 ns
tACO Array Latch Clock-to-Out
(Pad-to-Pad) 32 I/O 7.8 8.6 9.8 11.5 16.1 ns
dTLH Capacitive Loading,
LOW to HIGH 0.07 0.08 0.09 0.10 0.14 ns/pF
dTHL Capacitive Loading,
HIGH to LOW 0.07 0.08 0.09 0.10 0.14 ns/pF
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External
setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD
signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
Table 45 • A42MX36 Timing Characteristics (Nominal 3.3 V Operation)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, TJ = 70°C)
Parameter / Description
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Logic Module Combinatorial Functions1
tPD Internal Array Module Delay 1.9 2.1 2.3 2.7 3.8 ns
tPDD Internal Decode Module Delay 2.2 2.5 2.8 3.3 4.7 ns
Logic Module Predicted Routing Delays2
tRD1 FO = 1 Routing Delay 1.3 1.5 1.7 2.0 2.7 ns
tRD2 FO = 2 Routing Delay 1.8 2.0 2.3 2.7 3.7 ns
tRD3 FO = 3 Routing Delay 2.3 2.5 2.8 3.4 4.7 ns
tRD4 FO = 4 Routing Delay 2.8 3.1 3.5 4.1 5.7 ns
Table 44 • A42MX36 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70°C) (continued)
Parameter / Description
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
C} Microsemi. Power Matters:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 82
tRD5 FO = 8 Routing Delay 4.6 5.2 5.8 6.9 9.6 ns
tRDD Decode-to-Output Routing Delay 0.5 0.5 0.6 0.7 1.0 ns
Logic Module Sequential Timing3, 4
tCO Flip-Flop Clock-to-Output 1.8 2.0 2.3 2.7 3.7 ns
tGO Latch Gate-to-Output 1.8 2.0 2.3 2.7 3.7 ns
tSUD Flip-Flop (Latch) Set-Up Time 0.4 0.5 0.6 0.7 0.9 ns
tHD Flip-Flop (Latch) Hold Time 0.0 0.0 0.0 0.0 0.0 ns
tRO Flip-Flop (Latch) Reset-to-Output 2.2 2.4 2.7 3.2 4.5 ns
tSUENA Flip-Flop (Latch) Enable Set-Up 1.0 1.1 1.2 1.4 2.0 ns
tHENA Flip-Flop (Latch) Enable Hold 0.0 0.0 0.0 0.0 0.0 ns
tWCLKA Flip-Flop (Latch)
Clock Active Pulse Width 4.6 5.2 5.8 6.9 9.6 ns
tWASYN Flip-Flop (Latch)
Asynchronous Pulse Width 6.1 6.8 7.7 9.0 12.6 ns
Synchronous SRAM Operations
tRC Read Cycle Time 9.5 10.5 11.9 14.0 19.6 ns
tWC Write Cycle Time 9.5 10.5 11.9 14.0 19.6 ns
tRCKHL Clock HIGH/LOW Time 4.8 5.3 6.0 7.0 9.8 ns
tRCO Data Valid After Clock HIGH/LOW 4.8 5.3 6.0 7.0 9.8 ns
tADSU Address/Data Set-Up Time 2.3 2.5 2.8 3.4 4.8 ns
Table 45 • A42MX36 Timing Characteristics (Nominal 3.3 V Operation)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, TJ = 70°C) (continued)
Parameter / Description
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
G Microsemi. Power Matters:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 83
Synchronous SRAM Operations
tADH Address/Data Hold Time 0.0 0.0 0.0 0.0 0.0 ns
tRENSU Read Enable Set-Up 0.9 1.0 1.1 1.3 1.8 ns
tRENH Read Enable Hold 4.8 5.3 6.0 7.0 9.8 ns
tWENSU Write Enable Set-Up 3.8 4.2 4.8 5.6 7.8 ns
tWENH Write Enable Hold 0.0 0.0 0.0 0.0 0.0 ns
tBENS Block Enable Set-Up 3.9 4.3 4.9 5.7 8.0 ns
tBENH Block Enable Hold 0.0 0.0 0.0 0.0 0.0 ns
Asynchronous SRAM Operations
tRPD Asynchronous Access Time 11.3 12.6 14.3 16.8 23.5 ns
tRDADV Read Address Valid 12.3 13.7 15.5 18.2 25.5 ns
tADSU Address/Data Set-Up Time 2.3 2.5 2.8 3.4 4.8 ns
tADH Address/Data Hold Time 0.0 0.0 0.0 0.0 0.0 ns
tRENSUA Read Enable Set-Up to Address
Valid 0.9 1.0 1.1 1.3 1.8 ns
tRENHA Read Enable Hold 4.8 5.3 6.0 7.0 9.8 ns
tWENSU Write Enable Set-Up 3.8 4.2 4.8 5.6 7.8 ns
tWENH Write Enable Hold 0.0 0.0 0.0 0.0 0.0 ns
tDOH Data Out Hold Time 1.8 2.0 2.1 2.5 3.5 ns
Input Module Propagation Delays
tINPY Input Data Pad-to-Y 1.4 1.6 1.8 2.1 3.0 ns
tINGO Input Latch Gate-to-Output 2.0 2.2 2.5 2.9 4.1 ns
tINH Input Latch Hold 0.0 0.0 0.0 0.0 0.0 ns
tINSU Input Latch Set-Up 0.7 0.7 0.8 1.0 1.4 ns
tILA Latch Active Pulse Width 6.5 7.3 8.2 9.7 13.5 ns
Table 45 • A42MX36 Timing Characteristics (Nominal 3.3 V Operation)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, TJ = 70°C) (continued)
Parameter / Description
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
C: Microsemi. Power Matters:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 84
Input Module Predicted Routing Delays2
tIRD1 FO = 1 Routing Delay 2.8 3.1 3.5 4.1 5.7 ns
tIRD2 FO = 2 Routing Delay 3.2 3.5 4.1 4.8 6.7 ns
tIRD3 FO = 3 Routing Delay 3.7 4.1 4.7 5.5 7.7 ns
tIRD4 FO = 4 Routing Delay 4.2 4.6 5.3 6.2 8.7 ns
tIRD8 FO = 8 Routing Delay 6.1 6.8 7.7 9.0 12.6 ns
Global Clock Network
tCKH Input LOW to HIGH FO = 32
FO = 635 4.6
5.0 5.1
5.6 5.7
6.3 6.7
7.4 9.3
10.3 ns
ns
tCKL Input HIGH to LOW FO = 32
FO = 635 5.3
6.8 5.9
7.6 6.7
8.6 7.8
10.1 11.0
14.1 ns
ns
tPWH Minimum Pulse
Width HIGH FO = 32
FO = 635 2.5
2.8 2.7
3.1 3.1
3.5 3.6
4.1 5.1
5.7 ns
ns
tPWL Minimum Pulse
Width LOW FO = 32
FO = 635 2.5
2.8 2.7
3.1 3.1
3.5 3.6
4.1 5.1
5.7 ns
ns
tCKSW Maximum Skew FO = 32
FO = 635 1.0
1.0 1.2
1.2 1.3
1.3 1.5
1.5 2.2
2.2 ns
ns
tSUEXT Input Latch
External Set-Up FO = 32
FO = 635 0.0
0.0 0.0
0.0 0.0
0.0 0.0
0.0 0.0
0.0 ns
ns
tHEXT Input Latch
External Hold FO = 32
FO = 635 4.0
4.6 4.4
5.2 5.0
5.9 5.9
6.9 8.2
9.6 ns
ns
tPMinimum Period
(1/fMAX)FO = 32
FO = 635 9.2
9.9 10.2
11.0 11.1
12.0 12.7
13.8 21.2
23.0 ns
ns
fMAX Maximum Datapath
Frequency FO = 32
FO = 635 108
100 98
91 90
83 79
73 47
44 MHz
MHz
TTL Output Module Timing5
tDLH Data-to-Pad HIGH 3.6 4.0 4.5 5.3 7.4 ns
tDHL Data-to-Pad LOW 4.2 4.6 5.2 6.2 8.6 ns
tENZH Enable Pad Z to HIGH 3.7 4.2 4.7 5.5 7.7 ns
tENZL Enable Pad Z to LOW 4.1 4.6 5.2 6.1 8.5 ns
tENHZ Enable Pad HIGH to Z 7.34 8.2 9.3 10.9 15.3 ns
TTL Output Module Timing5
tENLZ Enable Pad LOW to Z 6.9 7.6 8.7 10.2 14.3 ns
tGLH G-to-Pad HIGH 4.9 5.5 6.2 7.3 10.2 ns
tGHL G-to-Pad LOW 4.9 5.5 6.2 7.3 10.2 ns
tLSU I/O Latch Output Set-Up 0.7 0.7 0.8 1.0 1.4 ns
tLH I/O Latch Output Hold 0.0 0.0 0.0 0.0 0.0 ns
tLCO I/O Latch Clock-to-Out
(Pad-to-Pad) 32 I/O 7.9 8.8 10.0 11.8 16.5 ns
Table 45 • A42MX36 Timing Characteristics (Nominal 3.3 V Operation)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, TJ = 70°C) (continued)
Parameter / Description
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
G Microsemi. Power Matters:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 85
3.12 Pin Descriptions
This section lists the pin descriptions for 40MX and 42MX series FPGAs.
CLK/A/B, I/O Global Clock
Clock inputs for clock distribution networks. CLK is for 40MX while CLKA and CLKB are for 42MX
devices. The clock input is buffered prior to clocking the logic modules. This pin can also be used as an
I/O.
DCLK, I/ODiagnostic Clock
Clock input for diagnostic probe and device programming. DCLK is active when the MODE pin is HIGH.
This pin functions as an I/O when the MODE pin is LOW.
GND, Ground
Input LOW supply voltage.
I/O, Input/Output
tACO Array Latch Clock-to-Out
(Pad-to-Pad) 32 I/O 10.9 12.1 13.7 16.1 22.5 ns
dTLH Capacitive Loading, LOW to HIGH 0.10 0.11 0.12 0.14 0.20 ns/pF
dTHL Capacitive Loading, HIGH to LOW 0.10 0.11 0.12 0.14 0.20 ns/pF
CMOS Output Module Timing5
tDLH Data-to-Pad HIGH 4.9 5.5 6.2 7.3 10.3 ns
tDHL Data-to-Pad LOW 3.4 3.8 4.3 5.1 7.1 ns
tENZH Enable Pad Z to HIGH 3.7 4.1 4.7 5.5 7.7 ns
tENZL Enable Pad Z to LOW 4.1 4.6 5.2 6.1 8.5 ns
tENHZ Enable Pad HIGH to Z 7.4 8.2 9.3 10.9 15.3 ns
tENLZ Enable Pad LOW to Z 6.9 7.6 8.7 10.2 14.3 ns
tGLH G-to-Pad HIGH 7.0 7.8 8.9 10.4 14.6 ns
tGHL G-to-Pad LOW 7.0 7.8 8.9 10.4 14.6 ns
tLSU I/O Latch Set-Up 0.7 0.7 0.8 1.0 1.4 ns
tLH I/O Latch Hold 0.0 0.0 0.0 0.0 0.0 ns
tLCO I/O Latch Clock-to-Out
(Pad-to-Pad) 32 I/O 7.9 8.8 10.0 11.8 16.5 ns
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External
setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external
PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
Table 45 • A42MX36 Timing Characteristics (Nominal 3.3 V Operation)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, TJ = 70°C) (continued)
Parameter / Description
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
G Microsemi. Power Matters.-
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 86
Input, output, tristate or bidirectional buffer. Input and output levels are compatible with standard TTL and
CMOS specifications. Unused I/Os pins are configured by the Designer software as shown in Table 46,
page 86.
In all cases, it is recommended to tie all unused MX I/O pins to LOW on the board. This applies to all
dual-purpose pins when configured as I/Os as well.
LP, Low Power Mode
Controls the low power mode of all 42MX devices. The device is placed in the low power mode by
connecting the LP pin to logic HIGH. In low power mode, all I/Os are tristated, all input buffers are turned
OFF, and the core of the device is turned OFF. To exit the low power mode, the LP pin must be set to
LOW. The device enters the low power mode 800 ns after the LP pin is driven to a logic HIGH. It will
resume normal operation in 200 µs after the LP pin is driven to a logic LOW.
MODE, Mode
Controls the use of multifunction pins (DCLK, PRA, PRB, SDI, TDO). The MODE pin is held HIGH to
provide verification capability. The MODE pin should be terminated to GND through a 10k resistor so
that the MODE pin can be pulled HIGH when required.
NC, No Connection
This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be
left floating with no effect on the operation of the device.
PRA, I/O
PRB, I/OProbe A/B
The probe pin is used to output data from any user-defined design node within the device. Each
diagnostic pin can be used in conjunction with the other probe pin to allow real-time diagnostic output of
any signal path within the device. The probe pin can be used as a user-defined I/O when verification has
been completed. The pin's probe capabilities can be permanently disabled to protect programmed design
confidentiality. The probe pin is accessible when the MODE pin is HIGH. This pin functions as an I/O
when the MODE pin is LOW.
QCLKA/B/C/D, I/O Quadrant Clock
Quadrant clock inputs for A42MX36 devices. When not used as a register control signal, these pins can
function as user I/Os.
SDI, I/OSerial Data Input
Serial data input for diagnostic probe and device programming. SDI is active when the MODE pin is
HIGH. This pin functions as an I/O when the MODE pin is LOW.
SDO, I/OSerial Data Output
Serial data output for diagnostic probe and device programming. SDO is active when the MODE pin is
HIGH. This pin functions as an I/O when the MODE pin is LOW. SDO is available for 42MX devices only.
When Silicon Explorer II is being used, SDO will act as an output while the “checksum” command is run.
It will return to user I/O when “checksum” is complete.
Table 46 Configuration of Unused I/Os
Device Configuration
A40MX02, A40MX04 Pulled LOW
A42MX09, A42MX16 Pulled LOW
A42MX24, A42MX36 Tristated
O Microsemi Power Maners:
40MX and 42MX FPGAs
DS2316 Datasheet Revision 16.0 87
TCK, I/O Test Clock
Clock signal to shift the boundary scan test (BST) data into the device. This pin functions as an I/O when
“Reserve JTAG” is not checked in the Designer Software. BST pins are only available in A42MX24 and
A42MX36 devices.
TDI, I/OTest Data In
Serial data input for BST instructions and test data. Data is shifted in on the rising edge of TCK. This pin
functions as an I/O when “Reserve JTAG” is not checked in the Designer Software. BST pins are only
available in A42MX24 and A42MX36 devices.
TDO, I/OTest Data Out
Serial data output for BST instructions and test data. This pin functions as an I/O when "Reserve JTAG"
is not checked in the Designer Software. BST pins are only available in A42MX24 and A42MX36
devices.
TMS, I/OTest Mode Select
The TMS pin controls the use of the IEEE 1149.1 boundary scan pins (TCK, TDI, TDO). In flexible mode
when the TMS pin is set to LOW, the TCK, TDI and TDO pins act as boundary scan pins. Once the
boundary scan pins are in test mode, they will remain in that mode until the internal boundary scan state
machine reaches the “logic reset” state. At this point, the boundary scan pins will be released and will
function as regular I/O pins. The “logic reset” state is reached 5 TCK cycles after the TMS pin is set to
HIGH. In dedicated test mode, TMS functions as specified in the IEEE 1149.1 specifications. IEEE JTAG
specification recommends a 10k pull-up resistor on the pin. BST pins are only available in A42MX24
and A42MX36 devices.
VCC, Supply Voltage
Input supply voltage for 40MX devices
VCCA, Supply Voltage
Supply voltage for an array in 42MX devices
VCCI, Supply Voltage
Supply voltage for I/Os in 42MX devices
WD, I/OWide Decode Output
When a wide decode module is used in a 42MX device; this pin can be used as a dedicated output from
the wide decode module. This direct connection eliminates additional interconnect delays associated
with regular logic modules. To implement the direct I/O connection, connect an output buffer of any type
to the output of the wide decode macro and place this output on one of the reserved WD pins.
G Micmsemi. Power Matters: L|L|L|L|L|L|L|L|L|L|L|
Package Pin Assignments
DS2316 Datasheet Revision 16.0 88
4 Package Pin Assignments
The following figures and tables give the details of the package pin assignments.
Figure 38 • PL44
Table 47 • PL44
PL44
Pin Number A40MX02 Function A40MX04 Function
1I/O I/O
2I/O I/O
3VCC VCC
4I/O I/O
5I/O I/O
6I/O I/O
7I/O I/O
8I/O I/O
9I/O I/O
10 GND GND
11 I/O I/O
12 I/O I/O
13 I/O I/O
14 VCC VCC
15 I/O I/O
16 VCC VCC
17 I/O I/O
18 I/O I/O
19 I/O I/O
20 I/O I/O
44
1
44-Pin
PLCC
G Microsemi. Power Matters:
Package Pin Assignments
DS2316 Datasheet Revision 16.0 89
21 GND GND
22 I/O I/O
23 I/O I/O
24 I/O I/O
25 VCC VCC
26 I/O I/O
27 I/O I/O
28 I/O I/O
29 I/O I/O
30 I/O I/O
31 I/O I/O
32 GND GND
33 CLK, I/O CLK, I/O
34 MODE MODE
35 VCC VCC
36 SDI, I/O SDI, I/O
37 DCLK, I/O DCLK, I/O
38 PRA, I/O PRA, I/O
39 PRB, I/O PRB, I/O
40 I/O I/O
41 I/O I/O
42 I/O I/O
43 GND GND
44 I/O I/O
Table 47 • PL44 (continued)
PL44
Pin Number A40MX02 Function A40MX04 Function
G Micmsemi. Power Matters: UUUUUUUUUUUUUUUUU
Package Pin Assignments
DS2316 Datasheet Revision 16.0 90
Figure 39 • PL68
Table 48 • PL68
PL68
Pin Number A40MX02 Function A40MX04 Function
1 I/O I/O
2 I/O I/O
3 I/O I/O
4VCC VCC
5 I/O I/O
6 I/O I/O
7 I/O I/O
8 I/O I/O
9 I/O I/O
10 I/O I/O
11 I/O I/O
12 I/O I/O
13 I/O I/O
14 GND GND
15 GND GND
16 I/O I/O
17 I/O I/O
18 I/O I/O
19 I/O I/O
20 I/O I/O
21 VCC VCC
22 I/O I/O
23 I/O I/O
1 68
68-Pin
PLCC
C} Microsemi. Power Matters:
Package Pin Assignments
DS2316 Datasheet Revision 16.0 91
24 I/O I/O
25 VCC VCC
26 I/O I/O
27 I/O I/O
28 I/O I/O
29 I/O I/O
30 I/O I/O
31 I/O I/O
32 GND GND
33 I/O I/O
34 I/O I/O
35 I/O I/O
36 I/O I/O
37 I/O I/O
38 VCC VCC
39 I/O I/O
40 I/O I/O
41 I/O I/O
42 I/O I/O
43 I/O I/O
44 I/O I/O
45 I/O I/O
46 I/O I/O
47 I/O I/O
48 I/O I/O
49 GND GND
50 I/O I/O
51 I/O I/O
52 CLK, I/O CLK, I/O
53 I/O I/O
54 MODE MODE
55 VCC VCC
56 SDI, I/O SDI, I/O
57 DCLK, I/O DCLK, I/O
58 PRA, I/O PRA, I/O
59 PRB, I/O PRB, I/O
60 I/O I/O
Table 48 • PL68 (continued)
PL68
Pin Number A40MX02 Function A40MX04 Function
G Micmsemi. Power Matters:
Package Pin Assignments
DS2316 Datasheet Revision 16.0 92
Figure 40 • PL84
61 I/O I/O
62 I/O I/O
63 I/O I/O
64 I/O I/O
65 I/O I/O
66 GND GND
67 I/O I/O
68 I/O I/O
Table 49 • PL84
PL84
Pin Number A40MX04 Function A42MX09 Function A42MX16 Function A42MX24 Function
1 I/O I/O I/O I/O
2 I/O CLKB, I/O CLKB, I/O CLKB, I/O
3 I/O I/O I/O I/O
4 VCC PRB, I/O PRB, I/O PRB, I/O
5 I/O I/O I/O WD, I/O
6 I/O GND GND GND
7 I/O I/O I/O I/O
8 I/O I/O I/O WD, I/O
9 I/O I/O I/O WD, I/O
Table 48 • PL68 (continued)
PL68
Pin Number A40MX02 Function A40MX04 Function
184
84-Pin
PLCC
C: Microsemi. Power Matters:
Package Pin Assignments
DS2316 Datasheet Revision 16.0 93
10 I/O DCLK, I/O DCLK, I/O DCLK, I/O
11 I/O I/O I/O I/O
12 NC MODE MODE MODE
13 I/O I/O I/O I/O
14 I/O I/O I/O I/O
15 I/O I/O I/O I/O
16 I/O I/O I/O I/O
17 I/O I/O I/O I/O
18 GND I/O I/O I/O
19 GND I/O I/O I/O
20 I/O I/O I/O I/O
21 I/O I/O I/O I/O
22 I/O VCCA VCCI VCCI
23 I/O VCCI VCCA VCCA
24 I/O I/O I/O I/O
25 VCC I/O I/O I/O
26 VCC I/O I/O I/O
27 I/O I/O I/O I/O
28 I/O GND GND GND
29 I/O I/O I/O I/O
30 I/O I/O I/O I/O
31 I/O I/O I/O I/O
32 I/O I/O I/O I/O
33 VCC I/O I/O I/O
34 I/O I/O I/O TMS, I/O
35 I/O I/O I/O TDI, I/O
36 I/O I/O I/O WD, I/O
37 I/O I/O I/O I/O
38 I/O I/O I/O WD, I/O
39 I/O I/O I/O WD, I/O
40 GND I/O I/O I/O
41 I/O I/O I/O I/O
42 I/O I/O I/O I/O
43 I/O VCCA VCCA VCCA
44 I/O I/O I/O WD, I/O
45 I/O I/O I/O WD, I/O
46 VCC I/O I/O WD, I/O
Table 49 • PL84 (continued)
PL84
Pin Number A40MX04 Function A42MX09 Function A42MX16 Function A42MX24 Function
C: Microsemi. Power Matters:
Package Pin Assignments
DS2316 Datasheet Revision 16.0 94
47 I/O I/O I/O WD, I/O
48 I/O I/O I/O I/O