74HC(T)93 Datasheet by NXP USA Inc.

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@ PHILIPS
DATA SHEET
Product specification
File under Integrated Circuits, IC06
December 1990
INTEGRATED CIRCUITS
74HC/HCT93
4-bit binary ripple counter
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
December 1990 2
Philips Semiconductors Product specification
4-bit binary ripple counter 74HC/HCT93
FEATURES
Various counting modes
Asynchronous master reset
Output capability: standard
ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT93 are high-speed
Si-gate CMOS devices and are pin
compatible with low power Schottky
TTL (LSTTL). They are specified in
compliance with JEDEC standard
no. 7A.
The 74HC/HCT93 are 4-bit binary
ripple counters. The devices consist
of four master-slave flip-flops
internally connected to provide a
divide-by-two section and a
divide-by-eight section. Each section
has a separate clock input (CP0 and
CP1) to initiate state changes of the
counter on the HIGH-to-LOW clock
transition. State changes of the Qn
outputs do not occur simultaneously
because of internal ripple delays.
Therefore, decoded output signals
are subject to decoding spikes and
should not be used for clocks or
strobes.
A gated AND asynchronous master
reset (MR1 and MR2) is provided
which overrides both clocks and
resets (clears) all flip-flops.
Since the output from the
divide-by-two section is not internally
connected to the succeeding stages,
the device may be operated in various
counting modes. In a 4-bit ripple
counter the output Q0 must be
connected externally to input CP1.
The input count pulses are applied to
clock input CP0. Simultaneous
frequency divisions of 2, 4, 8 and 16
are performed at the Q0, Q1, Q2 and
Q3 outputs as shown in the function
table. As a 3-bit ripple counter the
input count pulses are applied to input
CP1.
Simultaneous frequency divisions of
2, 4 and 8 are available at the Q1, Q2
and Q3 outputs. Independent use of
the first flip-flop is available if the reset
function coincides with reset of the
3-bit ripple-through counter.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25°C; tr=t
f= 6 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD=C
PD ×VCC2×fi+∑(CL×VCC2×fo) where:
fi= input frequency in MHz; fo= output frequency in MHz
(CL×VCC2×fo) = sum of outputs
CL= output load capacitance in pF; VCC = supply voltage in V
2. For HC the condition is VI= GND to VCC; for HCT the condition is VI= GND to VCC 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
HC HCT
tPHL/ tPLH propagation delay CP0 to Q0CL= 15 pF; VCC =5 V 12 15 ns
fmax maximum clock frequency 100 77 MHz
CIinput capacitance 3.5 3.5 pF
CPD power dissipation capacitance per package notes 1 and 2 22 22 pF
Mn, I: I: me. n ma, E E on M. I 93 E] 93 ‘ Vcc E E «No VLB. s :1 °' mam ”'2 Eu: :3 u a u 11 12mm
December 1990 3
Philips Semiconductors Product specification
4-bit binary ripple counter 74HC/HCT93
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1CP1clock input 2nd, 3rd and 4th section (HIGH-to-LOW, edge-triggered)
2, 3 MR1, MR2asynchronous master reset (active HIGH)
4, 6, 7, 13 n.c. not connected
5V
CC positive supply voltage
10 GND ground (0 V)
12, 9, 8, 11 Q0 to Q3flip-flop outputs
14 CP0clock input 1st section (HIGH-to-LOW, edge-triggered)
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
z MR1 a M"2 u an I fix an 01 02 0: mam 12 9 a u MR‘ un, 02 a 0 n a a? GP av 0' m FF2 FF: FF‘ No no no Rn 72am
December 1990 4
Philips Semiconductors Product specification
4-bit binary ripple counter 74HC/HCT93
Fig.4 Functional diagram.
Fig.5 Logic diagram.
FUNCTION TABLE
Notes
1. Output Q0 connected to CP1.
H = HIGH voltage level
L = LOW voltage level
MODE SELECTION
COUNT OUTPUTS
Q0Q1Q2Q3
0
1
2
3
L
H
L
H
L
L
H
H
L
L
L
L
L
L
L
L
4
5
6
7
L
H
L
H
L
L
H
H
H
H
H
H
L
L
L
L
8
9
10
11
L
H
L
H
L
L
H
H
L
L
L
L
H
H
H
H
12
13
14
15
L
H
L
H
L
L
H
H
H
H
H
H
H
H
H
H
RESET
INPUTS OUTPUTS
MR1MR2Q0Q1Q2Q3
H
L
H
L
H
H
L
L
LLLL
count
count
count
December 1990 5
Philips Semiconductors Product specification
4-bit binary ripple counter 74HC/HCT93
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr=t
f= 6 ns; CL= 50 pF
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HC VCC
(V) WAVEFORMS+25 40 to +85 40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
CP0 to Q0
41
15
12
125
25
21
155
31
26
190
38
32
ns 2.0
4.5
6.0
Fig.6
tPHL/ tPLH propagation delay
CP1 to Q1
49
16
13
135
27
23
170
34
29
205
41
35
ns 2.0
4.5
6.0
Fig.6
tPHL/ tPLH propagation delay
CP1 to Q2
61
22
18
185
37
31
230
46
39
280
56
48
ns 2.0
4.5
6.0
Fig.6
tPHL/ tPLH propagation delay
CP1 to Q3
80
29
23
245
49
42
305
61
52
370
71
63
ns 2.0
4.5
6.0
Fig.6
tPHL propagation delay
MRn to Qn
50
18
14
155
31
26
195
39
33
235
47
40
ns 2.0
4.5
6.0
Fig.7
tTHL/ tTLH output transition time 19
7
6
75
15
13
95
19
16
110
22
19
ns 2.0
4.5
6.0
Fig.6
trem removal time
MRn to CP0, CP1
50
10
9
8
3
2
65
13
11
75
15
13
ns 2.0
4.5
6.0
Fig.7
tWpulse width
CP0, CP1
80
16
14
14
5
4
100
20
17
120
24
20
ns 2.0
4.5
6.0
Fig.6
tWmaster reset pulse width
MRn
80
16
14
14
5
4
100
20
17
120
24
20
ns 2.0
4.5
6.0
Fig.7
fmax maximum clock pulse
frequency
CP0, CP1
6.0
30
35
30
91
108
4.8
24
28
4.0
20
24
MHz 2.0
4.5
6.0
Fig.6
December 1990 6
Philips Semiconductors Product specification
4-bit binary ripple counter 74HC/HCT93
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications.
To determine ICC per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr=t
f= 6 ns; CL= 50 pF
INPUT UNIT LOAD COEFFICIENT
CP0, CP1
MRn
0.60
0.40
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HCT VCC
(V) WAVEFORMS+25 40 to +85 40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
CP0 to Q0
18 34 43 51 ns 4.5 Fig.6
tPHL/ tPLH propagation delay
CP1 to Q1
18 34 43 51 ns 4.5 Fig.6
tPHL/ tPLH propagation delay
CP1 to Q2
24 46 58 69 ns 4.5 Fig.6
tPHL/ tPLH propagation delay
CP1 to Q3
30 58 73 87 ns 4.5 Fig.6
tPHL propagation delay
MRn to Qn
17 33 41 50 ns 4.5 Fig.7
tTHL/ tTLH output transition time 7 15 19 22 ns 4.5 Fig.6
trem removal time
MRn to CP0, CP1
10 3 13 15 ns 4.5 Fig.7
tWpulse width
CP0, CP1
16 7 20 24 ns 4.5 Fig.6
tWmaster reset pulse width
MRn
16 5 20 24 ns 4.5 Fig.7
fmax maximum clock pulse
frequency
CP0, CP1
30 70 24 20 MHz 4.5 Fig.6
5,. wur on ouwuv nun! MR" Input 5,. Input 0,, new va m m
December 1990 7
Philips Semiconductors Product specification
4-bit binary ripple counter 74HC/HCT93
AC WAVEFORMS
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
Fig.6 Waveforms showing the clock (CPn) to output (Qn) propagation delays, the clock pulse width, output
transition times and the maximum clock pulse frequency.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: VM= 1.3 V; VI= GND to 3 V.
Fig.7 Waveforms showing the master reset (MRn) pulse width, the master reset to output (Qn) propagation
delays and the master reset to clock (CPn) removal time.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: VM= 1.3 V; VI= GND to 3 V.

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