74HC(T)7731 Datasheet by NXP USA Inc.

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@ PHILIPS
DATA SHEET
Product specification
File under Integrated Circuits, IC06
September 1993
INTEGRATED CIRCUITS
74HC/HCT7731
Quad 64-bit static shift register
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
September 1993 2
Philips Semiconductors Product specification
Quad 64-bit static shift register 74HC/HCT7731
FEATURES
Frequency range DC to 100 MHz.
Separate serial data inputs
Cascadable
Functionally compatible with
HEF 4731
Includes recycling mode
Direct shift out
Output capability: Standard
ICC category: LSI.
APPLICATIONS
Data storage
Delay line.
GENERAL DESCRIPTION
The HC/HCT7731 are high-speed
Si-gate CMOS devices. They are
specified in compliance with JEDEC
standard no. 7A.
The HC/HCT7731 are quad 64-bit
static shift registers with a recycling
mode. Each register has separate
data inputs Da to Dd, clock inputs CPa
to CPd and data outputs Qa to Qd.
Data shifts one place towards the
output, each LOW to HIGH transition
of the clock pulse. Each recycling
mode input controls two registers
RECab for registers A and B and
RECcd for registers C and D. When
the REC input is HIGH, the device is
in the recycling mode and data at the
output is shifted back into the input of
the register, so after 64 clock pulses
the contents of a register is again in
its original position. This enables the
user to tap off data from any position.
When the REC input is LOW external
data can be shifted in.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns.
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = (CPD x VCC2 x fi) + (CL + VCC2 x fo) + (Ipull-up x VCC)
where:
fi = input frequency in MHz.
fo = output frequency in MHz.
VCC = supply voltage in V.
CL = output load capacitance in pF.
Ipull-up = pull-up currents in µA.
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC 1.5 V.
3. See also power dissipation information.
ORDERING INFORMATION
SYMBOL PARAMETER CONDITIONS TYP. UNIT
HC HCT
tPHL/tPLH propagation delay
CPa-d to Qa-d
CL = 15 pF;
VCC = 5 V
15 20 ns
fmax maximum clock
frequency
100 100 MHz
CIinput capacitance 3.5 3.5 pF
CPD power dissipation
capacitance per register
notes 1, 2
and 3
58 61 pF
EXTENDED TYPE
NUMBER
PACKAGE
PINS PIN POSITION MATERIAL CODE
74HC/HCT7731N 16 DIL plastic SOT38Z
74HC/HCT7731D 16 SO16 plastic SOT109A
jjjjjjjj U CEEEEEEE
September 1993 3
Philips Semiconductors Product specification
Quad 64-bit static shift register 74HC/HCT7731
PINNING
SYMBOL PIN DESCRIPTION
Qa to Qd1, 7, 9, 15 data outputs
CPa to CPd2, 6, 10, 14 clock inputs
Da to Dd3, 5, 11, 13 data inputs
RECab, RECcd 4, 12 recycled enable input
GND 8 ground (0 V)
VCC 16 positive supply
Fig.1 Pin configuration.
handbook, halfpage
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Qa
CPa
Da
RECab
Db
CPb
Qb
GND
VCC
Qd
CPd
Dd
RECcd
Dc
CPc
Qc
7731
MBA341
Fig.2 Functional diagram.
handbook, full pagewidth
MBA342
64 - BIT
STATIC SHIFT
REGISTER
64 - BIT
STATIC SHIFT
REGISTER
64 - BIT
STATIC SHIFT
REGISTER
64 - BIT
STATIC SHIFT
REGISTER
Qa
CPa
Da
RECab
Db
CPb
Qb
Qd
CPd
Dd
RECcd
Dc
CPc
Qc
MUX
MUX
MUX
MUX
3
2
4
5
6
11
10
12
13
14
1
7
9
15
September 1993 4
Philips Semiconductors Product specification
Quad 64-bit static shift register 74HC/HCT7731
FUNCTION TABLE
Notes
1. L = LOW voltage level
H = HIGH voltage Level
= LOW-to-HIGH CP transition
INPUT OUTPUT
REC CP MODE
Lshift
Hrecycle
Fig.3 Logic diagram.
handbook, full pagewidth
to second shift register
DQ DQ
CPCP
Qn
FF64
FF2
DQ
CP
FF1
RECn
Dn
CPn
MBA345
September 1993 5
Philips Semiconductors Product specification
Quad 64-bit static shift register 74HC/HCT7731
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: LSI.
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF.
Note
1. The maximum power dissipation has to be observed. See power dissipation information.
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITION
+25 40 to +85 40 to +125 VCC
(V) WAVEFORMS
MIN TYP MAX MIN MAX MIN MAX
tPHL/tPLH propagation
delay time CP
to Qn
50
18
15
155
31
26
190
38
32
230
46
39
ns
ns
ns
2.0
4.5
6.0
Fig.4
tTHL/tTLH output transition
time
19
7
6
75
15
13
90
18
15
110
22
19
ns
ns
ns
2.0
4.5
6.0
Fig.4
tWclock pulse
width
HIGH or LOW
80
16
14
19
7
6
100
20
17
120
24
20
ns
ns
ns
2.0
4.5
6.0
Fig.4
tsu set-up time Dn
to CPn
60
12
10
8
3
3
75
15
13
90
18
15
ns
ns
ns
2.0
4.5
6.0
Fig.4
tsu set-up time
RECn to CPn
75
15
13
22
8
7
90
18
15
110
22
19
ns
ns
ns
2.0
4.5
6.0
Fig.5
thhold time Dn to
CPn
25
5
4
3
1
1
30
6
5
35
7
6
ns
ns
ns
2.0
4.5
6.0
Fig.4
thhold time RECn
to CPn
10
2
2
8
3
3
10
2
2
15
3
3
ns
ns
ns
2.0
4.5
6.0
Fig.5
fmax maximum clock
pulse frequency
6
30
35
26
78
93
4.8
24
28
4
20
23
MHz
MHZ
MHz
2.0
4.5
6.0
Fig.4 (note 1)
September 1993 6
Philips Semiconductors Product specification
Quad 64-bit static shift register 74HC/HCT7731
UNIT LOAD COEFFICIENT
Notes
1. The RS input has CMOS input switching levels.
2. The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To
determine ICC per input, multiply this value by the unit load coefficient shown in Table 1.
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF.
INPUT UNIT LOAD
COEFFICIENT
CPn0.7
RECn0.4
Dn0.5
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITION
+25 40 to +85 40 to +125 VCC
(V) WAVEFORMS
MIN TYP MAX MIN MAX MIN MAX
tPHL/tPLH propagation delay time
CP to Qn
24 42 52 63 ns 4.5 Fig.4
tTHL/tTLH output transmission time 71518 22 ns 4.5 Fig.4
tWclock pulse width
HIGH or LOW
16 7 20 24 ns 4.5 Fig.4
tsu set-up time Dn to CPn12 3 15 18 ns 4.5 Fig.4
tsu set-up time RECn to CPn15 6 18 22 ns 2 Fig.5
thhold time Dn to CPn5067ns 2 Fig.4
thhold time RECn to CPn2323ns 4.5 Fig.5
fmax maximum clock pulse
frequency
30 80 24 20 MHz 4.5 Fig.4 (note 1)
1— %fi m >\\ W/ A
September 1993 7
Philips Semiconductors Product specification
Quad 64-bit static shift register 74HC/HCT7731
AC WAVEFORMS
Fig.4 Waveforms showing the clock (CP) and data (D) input to output (Q) propagation delay, set-up, hold and
transition times.
handbook, full pagewidth
MBA320
tTLH
VM(1)
tW
1/ f max
tTHL
VM(1)
VM(1)
tsu thth
tsu
tPLH tPHL
Q OUTPUT
n
D INPUT
n
CP INPUT
n
(1) HC : VM= 50%; VI= GND to VCC
HCT : VM= 1.3 V; VI= GND to 3 V.
Fig.5 Waveforms showing the clock (CP) to recycle (REC) set-up and hold times.
handbook, full pagewidth
MBA321
tW
1/ f max
VM(1)
VM(1)
tsu thth
tsu
REC INPUT
n
CP INPUT
n
(1) HC : VM= 50%; VI= GND to VCC
HCT : VM= 1.3 V; VI= GND to 3 V.
September 1993 8
Philips Semiconductors Product specification
Quad 64-bit static shift register 74HC/HCT7731
Fig.6 CPD as a function of the duty factor.
handbook, halfpage
CPD
(pF)
00.2 0.4 0.6
duty factor
60
40
20
0
MLA166
POWER DISSIPATION INFORMATION
The power dissipation per register operating at the same
frequency is given by:
PD = (CPD x VCC2 x fi) + (CL + VCC2 x fo) + (Ipull-up x VCC)
As PD also depends on the frequency at which the
contents of the internal bits are changing, the value of CPD
is a function of the duty factor (df) being the ration between
data and clock frequency, see Fig.6.
Example:
As the maximum allowable power dissipation in an SO
package at Tamb = 125 °C is 60 mW, it is allowed to apply
4 registers at the same time under these conditions.
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
fi= clock input frequency
fo= data output frequency
CL= output load capacitance in pF
VCC = power supply voltage in V.
fi= 12 MHz
fo= 3 MHz
CL= 25 pF
VCC =5 V
d
f= 3/12 = 0.25
CPD = 42.5 pF
PD = (42.5 × 52× 12) + (25 × 52× 3) = 14625 µW

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