74HC(T)652 Datasheet by NXP USA Inc.

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@ PHILIPS
DATA SHEET
Product specification
File under Integrated Circuits, IC06
September 1993
INTEGRATED CIRCUITS
74HC/HCT652
Octal bus transceiver/register;
3-state
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
September 1993 2
Philips Semiconductors Product specification
Octal bus transceiver/register; 3-state 74HC/HCT652
FEATURES
Multiplexed real-time and stored
data
Independent register for A and B
buses
Independent enables for A and B
buses
3-state
Output capability: Bus driver
Low power consumption by CMOS
technology
ICC category: MSI.
APPLICATIONS
Bus interfaces.
DESCRIPTION
The 74HC/HCT652 are high-speed
SI-gate CMOS devices and are pin
compatible with Low power Schottky
TTL (LSTTL). They are specified in
compliance with Jedec standard
no. 7A.
The 74HC/HCT652 consist of 8
non-inverting bus transceiver circuits
with 3-state outputs, D-type flip-flops
and central circuitry arranged for
multiplexed transmission of data
directly from the data bus or from the
internal storage registers. Data on the
“A” or “B” or both buses, will be stored
in the internal registers, at the
appropriate clock pins (CPAB or
CPBA) regardless of the select pins
(SAB and SBA) or output enable (OEAB
and OEBA) control pins. Depending
on the select inputs SAB and SBA data
can directly go from input to output
(real time mode) or data can be
controlled by the clock (storage
mode), this is when the output enable
pins this operating mode permits. The
output enable pins OEAB and OEBA
determine the operation mode of the
transceiver. When OEAB is LOW, no
data transmission from Anto Bnis
possible and when OEBA is HIGH,
there is no data transmission from Bn
to Anpossible. When SAB and SBA are
in the real time transfer mode, it is
also possible to store data without
using the internal D-type flip-flops by
simultaneously enabling OEAB and
OEBA. In this configuration each
output reinforces its input. Thus when
all other data sources to the two sets
of bus lines are at high-impedance,
each set of the bus lines will remain at
its last state. This type differs from the
HC/HCT646 in one extra
bus-management function. This is the
possibility to transfer stored “A data to
the “B” bus and transfer stored ”B”
data to the ”A” bus at the same time.
The examples at the application
information demonstrate all bus
management functions.
Schmitt-trigger action in the clock
inputs makes the circuit highly
tolerant to slower clock rise and fall
times.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25°C; tr=t
f= 6 ns; VCC = 4.5 V; CL= 50 pF.
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD=C
PD × VCC2× fi+ ∑ (CL× VCC2 × fo) where:
fi= input frequency in MHz; CL= output load capacitance in pF;
fo= output frequency in MHz; VCC = supply voltage in V;
(CL× VCC2× fo) = sum of the outputs
2. For HC the condition is VI= GND to VCC
For HCT the condition is VI= GND to VCC 1.5 V
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
HC HCT
tPLH/tPZL propagation delay An/Bnto Bn/AnCL= 15 pF;
VCC =5 V
13 13 ns
propagation delay CPAB/CPBA to Bn/An18 20 ns
propagation delay SAB/SBA to Bn/An20 23 ns
tPHZ/tPZL 3-state output enable time OEAB/OEBA to Bn/An14 15 ns
tPHZ/tPLZ 3-state output disable time OEAB/OEBA to Bn/An12 13 ns
fmax maximum clock frequency 92 92 MHz
CIinput capacitance 3.5 3.5 pF
CPD power dissipation capacitance per channel notes 1 and 2 26 28 pF
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September 1993 3
Philips Semiconductors Product specification
Octal bus transceiver/register; 3-state 74HC/HCT652
ORDERING AND PACKAGE INFORMATION
PINNING
TYPE NUMBER PACKAGE
PINS PIN POSITION MATERIAL CODE
74HC/HCT652N 24 DIL plastic SOT101L
74HC/HCT652D 24 SO plastic SOT137A
SYMBOL PIN DESCRIPTION
CPAB 1 A to B clock input
SAB 2 select A to B source input
OEAB 3 output enable A to B input
A0..A74..11 A data inputs/outputs
GND 12 ground (0 V)
B7..B013..20 B data inputs/outputs
OEBA 21 output enable B to A input
SBA 22 select B to A source input
CPBA 23 B to A clock input
VCC 24 positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
456789mu
September 1993 4
Philips Semiconductors Product specification
Octal bus transceiver/register; 3-state 74HC/HCT652
FUNCTION TABLE
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
= LOW-to-HIGH transition
2. The data output functions may be enabled or disabled by various signals at OEAB and OEBA inputs. Data input
functions are always enabled, i.e., data at the bus inputs will be stored on every LOW-to-HIGH transition on the clock
inputs.
INPUTS (1) DATA I/O (2) OPERATION OR FUNCTION
OEAB OEBA CPAB CPBA SAB SBA A1THRU A8B1THRU B8HC/HCT652
L H H or L H or L X X Input Input Isolation
LH↑↑X X Store A and B data
XHH or L X X Input Not specified Store A, Hold B
HH↑↑L X Input Output Store A in both registers
L X H or L X X Not specified Input Hold A, Store B
LL↑↑X L Ouput Input Store B in both registers
LLXXXL Ouput Input Real Time B Data to A Bus
L L X H or L X H Stored B Data to A Bus
HHXXLX Input Output Real Time A Data to B Bus
H H H or L X H X Stored A Data to B Bus
H L H or L H or L H H Output Output Stored A Data to B Bus and
Stored B Data to A Bus
Fig.4 Functional diagram.
September 1993 5
Philips Semiconductors Product specification
Octal bus transceiver/register; 3-state 74HC/HCT652
Fig.5 Logic diagram.
September 1993 6
Philips Semiconductors Product specification
Octal bus transceiver/register; 3-state 74HC/HCT652
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: bus driver
ICC category: MSI.
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr=t
f= 6 ns; CL= 50 pF.
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HC VCC
(V) WAVEFORMS+25 40 to +85 40 to +125
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
tPHL/tPLH propagation delay
An, Bn to Bn, An
44
16
13
135
27
23
170
34
29
205
41
35
ns 2.0
4.5
6.0
Fig.6
tPHL/tPLH propagation delay
CPAB, CPBA to Bn, An
61
22
18
190
38
32
240
48
41
285
57
48
ns 2.0
4.5
6.0
Fig.7
tPHL/tPLH propagation delay
SAB, SBA to Bn, An
63
23
18
195
39
33
245
49
42
295
59
50
ns 2.0
4.5
6.0
Fig.8
tPZH/tPZL 3-state output enable
time
OEAB, OEBA to An, Bn
47
17
14
150
30
26
190
38
33
225
45
38
ns 2.0
4.5
6.0
Fig.9
tPHZ/tPLZ 3-state output disable
time
OEAB, OEBA to An, Bn
41
15
12
150
30
26
190
38
33
225
45
38
ns 2.0
4.5
6.0
Fig.9
tTHL/tTLH output transition time
14
5
4
60
12
10
75
15
13
90
18
15
ns 2.0
4.5
6.0
Figs 6, 8
tWclock pulse width
HIGH or LOW
CPAB or CPBA
80
16
14
17
6
5
100
20
17
120
24
20
ns 2.0
4.5
6.0
Fig.7
tsu set-up time
An, Bn to CPAB, CPBA
100
20
17
17
6
5
125
25
21
150
30
26
ns 2.0
4.5
6.0
Fig.7
thhold time
An, Bn to CPAB, CPBA
25
5
4
8
3
2
30
6
5
35
7
6
ns 2.0
4.5
6.0
Fig.7
fmax maximum clock pulse
frequency
6.0
30
35
16
83
98
4.8
24
28
4.0
20
24
MHz 2.0
4.5
6.0
Fig.7
September 1993 7
Philips Semiconductors Product specification
Octal bus transceiver/register; 3-state 74HC/HCT652
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: bus driver
ICC category: MSI.
Note to the HCT types
The value of additional quiescent supply current (ICC) for unit a load of 1 is given in the family specifications.
To determine ICC per input, multiply this value by the unit load coefficient shown in the table below
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr=t
f= 6 ns; CL= 50 pF.
INPUT UNIT LOAD COEFFICIENT
SAB, SBA 0.75
A0to A7 and B0to B70.75
CPAB, CPBA 1.50
OEAB 1.50
OEBA 1.50
INPUT PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
+25 40 to +85 40 to +125 VCC
(V) WAVEFORMS
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
tPHL/tPLH propagation delay
An, Bn to Bn, An
16 27 34 41 ns 4.5 Fig.6
tPHL/tPLH propagation delay
CPAB, CPBA to Bn, An
23 39 49 59 ns 4.5 Fig.7
tPHL/tPLH propagation delay
SAB, SBA to Bn, An
27 46 55 66 ns 4.5 Fig.8
tPZH/tPZL 3-state output enable
time
OEAB, OEBA to An, Bn
18 33 41 50 ns 4.5 Fig.9
tPHZ/tPLZ 3-state output disable
time
OEAB, OEBA to An, Bn
16 35 44 53 ns 4.5 Fig.9
tTHL/tTLH output transition time 51215 18 ns 4.5 Fig.6, 8
tWclock pulse width
HIGH or LOW
CPAB or CPBA
16 6 20 24 ns 4.5 Fig.7
tsu set-up time
An, Bn to CPAB, CPBA
10 5 13 15 ns 4.5 Fig.7
thhold time
An, Bn to CPAB, CPBA
5268ns 4.5 Fig.7
fmax maximum clock pulse
frequency
30 83 24 20 MHz 4.5 Fig.7
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September 1993 8
Philips Semiconductors Product specification
Octal bus transceiver/register; 3-state 74HC/HCT652
Fig.6 Waveforms showing the input An, Bn to
output Bn, Anpropagation delay times and
the output transition times.
(1) HC: VM= 50%; VI= GND to VCC.
HCT: VM= 1.3 V; VI= GND to 3 V. Fig.7 Waveforms showing the An, Bn to CPAB,
CPBA set-up and hold times, clock CPAB,
CPBA pulse width, maximum clock pulse
frequency and the CPAB, CPBA to output Bn,
Anpropagation delays.
(1) HC: VM= 50%; VI= GND to VCC.
HCT: VM= 1.3 V; VI= GND to 3 V.
Fig.8 Waveforms showing the input SAB, SBA to
output Bn, Anpropagation delay times and
the output transition times.
(1) HC: VM= 50%; VI= GND to VCC.
HCT: VM= 1.3 V; VI= GND to 3 V.
Fig.9 Waveforms showing the output enable
inputs (OEAB, OEBA) to outputs An, Bn
enable and disable times and the input
rise and fall times.
(1) HC: VM= 50%; VI= GND to VCC.
HCT: VM= 1.3 V; VI= GND to 3 V.
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September 1993 9
Philips Semiconductors Product specification
Octal bus transceiver/register; 3-state 74HC/HCT652
APPLICATION INFORMATION
Fig.10 Application information.
September 1993 10
Philips Semiconductors Product specification
Octal bus transceiver/register; 3-state 74HC/HCT652
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.

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