74HC(T)646 Datasheet by NXP USA Inc.

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DATA SHEET
Product specification
File under Integrated Circuits, IC06
September 1993
INTEGRATED CIRCUITS
74HC/HCT646
Octal bus transceiver/register;
3-state
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
September 1993 2
Philips Semiconductors Product specification
Octal bus transceiver/register; 3-state 74HC/HCT646
FEATURES
Independent register for A and B buses
Multiplexed real-time and stored data
Output capability: bus driver
ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT646 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT646 consist of bus transceiver circuits with
3-state outputs, D-type flip-flops, and control circuitry
arranged for multiplexed transmission of data directly from
the internal registers. Data on the “A” or “B” bus will be
clocked into the registers as the appropriate clock
(CPAB and CPBA) goes to a HIGH logic level. Output
enable (OE) and direction (DIR) inputs are provided to
control the transceiver function. In the transceiver mode,
data present at the high-impedance port may be stored in
either the “A” or “B” register, or in both. The select source
inputs (SAB and SBA) can multiplex stored and real-time
(transparent mode) data. The direction (DIR) input
determines which bus will receive data when OE is active
(LOW). In the isolation mode (OE = HIGH), “A” data may
be stored in the “B” register and/or “B” data may be stored
in the “A” register.
When an output function is disabled, the input function is
still enabled and may be used to store and transmit data.
Only one of the two buses, A or B, may be driven at a time.
The “646” is functionally identical to the “648”, but has
non-inverting data paths.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25°C; tr=t
f= 6 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD=C
PD ×VCC2×fi+ (CL×VCC2×fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
(CL×VCC2×fo) = sum of outputs
CL= output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI= GND to VCC
For HCT the condition is VI= GND to VCC 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
HC HCT
tPHL/ tPLH propagation delay An, Bn to Bn, AnCL= 15 pF; VCC =5V 11 13 ns
f
max maximum clock frequency 69 85 MHz
CIinput capacitance 3.5 3.5 pF
CPD power dissipation capacitance per channel notes 1 and 2 30 33 pF
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September 1993 3
Philips Semiconductors Product specification
Octal bus transceiver/register; 3-state 74HC/HCT646
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1CP
AB A to B clock input (LOW-to-HIGH, edge-triggered)
2S
AB select A to B source input
3 DIR direction control input
4, 5, 6, 7, 8, 9, 10, 11 A0 to A7A data inputs/outputs
12 GND ground (0 V)
20, 19, 18, 17, 16, 15, 14, 13 B0 to B7B data inputs/outputs
21 OE output enable input (active LOW)
22 SBA select B to A source input
23 CPBA B to A clock input (LOW-to-HIGH, edge-triggered)
24 VCC positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
mmn
September 1993 4
Philips Semiconductors Product specification
Octal bus transceiver/register; 3-state 74HC/HCT646
Fig.4 Functional diagram.
FUNCTION TABLE
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
= LOW-to-HIGH level transition
2. The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input
functions are always enabled, i.e., data at the bus inputs will be stored on every LOW-to-HIGH transition on the clock
inputs.
INPUTS (1) DATA I/O (2)
FUNCTION
OE DIR CPAB CPBA SAB SBA A0to A7B0to B7
H
H
X
X
H or L
H or L
X
X
X
Xinput input isolation
store A and B data
L
L
L
L
X
X
X
H or L
X
X
L
Houtput input real-time B data to A bus
stored B data to A bus
L
L
H
H
X
H or L
X
X
L
H
X
Xinput output real-time A data to B bus
stored A data to B bus
September 1993 5
Philips Semiconductors Product specification
Octal bus transceiver/register; 3-state 74HC/HCT646
Fig.5 Logic diagram.
September 1993 6
Philips Semiconductors Product specification
Octal bus transceiver/register; 3-state 74HC/HCT646
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: bus driver
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr=t
f= 6 ns; CL=50pF
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HC VCC
(V) WAVEFORMS+25 40 to +85 40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
An,Bn to Bn,An
39
14
11
135
27
23
170
34
29
205
41
35
ns 2.0
4.5
6.0
Fig.6
tPHL/ tPLH propagation delay
CPAB,CPBA to Bn,An
66
24
19
220
44
37
275
55
47
330
66
56
ns 2.0
4.5
6.0
Fig.7
tPHL/ tPLH propagation delay
SAB,SBA to Bn,An
55
20
16
190
38
32
240
48
41
285
57
48
ns 2.0
4.5
6.0
Fig.8
tPZH/ tPZL 3-state output enable
time
OE to An,Bn
47
17
14
175
35
30
220
44
37
265
53
45
ns 2.0
4.5
6.0
Fig.9
tPHZ/ tPLZ 3-state output disable
time OE to An,Bn
58
21
17
175
35
30
220
44
37
265
53
45
ns 2.0
4.5
6.0
Fig.9
tPZH/ tPZL 3-state output enable
time DIR to An,Bn
50
18
14
175
35
30
220
44
37
265
53
45
ns 2.0
4.5
6.0
Fig.10
tPHZ/ tPLZ 3-state output disable
time DIR to An,Bn
50
18
14
175
35
30
220
44
37
265
53
45
ns 2.0
4.5
6.0
Fig.10
tTHL/ tTLH output transition time 14
5
4
60
12
10
75
15
13
90
18
15
ns 2.0
4.5
6.0
Fig.6 and Fig.8
tWclock pulse width
HIGH or LOW
CPAB or CPBA
80
16
14
25
9
7
100
24
20
120
24
20
ns 2.0
4.5
6.0
Fig.7
tsu set-up time
An,Bnto CPAB,CPBA
60
12
10
3
1
1
75
15
13
90
18
15
ns
2.0
4.5
6.0
Fig.7
thhold time
An,Bnto CPAB,CPBA
35
7
6
6
2
2
45
9
8
55
11
9
ns
2.0
4.5
6.0
Fig.7
fmax maximum clock pulse
frequency
6.0
30
35
21
63
75
4.8
24
28
4.0
20
24
MHz
2.0
4.5
6.0
Fig.7
September 1993 7
Philips Semiconductors Product specification
Octal bus transceiver/register; 3-state 74HC/HCT646
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: bus driver
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications.
To determine ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT UNIT LOAD COEFFICIENT
SAB, SBA 0.60
A0 to A7and B0 to B70.75
INPUT UNIT LOAD COEFFICIENT
CPAB,CP
BA 1.50
OE
DIR
1.50
1.25
September 1993 8
Philips Semiconductors Product specification
Octal bus transceiver/register; 3-state 74HC/HCT646
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr=t
f= 6 ns; CL=50pF
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HCT VCC
(V) WAVEFORMS+25 40 to +85 40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
An,Bn to Bn,An
16 30 38 45 ns 4.5 Fig.6
tPHL/ tPLH propagation delay
CPAB,CPBA to Bn,An
23 44 55 66 ns 4.5 Fig.7
tPHL/ tPLH propagation delay
SAB,SBA to Bn,An
26 46 58 69 ns 4.5 Fig.8
tPZH/ tPZL 3-state output enable time
OE to An,Bn
21 40 50 60 ns 4.5 Fig.9
tPHZ/ tPLZ 3-state output disable time
OE to An,Bn
20 35 44 53 ns 4.5 Fig.9
tPZH/ tPZL 3-state output enable time
DIR to An,Bn
21 40 50 60 ns 4.5 Fig.10
tPHZ/ tPLZ 3-state output disable time
DIR to An,Bn
21 35 44 53 ns 4.5 Fig.10
tTHL/ tTLH output transition time 5 12 15 18 ns 4.5 Fig.6 and Fig.8
tWclock pulse width
HIGH or LOW
CPAB or CPBA
16 8 20 24 ns 4.5 Fig.7
tsu set-up time
An,Bnto CPAB,CPBA
12 3 15 18 ns 4.5 Fig.7
thhold time
An,Bnto CPAB,CPBA
5 1 5 5 ns 4.5 Fig.7
fmax maximum clock pulse
frequency
30 77 24 20 MHz 4.5 Fig.7
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September 1993 9
Philips Semiconductors Product specification
Octal bus transceiver/register; 3-state 74HC/HCT646
AC WAVEFORMS
Fig.6 Waveforms showing the input An, Bn to output Bn, An propagation delays and the output transition times.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: VM= 1.3 V; VI= GND to 3 V.
Fig.7 Waveforms showing the An,Bn to CPAB, CPBA set-up and hold times, clock CPAB,CPBA pulse width,
maximum clock pulse frequency and the CPAB,CPBA to output Bn,An propagation delays.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: VM= 1.3 V; VI= GND to 3 V.
Fig.8 Waveforms showing the input SAB,SBA to output Bn,An propagation delays and output transition times.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: VM= 1.3 V; VI= GND to 3 V.
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September 1993 10
Philips Semiconductors Product specification
Octal bus transceiver/register; 3-state 74HC/HCT646
Fig.9 Waveforms showing the input OE to output An,Bn 3-state enable and disable times.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: VM= 1.3 V; VI= GND to 3 V.
Fig.10 Waveforms showing the input DIR to output An, Bn 3-state enable and disable times.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: VM= 1.3 V; VI= GND to 3 V.
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September 1993 11
Philips Semiconductors Product specification
Octal bus transceiver/register; 3-state 74HC/HCT646
APPLICATION INFORMATION
Fig.11 Data storage from A and/or B bus.
Fig.12 Real-time transfer from bus A to bus B.
Fig.13 Real-time transfer from bus B to bus A.
September 1993 12
Philips Semiconductors Product specification
Octal bus transceiver/register; 3-state 74HC/HCT646
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.

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