74HC(T)4353 Datasheet by NXP USA Inc.

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@ PHILIPS
DATA SHEET
Product specification
File under Integrated Circuits, IC06
December 1990
INTEGRATED CIRCUITS
74HC/HCT4353
Triple 2-channel analog
multiplexer/demultiplexer with latch
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
December 1990 2
Philips Semiconductors Product specification
Triple 2-channel analog
multiplexer/demultiplexer with latch 74HC/HCT4353
FEATURES
Wide analog input voltage range: ±5 V
Low “ON” resistance:
80 (typ.) at VCC VEE = 4.5 V
70 (typ.) at VCC VEE = 6.0 V
60 (typ.) at VCC VEE = 9.0 V
Logic level translation:
to enable 5 V logic to communicate with ±5 V analog
signals
Typical “break before make” built in
Address latches provided
Output capability: non-standard
ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4353 are high-speed Si-gate CMOS
devices. They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT4353 are triple 2-channel analog
multiplexers/demultiplexers with two common enable
inputs (E1and E2) and a latch enable input (LE). Each
multiplexer has two independent inputs/outputs (nY0and
nY1), a common input/output (nZ) and select inputs (S1to
S3).
Each multiplexer/demultiplexer contains two bidirectional
analog switches, each with one side connected to an
independent input/output (nY0and nY1) and the other side
connected to a common input/output (nZ).
With E1LOW and E2HIGH, one of the two switches is
selected (low impedance ON-state) by S1to S3.
The data at the select inputs may be latched by using the
active LOW latch enable input (LE). When LE is HIGH, the
latch is transparent. When either of the two enable inputs,
E1(active LOW) and E2(active HIGH), is inactive, all
analog switches are turned off.
VCC and GND are the supply voltage pins for the digital
control inputs (S1to S3, LE, E1and E2). The VCC to GND
ranges are 2.0 to 10.0 V for HC and 4.5 to 5.5 V for HCT.
The analog inputs/outputs (nY0and nY1, and nZ) can
swing between VCC as a positive limit and VEE as a
negative limit. VCC VEE may not exceed 10.0 V.
For operation as a digital multiplexer/demultiplexer, VEE is
connected to GND (typically ground).
QUICK REFERENCE DATA
VEE = GND = 0 V; Tamb = 25 °C; tr= tf= 6 ns
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
HC HCT
tPZH/ tPZL turn “ON” time E1,E
2or Snto Vos CL= 50 pF; RL=1 k;
V
CC = 5 V
29 21 ns
tPHZ/ tPLZ turn “OFF” time E1,E
2or Snto Vos 20 22 ns
CIinput capacitance 3.5 3.5 pF
CPD power dissipation capacitance per switch notes 1 and 2 23 23 pF
CSmax. switch capacitance
independent (Y) 5 5 pF
common (Z) 8 8 pF
Notes
1. CPD is used to determine the dynamic power
dissipation (PDin µW):
PD=
CPD ×VCC2×fi+{(CL+C
S
)×V
CC2×fo} where:
fi= input frequency in MHz
CL= output load capacitance in pF
fo= output frequency in MHz
CS= max. switch capacitance in pF
{(CL×CS)×VCC2×fo} = sum of outputs
VCC = supply voltage in V
2. For HC the condition is VI= GND to VCC
For HCT the condition is VI= GND to VCC 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package
Information”
.
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December 1990 3
Philips Semiconductors Product specification
Triple 2-channel analog
multiplexer/demultiplexer with latch 74HC/HCT4353
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
2, 1 2Y0,2Y
1independent inputs/outputs
5 3Z common input/output
6, 4 3Y0,3Y
1independent inputs/outputs
3, 14 n.c. not connected
7E1enable input (active LOW)
8E
2enable input (active HIGH)
9V
EE negative supply voltage
10 GND ground (0 V)
11 LE latch enable input (active LOW)
15, 13, 12 S1to S3select inputs
16, 17 1Y0,1Y
1independent inputs/outputs
18 1Z common input/output
19 2Z common input/output
20 VCC positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
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December 1990 4
Philips Semiconductors Product specification
Triple 2-channel analog
multiplexer/demultiplexer with latch 74HC/HCT4353
FUNCTION TABLE
Notes
1. Last selected channel “ON”.
2. Selected channels latched.
H = HIGH voltage level
L = LOW voltage level
X = don’t care
= HIGH-to-LOW LE transition
APPLICATIONS
Analog multiplexing and demultiplexing
Digital multiplexing and demultiplexing
Signal gating
INPUTS CHANNEL
ON
E1E2LE Sn
H
X
H
L
X
X
X
X
none
none
L
L
H
H
H
H
L
H
nY0 nZ
nY1nZ
L
X
H
X
L
X
X
(1)
(2)
Fig.4 Functional diagram.
Fig.5 Schematic diagram (one switch).
December 1990 5
Philips Semiconductors Product specification
Triple 2-channel analog
multiplexer/demultiplexer with latch 74HC/HCT4353
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Voltages are referenced to VEE = GND (ground = 0 V)
Note to ratings
1. To avoid drawing VCC current out of terminals nZ, when switch current flows in terminals nYn, the voltage drop across
the bidirectional switch must not exceed 0.4 V. If the switch current flows into terminals nZ, no VCC current will flow
out of terminals nYn. In this case there is no limit for the voltage drop across the switch, but the voltages at nYnand
nZ may not exceed VCC or VEE.
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER MIN. MAX. UNIT CONDITIONS
VCC DC supply voltage 0.5 +11.0 V
±IIK DC digital input diode current 20 mA for VI<−0.5 V or VI>VCC + 0.5 V
±ISK DC switch diode current 20 mA for VS<−0.5 V or VS>VCC + 0.5 V
±ISDC switch current 25 mA for 0.5 V <VS<VCC + 0.5 V
±IEE DC VEE current 20 mA
±ICC;
±IGND
DC VCC or GND current 50 mA
Tstg storage temperature range 65 +150 °C
Ptot power dissipation per package for temperature range: 40 to +125 °C
74HC/HCT
plastic DIL 750 mW above +70 °C: derate linearly with 12 mW/K
plastic mini-pack (SO) 500 mW above +70 °C: derate linearly with 8 mW/K
PSpower dissipation per switch 100 mW
SYMBOL PARAMETER 74HC 74HCT UNIT CONDITIONS
min. typ. max. min. typ. max.
VCC DC supply voltage VCCGND 2.0 5.0 10.0 4.5 5.0 5.5 V see Figs 6 and 7
VCC DC supply voltage VCCVEE 2.0 5.0 10.0 2.0 5.0 10.0 V see Figs 6 and 7
VIDC input voltage range GND VCC GND VCC V
VSDC switch voltage range VEE VCC VEE VCC V
Tamb operating ambient temperature range 40 +85 40 +85 °C see DC and AC
CHARACTER-
ISTICS
Tamb operating ambient temperature range 40 +125 40 +125 °C
tr,t
finput rise and fall times
6.0
1000
500
400
250
6.0 500 ns
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VCC = 10.0 V
umu u vmmm (v1 5 o z A s a lo Voc'VEE (v)
December 1990 6
Philips Semiconductors Product specification
Triple 2-channel analog
multiplexer/demultiplexer with latch 74HC/HCT4353
Fig.6 Guaranteed operating area as a function of
the supply voltages for 74HC4353.
handbook, halfpage
10
8
6
4
2
00246810
V
CC- VEE (V)
VCC - GND
(V)
MBA334
operating area
Fig.7 Guaranteed operating area as a function of
the supply voltages for 74HCT4353.
DC CHARACTERISTICS FOR 74HC/HCT
For 74HC: VCC GND or VCC VEE = 2.0, 4.5, 6.0 and 9.0 V
For 74HCT: VCC GND = 4.5 and 5.5 V; VCC VEE = 2.0, 4.5, 6.0 and 9.0 V
Notes to DC characteristics
1. At supply voltages (VCC VEE) approaching 2.0 V the analog switch ON-resistance becomes extremely non-linear.
There it is recommended that these devices be used to transmit digital signals only, when using these supply
voltages.
2. For test circuit measuring RON see Fig.8.
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HC/HCT VCC
(V) VEE
(V) IS
(µA) Vis VI
+25 40 to +85 40 to +125
min. typ. max. min. max. min. max.
RON ON resistance
(peak)
100
90
70
180
160
130
225
200
165
270
240
195
2.0
4.5
6.0
4.5
0
0
0
4.5
100
1000
1000
1000
VCC
to
VEE
VIN
or
VIL
RON ON resistance
(rail)
150
80
70
60
140
120
105
175
150
130
210
180
160
2.0
4.5
6.0
4.5
0
0
0
4.5
100
1000
1000
1000
VEE VIH
or
VIL
RON ON resistance 150
90
80
65
160
140
120
200
175
150
240
210
180
2.0
4.5
6.0
4.5
0
0
0
4.5
100
1000
1000
1000
VCC VIH
or
VIL
RON maximum
ON resistance
between any two
channels
9
8
6
2.0
4.5
6.0
4.5
0
0
0
4.5
VCC
to
VEE
VIH
or
VIL
December 1990 7
Philips Semiconductors Product specification
Triple 2-channel analog
multiplexer/demultiplexer with latch 74HC/HCT4353
DC CHARACTERISTICS FOR 74HC
Voltages are referenced to GND (ground = 0 V)
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HC VCC
(V) VEE
(V) VIOTHER+25 40 to +85 40 to +125
min. typ. max. min. max. min. max.
VIH HIGH level
input voltage
1.5
3.15
4.2
6.3
1.2
2.4
3.2
4.7
1.5
3.15
4.2
6.3
1.5
3.15
4.2
6.3
V 2.0
4.5
6.0
9.0
VIL LOW level
input voltage
0.8
2.1
2.8
4.3
0.5
1.35
1.8
2.7
0.5
1.35
1.8
2.7
0.5
1.35
1.8
2.7
V 2.0
4.5
6.0
9.0
±IIinput leakage
current
0.1
0.2
1.0
2.0
1.0
2.0
µA6.0
10.0
0
0
VCC
or
GND
±ISanalog switch
OFF-state
current per
channel
0.1 1.0 1.0 µA10.0 0V
IH
or
VIL
VS=
VCC VEE
(see Fig.10)
±ISanalog switch
OFF-state
current all
channels
0.1 1.0 1.0 µA10.0 0V
IH
or
VIL
VS=
VCC VEE
(see Fig.10)
±ISanalog switch
ON-state
current
0.1 1.0 1.0 µA10.0 0V
IH
or
VIL
VS=
VCC VEE
(see Fig.11)
ICC quiescent
supply current
8.0
16.0
80.0
160.0
160.0
320.0
µA6.0
10.0
0
0
VCC
or
GND
Vis =V
EE or
VCC;V
os =
VCC or VEE
December 1990 8
Philips Semiconductors Product specification
Triple 2-channel analog
multiplexer/demultiplexer with latch 74HC/HCT4353
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr=t
f= 6 ns; CL= 50 pF
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HC VCC
(V) VEE
(V) OTHER+25 40 to +85 40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
Vis to Vos
14
5
4
4
60
12
10
8
75
15
13
10
90
18
15
12
ns 2.0
4.5
6.0
4.5
0
0
0
4.5
RL=;
CL= 50 pF
(see Fig.18)
tPZH/ tPZL turn “ON” time
E1;E
2to Vos
61
22
18
18
250
50
43
40
315
63
54
50
375
75
64
60
ns 2.0
4.5
6.0
4.5
0
0
0
4.5
RL=1k;
C
L= 50 pF
(see Fig.19)
tPZH/ tPZL turn “ON” time
LE to Vos
55
20
16
17
200
40
34
40
250
50
43
50
300
60
51
60
ns 2.0
4.5
6.0
4.5
0
0
0
4.5
RL=1k;
C
L= 50 pF
(see Fig.19)
tPZH/ tPZL turn “ON” time
Snto Vos
61
22
18
17
225
45
38
40
280
56
48
50
340
68
58
60
ns 2.0
4.5
6.0
4.5
0
0
0
4.5
RL=1k;
C
L= 50 pF
(see Fig.19)
tPHZ/ tPLZ turn “OFF” time
E1;E
2to Vos
66
24
19
19
250
50
43
40
315
63
54
50
375
75
64
60
ns 2.0
4.5
6.0
4.5
0
0
0
4.5
RL=1k;
C
L= 50 pF
(see Fig.19)
tPHZ/ tPLZ turn “OFF” time
Snto Vos; LE to Vos
55
20
16
19
200
40
34
40
250
50
43
50
300
60
51
60
ns 2.0
4.5
6.0
4.5
0
0
0
4.5
RL=1k;
C
L= 50 pF
(see Fig.19)
tsu set-up time Snto LE 60
12
10
18
17
6
5
8
75
15
13
23
90
18
15
27
ns 2.0
4.5
6.0
4.5
0
0
0
4.5
RL=1k;
C
L= 50 pF
(see Fig.20)
thhold time Snto LE 5
5
5
5
6
2
2
3
5
5
5
5
5
5
5
5
ns 2.0
4.5
6.0
4.5
0
0
0
4.5
RL=1k;
C
L= 50 pF
(see Fig.20)
tWLE minimum pulse
width HIGH
80
16
14
16
11
4
3
6
100
20
17
20
120
24
20
24
ns 2.0
4.5
6.0
4.5
0
0
0
4.5
RL=1k;
C
L= 50 pF
(see Fig.20)
December 1990 9
Philips Semiconductors Product specification
Triple 2-channel analog
multiplexer/demultiplexer with latch 74HC/HCT4353
DC CHARACTERISTICS FOR 74HCT
Voltages are referenced to GND (ground = 0 V)
Note to HCT types
1. The value of additional quiescent supply current (ICC) for a unit load of 1 is given here.
To determine ICC per input, multiply this value by the unit load coefficient shown in the table below.
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HCT VCC
(V) VEE
(V) VIOTHER+25 40 to +85 40 to +125
min. typ. max. min. max. min. max.
VIH HIGH level input
voltage
2.0 1.6 2.0 2.0 V 4.5
to
5.5
VIL LOW level input
voltage
1.2 0.8 0.8 0.8 V 4.5
to
5.5
±IIinput leakage
current
0.1 1.0 1.0 µA 5.5 0 VCC
or
GND
±ISanalog switch
OFF-state
current per
channel
0.1 1.0 1.0 µA10.0 0V
IH
or
VIL
VS=
VCC VEE
Fig.10
±ISanalog switch
OFF-state current
all channels
0.1 1.0 1.0 µA10.0 0V
IH
or
VIL
VS=
VCC VEE
Fig.10
±ISanalog switch
ON-state current
0.1 1.0 1.0 µA10.0 0V
IH
or
VIL
VS=
VCC VEE
Fig.11
ICC quiescent supply
current
8.0
16.0
80.0
160.0
160.0
320.0
µA 5.5
5.0
0
5.0
VCC
or
GND
Vis =V
EE
or VCC;
Vos =
VCC or VEE
ICC additional
quiescent supply
current per input
pin for unit load
coefficient is 1
(note 1)
100 360 450 490 µA 4.5
to
5.5
0VCC
2.1
V
other
inputs at
VCC or
GND
INPUT UNIT LOAD COEFFICIENT
E1,E
2
S
n
LE
0.50
0.50
1.5
December 1990 10
Philips Semiconductors Product specification
Triple 2-channel analog
multiplexer/demultiplexer with latch 74HC/HCT4353
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr=t
f= 6 ns; CL= 50 pF
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HCT VCC
(V) VEE
(V) OTHER+25 40 to +85 40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
Vis to Vos
5
4
12
8
15
10
18
12
ns 4.5
4.5
0
4.5
RL=;
CL= 50 pF
(see Fig.18)
tPZH/ tPZL turn “ON” time
E1to Vos
26
22
55
45
69
56
83
68
ns 4.5
4.5
0
4.5
RL=1k;
C
L= 50 pF
(see Fig.19)
tPZH/ tPZL turn “ON” time
E2to Vos
22
18
50
40
63
50
75
60
ns 4.5
4.5
0
4.5
RL=1k;
C
L= 50 pF
(see Fig.19)
tPZH/ tPZL turn “ON” time
LE to Vos
21
17
45
40
56
50
68
60
ns 4.5
4.5
0
4.5
RL=1k;
C
L= 50 pF
(see Fig.19)
tPZH/ tPZL turn “ON” time
Snto Vos
25
19
50
45
63
56
75
68
ns 4.5
4.5
0
4.5
RL=1k;
C
L= 50 pF
(see Fig.19)
tPHZ/ tPLZ turn “OFF” time
E1to Vos
23
19
50
40
63
50
75
60
ns 4.5
4.5
0
4.5
RL=1k;
C
L= 50 pF
(see Fig.19)
tPHZ/ tPLZ turn “OFF” time
E2to Vos
27
23
50
40
63
50
75
60
ns 4.5
4.5
0
4.5
RL=1k;
C
L= 50 pF
(see Fig.19)
tPHZ/ tPLZ turn “OFF” time
LE to Vos
19
19
40
40
50
50
60
60
ns 4.5
4.5
0
4.5
RL=1k;
C
L= 50 pF
(see Fig.19)
tPHZ/ tPLZ turn “OFF” time
Snto Vos
22
22
45
45
56
56
68
68
ns 4.5
4.5
0
4.5
RL=1k;
C
L= 50 pF
(see Fig.19)
tsu set-up time
Snto LE
12
15
7
9
15
19
18
22
ns 4.5
4.5
0
4.5
RL=1k;
C
L= 50 pF
(see Fig.20)
thhold time
Snto LE
5
5
0
2
5
5
5
5
ns 4.5
4.5
0
4.5
RL=1k;
C
L= 50 pF
(see Fig.20)
tWLE minimum pulse
width HIGH
16
16
3
5
20
20
24
24
ns 4.5
4.5
0
4.5
RL=1k;
C
L= 50 pF
(see Fig.20)
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December 1990 11
Philips Semiconductors Product specification
Triple 2-channel analog
multiplexer/demultiplexer with latch 74HC/HCT4353
Fig.8 Test circuit for measuring RON.Fig.9 Typical RON as a function of input voltage
Vis for Vis = 0 to VCC VEE.
Fig.10 Test circuit for measuring OFF-state current.
Fig.11 Test circuit for measuring ON-state current.
um“ mu .ma 1 1 . « . m m In m m “m, m
December 1990 12
Philips Semiconductors Product specification
Triple 2-channel analog
multiplexer/demultiplexer with latch 74HC/HCT4353
ADDITIONAL AC CHARACTERISTICS FOR 74HC/HCT
Recommended conditions and typical values
GND = 0 V; Tamb =25°C
Notes to the AC characteristics
1. Adjust input voltage Vis to 0 dBm level (0 dBm = 1 mW into 600 ).
2. Adjust input voltage Vis to 0 dBm level at Vos for 1 MHz (0 dBm = 1 mW into 50 ).
General note
Vis is the input voltage at an nYnor nZ terminal, whichever is assigned as an input.
Vos is the output voltage at an nYnor nZ terminal, whichever is assigned as an output.
SYMBOL PARAMETER typ. UNIT VCC
(V) VEE
(V) Vis(p-p)
(V) CONDITIONS
sine-wave distortion
f = 1 kHz
0.04
0.02
%
%
2.25
4.5
2.25
4.5
4.0
8.0
RL= 10 k;C
L= 50 pF
(see Fig.14)
sine-wave distortion
f = 10 kHz
0.12
0.06
%
%
2.25
4.5
2.25
4.5
4.0
8.0
RL= 10 k;C
L= 50 pF
(see Fig.14)
switch “OFF” signal
feed-through
50
50
dB
dB
2.25
4.5
2.25
4.5
note 1 RL= 600 ;C
L= 50 pF
f = 1 MHz (see Figs 12 and 15)
crosstalk between
any two switches/
multiplexers
60
60
dB
dB
2.25
4.5
2.25
4.5
note 1 RL= 600 ;C
L= 50 pF;
f = 1 MHz (see Fig.16)
V(pp) crosstalk voltage between
control and any switch
(peak-to-peak value)
110
220
mV
mV
4.5
4.5
0
4.5
RL= 600 ;C
L= 50 pF;
f = 1 MHz (E1,E
2or Sn,
square-wave between
VCC and GND, tr=t
f= 6 ns)
(see Fig.17)
fmax minimum frequency response
(3dB)
160
170
MHz
MHz
2.25
4.5
2.25
4.5
note 2 RL=50;C
L= 10 pF
(see Figs 13 and 14)
CSmaximum switch capacitance
independent (Y)
common (Z)
5
12
pF
pF
Fig.12 Typical switch “OFF” signal feed-through as a function of frequency.
Test conditions:
VCC = 4.5 V; GND = 0 V; VEE =4.5 V;
RL=50;R
source =1 k.
mm- (-1 w m2 m: m m- , M, m Gnu Mn Gun 1mm Vac an "Va/"l BUY :uL VIII-v) 1mm
December 1990 13
Philips Semiconductors Product specification
Triple 2-channel analog
multiplexer/demultiplexer with latch 74HC/HCT4353
Fig.13 Typical frequency response.
Test conditions:
VCC = 4.5 V; GND = 0 V; VEE =4.5 V;
RL=50;R
source =1 k.
Fig.14 Test circuit for measuring sine-wave
distortion and minimum frequency
response.
Fig.15 Test circuit for measuring switch
“OFF” signal feed-through.
Fig.16 Test circuits for measuring crosstalk between any two switches/multiplexers.
(a) = channel ON condition (b) channel OFF condition.
Fig.17 Test circuit for measuring crosstalk between control and any switch.
The crosstalk is defined as follows
(oscilloscope output):
:, mm v“ mm m . r,” m '- v6. uurrur v_ m m uuun V_ cm: mm“ mm ~oss~ "on" 5" mm VMm ‘_. v., 4..u. a man vu‘“ mm
December 1990 14
Philips Semiconductors Product specification
Triple 2-channel analog
multiplexer/demultiplexer with latch 74HC/HCT4353
AC WAVEFORMS
Fig.18 Waveforms showing the input (Vis)to
output (Vos) propagation delays.
Fig.19 Waveforms showing the turn-ON and
turn-OFF times.
(1) HC : VM= 50%; VI= GND to VCC.
HCT : VM= 1.3 V; VI= GND to 3 V.
Fig.20 Waveforms showing the set-up and hold
times from Sn inputs to LE input, and
minimum pulse width of LE.
(1) HC : VM= 50%; VI= GND to VCC.
HCT : VM= 1.3 V; VI= GND to 3 V.
Vcc V». Vcc stE V’ GEMEIAYDI " u.v. n, mm. .— m ——— W AurLII’uDE uscmv: mruv ms: w — Aumrunz msmv: mm runs m M o—‘w—-—. mum
December 1990 15
Philips Semiconductors Product specification
Triple 2-channel analog
multiplexer/demultiplexer with latch 74HC/HCT4353
TEST CIRCUIT AND WAVEFORMS
Fig.21 Test circuit for measuring AC performance.
Conditions
TEST SWITCH Vis
tPZH
tPZL
tPHZ
tPLZ
others
VEE
VCC
VEE
VCC
open
VCC
VEE
VCC
VEE
pulse
FAMILY AMPLITUDE VM
tr;t
f
f
max;
PULSE WIDTH OTHER
74HC VCC 50% <2 ns 6 ns
74HCT 3.0 V 1.3 V <2 ns 6 ns
CL= load capacitance including jig and probe capacitance (see AC CHARACTERISTICS for values).
RT= termination resistance should be equal to the output impedance ZOof the pulse generator.
tr=t
f
= 6 ns; when measuring fmax, there is no constraint on tr, tfwith 50% duty factor.
Fig.22 Input pulse definitions.
Conditions
TEST SWITCH Vis
tPZH
tPZL
tPHZ
tPLZ
others
VEE
VCC
VEE
VCC
open
VCC
VEE
VCC
VEE
pulse
FAMILY AMPLITUDE VM
tr;t
f
f
max;
PULSE WIDTH OTHER
74HC VCC 50% <2 ns 6 ns
74HCT 3.0 V 1.3 V <2 ns 6 ns
CL= load capacitance including jig and probe capacitance (see AC CHARACTERISTICS for values).
RT= termination resistance should be equal to the output impedance ZOof the pulse generator.
tr=t
f
= 6 ns; when measuring fmax, there is no constraint on tr, tfwith 50% duty factor.
December 1990 16
Philips Semiconductors Product specification
Triple 2-channel analog
multiplexer/demultiplexer with latch 74HC/HCT4353
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.

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