74HC(T)03 Datasheet by NXP USA Inc.

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1. General description
The 74HC03; 74HCT03 is a quad 2-input NAND gate with open-drain outputs. Inputs
include clamp diodes that enable the use of current limiting resistors to interface inputs to
voltages in excess of VCC.
2. Features and benefits
Input levels:
For 74HC03: CMOS level
For 74HCT03: TTL level
Complies with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
3. Ordering information
74HC03; 74HCT03
Quad 2-input NAND gate; open-drain output
Rev. 4 — 27 November 2015 Product data sheet
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74HC03D 40 C to +125 C SO14 plastic small outline package; 14 leads; body width
3.9 mm SOT108-1
74HCT03D
74HC03DB 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body
width 5.3 mm SOT337-1
74HCT03DB
74HC03PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm SOT402-1
74HCT03PW
H T H T H T 9; m3 III/13212 ass-009093 ammm n o U U U U H U U U U U U U U U flflflflflflfl UUUUUUU ass-009064 ass-009055
74HC_HCT03 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 27 November 2015 2 of 14
NXP Semiconductors 74HC03; 74HCT03
Quad 2-input NAND gate; open-drain output
4. Functional diagram
5. Pinning information
5.1 Pinning
5.2 Pin description
Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate)
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Fig 4. Pin configuration SO14 Fig 5. Pin configuration (T)SSOP14
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Table 2. Pin description
Symbol Pin Description
1A to 4A 1, 4, 9, 12 data input
1B to 4B 2, 5, 10, 13 data input
1Y to 4Y 3, 6, 8, 11 data output
GND 7 ground (0 V)
VCC 14 supply voltage
la,
74HC_HCT03 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 27 November 2015 3 of 14
NXP Semiconductors 74HC03; 74HCT03
Quad 2-input NAND gate; open-drain output
6. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state.
7. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO14 package: Ptot derates linearly with 8 mW/K above 70 C.
For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
8. Recommended operating conditions
Table 3. Function table[1]
Input Output
nA nB nY
LLZ
LHZ
HL Z
HHL
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +7 V
VOoutput voltage [1] 0.5 +7 V
IIK input clamping current VI < 0.5 V or VI>V
CC +0.5 V [1] -20 mA
IOK output clamping current VO<0.5 V [1] -20 mA
IOoutput current 0.5 V < VO-25 mA
ICC supply current - 50 mA
IGND ground current 50 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation [2]
SO14 and (T)SSOP14
packages -500mW
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions 74HC03 74HCT03 Unit
Min Typ Max Min Typ Max
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
VIinput voltage 0 - VCC 0-V
CC V
VOoutput voltage 0 - VCC 0-V
CC V
Tamb ambient temperature 40 +25 +125 40 +25 +125 C
t/V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V - - 83 - - - ns/V
74HC_HCT03 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 27 November 2015 4 of 14
NXP Semiconductors 74HC03; 74HCT03
Quad 2-input NAND gate; open-drain output
9. Static characteristics
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
74HC03
VIH HIGH-level
input voltage VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V
VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V
VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V
VIL LOW-level
input voltage VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V
VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V
VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V
VOL LOW-level
output voltage VI = VIH or VIL
IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V
IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V
IIinput leakage
current VI = VCC or GND;
VCC =6.0V -0.1- - 1-1A
IOZ OFF-state
output current per input pin; VI=V
IL;
VO=V
CC or GND;
other inputs at VCC or GND;
VCC =6.0V; I
O=0A
- - ±0.5 - ±5.0 - ±10 A
ICC supply current VI = VCC or GND; IO=0A;
VCC =6.0V -2.0- - 20 - 40A
CIinput
capacitance -3.5- - - - -pF
74HCT03
VIH HIGH-level
input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V
VIL LOW-level
input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V
VOL LOW-level
output voltage VI=V
IH or VIL; VCC =4.5V
IO=20A - 0 0.1 - 0.1 - 0.1 V
IO= 4.0 mA - 0.15 0.26 - 0.33 - 0.4 V
IIinput leakage
current VI=V
CC or GND;
VCC =5.5V --0.1 - 1-1A
IOZ OFF-state
output current per input pin; VI=V
IL;
VO=V
CC or GND;
other inputs at VCC or GND;
VCC = 5.5 V; IO=0A
- - ±0.5 - ±5.0 - ±10 A
Figure 7 Figure 6
74HC_HCT03 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 27 November 2015 5 of 14
NXP Semiconductors 74HC03; 74HCT03
Quad 2-input NAND gate; open-drain output
10. Dynamic characteristics
ICC supply current VI = VCC or GND; IO=0A;
VCC =5.5V --2.0- 20 - 40A
ICC additional
supply current per input pin;
VI=V
CC 2.1 V; IO=0A;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V
- 100 360 - 450 - 490 A
CIinput
capacitance -3.5- - - - -pF
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
Table 7. Dynamic characteristics
GND = 0 V; CL= 50 pF; for test circuit, see Figure 7.
Symbol Parameter Conditions 25 C40 C to +125 CUnit
Min Typ Max Max
(85 C) Max
(125 C)
74HC03
tpd propagation delay nA, nB to nY; see Figure 6 [1]
VCC = 2.0 V - 28 95 120 145 ns
VCC = 4.5 V - 10 19 24 29 ns
VCC = 5.0 V; CL=15pF - 8 - - - ns
VCC = 6.0 V - 8 16 20 25 ns
tttransition time see Figure 6 [2]
VCC = 2.0 V - 19 75 95 110 ns
VCC = 4.5 V - 7 15 19 22 ns
VCC = 6.0 V - 6 13 16 19 ns
CPD power dissipation
capacitance per package; VI=GNDtoV
CC [3] -4- - -pF
Fig r97
74HC_HCT03 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 27 November 2015 6 of 14
NXP Semiconductors 74HC03; 74HCT03
Quad 2-input NAND gate; open-drain output
[1] tpd is the same as tPLZ and tPZL.
[2] tt is the same as tTHL.
[3] CPD is used to determine the dynamic power dissipation (PD in W):
PD=C
PD VCC2fiN+ (CLVCC2fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CLVCC2fo) = sum of outputs.
11. Waveforms
74HCT03
tpd propagation delay nA, nB to nY; see Figure 6 [1]
VCC = 4.5 V - 12 24 30 36 ns
VCC = 5.0 V; CL=15pF - 10 - - - ns
tttransition time VCC = 4.5 V; see Figure 6 [2] - 7 15 19 22 ns
CPD power dissipation
capacitance per package;
VI=GNDtoV
CC 1.5 V
[3] -4- - -pF
Table 7. Dynamic characteristics …continued
GND = 0 V; CL= 50 pF; for test circuit, see Figure 7.
Symbol Parameter Conditions 25 C40 C to +125 CUnit
Min Typ Max Max
(85 C) Max
(125 C)
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6. Input to output propagation delays
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Table 8. Measurement points
Type Input Output
VMVMVX
74HC03 0.5VCC 0.5VCC 0.1VCC
74HCT03 1.3 V 1.3 V 0.1VCC
74HC_HCT03 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 27 November 2015 7 of 14
NXP Semiconductors 74HC03; 74HCT03
Quad 2-input NAND gate; open-drain output
Test data is given in Table 9.
Definitions test circuit:
RT = termination resistance should be equal to output impedance Zo of the pulse generator.
CL = load capacitance including jig and probe capacitance.
Fig 7. Test circuit for measuring switching times
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Table 9. Test data
Type Input Load S1 position
VItr, tfCLRLtPZL, tPLZ
74HC03 VCC 6ns 15pF, 50pF 1kVCC
74HCT03 3.0 V 6 ns 15 pF, 50 pF 1 kVCC
74HC_HCT03 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 27 November 2015 8 of 14
NXP Semiconductors 74HC03; 74HCT03
Quad 2-input NAND gate; open-drain output
12. Package outline
Fig 8. Package outline SOT108-1 (SO14)
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74HC_HCT03 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 27 November 2015 9 of 14
NXP Semiconductors 74HC03; 74HCT03
Quad 2-input NAND gate; open-drain output
Fig 9. Package outline SOT337-1 (SSOP14)
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74HC_HCT03 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 27 November 2015 10 of 14
NXP Semiconductors 74HC03; 74HCT03
Quad 2-input NAND gate; open-drain output
Fig 10. Package outline SOT402-1 (TSSOP14)
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74HC_HCT03 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 27 November 2015 11 of 14
NXP Semiconductors 74HC03; 74HCT03
Quad 2-input NAND gate; open-drain output
13. Abbreviations
14. Revision history
Table 10. Abbreviations
Acronym Description
CMOS Complementary Metal-Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74HC_HCT03 v.4 20151127 Product data sheet - 74HC_HCT03 v.3
Modifications: Type numbers 74HC03N and 74HCT03N (SOT27-1) removed.
74HC_HCT03 v.3 20130627 Product data sheet - 74HC_HCT03_CNV v.2
Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines
of NXP Semiconductors.
Legal texts have been adapted to the new company name where appropriate.
74HC_HCT03_CNV v.2 19970827 Product specification - -
74HC_HCT03 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 27 November 2015 12 of 14
NXP Semiconductors 74HC03; 74HCT03
Quad 2-input NAND gate; open-drain output
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
hug :l/www. nxgcom salesaddresses®nx9£0m
74HC_HCT03 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 27 November 2015 13 of 14
NXP Semiconductors 74HC03; 74HCT03
Quad 2-input NAND gate; open-drain output
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74HC03; 74HCT03
Quad 2-input NAND gate; open-drain output
© NXP Semiconductors N.V. 2015. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 27 November 2015
Document identifier: 74HC_HCT03
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2
6 Functional description . . . . . . . . . . . . . . . . . . . 3
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
8 Recommended operating conditions. . . . . . . . 3
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 11
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 11
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 12
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
16 Contact information. . . . . . . . . . . . . . . . . . . . . 13
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

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