74ABT646A Datasheet by NXP USA Inc.

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1. General description
The 74ABT646A high-performance BiCMOS device combines low static and dynamic
power dissipation with high speed and high output drive.
The 74ABT646A transceiver/register consists of bus transceiver circuits with 3-state
outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of
data directly from the input bus or the internal registers. Data on the A bus or B bus will be
clocked into the registers as the appropriate clock pin (CPAB or CPBA) goes HIGH.
Output Enable (OE) and Direction (DIR) pins are provided to control the transceiver
function. In the transceiver mode, data present at the high-impedance port may be stored
in either the A or B register or both.
The Select (SAB, SBA) pins determine whether data is stored or transferred through the
device in real-time. The DIR pin determines which bus receives data when OE is active
(LOW). In isolation mode (OE = HIGH), data from bus A may be stored in the B register
and/or data from bus B may be stored in the A register. When an output function is
disabled, the input function is still enabled and may be used to store and transmit data.
Only one of the two buses, A or B, may be driven at a time. The examples in Figure 5
“Real time bus transfer and storage” on page 6 demonstrate the four fundamental bus
management functions that can be performed with the 74ABT646A.
2. Features and benefits
nCombines 74ABT245 and 74ABT373A type functions in one device
nIndependent registers for A and B buses
nMultiplexed real-time and stored data
nLive insertion and extraction permitted
nOutput capability: +64 mA to 32 mA
nPower-up 3-state
nPower-up reset
nLatch-up protection exceeds 500 mA per JESD78B class II level A
nESD protection:
uHBM JESD22-A114F exceeds 2000 V
uMM JESD22-A115-A exceeds 200 V
74ABT646A
Octal bus transceiver/register; 3-state
Rev. 03 — 15 March 2010 Product data sheet
11111111 111111 11111111
74ABT646A_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 03 — 15 March 2010 2 of 19
NXP Semiconductors 74ABT646A
Octal bus transceiver/register; 3-state
3. Ordering information
4. Functional diagram
Table 1. Ordering information
Type number Package
Temperature
range Name Description Version
74ABT646AD 40 °C to +85 °C SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1
74ABT646ADB 40 °C to +85 °C SSOP24 plastic shrink small outline package; 24 leads;
body width 5.3 mm SOT340-1
74ABT646APW 40 °C to +85 °C TSSOP24 plastic thin shrink small outline package; 24 leads;
body width 4.4 mm SOT355-1
Fig 1. Logic symbol Fig 2. IEC logic symbol
001aae891
22
21
SBA
OE
B0 B1 B2 B3 B4 B5 B6 B7
A0 A1 A2 A3 A4 A5 A6 A7
20 19 18 17 16 15 14 13
4567891011
23 CPBA
3 DIR
SAB
CPAB
2
1
001aae892
519
1
1
6
61
4D
5D
17
7
C4
C5
3EN2[AB]
G7
3EN1[BA]
618
717
816
915
10 14
11 13
1
2
3
2
23
G6
22
1
4
G3
21
20
74ABT646A_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 03 — 15 March 2010 3 of 19
NXP Semiconductors 74ABT646A
Octal bus transceiver/register; 3-state
Fig 3. Logic diagram
001aae894
5
Q
A1
4
A0
2
SAB
1
CPAB
22
SBA
23
CPBA
3
DIR
21
OE
1D
1 of 8 channels
DETAIL A × 7
6
A2 7
A3 8
A4 9
A5 10
A6 11
A7
B1
C1
B2
B3
B4
B5
B6
B7
19
B0
20
18
17
16
15
14
13
Q
1D
C1
_ jjjjjjjjjjjj O EEEEEEEEEEEE
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Product data sheet Rev. 03 — 15 March 2010 4 of 19
NXP Semiconductors 74ABT646A
Octal bus transceiver/register; 3-state
5. Pinning information
5.1 Pinning
5.2 Pin description
Fig 4. Pin configuration
74ABT646A
CPAB VCC
SAB CPBA
DIR SBA
A0 OE
A1 B0
A2 B1
A3 B2
A4 B3
A5 B4
A6 B5
A7 B6
GND B7
001aae890
1
2
3
4
5
6
7
8
9
10
11
12
14
13
16
15
18
17
20
19
22
21
24
23
Table 2. Pin description
Symbol Pin Description
CPAB 1 A to B clock input
SAB 2 A to B select input
DIR 3 direction control input
A0, A1, A2, A3, A4, A5, A6, A7 4, 5, 6, 7, 8, 9, 10, 11 data input/output (A side)
GND 12 ground (0 V)
B0, B1, B2, B3, B4, B5, B6, B7 20, 19, 18, 17, 16, 15, 14, 13 data input/output (B side)
OE 21 output enable input (active LOW)
SBA 22 B to A select input
CPBA 23 B to A clock input
VCC 24 positive supply voltage
74ABT646A_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 03 — 15 March 2010 5 of 19
NXP Semiconductors 74ABT646A
Octal bus transceiver/register; 3-state
6. Functional description
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
= LOW-to-HIGH clock transition;
[2] The data output function may be enabled or disabled by various signals at the OE input. Data input functions are always enabled,
i.e. data at the bus pins will be stored on every LOW-to-HIGH transition of the clock.
Table 3. Function table[1]
Inputs Data I/O Operating mode
OE DIR CPAB CPBA SAB SBA An Bn
XXX X X input unspecified
output[2] store A, B unspecified
XXXX X unspecified
output[2] input store B, A unspecified
HX↑↑X X input input store A and B data
H X H or L H or L X X input input isolation, hold storage
LLXXXLoutput input real time B data to A bus
L L X H or L X H output input stored B data to A bus
L H X X L X input output real time A data to B bus
L H H or L X H X input output stored A data to B bus
my
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
74ABT646A_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 03 — 15 March 2010 6 of 19
NXP Semiconductors 74ABT646A
Octal bus transceiver/register; 3-state
Fig 5. Real time bus transfer and storage
CPAB
X
AB
CPBA
X
DIR
LSAB
XSBA
L
OE
L
REAL TIME BUS TRANSFER
BUS B TO BUS A
AB
CPAB
XCPBA
X
DIR
HSAB
LSBA
X
OE
L
REAL TIME BUS TRANSFER
BUS A TO BUS B
CPAB
X
CPBA
X
DIR
H
L
X
SAB
X
X
X
SBA
X
X
X
OE
L
L
H
AB
STORAGE FROM
A, B, OR A AND B
001aae893
CPAB
X
H/L
CPBA
H/L
X
DIR
L
H
SAB
X
H
SBA
H
X
OE
L
L
AB
TRANSFER STORED DATA
TO A OR B
74ABT646A_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 03 — 15 March 2010 7 of 19
NXP Semiconductors 74ABT646A
Octal bus transceiver/register; 3-state
7. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C.
8. Recommended operating conditions
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +7.0 V
VIinput voltage [1] 1.2 +7.0 V
VOoutput voltage output in OFF-state or HIGH-state [1] 0.5 +5.5 V
IIK input clamping current VI < 0 V 18 - mA
IOK output clamping current VO < 0 V 50 - mA
IOoutput current output in LOW-state - 128 mA
Tjjunction temperature [2] - 150 °C
Tstg storage temperature 65 +150 °C
Table 5. Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
VCC supply voltage 4.5 - 5.5 V
VIinput voltage 0 - VCC V
VIH HIGH-level input voltage 2.0 - - V
VIL LOW-level input voltage - - 0.8 V
IOH HIGH-level output current 32--mA
IOL LOW-level output current - - 64 mA
t/V input transition rise and fall rate 0 - 10 ns/V
Tamb ambient temperature in free air 40 - +85 °C
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Product data sheet Rev. 03 — 15 March 2010 8 of 19
NXP Semiconductors 74ABT646A
Octal bus transceiver/register; 3-state
9. Static characteristics
[1] For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
[2] This parameter is valid for any VCC between 0 V and 2.1 V with a transition time of up to 10 ms. For VCC =2.1VtoV
CC =5V±10 %, a
transition time of up to 100 µs is permitted.
[3] Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
[4] This is the increase in supply current for each input at 3.4 V.
[5] This data sheet limit may vary among suppliers.
Table 6. Static characteristics
Symbol Parameter Conditions 25 °C40 °Cto85°C Unit
Min Typ Max Min Max
VIK input clamping voltage VCC = 4.5 V; IIK =18 mA 1.2 0.9 - 1.2 - V
VOH HIGH-level output
voltage VI = VIL or VIH
VCC = 4.5 V; IOH =3 mA 2.5 3.0 - 2.5 - V
VCC = 5.0 V; IOH =3 mA 3.0 3.5 - 3.0 - V
VCC = 4.5 V; IOH =32 mA 2.0 2.4 - 2.0 - V
VOL LOW-level output voltage VCC = 4.5 V; IOL =64mA;
VI=V
IL or VIH
- 0.3 0.55 - 0.55 V
VOL(pu) power-up LOW-level
output voltage VCC = 5.5 V; IO= 1 mA;
VI= GND or VCC
[1] - 0.13 0.55 - 0.55 V
IIinput leakage current VCC = 5.5 V; VI = GND or 5.5 V
control pins - ±0.0
1±1.0 - ±1.0 µA
data pins - ±5±100 - ±100 µA
IOFF power-off leakage current VCC = 0 V; VIor VO 4.5 V - ±5.0 ±100 - ±100 µA
IO(pu/pd) power-up/power-down
output current VCC = 2.1 V; VO = 0.5 V;
VI= GND or VCC; OE HIGH
[2] -±5.0 ±50 - ±50 µA
IOZ OFF-state output current VCC = 5.5 V; VI=V
IL or VIH
VO = 2.7 V - 5.0 50 - 50 µA
VO = 0.5 V - 5.0 50 - 50 µA
ILO output leakage current VCC = 5.5 V; HIGH-state;
VO= 5.5 V; VCC = 5.5 V;
VI= GND or VCC
- 5.0 50 - 50 µA
IOoutput current VCC = 5.5 V; VO = 2.5 V [3][5] 180 65 40 180 40 mA
ICC supply current VCC = 5.5 V; VI = GND or VCC
outputs HIGH-state - 110 250 - 250 µA
outputs LOW-state - 20 30 - 30 mA
outputs disabled - 110 250 - 250 µA
ICC additional supply current per input pin; VCC = 5.5 V; one input
at 3.4 V; other inputs at VCC or GND
[4] - 0.6 1.5 - 1.5 mA
CIinput capacitance control pins; VI = 0 V or VCC -4- - -pF
CI/O input/output capacitance I/O pins; outputs disabled; VO=0V
or VCC
-7- - -pF
74ABT646A_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 03 — 15 March 2010 9 of 19
NXP Semiconductors 74ABT646A
Octal bus transceiver/register; 3-state
10. Dynamic characteristics
[1] This data sheet limit may vary among suppliers.
Table 7. Dynamic characteristics
GND = 0 V; for test circuit, see Figure 11.
Symbol Parameter Conditions 25 °C; VCC = 5.0 V 40 °C to +85 °C;
VCC = 5.0 V ±0.5 V Unit
Min Typ Max Min Max
fmax maximum frequency see Figure 6 125 350 - 125 - MHz
tPLH LOW to HIGH
propagation delay CPAB to Bn or CPBA to An;
see Figure 6 2.2 3.9 5.1 2.2 5.6 ns
An to Bn or Bn to An; see Figure 7 1.5 3.2 4.3 1.5 4.8 ns
SAB to Bn or SBA to An; see Figure 7 1.5 3.8 5.1 1.5 6.5 ns
tPHL HIGH to LOW
propagation delay CPAB to Bn or CPBA to An;
see Figure 6 1.7 4.4 5.2[1] 1.7 5.6 ns
An to Bn or Bn to An; see Figure 7 1.5 3.7 4.6 1.5 5.4 ns
SAB to Bn or SBA to An; see Figure 7 1.5 4.4 5.3[1] 1.5 5.9 ns
tPZH OFF-state to HIGH
propagation delay OE to An or Bn; see Figure 8 1.5 3.5 5.3 1.5 6.3 ns
DIR to An or Bn; see Figure 8 1.5 3.9 5.7 1.2 6.7 ns
tPZL OFF-state to LOW
propagation delay OE to An or Bn; see Figure 9 3.0 4.5 7.4 3.0 8.8 ns
DIR to An or Bn; see Figure 9 2.5 4.7 9.0 2.5 9.5 ns
tPHZ HIGH to OFF-state
propagation delay OE to An or Bn; see Figure 8 1.5 4.0 4.8[1] 1.5 5.3[1] ns
DIR to An or Bn; see Figure 8 1.5 4.0 5.0 1.5 5.7 ns
tPLZ LOW to OFF-state
propagation delay OE to An or Bn; see Figure 9 1.5 3.3 4.0 1.5 4.5 ns
DIR to An or Bn; see Figure 9 1.5 3.5 4.7 1.5 6.0 ns
tsu(H) set-up time HIGH An to CPAB, Bn to CPBA; see Figure 10 3.0 0.7 - 3.0 - ns
tsu(L) set-up time LOW An to CPAB, Bn to CPBA; see Figure 10 3.0 0.7 - 3.0 - ns
th(H) hold time HIGH An to CPAB, Bn to CPBA; see Figure 10 +0.0 0.5 - 0.0 - ns
th(L) hold time LOW An to CPAB, Bn to CPBA; see Figure 10 +0.0 0.5 - 0.0 - ns
tWH pulse width HIGH CPAB, CPBA; see Figure 6 4.0 0.9 - 4.0 - ns
tWL pulse width LOW LE; see Figure 6 4.0 1.4 - 4.0 - ns
%w P A
74ABT646A_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 03 — 15 March 2010 10 of 19
NXP Semiconductors 74ABT646A
Octal bus transceiver/register; 3-state
11. Waveforms
VM = 1.5 V
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6. Propagation delay clock input to output and clock pulse width, maximum clock frequency
001aae839
tPHL tPLH
tWH tWL
1 / fmax
VM
VI
VOH
GND
VOL
VMVM
VMVM
CPBA or
CPAB
An or Bn
VM = 1.5 V
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7. Propagation delay, SAB to Bn or SBA to An, An to Bn or Bn to An
001aae895
VM
VI
GND
VOH
VOL
VM
tPLH tPHL
VMVM
SBA or SAB,
An or Bn
An or Bn
VM = 1.5 V
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 8. 3-state output enable time to HIGH-level and output disable time from HIGH-level
001aae896
An or Bn
VM
VI
GND
VOH
GND
VOH 0.3 V
VM
tPHZ
tPZH
VM
OE, DIR
74ABT646A_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 03 — 15 March 2010 11 of 19
NXP Semiconductors 74ABT646A
Octal bus transceiver/register; 3-state
VM = 1.5 V
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 9. 3-state output enable time to LOW-level and output disable time from LOW-level
001aae898
An or Bn
VM
VI
GND
3.5 V
VOL
VM
tPLZ
tPZL
VM
OE, DIR
VOL + 0.3 V
VM = 1.5 V
VOL and VOH are typical voltage output levels that occur with the output load.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 10. Data set-up and hold times
001aae849
VM
VI
GND
VI
GND
An, Bn
CPBA or
CPAB
VMVM
VMVM
VM
tsu(H) th(H) tsu(L)
tWL
th(L)
ifliifl
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Product data sheet Rev. 03 — 15 March 2010 12 of 19
NXP Semiconductors 74ABT646A
Octal bus transceiver/register; 3-state
a. Input pulse definition b. Test circuit
Test data is given in Table 8.
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = Test voltage for switching times.
Fig 11. Load circuitry for switching times
001aai298
VMVM
tW
tW
10 %
90 % 90 %
0 V
VI
VI
negative
pulse
positive
pulse
0 V
VMVM
90 %
10 %
90 %
10 % 10 %
tf
tr
tr
tf
VEXT
VCC
VIVO
mna616
DUT
CL
RT
RL
RL
G
Table 8. Test data
Input Load VEXT
VIfItWtr, tfCLRLtPHL, tPLH tPZH, tPHZ tPZL, tPLZ
3.0 V 1 MHz 500 ns 2.5 ns 50 pF 500 open open 7.0 V
Emmi ‘fl_ MHHHHHHHHHHH , ng’ ‘ :%7 A A >%‘ :4? HHHHjJDHL‘HHHHJH. S
74ABT646A_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 03 — 15 March 2010 13 of 19
NXP Semiconductors 74ABT646A
Octal bus transceiver/register; 3-state
12. Package outline
Fig 12. Package outline SOT137-1 (SO24)
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZ
ywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
2.65 0.3
0.1 2.45
2.25 0.49
0.36 0.32
0.23 15.6
15.2 7.6
7.4 1.27 10.65
10.00 1.1
1.0 0.9
0.4 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.1
0.4
SOT137-1
X
12
24
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
c
L
vMA
13
(A )
3
A
y
0.25
075E05 MS-013
pin 1 index
0.1 0.012
0.004 0.096
0.089 0.019
0.014 0.013
0.009 0.61
0.60 0.30
0.29 0.05
1.4
0.055
0.419
0.394 0.043
0.039 0.035
0.016
0.01
0.25
0.01 0.004
0.043
0.016
0.01
e
1
0 5 10 mm
scale
SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1
99-12-27
03-02-19
74ABT646A_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 03 — 15 March 2010 14 of 19
NXP Semiconductors 74ABT646A
Octal bus transceiver/register; 3-state
Fig 13. Package outline SOT340-1 (SSOP24)
UNIT A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.21
0.05 1.80
1.65 0.38
0.25 0.20
0.09 8.4
8.0 5.4
5.2 0.65 1.25
7.9
7.6 0.9
0.7 0.8
0.4 8
0
o
o
0.13 0.10.2
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
1.03
0.63
SOT340-1 MO-150 99-12-27
03-02-19
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
112
24 13
0.25
y
pin 1 index
0 2.5 5 mm
scale
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1
A
max.
2
HHHHWLHHHH‘HH ’m ,_ |:|
74ABT646A_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 03 — 15 March 2010 15 of 19
NXP Semiconductors 74ABT646A
Octal bus transceiver/register; 3-state
Fig 14. Package outline SOT355-1 (TSSOP24)
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 7.9
7.7 4.5
4.3 0.65 6.6
6.2 0.4
0.3 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT355-1 MO-153 99-12-27
03-02-19
0.25 0.5
0.2
wM
bp
Z
e
112
24 13
pin 1 index
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
D
y
0 2.5 5 mm
scale
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1
A
max.
1.1
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Product data sheet Rev. 03 — 15 March 2010 16 of 19
NXP Semiconductors 74ABT646A
Octal bus transceiver/register; 3-state
13. Abbreviations
14. Revision history
Table 9. Abbreviations
Acronym Description
BiCMOS Bipolar Complementary Metal-Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
Table 10. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74ABT646A_3 20100315 Product data sheet - 74ABT646A_2
Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines
of NXP Semiconductors.
Legal texts have been adapted to the new company name where appropriate.
DIP 24 (SOT222-1) package removed from Section 3 “Ordering information” and Section 12
“Package outline”.
74ABT646A_2 19980217 Product specification - 74ABT646A_1
74ABT646A_1 19950906 Product specification - -
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Product data sheet Rev. 03 — 15 March 2010 17 of 19
NXP Semiconductors 74ABT646A
Octal bus transceiver/register; 3-state
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation -
lost profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the
Terms and conditions of commercial sale
of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. The product is not designed, authorized or warranted to be
suitable for use in medical, military, aircraft, space or life support equipment,
nor in applications where failure or malfunction of an NXP Semiconductors
product can reasonably be expected to result in personal injury, death or
severe property or environmental damage. NXP Semiconductors accepts no
liability for inclusion and/or use of NXP Semiconductors products in such
equipment or applications and therefore such inclusion and/or use is at the
customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on a weakness or default in the
customer application/use or the application/use of customer’s third party
customer(s) (hereinafter both referred to as “Application”). It is customer’s
sole responsibility to check whether the NXP Semiconductors product is
suitable and fit for the Application planned. Customer has to do all necessary
testing for the Application in order to avoid a default of the Application and the
product. NXP Semiconductors does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
74ABT646A_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 03 — 15 March 2010 18 of 19
NXP Semiconductors 74ABT646A
Octal bus transceiver/register; 3-state
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74ABT646A
Octal bus transceiver/register; 3-state
© NXP B.V. 2010. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 15 March 2010
Document identifier: 74ABT646A_3
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6 Functional description . . . . . . . . . . . . . . . . . . . 5
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7
8 Recommended operating conditions. . . . . . . . 7
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 8
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 16
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
15.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
16 Contact information. . . . . . . . . . . . . . . . . . . . . 18
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

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