74ABT544 Datasheet by NXP USA Inc.

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1. General description
The 74ABT544 high performance BiCMOS device combines low static and dynamic
power dissipation with high speed and high output drive.
The 74ABT544 octal latched transceiver contains two sets of D-type latches for temporary
storage of data flowing in either direction. Separate latch enable (LEAB, LEBA) and output
enable (OEAB, OEBA) inputs are provided for each register to permit independent control
of data transfer in either direction. The outputs are guaranteed to sink 64 mA.
2. Features and benefits
Combines 74ABT640 and 74ABT373 type functions in one device
8-bit octal transceiver with D-type latch
Back-to-back registers for storage
Separate controls for data flow in each direction
Live insertion and extraction permitted
Output capability: +64 mA to 32 mA
Power-up 3-state
Power-up reset
Latch-up protection exceeds 500 mA per JESD78B class II level A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
3. Ordering information
74ABT544
Octal latched transceiver with dual enable; 3-state
Rev. 6 — 3 November 2011 Product data sheet
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74ABT544D 40 Cto+85C SO24 plastic small outline package; 24 leads;
body width 7.5 mm SOT137-1
74ABT544DB 40 Cto+85C SSOP24 plastic shrink small outline package; 24 leads;
body width 5.3 mm SOT340-1
74ABT544PW 40 Cto+85C TSSOP24 plastic thin shrink small outline package; 24 leads;
body width 4.4 mm SOT355-1
11111111 111$ TT 11111111
74ABT544 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 3 November 2011 2 of 16
NXP Semiconductors 74ABT544
Octal latched transceiver with dual enable; 3-state
4. Functional diagram
Fig 1. Logic symbol Fig 2. IEC logic symbol
001aae900
14
1
LEAB
LEBA
B0 B1 B2 B3 B4 B5 B6 B7
A0 A1 A2 A3 A4 A5 A6 A7
22 21 20 19 18 17 16 15
345678910
23
2
13EBA
OEBA
OEAB
11 EAB
001aae901
2
3
6D
5D 22
421
3
G1
2EN4 (AB)
1C5
2
1
1EN3 (BA)
13
G2
2C6
23
14
11
520
619
718
817
916
10 15
Fig 3. Logic diagram
001aac758
4
Q
A1
3
A0
D
LE
DETAIL A
DETAIL A × 7
5
A2 6
A3 7
A4 8
A5 9
A6 10
A7
B1
B2
B3
B4
B5
B6
B7
21
B0
22
20
19
18
17
16
15
QD
LE
2
OEBA
23
EBA
1
LEBA
OEAB
13
EAB
11
LEAB
14
i 7 7 33333333333: O EEEEEEEEEEEE
74ABT544 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 3 November 2011 3 of 16
NXP Semiconductors 74ABT544
Octal latched transceiver with dual enable; 3-state
5. Pinning information
5.1 Pinning
5.2 Pin description
Fig 4. Pin configuration
LEBA
OEAB
74ABT544
VCC
OEBA EBA
A0 B0
A1 B1
A2 B2
A3 B3
A4 B4
A5 B5
A6 B6
A7 B7
EAB LEAB
GND
001aac755
1
2
3
4
5
6
7
8
9
10
11
12
14
13
16
15
18
17
20
19
22
21
24
23
Table 2. Pin description
Symbol Pin Description
LEBA 1 B-to-A latch enable input (active LOW)
OEBA 2 B-to-A output enable input (active LOW)
A0 to A7 3, 4, 5, 6, 7, 8, 9, 10 data input or output
EAB 11 A-to-B enable input (active LOW)
GND 12 ground (0 V)
OEAB 13 A-to-B output enable input (active LOW)
LEAB 14 A-to-B latch enable input (active LOW)
B0 to B7 22, 21, 20, 19, 18, 17, 16, 15 data input or output
EBA 23 B-to-A enable input (active LOW)
VCC 24 positive supply voltage
74ABT544 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 3 November 2011 4 of 16
NXP Semiconductors 74ABT544
Octal latched transceiver with dual enable; 3-state
6. Functional description
6.1 Function table
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition of LEXX or EXX (XX = AB or BA);
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition of LEXX or EXX (XX = AB or BA);
= LOW-to-HIGH clock transition of LEXX or EXX (XX = AB or BA);
NC = no change;
X = don’t care;
Z = high-impedance OFF-state.
6.2 Description
The 74ABT544 contains two sets of eight D-type latches, with separate control pins for
each set.
Using data flow from A-to-B as an example, when the A-to-B enable (EAB) input, the
A-to-B latch enable (LEAB) input and the A-to-B output enable (OEAB) input are all LOW,
the A-to-B path is transparent.
A subsequent LOW-to-HIGH transition of the LEAB signal puts the A data into the latches
where it is stored and the B outputs no longer change with the A inputs. With EAB and
OEAB both LOW, the 3-state B output buffers are active and display the data present at
the outputs of the A latches.
Control of data flow from B-to-A is similar, but using the EBA, LEBA, and OEBA inputs.
Table 3. Function selection[1]
Input Output Status
OEXX EXX LEXX An or Bn Bn or An
H X X X Z disabled
XHXXZ
LL h Z disabled + latch
lZ
LLh L latch + display
lH
L L L H L transparent
LH
L L H X NC hold
74ABT544 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 3 November 2011 5 of 16
NXP Semiconductors 74ABT544
Octal latched transceiver with dual enable; 3-state
7. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 C.
8. Recommended operating conditions
9. Static characteristics
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +7.0 V
VIinput voltage [1] 1.2 +7.0 V
VOoutput voltage output in OFF-state or HIGH-state [1] 0.5 +5.5 V
IIK input clamping current VI < 0 V 18 - mA
IOK output clamping current VO < 0 V 50 - mA
IOoutput current output in LOW-state - 128 mA
Tjjunction temperature [2] -150C
Tstg storage temperature 65 +150 C
Table 5. Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
VCC supply voltage 4.5 - 5.5 V
VIinput voltage 0 - VCC V
VIH HIGH-level input voltage 2.0 - - V
VIL LOW-level input voltage - - 0.8 V
IOH HIGH-level output current 32--mA
IOL LOW-level output current - - 64 mA
t/V input transition rise and fall rate 0 - 10 ns/V
Tamb ambient temperature in free air 40 - +85 C
Table 6. Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C40 C to +85 CUnit
Min Typ Max Min Max
VIK input clamping voltage VCC = 4.5 V; IIK =18 mA 1.2 0.9 - 1.2 - V
VOH HIGH-level output
voltage VI = VIL or VIH
VCC = 4.5 V; IOH =3 mA 2.5 3.2 - 2.5 - V
VCC = 5.0 V; IOH =3 mA 3.0 3.7 - 3.0 - V
VCC = 4.5 V; IOH =32 mA 2.0 2.3 - 2.0 - V
VOL LOW-level output
voltage VCC = 4.5 V; IOL =64mA;
VI=V
IL or VIH
- 0.42 0.55 - 0.55 V
cilcuit, see Figure 10 Figure 5 Figure 6
74ABT544 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 3 November 2011 6 of 16
NXP Semiconductors 74ABT544
Octal latched transceiver with dual enable; 3-state
[1] For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
[2] This parameter is valid for any VCC between 0 V and 2.1 V, with a transition time of up to 10 ms. From VCC = 2.1 V to VCC = 5 V 10 %,
a transition time of up to 100 s is permitted.
[3] Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
[4] This is the increase in supply current for each input at 3.4 V.
10. Dynamic characteristics
VOL(pu) power-up LOW-level
output voltage VCC = 5.5 V; IO=1mA;
VI=GNDorV
CC
[1] - 0.13 0.55 - 0.55 V
IIinput leakage current VCC = 5.5 V; VI=GNDor 5.5V
control pins - 0.01 1.0 - 1.0 A
An, Bn - 5.0 100 - 100 A
IOFF power-off leakage
current VCC = 0 V; VI or VO 4.5 V - 5.0 100 - 100 A
IO(pu/pd) power-up/power-down
output current VCC = 2.1 V; VO=0.5V;
VI=GNDor V
CC;
OEAB,OEBAdon’t care
[2] -5.0 50 - 50 A
IOZ OFF-state output
current VCC = 5.5 V; VI = VIL or VIH
VO = 2.7 V - 5.0 50 - 50 A
VO = 0.5 V - 5.0 50 - 50 A
ILO output leakage current HIGH-state; VO=5.5V;
VCC =5.5V; V
I=GNDor V
CC
-5.050 - 50A
IOoutput current VCC = 5.5 V; VO = 2.5 V [3] 180 65 50 180 50 mA
ICC supply current VCC = 5.5 V; VI = GND or VCC
outputs HIGH-state - 110 250 - 250 A
outputs LOW-state - 20 30 - 30 mA
outputs disabled - 110 250 - 250 A
ICC additional supply
current per input pin; VCC = 5.5 V; one input
pin at 3.4 V, other inputs at VCC or
GND
[4] - 0.3 1.5 - 1.5 mA
CIinput capacitance VI = 0 V or VCC -4- - -pF
CI/O input/output
capacitance outputs disabled; VO=0V orV
CC -7- - -pF
Table 6. Static characteristics …continued
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C40 C to +85 CUnit
Min Typ Max Min Max
Table 7. Dynamic characteristics
GND = 0 V; for test circuit, see Figure 10.
Symbol Parameter Conditions 25 C; VCC = 5.0 V 40 C to +85 C;
VCC = 5.0 V 0.5 V Unit
Min Typ Max Min Max
tPLH LOW to HIGH
propagation delay An to Bn or Bn to An; see Figure 5 1.7 3.0 3.8 1.7 4.7 ns
LEBA to An or LEAB to Bn; see Figure 6 2.1 3.5 4.2 2.1 5.2 ns
circuit, see Figure 10 Figure 5 Figure 6 Figure 7 Figure 7 Figure 8 Figure 8 Figure 7 Figure 7 Figure 8 Figure 8 Figure 9 Figure 9 Figure 9 Figure 9 Figure 9 Figure 9 Figure 9 Figure 9 Figure 9
74ABT544 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 3 November 2011 7 of 16
NXP Semiconductors 74ABT544
Octal latched transceiver with dual enable; 3-state
11. Waveforms
tPHL HIGH to LOW
propagation delay An to Bn or Bn to An; see Figure 5 2.4 3.6 4.5 2.4 5.2 ns
LEBA to An or LEAB to Bn; see Figure 6 3.0 4.4 5.3 3.0 6.2 ns
tPZH OFF-state to HIGH
propagation delay OEBA to An, OEAB to Bn; see Figure 7 1.8 3.0 3.9 1.8 4.7 ns
EBA to An, EAB to Bn; see Figure 7 1.9 3.4 4.1 1.9 5.0 ns
tPZL OFF-state to LOW
propagation delay OEBA to An, OEAB to Bn; see Figure 8 2.9 4.2 5.2 2.9 6.1 ns
EBA to An, EAB to Bn; see Figure 8 3.1 4.6 5.5 3.1 6.5 ns
tPHZ HIGH to OFF-state
propagation delay OEBA to An, OEAB to Bn; see Figure 7 2.0 3.3 4.3 2.0 4.9 ns
EBA to An, EAB to Bn; see Figure 7 2.1 3.4 4.5 2.1 5.2 ns
tPLZ LOW to OFF-state
propagation delay OEBA to An, OEAB to Bn; see Figure 8 2.0 2.8 5.8 2.0 6.3 ns
EBA to An, EAB to Bn; see Figure 8 2.0 3.0 6.2 2.0 6.7 ns
tsu(H) set-up time HIGH An to LEAB, Bn to LEBA; see Figure 9 3.0 1.5 - 3.0 - ns
An to EAB, Bn to EBA; see Figure 9 3.0 1.5 - 3.0 - ns
tsu(L) set-up time LOW An to LEAB, Bn to LEBA; see Figure 9 3.0 0.6 - 3.0 - ns
An to EAB, Bn to EBA; see Figure 9 3.0 0.6 - 3.0 - ns
th(H) hold time HIGH LEAB to An, LEBA to Bn; see Figure 9 +0.5 0.3 - 0.5 - ns
EAB to An, EBA to Bn; see Figure 9 +0.5 0.2 - 0.5 - ns
th(L) hold time LOW LEAB to An, LEBA to Bn; see Figure 9 +0.5 1.3 - 0.5 - ns
EAB to An, EBA to Bn; see Figure 9 +0.5 1.3 - 0.5 - ns
tWL pulse width LOW latch enable; see Figure 9 3.5 1.8 - 3.5 - ns
Table 7. Dynamic characteristics …continued
GND = 0 V; for test circuit, see Figure 10.
Symbol Parameter Conditions 25 C; VCC = 5.0 V 40 C to +85 C;
VCC = 5.0 V 0.5 V Unit
Min Typ Max Min Max
VM=1.5V
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 5. Propagation delay input (An, Bn) to output (Bn, An)
001aac759
VOL
VOH
VMVM
tPHL tPLH
VMVM
An, Bn
VI
GND
Bn, An
74ABT544 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 3 November 2011 8 of 16
NXP Semiconductors 74ABT544
Octal latched transceiver with dual enable; 3-state
VM=1.5V
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6. Propagation delay latch enable (LEAB, LEBA) to output (An, Bn)
001aac761
VOL
VOH
VI
VMVM
tPLH tPHL
VMVM
GND
LEBA, LEAB
An, Bn
VM=1.5V
VOH is a typical voltage output level that occurs with the output load.
Fig 7. Propagation delay 3-state output enable to HIGH-level and output disable from HIGH-level
001aae907
V
M
V
M
V
OH
0.3 V
V
OH
GND
V
I
GND
V
M
t
PHZ
t
PZH
An, Bn
OEAB, OEBA,
EAB, EBA
VM=1.5V
VOL is a typical voltage output level that occurs with the output load.
Fig 8. Propagation delay 3-state output enable to LOW-level and output disable from LOW-level
001aae906
V
M
V
M
3.5 V
V
OL
+ 0.3 V
V
M
t
PLZ
t
PZL
An, Bn
OEAB, OEBA,
EAB, EBA
V
OL
V
I
GND
v vM v vM A—E V ifliifl
74ABT544 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 3 November 2011 9 of 16
NXP Semiconductors 74ABT544
Octal latched transceiver with dual enable; 3-state
VM=1.5V
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 9. Data set-up and hold times and latch enable pulse width
001aae905
VM
An, Bn
LEAB, LEBA,
EAB, EBA
VMVM
VMVM
VM
tsu(H) th(H) tsu(L) th(L)
tWL
VI
GND
VI
GND
a. Input pulse definition b. Test circuit
Test data is given in Table 8.
Definitions test circuit:
RL = Load resistor.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = Test voltage for switching times.
Fig 10. Load circuitry for switching times
001aai298
VMVM
tW
tW
10 %
90 % 90 %
0 V
VI
VI
negative
pulse
positive
pulse
0 V
VMVM
90 %
10 %
90 %
10 % 10 %
tf
tr
tr
tf
VEXT
VCC
VIVO
mna616
DUT
CL
RT
RL
RL
G
Table 8. Test data
Input Load VEXT
VIfItWtr, tfCLRLtPHL, tPLH tPZH, tPHZ tPZL, tPLZ
3.0 V 1 MHz 500 ns 2.5 ns 50 pF 500 open open 7.0 V
HHHHflW‘HHHHfiH-E
74ABT544 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 3 November 2011 10 of 16
NXP Semiconductors 74ABT544
Octal latched transceiver with dual enable; 3-state
12. Package outline
Fig 11. Package outline SOT137-1 (SO24)
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZ
ywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
2.65 0.3
0.1 2.45
2.25 0.49
0.36 0.32
0.23 15.6
15.2 7.6
7.4 1.27 10.65
10.00 1.1
1.0 0.9
0.4 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.1
0.4
SOT137-1
X
12
24
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
c
L
vMA
13
(A )
3
A
y
0.25
075E05 MS-013
pin 1 index
0.1 0.012
0.004 0.096
0.089 0.019
0.014 0.013
0.009 0.61
0.60 0.30
0.29 0.05
1.4
0.055
0.419
0.394 0.043
0.039 0.035
0.016
0.01
0.25
0.01 0.004
0.043
0.016
0.01
e
1
0 5 10 mm
scale
SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1
99-12-27
03-02-19
m \__TFQP Miflfllfljfl 212‘ mi “/ WHWWHHHH ‘ 4i; ‘ V , ,,,,,, T ,,,,, 7 M d 1 f ‘: £er E SQ 994.347»
74ABT544 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 3 November 2011 11 of 16
NXP Semiconductors 74ABT544
Octal latched transceiver with dual enable; 3-state
Fig 12. Package outline SOT340-1 (SSOP24)
UNIT A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.21
0.05 1.80
1.65 0.38
0.25 0.20
0.09 8.4
8.0 5.4
5.2 0.65 1.25
7.9
7.6 0.9
0.7 0.8
0.4 8
0
o
o
0.13 0.10.2
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
1.03
0.63
SOT340-1 MO-150 99-12-27
03-02-19
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
112
24 13
0.25
y
pin 1 index
0 2.5 5 mm
scale
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1
A
max.
2
WHHHHH‘HHHHHH % Ti} 6;} iiiii i wig; HHHHWHHHHHH “d ,D :I SQ
74ABT544 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 3 November 2011 12 of 16
NXP Semiconductors 74ABT544
Octal latched transceiver with dual enable; 3-state
Fig 13. Package outline SOT355-1 (TSSOP24)
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 7.9
7.7 4.5
4.3 0.65 6.6
6.2 0.4
0.3 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT355-1 MO-153 99-12-27
03-02-19
0.25 0.5
0.2
wM
bp
Z
e
112
24 13
pin 1 index
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
D
y
0 2.5 5 mm
scale
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1
A
max.
1.1
74ABT544 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 3 November 2011 13 of 16
NXP Semiconductors 74ABT544
Octal latched transceiver with dual enable; 3-state
13. Abbreviations
14. Revision history
Table 9. Abbreviations
Acronym Description
BiCMOS Bipolar Complementary Metal-Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
Table 10. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74ABT544 v.6 20111103 Product data sheet - 74ABT544 v.5
Modifications: Legal pages updated
74ABT544 v.5 20100520 Product data sheet - 74ABT544 v.4
74ABT544 v.4 20100115 Product data sheet - 74ABT544 v.3
74ABT544 v.3 20050420 Product specification - 74ABT544 v.2
74ABT544 v.2 20021118 Product specification - 74ABT544
74ABT544 19930701 Product specification - -
74ABT544 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 3 November 2011 14 of 16
NXP Semiconductors 74ABT544
Octal latched transceiver with dual enable; 3-state
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
: hitE:I/www.nxg.com salesaddresses®nx9£0m
74ABT544 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 3 November 2011 15 of 16
NXP Semiconductors 74ABT544
Octal latched transceiver with dual enable; 3-state
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74ABT544
Octal latched transceiver with dual enable; 3-state
© NXP B.V. 2011. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 3 November 2011
Document identifier: 74ABT544
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6 Functional description . . . . . . . . . . . . . . . . . . . 4
6.1 Function table. . . . . . . . . . . . . . . . . . . . . . . . . . 4
6.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
8 Recommended operating conditions. . . . . . . . 5
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 13
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 13
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
16 Contact information. . . . . . . . . . . . . . . . . . . . . 15
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

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