74ABT374A Datasheet by NXP USA Inc.

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1. General description
The 74ABT374A high-performance BiCMOS device combines low static and dynamic
power dissipation with high speed and high output drive.
The 74ABT374A is an 8-bit, edge triggered register coupled to eight 3-state output
buffers. The two sections of the device are controlled independently by the clock input
(CP) and output enable input (OE) control gates.
The register is fully edge-triggered. The state of each D input, one set-up time before the
LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output.
The 3-state output buffers are designed to drive heavily loaded 3-state buses, MOS
memories, or MOS microprocessors. The active LOW output enable (OE) controls all
eight 3-state buffers independent of the clock operation.
When OE is LOW, the stored data appears at the outputs. When OE is HIGH, the outputs
are in the high-impedance “OFF” state, which means they will neither drive nor load the
bus.
2. Features and benefits
8-bit positive edge triggered register
3-state output buffers
Power-on 3-state
Power-on reset
Output capability: +64 mA/32 mA
Latch-up protection exceeds 500 mA per JESD78B class II level A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Live insertion/extraction permitted
74ABT374A
Octal D-type flip-flop; positive-edge trigger; 3-state
Rev. 2 — 18 December 2012 Product data sheet
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74ABT374A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 18 December 2012 2 of 16
NXP Semiconductors 74ABT374A
Octal D-type flip-flop; positive-edge trigger; 3-state
3. Ordering information
4. Functional diagram
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74ABT374AN 40 Cto+85C DIP20 plastic dual in-line package; 20 leads (300 mil) SOT146-1
74ABT374AD 40 Cto+85C SO20 plastic small outline package; 20 leads;
body width 7.5 mm SOT163-1
74ABT374ADB 40 Cto+85C SSOP20 plastic shrink small outline package; 20 leads;
body width 5.3 mm SOT339-1
74ABT374APW 40 Cto+85C TSSOP20 plastic thin shrink small outline package; 20 leads;
body width 4.4 mm SOT360-1
Fig 1. Logic symbol Fig 2. IEC logic symbol
mna891
D0
D1
D2
D3
D4
D5
D6
D7 OE
CP
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
11
1
19
16
15
12
9
6
5
2
18
17
14
13
8
7
4
3
mna196
19
16
15
12
9
6
5
11 C1
1EN
1D 2
18
17
14
13
8
7
4
3
Fig 3. Logic diagram
001aah077
D0
CP
OE
Q0
D
CP
Q
FF1
D1
Q1
D
CP
Q
FF2
D2
Q2
D
CP
Q
FF3
D3
Q3
D
CP
Q
FF4
D4
Q4
D
CP
Q
FF5
D5
Q5
D
CP
Q
FF6
D6
Q6
D
CP
Q
FF7
D7
Q7
D
CP
Q
FF8
74AET374A 0 3333333333 O 8534705305 iEEEEEEEEE 74ABT374A c jjjjjjjjjj TEEEEEEEEE gas-005305 le
74ABT374A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 18 December 2012 3 of 16
NXP Semiconductors 74ABT374A
Octal D-type flip-flop; positive-edge trigger; 3-state
5. Pinning information
5.1 Pinning
5.2 Pin description
6. Functional description
[1] H = HIGH voltage level
h = HIGH voltage level one setup time prior to the LOW-to-HIGH CP transition
L = LOW voltage level
l = LOW voltage level one setup time prior to the LOW-to-HIGH CP transition
Z = high-impedance OFF-state
= LOW-to-HIGH clock transition
Fig 4. Pin configuration for DIP20 and SO20 Fig 5. Pin configuration for SSOP20 and TSSOP20
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Table 2. Pin description
Symbol Pin Description
OE 1 3-state output enable input (active LOW)
D0, D1, D2, D3, D4, D5, D6, D7 3, 4, 7, 8, 13, 14, 17, 18 data input
GND 10 ground (0 V)
CP 11 clock pulse input (active rising edge)
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 2, 5, 6, 9, 12, 15, 16, 19 3-state flip-flop output
VCC 20 supply voltage
Table 3. Function table[1]
Operating mode Input Internal
flip-flop Output
OE CP Dn Qn
Load and read register L lL L
LhH H
Load register and disable output H lL Z
HhH Z
74ABT374A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 18 December 2012 4 of 16
NXP Semiconductors 74ABT374A
Octal D-type flip-flop; positive-edge trigger; 3-state
7. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 C.
8. Recommended operating conditions
9. Static characteristics
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +7.0 V
VIinput voltage [1] 1.2 +7.0 V
VOoutput voltage output in OFF-state or HIGH-state [1] 0.5 +5.5 V
IIK input clamping current VI < 0 V 18 - mA
IOK output clamping current VO < 0 V 50 - mA
IOoutput current output in LOW-state - 128 mA
Tjjunction temperature [2] - 150 C
Tstg storage temperature 65 +150 C
Table 5. Operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
VCC supply voltage 4.5 - 5.5 V
VIinput voltage 0 - VCC V
VIH HIGH-level input voltage 2.0 - - V
VIL LOW-level input voltage - - 0.8 V
IOH HIGH-level output current 32--mA
IOL LOW-level output current - - 64 mA
t/V input transition rise and fall rate 0 - 10 ns/V
Tamb ambient temperature in free air 40 - +85 C
Table 6. Static characteristics
Symbol Parameter Conditions 25 C40 C to +85 CUnit
Min Typ Max Min Max
VIK input clamping voltage VCC = 4.5 V; IIK =18 mA 1.2 0.9 - 1.2 - V
VOH HIGH-level output
voltage VI = VIL or VIH
VCC = 4.5 V; IOH =3 mA 2.5 2.9 - 2.5 - V
VCC = 5.0 V; IOH =3 mA 3.0 3.4 - 3.0 - V
VCC = 4.5 V; IOH =32 mA 2.0 2.4 - 2.0 - V
VOL LOW-level output
voltage VCC = 4.5 V; IOL =64mA;
VI=V
IL or VIH
- 0.42 0.55 - 0.55 V
circuit, see Figure 9 Figure 6 Figure 6 Figure 6 Figure 8
74ABT374A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 18 December 2012 5 of 16
NXP Semiconductors 74ABT374A
Octal D-type flip-flop; positive-edge trigger; 3-state
[1] For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
[2] This parameter is valid for any VCC between 0 V and 2.1 V, with a transition time of up to 10 ms. From VCC = 2.1 V to VCC = 5 V 10 %
a transition time of up to 100 s is permitted.
[3] Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
[4] This is the increase in supply current for each input at 3.4 V.
10. Dynamic characteristics
VOL(pu) power-up LOW-level
output voltage VCC = 5.5 V; IO=1mA;
VI=GNDor V
CC
[1] - 0.13 0.55 - 0.55 V
IIinput leakage current VCC =5.5V; V
I=V
CC or GND - 0.01 1.0 - 1.0 A
IOFF power-off leakage
current VCC = 0 V; VI or VO 4.5 V - 5.0 100 - 100 A
IO(pu/pd) power-up/power-down
output current VCC =2.0V; V
O=0.5V;
VI=GNDor V
CC; OE HIGH
[2] -5.0 50 - 50 A
IOZ OFF-state output
current VCC = 5.5 V; VI = VIL or VIH
VO = 2.7 V - 5.0 50 - 50 A
VO = 0.5 V 50 5.0 - 50 - A
ILO output leakage current HIGH-state; VO=5.5V;
VCC =5.5V; V
I=GNDor V
CC
-5.050 - 50A
IOoutput current VCC = 5.5 V; VO = 2.5 V [3] 180 100 50 180 50 mA
ICC supply current VCC = 5.5 V; VI = GND or VCC
outputs HIGH-state - 110 250 - 250 A
outputs LOW-state - 24 30 - 30 mA
outputs disabled - 110 250 - 250 A
ICC additional supply
current per input pin; VCC = 5.5 V;
one input at 3.4 V;
other inputs at VCC or GND
[4] -0.51.5 - 1.5mA
CIinput capacitance VI=0Vor V
CC -4- - -pF
COoutput capacitance outputs disabled; VO=0Vor V
CC -7- - -pF
Table 6. Static characteristics …continued
Symbol Parameter Conditions 25 C40 C to +85 CUnit
Min Typ Max Min Max
Table 7. Dynamic characteristics
GND = 0 V; for test circuit, see Figure 9.
Symbol Parameter Conditions 25 C; VCC = 5.0 V 40 C to +85 C;
VCC = 5.0 V 0.5 V Unit
Min Typ Max Min Max
fmax maximum
frequency see Figure 6 200 300 - 200 - MHz
tPLH LOW to HIGH
propagation delay CP to Qn; see Figure 6 1.7 3.4 4.5 1.7 5.1 ns
tPHL HIGH to LOW
propagation delay CP to Qn; see Figure 6 2.0 3.8 4.9 2.0 5.2 ns
tPZH OFF-state to HIGH
propagation delay OE to Qn; see Figure 8 1.2 3.5 4.5 1.2 5.4 ns
circuir, see Figure 9 Figure 8 Figure 8 Figure 8 Figure 7 Figure 7 Figure 7 Figure 7 Figure 6 Figure 6
74ABT374A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 18 December 2012 6 of 16
NXP Semiconductors 74ABT374A
Octal D-type flip-flop; positive-edge trigger; 3-state
11. Waveforms
tPZL OFF-state to LOW
propagation delay OE to Qn; see Figure 8 2.2 4.3 5.4 2.2 6.2 ns
tPHZ HIGH to OFF-state
propagation delay OE to Qn; see Figure 8 1.8 3.6 4.7 1.8 5.2 ns
tPLZ LOW to OFF-state
propagation delay OE to Qn; see Figure 8 1.5 3.0 4.1 1.5 4.3 ns
tsu(H) set-up time HIGH Dn to CP; see Figure 7 1.5 0.6 - 1.5 - ns
tsu(L) set-up time LOW Dn to CP; see Figure 7 1.2 0.3 - 1.2 - ns
th(H) hold time HIGH CP to Dn; see Figure 7 1.0 0.3 - 1.0 - ns
th(L) hold time LOW CP to Dn; see Figure 7 1.0 0.5 - 1.0 - ns
tWH pulse width HIGH CP; see Figure 6 2.0 0.8 - 2.0 - ns
tWL pulse width LOW CP; see Figure 6 2.8 1.0 - 2.8 - ns
Table 7. Dynamic characteristics …continued
GND = 0 V; for test circuit, see Figure 9.
Symbol Parameter Conditions 25 C; VCC = 5.0 V 40 C to +85 C;
VCC = 5.0 V 0.5 V Unit
Min Typ Max Min Max
VM = 1.5 V
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 6. Propagation delay clock input (CP) to output (Qn), clock pulse (CP) width and maximum clock (CP)
frequency
001aac445
CP input
Qn output
t
PHL
t
PLH
t
WH
t
WL
1 / f
max
V
M
V
OH
V
I
GND
V
OL
V
M
74ABT374A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 18 December 2012 7 of 16
NXP Semiconductors 74ABT374A
Octal D-type flip-flop; positive-edge trigger; 3-state
VM = 1.5 V
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 7. Set-up and hold times data output (Dn) to clock (CP)
001aac738
V
M
CP input
V
M
V
M
V
M
V
M
V
M
t
su(H)
t
h(H)
t
su(L)
t
h(L)
Dn input
V
l
GND
V
l
GND
VM = 1.5 V
VOL and VOH are typical output voltage levels that occur with the output load
Fig 8. 3-state output (Qn) enable and disable times
MHH
74ABT374A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 18 December 2012 8 of 16
NXP Semiconductors 74ABT374A
Octal D-type flip-flop; positive-edge trigger; 3-state
a. Input pulse definition b. Test circuit
Test data is given in Table 8.
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 9. Test circuit for measuring switching times
001aai298
VMVM
tW
tW
10 %
90 % 90 %
0 V
VI
VI
negative
pulse
positive
pulse
0 V
VMVM
90 %
10 %
90 %
10 % 10 %
tf
tr
tr
tf
VEXT
VCC
VIVO
mna616
DUT
CL
RT
RL
RL
G
Table 8. Test data
Input Load VEXT
VIfitWtr, tfCLRLtPHL, tPLH tPZH, tPHZ tPZL, tPLZ
3.0 V 1 MHz 500 ns 2.5 ns 50 pF 500 open open 7.0 V
%mmm mmmmmh WWWWU‘UVWUV E©W
74ABT374A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 18 December 2012 9 of 16
NXP Semiconductors 74ABT374A
Octal D-type flip-flop; positive-edge trigger; 3-state
12. Package outline
Fig 10. Package outline SOT146-1 (DIP20)
UNIT A
max. 1 2 b1cD E e M
H
L
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
SOT146-1 99-12-27
03-02-13
A
min. A
max. bZ
max.
w
ME
e1
1.73
1.30 0.53
0.38 0.36
0.23 26.92
26.54 6.40
6.22 3.60
3.05 0.2542.54 7.62 8.25
7.80 10.0
8.3 24.2 0.51 3.2
0.068
0.051 0.021
0.015 0.014
0.009 1.060
1.045 0.25
0.24 0.14
0.12 0.010.1 0.3 0.32
0.31 0.39
0.33 0.0780.17 0.02 0.13
SC-603MS-001
MH
c
(e )
1
ME
A
L
seating plane
A1
wM
b1
e
D
A2
Z
20
1
11
10
b
E
pin 1 index
0 5 10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
(1)
(1) (1)
DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1
74ABT374A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 18 December 2012 10 of 16
NXP Semiconductors 74ABT374A
Octal D-type flip-flop; positive-edge trigger; 3-state
Fig 11. Package outline SOT163-1 (SO20)
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZ
ywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
2.65 0.3
0.1 2.45
2.25 0.49
0.36 0.32
0.23 13.0
12.6 7.6
7.4 1.27 10.65
10.00 1.1
1.0 0.9
0.4 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.1
0.4
SOT163-1
10
20
wM
bp
detail X
Z
e
11
1
D
y
0.25
075E04 MS-013
pin 1 index
0.1 0.012
0.004 0.096
0.089 0.019
0.014 0.013
0.009 0.51
0.49 0.30
0.29 0.05
1.4
0.055
0.419
0.394 0.043
0.039 0.035
0.016
0.01
0.25
0.01 0.004
0.043
0.016
0.01
0 5 10 mm
scale
X
θ
A
A1
A2
HE
Lp
Q
E
c
L
vMA
(A )
3
A
SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
99-12-27
03-02-19
F a» _..r 2: ll ‘ fHHHWHHHHH d ‘ * \* HHHyDHLiH H HJH S
74ABT374A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 18 December 2012 11 of 16
NXP Semiconductors 74ABT374A
Octal D-type flip-flop; positive-edge trigger; 3-state
Fig 12. Package outline SOT339-1 (SSOP20)
UNIT A1A2A3bpcD
(1) E(1) eH
ELL
pQ(1)
Zywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.21
0.05 1.80
1.65 0.38
0.25 0.20
0.09 7.4
7.0 5.4
5.2 0.65 7.9
7.6 0.9
0.7 0.9
0.5 8
0
o
o
0.131.25 0.2 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
1.03
0.63
SOT339-1 MO-150 99-12-27
03-02-19
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
110
20 11
y
0.25
pin 1 index
0 2.5 5 mm
scale
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1
A
max.
2
H H HHDHLH H HH- E© W
74ABT374A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 18 December 2012 12 of 16
NXP Semiconductors 74ABT374A
Octal D-type flip-flop; positive-edge trigger; 3-state
Fig 13. Package outline SOT360-1 (TSSOP20)
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 6.6
6.4 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.5
0.2 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT360-1 MO-153 99-12-27
03-02-19
wM
bp
D
Z
e
0.25
110
20 11
pin 1 index
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
y
0 2.5 5 mm
scale
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1
A
max.
1.1
74ABT374A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 18 December 2012 13 of 16
NXP Semiconductors 74ABT374A
Octal D-type flip-flop; positive-edge trigger; 3-state
13. Abbreviations
14. Revision history
Table 9. Abbreviations
Acronym Description
BiCMOS Bipolar Complementary Metal-Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
Table 10. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74ABT374A v.2 20121218 Product data sheet - 74ABT374A v.1
Modifications: The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
Legal texts have been adapted to the new company name where appropriate.
74ABT374A v.1 19950906 Product specification - -
74ABT374A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 18 December 2012 14 of 16
NXP Semiconductors 74ABT374A
Octal D-type flip-flop; positive-edge trigger; 3-state
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
: hitE:I/www.nxg.com salesaddresses®nx9£0m
74ABT374A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 18 December 2012 15 of 16
NXP Semiconductors 74ABT374A
Octal D-type flip-flop; positive-edge trigger; 3-state
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74ABT374A
Octal D-type flip-flop; positive-edge trigger; 3-state
© NXP B.V. 2012. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 18 December 2012
Document identifier: 74ABT374A
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6 Functional description . . . . . . . . . . . . . . . . . . . 3
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
8 Recommended operating conditions. . . . . . . . 4
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 13
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 13
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
15.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
16 Contact information. . . . . . . . . . . . . . . . . . . . . 15
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

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