74ABT16373B Datasheet by NXP USA Inc.

View All Related Products | Download PDF Datasheet
@ATA $[Ffl ET 513 \g; PHILIPS


74ABT16373B
16-bit transparent latch (3-State)
Product data
Replaces 74ABT16373B/74ABTH16373B of 1998 Feb 27
2004 Feb 27
INTEGRATED CIRCUITS
jjjjjjjjjjjjjjjjjjjjjjjj EEEEEEEEEEEEEEEEEEEEEEEE , 7 m m u c M P u s m e n m u Q
Philips Semiconductors Product data
74ABT16373B16-bit transparent latch (3-State)
2
2004 Feb 27
FEATURES
16-bit transparent latch
Multiple VCC and GND pins minimize switching noise
Power-up 3-State
Live insertion/extraction permitted
Power-up reset
3-State output buffers
Output capability: +64 mA/–32 mA
ICCL –19 mA maximum
Latch-up protection exceeds 500 mA per JEDEC Std 17
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
DESCRIPTION
The 74ABT16373B high-performance BiCMOS device combines
low static and dynamic power dissipation with high speed and high
output drive.
The 74ABT16373B device is a dual octal transparent latch coupled
to two sets of eight 3-State output buffers. The two sections of the
device are controlled independently by Enable (nE) and Output
Enable (nOE) control gates.
The data on each set of D inputs are transferred to the latch outputs
when the Latch Enable (nE) input is HIGH. The latch remains
transparent to the data inputs while nE is HIGH, and stores the data
that is present one set-up time before the HIGH-to-LOW enable
transition.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. Each
active-LOW Output Enable (nOE) controls eight 3-State buffers
independent of the latch operation.
When nOE is LOW, the latched or transparent data appears at the
outputs. When nOE is HIGH, the outputs are in the high-impedance
“OFF” state, which means they will neither drive nor load the bus.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1OE
1Q0
1Q1
GND
1Q2
1Q3
1Q4
1Q5
GND
1Q6
1Q7
2Q0
2Q1
GND
2Q3
VCC
2Q4
VCC
2Q2
2Q5
GND
2Q7
2OE
2Q6
1E
1D0
1D1
GND
1D2
1D3
1D4
1D5
GND
1D6
1D7
2D0
2D1
GND
2D3
VCC
2D4
VCC
2D2
2D5
GND
2D7
2E
2D6
SA00379
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS
Tamb = 25 °C; GND = 0 V TYPICAL UNIT
tPLH
tPHL
Propagation delay
Dn to Qn CL = 50 pF; VCC = 5 V 2.5
2.0 ns
CIN Input capacitance VI = 0 V or VCC 4 pF
COUT Output capacitance VO = 0 V or VCC; 3-State 7 pF
ICCZ
Quiescent su
pp
ly current
Outputs disabled; VCC = 5.5 V 500 µA
ICCL
Q
u
iescent
s
u
ppl
y
c
u
rrent
Outputs low; VCC = 5.5 V 8 mA
ORDERING INFORMATION
T
amb
= –40
°
C to +85
°
C
Type number Package
Name Description Version
74ABT16373BDL SSOP48 plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1
74ABT16373BDGG TSSOP48 plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1
fl ’7 \ fl ’7 \ fl ’7 \ \ \
Philips Semiconductors Product data
74ABT16373B16-bit transparent latch (3-State)
2004 Feb 27 3
PIN DESCRIPTION
PIN NUMBER SYMBOL FUNCTION
47, 46, 44, 43, 41, 40,
38, 37, 36, 35, 33, 32,
30, 29, 27, 26
1D0 – 1D7
2D0 – 2D7 Data inputs
2, 3, 5, 6, 8, 9, 11, 12,
13, 14, 16, 17, 19, 20,
22, 23
1Q0 – 1Q7
2Q0 – 2Q7 Data outputs
1, 24 1OE, 2OE Output enable inputs
(active-LOW)
48, 25 1E, 2E Enable inputs
(active-HIGH)
4, 10, 15, 21, 28, 34,
39, 45 GND Ground (0 V)
7, 18, 31, 42 VCC Positive supply voltage
LOGIC SYMBOL
32
1Q0 1Q1 1Q2
65
1Q3
47 46 44 43
1D0 1D1 1D2 1D3
48
1
98
1Q4 1Q5 1Q6
1211
1Q7
41 40 38 37
1D4 1D5 1D6 1D7
1E
1OE
1413 1716
36 35 33 32
25
24
2019 2322
30 29 27 26
2Q0 2Q1 2Q2 2Q3
2D0 2D21 2D2 2D3
2Q4 2Q5 2Q6 2Q7
2D4 2D5 2D6 2D7
2E
2OE
SA00044
LOGIC SYMBOL (IEEE/IEC)
48
1EN
1
46
44
43
41
40
38
37
36
C3
2EN
C4
2
1
24
25
47
35
33
32
30
29
27
26
3
2
5
6
8
9
11
12
13
14
16
17
19
20
22
23
SA00380
1OE
1E
2OE
2E
1D0
1D1
1D2
1D3
1D4
1D5
1D6
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q7
1D7
2Q5
2Q6
3D
4D
LOGIC DIAGRAM
E Q
D
nD0
nQ0
EQ
D
nD1
EQ
D
nD2
EQ
D
nD3
EQ
D
nD4
EQ
D
nD5
EQ
D
nD6
EQ
D
nD7
nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 nQ7
nE
nOE
SA00046
OPERATING MODE SYMBOL DC output current PARAMETER
Philips Semiconductors Product data
74ABT16373B16-bit transparent latch (3-State)
2004 Feb 27 4
FUNCTION TABLE
INPUTS INTERNAL OUTPUTS
OPERATING MODE
nOE nE nDx REGISTER nQ0 – nQ7
OPERATING
MODE
L
LH
HL
HL
HL
HEnable and read register
L
L
i
hL
HL
HLatch and read register
L L X NC NC Hold
H
HL
HX
Dn NC
Dn Z
ZDisable outputs
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW E transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the HIGH-to-LOW E transition
NC= No change
X = Don’t care
Z = High-impedance “off” state
= HIGH-to-LOW E transition
ABSOLUTE MAXIMUM RATINGS1, 2
SYMBOL PARAMETER CONDITIONS RATING UNIT
VCC DC supply voltage –0.5 to +7.0 V
IIK DC input diode current VI < 0 V –18 mA
VIDC input voltage3–1.2 to +7.0 V
IOK DC output diode current VO < 0 V –50 mA
VOUT DC output voltage3output in Off or HIGH state –0.5 to +5.5 V
IO
DC out
p
ut current
output in LOW state 128
mA
I
OUT
DC
o
u
tp
u
t
c
u
rrent
output in HIGH state –64
mA
Tstg Storage temperature range –65 to 150 °C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
SYMBOL
PARAMETER
MIN MAX
UNIT
VCC DC supply voltage 4.5 5.5 V
VIInput voltage 0 VCC V
VIH HIGH-level input voltage 2.0 – V
VIL LOW-level Input voltage 0.8 V
IOH HIGH-level output current –32 mA
IOL LOW-level output current 64 mA
t/vInput transition rise or fall rate 0 10 ns/V
Tamb Operating free-air temperature range –40 +85 °C
Philips Semiconductors Product data
74ABT16373B16-bit transparent latch (3-State)
2004 Feb 27 5
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL PARAMETER TEST CONDITIONS Tamb = +25 °CTamb = –40 °C
to +85 °CUNIT
MIN TYP MAX MIN MAX
VIK Input clamp voltage VCC = 4.5 V; IIK = –18 mA –0.9 –1.2 –1.2 V
VCC = 4.5 V; IOH = –3 mA; VI = VIL or VIH 2.5 2.9 – 2.5 V
VOH High-level output voltage VCC = 5.0 V; IOH = –3 mA; VI = VIL or VIH 3.0 3.4 – 3.0 V
VCC = 4.5 V; IOH = –32 mA; VI = VIL or VIH 2.0 2.4 – 2.0 V
VOL Low-level output voltage VCC = 4.5 V; IOL = 64 mA; VI = VIL or VIH 0.42 0.55 0.55 V
VRST Power-up output voltage3VCC = 5.5 V; IO = 1 mA; VI = GND or VCC 0.13 0.55 0.55 V
IIInput leakage current VCC = 5.5 V; VI = VCC or GND ±0.01 ±1 – ±1µA
IOFF Power-off leakage current VCC = 0.0 V; VO or VI 4.5 V ±5.0 ±100 – ±100 µA
IPU/IPD Power-up/down 3-State
output current4VCC = 2.1 V; VO = 0.5 V; VI = GND or VCC;
VOE = GND ±5.0 ±50 – ±50 µA
IOZH 3-State output HIGH
current VCC = 5.5 V; VO = 5.5 V; VI = VIL or VIH 0.5 10 10 µA
IOZL 3-State output LOW current VCC = 5.5 V; VO = 0.0 V; VI = VIL or VIH –0.5 –10 –10 µA
IOOutput current1VCC = 5.5 V; VO = 2.5 V –50 –70 –180 –50 –180 mA
ICEX Output HIGH leakage
current VCC = 5.5 V; VO = 5.5 V; VI = GND or VCC 0.1 50 50 µA
ICCH VCC = 5.5 V; Outputs HIGH;
VI = GND or VCC – 0.5 2 2 mA
ICCL Quiescent supply current VCC = 5.5 V; Outputs Low;
VI = GND or VCC 8 19 19 mA
ICCZ VCC = 5.5 V; Outputs 3-State;
VI = GND or VCC – 0.5 2 2 mA
ICC Additional supply current
per input pin2VCC = 5.5 V; one input at 3.4 V, other inputs
at VCC or GND 5 100 100 µA
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4 V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This parameter is valid for any VCC between 0 V and 2.1 V, with a transition time of up to 10 msec. From VCC = 2.1 to VCC = 5 V ± 10% a
transition time of up to 100 µsec is permitted.
5. Unused pins at VCC or GND.
5?
Philips Semiconductors Product data
74ABT16373B16-bit transparent latch (3-State)
2004 Feb 27 6
AC CHARACTERISTICS
GND = 0 V, tR = tF = 2.5 ns, CL = 50 pF, RL = 500
LIMITS
SYMBOL PARAMETER WAVEFORM Tamb = +25 °C
VCC = +5.0 V Tamb = –40 °C to +85 °C
VCC = +5.0V ± 0.5 V UNIT
MIN TYP MAX MIN MAX
tPLH
tPHL
Propagation delay
nDx to nQx 21.5
1.1 2.5
2.0 3.8
3.1 1.5
1.1 4.4
3.8 ns
tPLH
tPHL
Propagation delay
nE to nQx 11.6
1.3 2.5
2.1 3.8
3.1 1.6
1.3 4.4
3.6 ns
tPZH
tPZL
Output enable time
to HIGH and LOW level 4
51.2
1.3 2.3
2.3 3.5
3.5 1.2
1.3 4.6
4.5 ns
tPHZ
tPLZ
Output disable time
from HIGH and LOW level 4
51.9
1.7 3.1
2.6 4.5
3.8 1.9
1.7 5.3
4.2 ns
AC SET-UP REQUIREMENTS
GND = 0 V, tR = tF = 2.5 ns, CL = 50 pF, RL = 500
LIMITS
SYMBOL PARAMETER WAVEFORM Tamb = +25 °C
VCC = +5.0 V Tamb = –40 °C to +85 °C
VCC = +5.0 V ± 0.5 V UNIT
MIN TYP MIN
ts(H)
ts(L) Set-up time, HIGH or LOW
nDx to nE 31.0
1.0 0.0
0.3 1.0
1.0 ns
th(H)
th(L) Hold time, HIGH or LOW
nDx to nE 30.5
0.5 –0.2
0.0 0.5
0.5 ns
tw(H) Enable pulse width
HIGH 1 2.5 1.0 2.5 ns
AC WAVEFORMS
For all waveforms, VM = 1.5 V.
tw(H)
tPHL tPLH
nE
nQx
SA00047
VMVMVM
VMVM
Waveform 1. Propagation Delay, Enable to Output, and
Enable Pulse Width
nDx VM
tPLH tPHL
nQx VM
VM
VM
SA00048
Waveform 2. Propagation Delay for Data to Outputs
i? i? : fifi i
Philips Semiconductors Product data
74ABT16373B16-bit transparent latch (3-State)
2004 Feb 27 7
NOTE: The shaded areas indicate when the input is per-
mitted to change for predictable output performance.
VM
nDx
VMVM
VMVM
nE
ts(H) th(H) ts(L) th(L)
SA00049
VM
Waveform 3. Data Set-up and Hold Times
nOE VM
tPZH tPHZ
0V
nQx VM
VM
SA00050
VOH
VOH – 0.3V
Waveform 4. 3-State Output Enable Time to HIGH Level and
Output Disable Time from HIGH Level
nOE
tPZL tPLZ
nQx
VM
VM
VM
SA00051
VOL + 0.3V
VOL
Waveform 5. 3-State Output Enable Time to LOW Level and
Output Disable Time from LOW Level
TEST CIRCUIT AND WAVEFORM
PULSE
GENERATOR
RT
VIN
D.U.T.
VOUT
RL
VCC
RL
7.0 V
Test Circuit for 3-State Outputs
VMVM
tWAMP (V)
NEGATIVE
PULSE 10% 10%
90% 90%
0 V
VMVM
tW
AMP (V)
POSITIVE
PULSE
90% 90%
10% 10% 0 V
tTHL (tF)
tTLH (tR)t
THL (tF)
tTLH (tR)
VM = 1.5 V
Input Pulse Definition
DEFINITIONS
RL = Load resistor; see AC CHARACTERISTICS for value.
CL = Load capacitance includes jig and probe capacitance;
see AC CHARACTERISTICS for value.
RT = Termination resistance should be equal to ZOUT of
pulse generators.
INPUT PULSE REQUIREMENTS
FAMILY Amplitude Rep. Rate tWtRtF
74ABT 3.0 V 1 MHz 500 ns 2.5 ns 2.5 ns
SWITCH POSITION
TEST SWITCH
tPLZ closed
tPZL closed
All other open
SA00654
CL
5 10mm W DIMENSIONS (mm mm: orlqlnnl dlmenslona) uurr max. A, A: A; b, c DW E") e HE L Ll, v w y z") e m :3 2: s: 3?: :22: ii :3: .. a: 3:: s: Mme 1. Plasuc or mam prokruswons No.25 mm maxwmum per we are not included. ‘v’é'é's‘lgfi ,Ec JEDECREFEREWESJEM é‘é’ifififi‘u ISSUEWE sow/04 Morns E Q m
Philips Semiconductors Product data
74ABT16373B16-bit transparent latch (3-State)
2004 Feb 27 8
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1
pvmindex +\a O | w. f L fitlHHflHHHgWHE’IflHHHHEflL E‘ W o 25 5mm LI—I—A—A—l—A—A—A—A—l same A mm mm A1 A: A; an e D") Em e N; L Lv 43 v w y z 9 0,15 1.05 023 0.2 12.5 6.2 3.3 0.0 0.50 0.0 5“ mm “2 0,05 mas 0'25 017 01 12.4 6.0 05 7.9 ‘ 0.4 035 “'25 “'05 0" 0A 0“ "Me: 1 Magic of man: prouusions arms mm maximum per side are not inc‘uded. 2 Wash: menead pmmsuons at 0.25 mm maxim um per side an n0! mcludea OUTLINE REFERENCES EUROPEAN lssllEDA‘l’E VERSION .EC JEDEC JEITA maJEcnou $073024 M0453 a @ 09937035
Philips Semiconductors Product data
74ABT16373B16-bit transparent latch (3-State)
2004 Feb 27 9
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1
Philips Semiconductors Product data
74ABT16373B16-bit transparent latch (3-State)
2004 Feb 27 10
REVISION HISTORY
Rev Date Description
_3 20040227 Product data (9397 750 12821); 853-1751 ECN 01–A15429 of 27 January 2004.
Replaces data sheet 74ABT_H16373B_2 of 1998 Feb 27 (9397 750 03491).
Modifications:
Delete all references to 74ABTH16373B (product discontinued).
_2 19980227 Product specification (9397 750 03491); ECN 853-1751 19027 of 27 February 1998.
Supersedes data of 1995 Aug 03.
_1 19950803
sales.addresses@www.semiconduclorsphilipsxmm, Mémmbm PHILIPS
Philips Semiconductors Product data
74ABT16373B16-bit transparent latch (3-State)
2004 Feb 27 11
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given
in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no
representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be
expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree
to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described
or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated
via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys
no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent,
copyright, or mask work right infringement, unless otherwise specified.
Contact information
For additional information please visit
http://www.semiconductors.philips.com. Fax: +31 40 27 24825
For sales offices addresses send e-mail to:
sales.addresses@www.semiconductors.philips.com.
Koninklijke Philips Electronics N.V. 2004
All rights reserved. Printed in U.S.A.
Date of release: 01-04
Document order number: 9397 750 12985


Data sheet status[1]
Objective data
Preliminary data
Product data
Product
status[2] [3]
Development
Qualification
Production
Definitions
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
Data sheet status
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL
http://www.semiconductors.philips.com.
[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Level
I
II
III

Products related to this Datasheet

IC 16BIT D TYPE LATCH 48TSSOP
IC 16BIT D TYPE LATCH 48TSSOP
IC 16BIT D TYPE LATCH 48SSOP
IC 16BIT D TYPE LATCH 48SSOP
IC 16BIT D TYPE LATCH 48TSSOP
IC 16BIT D TYPE LATCH 48TSSOP
IC LATCH 16BIT D TYPE 48SSOP
IC LATCH 16BIT D TYPE 48SSOP