PIC16(L)F151x,152x Programming Spec Datasheet by Microchip Technology

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‘3‘ MICRDCHIP MCLR e MCLR MCLR vMCLR
2010-2011 Microchip Technology Inc. Advance Information DS41442B-page 1
This document includes the
programming specifications for the
following devices:
1.0 OVERVIEW
The PIC16(L)F151X/152X devices can be
programmed using either the high-voltage In-Circuit
Serial Programming™ (ICSP™) method or the low-
voltage ICSP™ method.
1.1 Hardware Requirements
1.1.1 HIGH-VOLTAGE ICSP
PROGRAMMING
In High-Voltage ICSP™ mode, these devices require
two programmable power supplies; one for VDD and
one for the MCLR/VPP pin.
1.1.2 LOW-VOLTAGE ICSP
PROGRAMMING
In Low-Voltage ICSP™ mode, these devices can be
programmed using a single VDD source in the
operating range. The MCLR/VPP pin does not have to
be brought to a different voltage, but can instead be left
at the normal operating voltage.
1.1.2.1 Single-Supply ICSP Programming
The LVP bit in Configuration Word 2 enables single-
supply (low-voltage) ICSP programming. The LVP bit
defaults to a ‘1’ (enabled) from the factory. The LVP bit
may only be programmed to ‘0’ by entering the High-
Voltage ICSP mode, where the MCLR/VPP pin is raised
to VIHH. Once the LVP bit is programmed to a ‘0’, only
the High-Voltage ICSP mode is available and only the
High-Voltage ICSP mode can be used to program the
device.
• PIC16F1512 • PIC16LF1512
• PIC16F1513 • PIC16LF1513
• PIC16F1516 • PIC16LF1516
• PIC16F1517 • PIC16LF1517
• PIC16F1518 • PIC16LF1518
• PIC16F1519 • PIC16LF1519
• PIC16F1526 • PIC16LF1526
• PIC16F1527 • PIC16LF1527
Note 1: The High-Voltage ICSP mode is always
available, regardless of the state of the
LVP bit, by applying VIHH to the MCLR/
VPP pin.
2: While in Low-Voltage ICSP mode, MCLR
is always enabled, regardless of the
MCLRE bit, and the port pin can no
longer be used as a general purpose
input.
PIC16(L)F151X/152X Memory Programming Specification
PIC16(L)F151X/152X
PIC16(L)F151X/152X
DS41442B-page 2 Advance Information 2010-2011 Microchip Technology Inc.
1.2 Pin Utilization
Five pins are needed for ICSP™ programming. The
pins are listed in Ta b l e 1 - 1 and Table 1-2 .
TABLE 1-1: PIN DESCRIPTIONS DURING PROGRAMMING – PIC16(L)F1526 AND PIC16(L)F1527
Pin Name
During Programming
Function Pin Type Pin Description
RB6 ICSPCLK I Clock Input – Schmitt Trigger Input
RB7 ICSPDAT I/O Data Input/Output – Schmitt Trigger Input
RG5/MCLR/VPP Program/Verify mode P(1) Program Mode Select/Programming Power Supply
VDD VDD P Power Supply
VSS VSS P Ground
Legend: I = Input, O = Output, P = Power
Note 1: The programming high voltage is internally generated. To activate the Program/Verify mode, high voltage needs to be
applied to MCLR input. Since the MCLR is used for a level source, MCLR does not draw any significant current.
TABLE 1-2: PIN DESCRIPTIONS DURING PROGRAMMING – PIC16(L)F1512, PIC16(L)F1513,
PIC16(L)F1516, PIC16(L)F1517, PIC16(L)F1518 and PIC16(L)F1519
Pin Name
During Programming
Function Pin Type Pin Description
RB6 ICSPCLK I Clock Input – Schmitt Trigger Input
RB7 ICSPDAT I/O Data Input/Output – Schmitt Trigger Input
RE3/MCLR/VPP Program/Verify mode P(1) Program Mode Select/Programming Power Supply
VDD VDD P Power Supply
VSS VSS P Ground
Legend: I = Input, O = Output, P = Power
Note 1: The programming high voltage is internally generated. To activate the Program/Verify mode, high voltage needs to be
applied to MCLR input. Since the MCLR is used for a level source, MCLR does not draw any significant current.
2010-2011 Microchip Technology Inc. Advance Information DS41442B-page 3
PIC16(L)F151X/152X
2.0 DEVICE PINOUTS
The pin diagrams for the PIC16(L)F151X/152X family
are shown in Figure 2-1 through Figure 2-7. The pins
that are required for programming are listed in Table 1-1
and shown in bold lettering in the pin diagrams.
FIGURE 2-1: 28-PIN SPDIP, SOIC, SSOP DIAGRAM FOR PIC16(L)F1512, PIC16(L)F1513,
PIC16(L)F1516 AND PIC16(L)F1518
SPDIP, SOIC, SSOP
PIC16(L)F1512
PIC16(L)F1513
PIC16(L)F1516
PIC16(L)F1518
1
2
3
4
5
6
7
8
9
10
VPP/MCLR/RE3
RA0
RA1
RA2
RA3
RA4
RA5
RB6/ICSPCLK
RB5
RB4
RB3
RB2
RB1
RB0
VDD
VSS
11
12
13
14 15
16
17
18
19
20
28
27
26
25
24
23
22
21
VSS
RA7
RA6
RC0
RC1
RC2
RC3
RC5
RC4
RC7
RC6
RB7/ICSPDAT
tHHH
PIC16(L)F151X/152X
DS41442B-page 4 Advance Information 2010-2011 Microchip Technology Inc.
FIGURE 2-2: 28-PIN UQFN DIAGRAM FOR PIC16(L)F1512, PIC16(L)F1513, PIC16(L)F1516
AND PIC16(L)F1518
2
3
6
1
18
19
20
21
15
7
16
17
RC0
5
4
RB7/ICSPDAT
RB6/ICSPCLK
RB5
RB4
RB3
RB2
RB1
RB0
VDD
VSS
RC7
RC6
RC5
RC4
RE3/MCLR/VPP
RA0
RA1
RA2
RA3
RA4
RA5
VSS
RA7
RA6
RC1
RC2
RC3
9
10
13
8
14
12
11
27
26
23
28
22
24
25
UQFN
PIC16(L)F1512
PIC16(L)F1513
PIC16(L)F1516
PIC16(L)F1518
2010-2011 Microchip Technology Inc. Advance Information DS41442B-page 5
PIC16(L)F151X/152X
FIGURE 2-3: 40-PIN PDIP DIAGRAM FOR PIC16(L)F1517 AND PIC16(L)F1519
FIGURE 2-4: 40-PIN UQFN DIAGRAM FOR PIC16(L)F1517 AND PIC16(L)F1519
PDIP
PIC16(L)F1517
PIC16(L)F1519
2
3
4
5
6
7
8
9
10
VPP/MCLR/RE3
RA0
RA1
RA2
RA3
RA4
RA5
RE0
RE1
RE2
RB6/ICSPCLK/ICDCLK
RB5
RB4
RB3
RB2
RB1
RB0
VDD
VSS
RD2
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VDD
VSS
RA7
RA6
RC0
RC1
RC2
RC3
RD0
RD1
RC5
RC4
RD3
RD4
RC7
RC6
RD7
RD6
RD5
RB7/ICSPDAT/ICDDAT
1
10
2
3
4
5
6
1
17
18
19
20
11
12
13
14
34
8
7
40
39
38
37
36
35
15
16
26
27
28
29
30
21
22
23
24
25
32
31
9
33
RA1
RA0
VPP/MCLR/RE3
RB3
ICDDAT/ICSPDAT/RB7
ICDCLK/ICSPCLK/RB6
RB5
RB4
RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1
RC0
RA7
VSS
VDD
RE2
RE1
RE0
RA5
RC7
RD4
RD5
RD6
RD7
VSS
VDD
RB0
RB1
RB2
UQFN
RA3
RA2
PIC16(L)F1517
PIC16(L)F1519
RA6
RA4
PIC16(L)F151X/152X
DS41442B-page 6 Advance Information 2010-2011 Microchip Technology Inc.
FIGURE 2-5: 44-PIN TQFP DIAGRAM FOR PIC16(L)F1517 AND PIC16(L)F1519
10
11
2
3
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
37
RA3
RA2
RA1
RA0
VPP/MCLR/RE3
NC
ICDDAT/ICSPDAT/RB7
ICDCLK/ICSPCLK/RB6
RB5
RB4
NC
NC
NC
RC0
VSS
VDD
RB0
RB1
RB2
RB3
5
4
TQFP
RA6
RA7
VSS
VDD
RE2
RE1
RE0
RA5
RA4
RC7
RD4
RD5
RD6
RD7
RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1
PIC16(L)F1517
PIC16(L)F1519
3333333333333333
2010-2011 Microchip Technology Inc. Advance Information DS41442B-page 7
PIC16(L)F151X/152X
FIGURE 2-6: 64-PIN QFN DIAGRAM FOR PIC16(L)F1526 AND PIC16(L)F1527
FIGURE 2-7: 64-PIN TQFP DIAGRAM FOR PIC16(L)F1526 AND PIC16(L)F1527
1
2
3
4
5
6
7
8
9
10
11
12
13
14
38
37
36
35
34
33
50 49
17 18 19 20 21 22 23 24 25 26
RE2
RE3
RE4
RE5
RE6
RE7
RD0
VDD
VSS
RD1
RD2
RD3
RD4
RD5
RD6
RD7
RE1
RE0
RG0
RG1
RG2
RG3
VPP/MCLR/RG5
RG4
VSS
VDD
RF7
RF6
RF5
RF4
RF3
RF2
RB0
RB1
RB2
RB3
RB4
RB5
RB6/ICSPCLK/ICDCLK
VSS
RA6
RA7
VDD
RB7/ICSPDAT/ICDDAT
RC4
RC3
RC2
RF0
RF1
AVDD
AVSS
RA3
RA2
RA1
RA0
VSS
VDD
RA4
RA5
RC1
RC0
RC7
RC6
RC5
15
16
31
40
39
27 28 29 30 32
48
47
46
45
44
43
42
41
54 53 52 5158 57 56 5560 59
64 63 62 61
QFN
PIC16(L)F1526
PIC16(L)F1527
1
2
3
4
5
6
7
8
9
10
11
12
13
14
38
37
36
35
34
33
50 49
17 18 19 20 21 22 23 24 25 26
RE2
RE3
RE4
RE5
RE6
RE7
RD0
VDD
VSS
RD1
RD2
RD3
RD4
RD5
RD6
RD7
RE1
RE0
RG0
RG1
RG2
RG3
VPP/MCLR/RG5
RG4
VSS
VDD
RF7
RF6
RF5
RF4
RF3
RF2
RB0
RB1
RB2
RB3
RB4
RB5
RB6/ICSPCLK/ICDCLK
VSS
RA6
RA7
VDD
RB7/ICSPDAT/ICDDAT
RC4
RC3
RC2
VRF0
RF1
AVDD
AVSS
RA3
RA2
RA1
RA0
VSS
VDD
RA4
RA5
RC1
RC0
RC7
RC6
RC5
15
16
31
40
39
27 28 29 30 32
48
47
46
45
44
43
42
41
54 53 52 5158 57 56 5560 59
64 63 62 61
TQFP
PIC16(L)F1526
PIC16(L)F1527
07FFh
PIC16(L)F151X/152X
DS41442B-page 8 Advance Information 2010-2011 Microchip Technology Inc.
3.0 MEMORY MAP
The memory for the PIC16(L)F151X/152X
devices is broken into two sections: program memory
and configuration memory. Only the size of the
program memory changes between devices, the
configuration memory remains the same.
FIGURE 3-1: PIC16(L)F1512 PROGRAM MEMORY MAPPING
7FFF
h
8000
h
8200
h
FFFF
h
2 KW
Implemented
Maps to
Program Memory
Configuration Memory
8000-81FFh
User ID Location
User ID Location
User ID Location
User ID Location
Reserved
Reserved
Device ID
Configuration Word 1
Configuration Word 2
Calibration Word 1
Calibration Word 2
Reserved
8000h
8001h
8002h
8003h
8004h
8005h
8006h
8007h
8009h
8008h
800Ah
Implemented
0000h
Maps to
0-07FFh
07FFh
800Bh-81FFh
DFFFh
2010-2011 Microchip Technology Inc. Advance Information DS41442B-page 9
PIC16(L)F151X/152X
FIGURE 3-2: PIC16(L)F1513 PROGRAM MEMORY MAPPING
7FFF
h
8000
h
8200
h
FFFF
h
4 KW
Implemented
Maps to
Program Memory
Configuration Memory
8000-81FFh
User ID Location
User ID Location
User ID Location
User ID Location
Reserved
Reserved
Device ID
Configuration Word 1
Configuration Word 2
Calibration Word 1
Calibration Word 2
Reserved
8000h
8001h
8002h
8003h
8004h
8005h
8006h
8007h
8009h
8008h
800Ah
Implemented
0000h
Maps to
0-0FFFh
0FFFh
800Bh-81FFh
TFFFh
PIC16(L)F151X/152X
DS41442B-page 10 Advance Information 2010-2011 Microchip Technology Inc.
FIGURE 3-3: PIC16(L)F1526, PIC16(L)F1516 AND PIC16(L)F1517 PROGRAM MEMORY MAPPING
7FFF
h
8000
h
8200
h
FFFF
h
8 KW
Implemented
Maps to
Program Memory
Configuration Memory
8000-81FFh
User ID Location
User ID Location
User ID Location
User ID Location
Reserved
Reserved
Device ID
Configuration Word 1
Configuration Word 2
Calibration Word 1
Calibration Word 2
Reserved
8000h
8001h
8002h
8003h
8004h
8005h
8006h
8007h
8009h
8008h
800Ah
Implemented
0000h
Maps to
0-1FFFh
1FFFh
800Bh-81FFh
2010-2011 Microchip Technology Inc. Advance Information DS41442B-page 11
PIC16(L)F151X/152X
FIGURE 3-4: PIC16(L)F1527, PIC16(L)F1518 AND PIC16(L)F1519 PROGRAM MEMORY
MAPPING
7FFF
h
8000
h
8200
h
FFFF
h
Implemented
16KW
Implemented
3FFFh
Maps to
0-3FFFh
Maps to
Program Memory
Configuration Memory
8000-81FFh
User ID Location
User ID Location
User ID Location
User ID Location
Reserved
Reserved
Device ID
Configuration Word 1
Configuration Word 2
Calibration Word 1
Calibration Word 2
Reserved
8000h
8001h
8002h
8003h
8004h
8005h
8006h
8007h
8009h
8008h
800Ah
0000h
800Bh-81FFh
AB®
PIC16(L)F151X/152X
DS41442B-page 12 Advance Information 2010-2011 Microchip Technology Inc.
3.1 User ID Location
A user may store identification information (user ID) in
four designated locations. The user ID locations are
mapped to 8000h-8003h. Each location is 14 bits in
length. Code protection has no effect on these memory
locations. Each location may be read with code
protection enabled or disabled.
3.2 Device ID
The device ID word is located at 8006h. This location is
read-only and cannot be erased or modified.
Note: MPLAB® IDE only displays the 7 Least
Significant bits (LSb) of each user ID
location, the upper bits are not read. It is
recommended that only the 7 LSbs be
used if MPLAB IDE is the primary tool
used to read these addresses.
REGISTER 3-1: DEVICE ID: DEVICE ID REGISTER(1)
RRRRRR
DEV<8:3>
bit 13 bit 8
R R RRRRRR
DEV<2:0> REV<4:0>
bit 7 bit 0
Legend: P = Programmable bit U = Unimplemented bit, read as ‘0’
R = Readable bit W = Writable bit ‘0’ = Bit is cleared
-n = Value at POR ‘1’ = Bit is set x = Bit is unknown
bit 13-5 DEV<8:0>: Device ID bits
These bits are used to identify the part number.
bit 4-0 REV<4:0>: Revision ID bits
These bits are used to identify the revision.
Note 1: This location cannot be written.
2010-2011 Microchip Technology Inc. Advance Information DS41442B-page 13
PIC16(L)F151X/152X
TABLE 3-1: DEVICE ID VALUES
3.3 Configuration Words
There are two Configuration Words, Configuration Word
1 (8007h) and Configuration Word 2 (8008h). The
individual bits within these Configuration Words are
used to enable or disable device functions such as the
Brown-out Reset, code protection and Power-up Timer.
3.4 Calibration Words
The internal calibration values are factory calibrated
and stored in Calibration Words 1 and 2 (8009h,
800Ah).
The Calibration Words do not participate in erase
operations. The device can be erased without affecting
the Calibration Words.
DEVICE
DEVICE ID VALUES
DEV REV
PIC16F1527 0001 0101 101 x xxxx
PIC16F1526 0001 0101 100 x xxxx
PIC16LF1527 0001 0101 111 x xxxx
PIC16LF1526 0001 0101 110 x xxxx
PIC16F1519 0001 0110 111 x xxxx
PIC16F1518 0001 0110 110 x xxxx
PIC16F1517 0001 0110 101 x xxxx
PIC16F1516 0001 0110 100 x xxxx
PIC16F1513 0001 0110 010 x xxxx
PIC16F1512 0001 0111 000 x xxxx
PIC16LF1519 0001 0111 111 x xxxx
PIC16LF1518 0001 0111 110 x xxxx
PIC16LF1517 0001 0111 101 x xxxx
PIC16LF1516 0001 0111 100 x xxxx
PIC16LF1513 0001 0111 010 x xxxx
PIC16LF1512 0001 0111 001 x xxxx
ll LVF' bu : J ll LVF' bu : a
PIC16(L)F151X/152X
DS41442B-page 14 Advance Information 2010-2011 Microchip Technology Inc.
REGISTER 3-2: CONFIGURATION WORD 1
R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 U-1
FCMEN IESO CLKOUTEN BOREN<1:0>
bit 13 bit 8
R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
CP MCLRE PWRTE WDTE<1:0> FOSC<2:0>
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1
‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase
bit 13 FCMEN: Fail-Safe Clock Monitor Enable bit
1 = Fail-Safe Clock Monitor is enabled
0 = Fail-Safe Clock Monitor is disabled
bit 12 IESO: Internal External Switchover bit
1 = Internal/External Switchover mode is enabled
0 = Internal/External Switchover mode is disabled
bit 11 CLKOUTEN: Clock Out Enable bit
1 = CLKOUT function is disabled. I/O or oscillator function on CLKOUT pin.
0 = CLKOUT function is enabled on CLKOUT pin
bit 10-9 BOREN<1:0>: Brown-out Reset Enable bits(1)
11 = BOR enabled
10 = BOR enabled during operation and disabled in Sleep
01 = BOR controlled by SBOREN bit of the PCON register
00 = BOR disabled
bit 8 Unimplemented: Read as ‘1
bit 7 CP: Code Protection bit(2)
1 = Program memory code protection is disabled
0 = Program memory code protection is enabled
bit 6 MCLRE: MCLR/VPP Pin Function Select bit
If LVP bit = 1:
This bit is ignored.
If LVP bit = 0:
1 =MCLR
/VPP pin function is MCLR; Weak pull-up enabled.
0 =MCLR
/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of WPUA register.
bit 5 PWRTE: Power-up Timer Enable bit(1)
1 = PWRT disabled
0 = PWRT enabled
bit 4-3 WDTE<1:0>: Watchdog Timer Enable bit
11 = WDT enabled
10 = WDT enabled while running and disabled in Sleep
01 = WDT controlled by the SWDTEN bit in the WDTCON register
00 = WDT disabled
bit 2-0 FOSC<2:0>: Oscillator Selection bits
111 = ECH: External Clock, High-Power mode: on CLKIN pin
110 = ECM: External Clock, Medium-Power mode: on CLKIN pin
101 = ECL: External Clock, Low-Power mode: on CLKIN pin
100 = INTOSC oscillator: I/O function on OSC1 pin
011 = EXTRC oscillator: RC function on OSC1 pin
010 = HS oscillator: High-speed crystal/resonator on OSC2 pin and OSC1 pin
001 = XT oscillator: Crystal/resonator on OSC2 pin and OSC1 pin
000 = LP oscillator: Low-power crystal on OSC2 pin and OSC1 pin
Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.
2: The entire program memory will be erased when the code protection is turned off.
2 kw Flash memorylPlCla L F1512 4 kw Flash memorylPlCla L F1513 a kw Flash memory (PlClBF/LF1516/1517/1526 16 kw Flash memog PlClaF/LFlSlallSlBHSN
2010-2011 Microchip Technology Inc. Advance Information DS41442B-page 15
PIC16(L)F151X/152X
REGISTER 3-3: CONFIGURATION WORD 2
R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 U-1
LVP DEBUG LPBOR BORV STVREN
bit 13 bit 8
U-1 U-1 U-1 R/P-1 U-1 U-1 R/P-1 R/P-1
— — —VCAPEN
(2) —WRT<1:0>
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1
‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase
bit 13 LVP: Low-Voltage Programming Enable bit(1)
1 = Low-voltage programming enabled
0 = HV on MCLR/VPP must be used for programming
bit 12 DEBUG: In-Circuit Debugger Mode bit
1 = In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins
0 = In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger
bit 11 LPBOR: Low-Power BOR
1 = Low-Power BOR is disabled
0 = Low-Power BOR is enabled
bit 10 BORV: Brown-out Reset Voltage Selection bit
1 = Brown-out Reset voltage (VBOR), low trip point selected
0 = Brown-out Reset voltage (VBOR), high trip point selected
bit 9 STVREN: Stack Overflow/Underflow Reset Enable bit
1 = Stack Overflow or Underflow will cause a Reset
0 = Stack Overflow or Underflow will not cause a Reset
bit 8-5 Unimplemented: Read as ‘1
bit 4 VCAPEN: Voltage Regulator Capacitor Enable bits(1)
0 = VCAP functionality is enabled on VCAP pin
1 = All VCAP pin functions are disabled
bit 3-2 Unimplemented: Read as1
bit 1-0 WRT<1:0>: Flash Memory Self-Write Protection bits
2 kW Flash memory (PIC16(L)F1512):
11 = Write protection off
10 = 000h to 1FFh write-protected, 200h to 7FFh may be modified by PMCON control
01 = 000h to FFFh write-protected, 400h to 7FFh may be modified by PMCON control
00 = 000h to 7FFh write-protected, no addresses may be modified by PMCON control
4 kW Flash memory (PIC16(L)F1513):
11 = Write protection off
10 = 000h to 1FFh write-protected, 200h to FFFh may be modified by PMCON control
01 = 000h to 7FFh write-protected, 800h to FFFh may be modified by PMCON control
00 = 000h to FFFh write-protected, no addresses may be modified by PMCON control
8 kW Flash memory (PIC16F/LF1516/1517/1526):
11 = Write protection off
10 = 000h to 1FFh write-protected, 200h to 1FFFh may be modified by PMCON control
01 = 000h to FFFh write-protected, 1000h to 1FFFh may be modified by PMCON control
00 = 000h to 1FFFh write-protected, no addresses may be modified by PMCON control
16 kW Flash memory (PIC16F/LF1518/1519/1527):
11 = Write protection off
10 = 000h to 1FFh write-protected, 200h to 3FFFh may be modified by PMCON control
01 = 000h to 1FFFh write-protected, 2000h to 3FFFh may be modified by PMCON control
00 = 000h to 3FFFh write-protected, no addresses may be modified by PMCON control
Note 1: The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP.
2: Applies to PIC16F151X/152X devices only. On PIC16LF151X/152X, the VCAPEN bit is unimplemented.
MCLR MCLR MCLR MCLR MCLR MCLR PWRTE MCLR
PIC16(L)F151X/152X
DS41442B-page 16 Advance Information 2010-2011 Microchip Technology Inc.
4.0 PROGRAM/VERIFY MODE
In Program/Verify mode, the program memory and the
configuration memory can be accessed and
programmed in serial fashion. ICSPDAT and
ICSPCLK are used for the data and the clock,
respectively. All commands and data words are
transmitted LSb first. Data changes on the rising edge
of the ICSPCLK and latched on the falling edge. In
Program/Verify mode both the ICSPDAT and
ICSPCLK are Schmitt Trigger inputs. The sequence
that enters the device into Program/Verify mode
places all other logic into the Reset state. Upon
entering Program/Verify mode, all I/Os are
automatically configured as high-impedance inputs
and the address is cleared.
4.1 High-Voltage Program/Verify Mode
Entry and Exit
There are two different methods of entering Program/
Verify mode via high-voltage:
•VPP – First entry mode
•V
DD – First entry mode
4.1.1 VPP – FIRST ENTRY MODE
To enter Program/Verify mode via the VPP-first method
the following sequence must be followed:
1. Hold ICSPCLK and ICSPDAT low. All other pins
should be unpowered.
2. Raise the voltage on MCLR from 0V to VIHH.
3. Raise the voltage on VDD FROM 0V to the
desired operating voltage.
The VPP-first entry prevents the device from executing
code prior to entering Program/Verify mode. For
example, when Configuration Word 1 has MCLR
disabled (MCLRE = 0), the power-up time is disabled
(PWRTE =0), the internal oscillator is selected
(FOSC =100), and ICSPCLK and ICSPDAT pins are
driven by the user application, the device will execute
code. Since this may prevent entry, VPP-first entry
mode is strongly recommended. See the timing
diagram in Figure 8-2.
4.1.2 VDD – FIRST ENTRY MODE
To enter Program/Verify mode via the VDD-first method
the following sequence must be followed:
1. Hold ICSPCLK and ICSPDAT low.
2. Raise the voltage on VDD from 0V to the desired
operating voltage.
3. Raise the voltage on MCLR from VDD or below
to VIHH.
The VDD-first method is useful when programming the
device when VDD is already applied, for it is not
necessary to disconnect VDD to enter Program/Verify
mode. See the timing diagram in Figure 8-1.
4.1.3 PROGRAM/VERIFY MODE EXIT
To exit Program/Verify mode take MCLR to VDD or
lower (VIL). See Figures 8-3 and 8-4.
4.2 Low-Voltage Programming (LVP)
Mode
The Low-Voltage Programming mode allows the
PIC16(L)F151X/152X devices to be programmed using
VDD only, without high voltage. When the LVP bit of
Configuration Word 2 register is set to ‘1’, the low-
voltage ICSP programming entry is enabled. To disable
the Low-Voltage ICSP mode, the LVP bit must be
programmed to ‘0’. This can only be done while in the
High-Voltage Entry mode.
Entry into the Low-Voltage ICSP Program/Verify modes
requires the following steps:
1. MCLR is brought to VIL.
2. A 32-bit key sequence is presented on
ICSPDAT, while clocking ICSPCLK.
The key sequence is a specific 32-bit pattern, '0100
1101 0100 0011 0100 1000 0101 0000' (more
easily remembered as MCHP in ASCII). The device will
enter Program/Verify mode only if the sequence is
valid. The Least Significant bit of the Least Significant
nibble must be shifted in first.
Once the key sequence is complete, MCLR must be
held at VIL for as long as Program/Verify mode is to be
maintained.
For low-voltage programming timing, see Figure 8-8
and Figure 8-9.
Exiting Program/Verify mode is done by no longer
driving MCLR to VIL. See Figure 8-8 and Figure 8-9.
Note: To enter LVP mode, the LSB of the Least
Significant nibble must be shifted in first.
This differs from entering the key
sequence on other parts.
2010-2011 Microchip Technology Inc. Advance Information DS41442B-page 17
PIC16(L)F151X/152X
4.3 Program/Verify Commands
The PIC16(L)F151X/152X implements 10
programming commands; each six bits in length. The
commands are summarized in Ta bl e 4 - 1 .
Commands that have data associated with them are
specified to have a minimum delay of TDLY between the
command and the data. After this delay 16 clocks are
required to either clock in or clock out the 14-bit data
word. The first clock is for the Start bit and the last clock
is for the Stop bit.
4.3.1 LOAD CONFIGURATION
The Load Configuration command is used to access
the configuration memory (User ID Locations,
Configuration Words, Calibration Words). The Load
Configuration command sets the address to 8000h and
loads the data latches with one word of data (see
Figure 4-1).
After issuing the Load Configuration command, use the
Increment Address command until the proper address
to be programmed is reached. The address is then pro-
grammed by issuing either the Begin Internally Timed
Programming or Begin Externally Timed Programming
command.
The only way to get back to the program memory
(address 0) is to exit Program/Verify mode or issue the
Reset Address command after the configuration memory
has been accessed by the Load Configuration command.
FIGURE 4-1: LOAD CONFIGURATION
TABLE 4-1: COMMAND MAPPING
Command
Mapping Data/Note
Binary (MSb … LSb) Hex
Load Configuration x00000 00h 0, data (14), 0
Load Data For Program Memory x00010 02h 0, data (14), 0
Read Data From Program Memory x00100 04h 0, data (14), 0
Increment Address x00110 06h —
Reset Address x10110 16h —
Begin Internally Timed Programming x01000 08h —
Begin Externally Timed Programming x11000 18h —
End Externally Timed Programming x010100Ah —
Bulk Erase Program Memory x01001 09h Internally Timed
Row Erase Program Memory x10001 11h Internally Timed
Note: Externally timed writes are not supported
for Configuration and Calibration bits. Any
externally timed write to the Configuration
or Calibration Word will have no effect on
the targeted word.
X00
LSb MSb 0
123 4561215 16
ICSPCLK
ICSPDAT
0000
TDLY
PIC16(L)F151X/152X
DS41442B-page 18 Advance Information 2010-2011 Microchip Technology Inc.
4.3.2 LOAD DATA FOR PROGRAM
MEMORY
The Load Data for Program Memory command is used
to load one 14-bit word into the data latches. The word
programs into program memory after the Begin
Internally Timed Programming or Begin Externally
Timed Programming command is issued (see
Figure 4-2).
FIGURE 4-2: LOAD DATA FOR PROGRAM MEMORY
4.3.3 READ DATA FROM PROGRAM
MEMORY
The Read Data from Program Memory command will
transmit data bits out of the program memory map
currently accessed, starting with the second rising edge
of the clock input. The ICSPDAT pin will go into Output
mode on the first falling clock edge, and it will revert to
Input mode (high-impedance) after the 16th falling edge
of the clock. If the program memory is code-protected
(CP), the data will be read as zeros (see Figure 4-3).
FIGURE 4-3: READ DATA FROM PROGRAM MEMORY
ICSPCLK
ICSPDAT
123 4561215 16
X0 0LSb MSb 0
010 0
TDLY
1 2 3 4 5 6 1 2 15 16
LSb MSb
TDLY
ICSPCLK
ICSPDAT
Input Input
Output
x
(from Programmer)
X
0
001 0
ICSPDAT
(from device)
2010-2011 Microchip Technology Inc. Advance Information DS41442B-page 19
PIC16(L)F151X/152X
4.3.4 INCREMENT ADDRESS
The address is incremented when this command is
received. It is not possible to decrement the address.
To reset this counter, the user must use the Reset
Address command or exit Program/Verify mode and re-
enter it. If the address is incremented from address
7FFFh, it will wrap-around to location 0000h. If the
address is incremented from FFFFh, it will wrap-around
to location 8000h.
FIGURE 4-4: INCREMENT ADDRESS
4.3.5 RESET ADDRESS
The Reset Address command will reset the address to
0000h, regardless of the current value. The address is
used in program memory or the configuration memory.
FIGURE 4-5: RESET ADDRESS
X
0
123 45612
ICSPCLK
ICSPDAT
011
3
XXX
TDLY
Next Command
0
Address + 1
Address
X
0
123 4561
2
ICSPCLK
ICSPDAT
011
3
XXX
TDLY
Next Command
1
0000h
N
Address
PIC16(L)F151X/152X
DS41442B-page 20 Advance Information 2010-2011 Microchip Technology Inc.
4.3.6 BEGIN INTERNALLY TIMED
PROGRAMMING
A Load Configuration or Load Data for Program
Memory command must be given before every Begin
Programming command. Programming of the
addressed memory will begin after this command is
received. An internal timing mechanism executes the
write. The user must allow for the program cycle time,
TPINT, for the programming to complete.
The End Externally Timed Programming command is
not needed when the Begin Internally Timed
Programming is used to start the programming.
The program memory address that is being
programmed is not erased prior to being programmed.
FIGURE 4-6: BEGIN INTERNALLY TIMED PROGRAMMING
4.3.7 BEGIN EXTERNALLY TIMED
PROGRAMMING
A Load Configuration or Load Data for Program
Memory command must be given before every Begin
Programming command. Programming of the
addressed memory will begin after this command is
received. To complete the programming the End
Externally Timed Programming command must be sent
in the specified time window defined by TPEXT (see
Figure 4-7).
Externally timed writes are not supported for
Configuration and Calibration bits. Any externally timed
write to the Configuration or Calibration Word will have
no effect on the targeted word.
FIGURE 4-7: BEGIN EXTERNALLY TIMED PROGRAMMING
12345612
ICSPCLK
ICSPDAT
3
TPINT
X
1
000XXX
0
Next Command
X
10
123 4561
2
ICSPCLK
ICSPDAT
00 0 110
End Externally Timed Programming
Command
TPEXT
3
2010-2011 Microchip Technology Inc. Advance Information DS41442B-page 21
PIC16(L)F151X/152X
4.3.8 END EXTERNALLY TIMED
PROGRAMMING
This command is required after a Begin Externally
Timed Programming command is given. This
command must be sent within the time window
specified by TPEXT after the Begin Externally Timed
Programming command is sent.
After sending the End Externally Timed Programming
command, an additional delay (TDIS) is required before
sending the next command. This delay is longer than
the delay ordinarily required between other commands
(see Figure 4-8).
FIGURE 4-8: END EXTERNALLY TIMED PROGRAMMING
4.3.9 BULK ERASE PROGRAM MEMORY
The Bulk Erase Program Memory command performs
two different functions dependent on the current state
of the address.
A Bulk Erase Program Memory command should not
be issued when the address is greater than 8008h.
After receiving the Bulk Erase Program Memory
command the erase will not complete until the time
interval, T
ERAB, has expired.
FIGURE 4-9: BULK ERASE PROGRAM MEMORY
12345612
ICSPCLK
ICSPDAT
3
TDIS
X
1
010XXX
1
Next Command
Address 0000h-7FFFh:
Program Memory is erased
Configuration Words are erased
Address 8000h-8008h:
Program Memory is erased
Configuration Words are erased
User ID Locations are erased
Note: The code protection Configuration bit
(CP) has no effect on the Bulk Erase
Program Memory command.
123 45612
ICSPCLK
ICSPDAT
3
TERAB
X
1
100XXX
0
Next Command
PIC16(L)F151X/152X
DS41442B-page 22 Advance Information 2010-2011 Microchip Technology Inc.
4.3.10 ROW ERASE PROGRAM MEMORY
The Row Erase Program Memory command will erase
an individual row. Refer to Ta b l e 4 - 2 for row sizes of
specific devices and the PC bits used to address them.
If the program memory is code-protected the Row
Erase Program Memory command will be ignored.
When the address is 8000h-8008h the Row Erase
Program Memory command will only erase the user ID
locations regardless of the setting of the CP
Configuration bit.
After receiving the Row Erase Program Memory
command the erase will not complete until the time
interval, T
ERAR, has expired.
FIGURE 4-10: ROW ERASE PROGRAM MEMORY
TABLE 4-2: PROGRAMMING ROW SIZE AND LATCHES
Devices PC Row Size Number of Latches
PIC16(L)F151X/152X <15:5> 32 32
12345612
ICSPCLK
ICSPDAT
3
TERAR
X
0
100XXX
1
Next Command
2010-2011 Microchip Technology Inc. Advance Information DS41442B-page 23
PIC16(L)F151X/152X
5.0 PROGRAMMING ALGORITHMS
The devices use internal latches to temporarily store
the 14-bit words used for programming. Refer to
Table 4-2 for specific latch information. The data
latches allow the user to write the program words with
a single Begin Externally Timed Programming or Begin
Internally Timed Programming command. The Load
Program Data or the Load Configuration command is
used to load a single data latch. The data latch will hold
the data until the Begin Externally Timed Programming
or Begin Internally Timed Programming command is
given.
The data latches are aligned with the LSbs of the
address. The PC’s address at the time the Begin
Externally Timed Programming or Begin Internally
Timed Programming command is given will determine
which location(s) in memory are written. Writes cannot
cross the physical boundary. For example, with the
PIC16F1527, attempting to write from address 0002h-
0009h will result in data being written to 0008h-000Fh.
If more than the maximum number of data latches are
written without a Begin Externally Timed Programming
or Begin Internally Timed Programming command, the
data in the data latches will be overwritten. The
following figures show the recommended flowcharts for
programming.
PIC16(L)F151X/152X
DS41442B-page 24 Advance Information 2010-2011 Microchip Technology Inc.
FIGURE 5-1: DEVICE PROGRAM/VERIFY FLOWCHART
Done
Start
Bulk Erase
Device
Write User IDs
Enter
Programming Mode
Write Program
Memory(1)
Verify User IDs
Write Configuration
Words(2)
Verify Configuration
Words
Exit Programming
Mode
Verify Program
Memory
Note 1: See Figure 5-2.
2: See Figure 5-5.
2010-2011 Microchip Technology Inc. Advance Information DS41442B-page 25
PIC16(L)F151X/152X
FIGURE 5-2: PROGRAM MEMORY FLOWCHART
Start
Read Data
Program Memory
Data Correct?
Report
Programming
Failure
All Locations
Done?
No
No
Increment
Address
Command
from
Bulk Erase
Program
Yes
Memory(1, 2)
Done
Yes
Note 1: This step is optional if device has already been erased or has not been previously programmed.
2: If the device is code-protected or must be completely erased, then Bulk Erase device per Figure 5-6.
3: See Figure 5-3 or Figure 5-4.
Program Cycle
(3)
PIC16(L)F151X/152X
DS41442B-page 26 Advance Information 2010-2011 Microchip Technology Inc.
FIGURE 5-3: ONE-WORD PROGRAM CYCLE
Begin
Programming
Wait TDIS
Load Data
for
Program Memory
Command
(Internally timed)
Begin
Programming
Wait TPEXT
Command
(Externally timed)(1)
End
Programming
Wait TPINT
Program Cycle
Command
Note 1: Externally timed writes are not supported for Configuration and Calibration bits.
2010-2011 Microchip Technology Inc. Advance Information DS41442B-page 27
PIC16(L)F151X/152X
FIGURE 5-4: MULTIPLE-WORD PROGRAM CYCLE
Begin
Programming
Wait TPINT
Load Data
for
Program Memory
Command
(Internally timed)
Wait TPEXT
End
Programming
Wait TDIS
Load Data
for
Program Memory
Increment
Address
Command
Load Data
for
Program Memory
Begin
Programming
Command
(Externally timed)
Latch 1
Latch 2
Latch n
Increment
Address
Command
Program Cycle
Command
Yes Rep Address : 30mm Dara Currecw narw
PIC16(L)F151X/152X
DS41442B-page 28 Advance Information 2010-2011 Microchip Technology Inc.
FIGURE 5-5: CONFIGURATION MEMORY PROGRAM FLOWCHART
Start
Load
Configuration
Program Cycle(2)
Read Data
Memory Command
Data Correct? Report
Programming
Failure
Address =
8004h?
Data Correct?
Report
Programming
Failure
Yes
No
Yes
Yes
No
Increment
Address
Command
No Increment
Address
Command
Done
One-word
One-word
Program Cycle(2)
(Config. Word 1)
Increment
Address
Command
Increment
Address
Command
(User ID)
From Program
Read Data
Memory Command
From Program
Program
Bulk Erase
Memory(1)
Data Correct?
Report
Programming
Failure
Yes
No
One-word
Program Cycle(2)
(Config. Word 2)
Increment
Address
Command
Read Data
Memory Command
From Program
Note 1: This step is optional if device is erased or not previously programmed.
2: See Figure 5-3.
C9
2010-2011 Microchip Technology Inc. Advance Information DS41442B-page 29
PIC16(L)F151X/152X
FIGURE 5-6: ERASE FLOWCHART
Start
Load Configuration
Done
Bulk Erase
Program Memory
Note: This sequence does not erase the Calibration Words.
PIC16(L)F151X/152X
DS41442B-page 30 Advance Information 2010-2011 Microchip Technology Inc.
6.0 CODE PROTECTION
Code protection is controlled using the CP bit in
Configuration Word 1. When code protection is
enabled, all program memory locations (0000h-7FFFh)
read as all ‘0’. Further programming is disabled for the
program memory (0000h-7FFFh).
The user ID locations and Configuration Words can be
programmed and read out regardless of the code
protection settings.
6.1 Program Memory
Code protection is enabled by programming the CP bit
in Configuration Word 1 register to ‘0’.
The only way to disable code protection is to use the
Bulk Erase Program Memory command.
7.0 HEX FILE USAGE
In the hex file there are two bytes per program word
stored in the Intel® INHX32 hex format. Data is stored
LSB first, MSB second. Because there are two bytes
per word, the addresses in the hex file are 2x the
address in program memory. (Example: Configuration
Word 1 is stored at 8007h on the PIC16(L)F151X/
152X. In the hex file this will be referenced as 1000Eh-
1000Fh).
7.1 Configuration Word
To allow portability of code, it is strongly recommended
that the programmer is able to read the Configuration
Words and user ID locations from the hex file. If the
Configuration Words information was not present in the
hex file, a simple warning message may be issued.
Similarly, while saving a hex file, Configuration Words
and user ID information should be included.
7.2 Device ID and Revision
If a device ID is present in the hex file at 1000Ch-
1000Dh (8006h on the part), the programmer should
verify the device ID (excluding the revision) against the
value read from the part. On a mismatch condition the
programmer should generate a warning message.
2010-2011 Microchip Technology Inc. Advance Information DS41442B-page 31
PIC16(L)F151X/152X
7.3 Checksum Computation
The checksum is calculated by two different methods
dependent on the setting of the CP Configuration bit.
7.3.1 PROGRAM CODE PROTECTION
DISABLED
With the program code protection disabled, the
checksum is computed by reading the contents of the
PIC16(L)F151X/152X program memory locations and
adding up the program memory data starting at address
0000h, up to the maximum user addressable location.
Any Carry bit exceeding 16 bits are ignored.
Additionally, the relevant bits of the Configuration Words
are added to the checksum. All unimplemented
Configuration bits are masked to ‘0’.
TABLE 7-1: CONFIGURATION WORD
MASK VALUES
Device Config. Word 1
Mask
Config. Word 2
Mask
PIC16F1512 3EFFh 3E13h
PIC16F1513 3EFFh 3E13h
PIC16F1516 3EFFh 3E13h
PIC16F1517 3EFFh 3E13h
PIC16F1518 3EFFh 3E13h
PIC16F1519 3EFFh 3E13h
PIC16LF1512 3EFFh 3E03h
PIC16LF1513 3EFFh 3E03h
PIC16LF1516 3EFFh 3E03h
PIC16LF1517 3EFFh 3E03h
PIC16LF1518 3EFFh 3E03h
PIC16LF1519 3EFFh 3E03h
PIC16F1526 3EFFh 3E13h
PIC16F1527 3EFFh 3E13h
PIC16LF1526 3EFFh 3E03h
PIC16LF1527 3EFFh 3E03h
VCAPEN
PIC16(L)F151X/152X
DS41442B-page 32 Advance Information 2010-2011 Microchip Technology Inc.
EXAMPLE 7-1: CHECKSUM COMPUTED WITH PROGRAM CODE PROTECTION DISABLED
PIC16F1527, BLANK DEVICE
EXAMPLE 7-2: CHECKSUM COMPUTED WITH PROGRAM CODE PROTECTION DISABLED
PIC16LF1527, 00AAh AT FIRST AND LAST ADDRESS
PIC16F1527 Sum of Memory addresses 0000h-3FFFh(1) C000h
Configuration Word 1(2) 3FFFh
Configuration Word 1 mask(3) 3EFFh
Configuration Word 2(2) 3FFFh
Configuration Word 2 mask(3) 3E13h
Checksum = C000h + (3FFFh and 3EFFh) + (3FFFh and 3E13h)
= C000h + 3EFFh + 3E13h
= 3D12h
Note 1: Sum of memory addresses = (Total number of program memory address locations) x (3FFFh) = C000h,
truncated to 16 bits.
2: Configuration Word 1 and 2 = all bits are ‘1’; thus, code-protect is disabled.
3: Configuration Word 1 and 2 Mask = all bits are set to1’, except for unimplemented bits that are ‘0’.
PIC16LF1527 Sum of Memory addresses 0000h-3FFFh(1) 4156h
Configuration Word 1(2) 3FFFh
Configuration Word 1 mask(3) 3EFFh
Configuration Word 2(2) 3FFFh
Configuration Word 2 mask(4) 3E03h
Checksum = 4156h + (3FFFh and 3EFFh) + (3FFFh and 3E03h)
= 4156h + 3EFFh + 3E03h
= BE58h
Note 1: Total number of Program memory address locations: 3FFFh + 1 = 4000h. Then, 4000h - 2 = 3FFEh.
Thus, [(3FFEh x 3FFFh) + (2 x 00AAh)] = 4156h, truncated to 16 bits.
2: Configuration Word 1 and 2 = all bits are ‘1’; thus, code-protect is disabled.
3: Configuration Word 1 Mask = all Configuration Word bits are set to ‘1’, except for unimplemented bits
that are ‘0’.
4: On the PIC16LF1527 device, the VCAPEN bit is not implemented in Configuration Word 2; Thus, all
unimplemented bits are ‘0’.
2010-2011 Microchip Technology Inc. Advance Information DS41442B-page 33
PIC16(L)F151X/152X
7.3.2 PROGRAM CODE PROTECTION
ENABLED
With the program code protection enabled, the
checksum is computed in the following manner: The
Least Significant nibble of each user ID is used to
create a 16-bit value. The masked value of user ID
location 8000h is the Most Significant nibble. This sum
of user IDs is summed with the Configuration Words (all
unimplemented Configuration bits are masked to ‘0’).
EXAMPLE 7-3: CHECKSUM COMPUTED WITH PROGRAM CODE PROTECTION ENABLED
PIC16F1527, BLANK DEVICE
PIC16F1527 Configuration Word 1(2) 3F7Fh
Configuration Word 1 mask(3) 3EFFh
Configuration Word 2(2) 3FFFh
Configuration Word 2 mask(3) 3E13h
User ID (8000h)(1) 0006h
User ID (8001h)(1) 0007h
User ID (8002h)(1) 0001h
User ID (8003h)(1) 0002h
Sum of User IDs(4) = (0006h and 000Fh) << 12 + (0007h and 000Fh) << 8 +
(0001h and 000Fh) << 4 + (0002h and 000Fh)
= 6000h + 0700h + 0010h + 0002h
= 6712h
Checksum = (3F7Fh and 3EFFh) + (3FFFh and 3E13h) + Sum of User IDs
= 3E7Fh +3713h + 6712h
= DCA4h
Note 1: User ID values in this example are random values.
2: Configuration Word 1 and 2 = all bits are ‘1’ except the code-protect enable bit.
3: Configuration Word 1 and 2 Mask = all Configuration Word bits are set to ‘1’, except for unimplemented
bits which read ‘0’.
4: << = shift left, thus the LSb of the first user ID value is the MSb of the sum of user IDs and so on, until
the LSb of the last user ID value becomes the LSb of the sum of user IDs.
e VCAPEN
PIC16(L)F151X/152X
DS41442B-page 34 Advance Information 2010-2011 Microchip Technology Inc.
EXAMPLE 7-4: CHECKSUM COMPUTED WITH PROGRAM CODE PROTECTION ENABLED
PIC16LF1527, 00AAh AT FIRST AND LAST ADDRESS
PIC16LF1527 Configuration Word 1(2) 3F7Fh
Configuration Word 1 mask(3) 3EFFh
Configuration Word 2(2) 3FFFh
Configuration Word 2 mask(3), (5) 3E03h
User ID (8000h)(1) 000Eh
User ID (8001h)(1) 0008h
User ID (8002h)(1) 0005h
User ID (8003h)(1) 0008h
Sum of User IDs(4) = (000Eh and 000Fh) << 12 + (0008h and 000Fh) << 8 +
(0005h and 000Fh) << 4 + (0008h and 000Fh)
= E000h + 0800h + 0050h + 0008h
= E858h
Checksum = (3F7Fh and 3EFFh) + (3FFFh and 3E03h) + Sum of User IDs
= 3E7Fh +3E03h + E858h
= 64DAh
Note 1: User ID values in this example are random values.
2: Configuration Word 1 and 2 = all bits are ‘1’ except the code-protect enable bit.
3: Configuration Word 1 and 2 Mask = all Configuration Word bits are set to1’, except for unimplemented
bits which read0’.
4: << = shift left, thus the LSb of the first user ID value is the MSb of the sum of user IDs and so on, until
the LSb of the last user ID value becomes the LSb of the sum of user IDs.
5: On the PIC16LF1527 device, the VCAPEN bit is not implemented in Configuration Word 2; thus, all
unimplemented bits are ‘0’.
Standard Operating Conditions Supply Volt ages and Currents PICtEFtsTX PlCiELF151X v Read/Wnte and Rew Erase operatmns v 7 v v v Bu‘k Erase operahuns 2.7 7 v v ICSFDAT eutput nTgn \evel v D-U 7 : a 5 mA‘ v D : 5v ICSFDAT eutput low leve\ v +0 6 : a rnA. v = 5v Programming Mode Entry and Exit Programmg made entry setup trrne, ICSPCLK‘ Programmg made entry hem trrne. ICSPCLK‘ Serial Program/Verify T Clock Lew Pulse wTdtn too 7 7 ns T Clock HTgn Pu‘se wmtn too 7 7 ns T Data m setup Mme before cluckL too 7 7 ns T Data VI note [me after c‘ocki too 7 7 ns ClockT te uata nut vahd (during a Clocki te uata \uw-Impedance (during a i T Bu‘k Erase eyele [me 7 7 5 ms Nate 1: Externany tTrneu wmles are net supported lur Cennguratmn and Cahbralmn mts.
2010-2011 Microchip Technology Inc. Advance Information DS41442B-page 35
PIC16(L)F151X/152X
8.0 ELECTRICAL SPECIFICATIONS
Refer to device specific data sheet for absolute
maximum ratings.
TABLE 8-1: AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY MODE
AC/DC CHARACTERISTICS Standard Operating Conditions
Production tested at 25°C
Sym. Characteristics Min. Typ. Max. Units Conditions/Comments
Supply Voltages and Currents
VDD Supply Voltage
(VDDMIN, VDDMAX)
PIC16F151X
PIC16F152X 2.3 — 5.5 V
PIC16LF151X
PIC16LF152X 1.8 — 3.6 V
VPEW Read/Write and Row Erase operations VDDMIN —VDDMAX V
VPBE Bulk Erase operations 2.7 VDDMAX V
IDDI Current on VDD, Idle 1.0 mA
IDDP Current on VDD, Programming 3.0 mA
IPP
VPP
Current on MCLR/VPP 600 A
VIHH High voltage on MCLR/VPP for
Program/Verify mode entry 8.0 — 9.0 V
TVHHR MCLR rise time (VIL to VIHH) for
Program/Verify mode entry ——1.0s
I/O pins
VIH (ICSPCLK, ICSPDAT, MCLR/VPP) input high
level 0.8 VDD —— V
VIL (ICSPCLK, ICSPDAT, MCLR/VPP) input low level 0.2 VDD V
VOH
ICSPDAT output high level VDD-0.7
VDD-0.7
VDD-0.7
—— V
IOH = 3.5 mA, VDD = 5V
IOH = 3 mA, VDD = 3.3V
IOH = 2 mA, VDD = 1.8V
VOL
ICSPDAT output low level
——
VSS+0.6
VSS+0.6
VSS+0.6
V
IOH = 8 mA, VDD = 5V
IOH = 6 mA, VDD = 3.3V
IOH = 3 mA, VDD = 1.8V
Programming Mode Entry and Exit
TENTS Programing mode entry setup time: ICSPCLK,
ICSPDAT setup time before VDD or MCLR 100 — ns
TENTH Programing mode entry hold time: ICSPCLK,
ICSPDAT hold time after VDD or MCLR 250 — s
Serial Program/Verify
TCKL Clock Low Pulse Width 100 ns
TCKH Clock High Pulse Width 100 ns
TDS Data in setup time before clock100 ns
TDH Data in hold time after clock100 ns
TCO Clock to data out valid (during a
Read Data command) 0 — 80 ns
TLZD Clock to data low-impedance (during a
Read Data command) 0 — 80 ns
THZD Clock to data high-impedance (during a
Read Data command) 0 — 80 ns
TDLY
Data input not driven to next clock input (delay
required between command/data or command/
command)
1.0 — s
TERAB Bulk Erase cycle time 5 ms
TERAR Row Erase cycle time 2.5 ms
Note 1: Externally timed writes are not supported for Configuration and Calibration bits.
Standard Operating Conditions Imemany timed programrmng uperalmn «me 7 7 2.5 ms Program memory T Externauy Umed pmgrammmg pulse 1.0 7 2.1 ms Nots1 Twme de‘ay lmm program to campare T Twme de‘ay when exmng Prugram/Venry mode 1 7 7 ns Nate 1: Exrernany urneu wmles are nm supponed lm Conflguralmn and Cahbrahun bfls.
PIC16(L)F151X/152X
DS41442B-page 36 Advance Information 2010-2011 Microchip Technology Inc.
8.1 AC Timing Diagrams
FIGURE 8-1: PROGRAMMING MODE
ENTRY – VDD FIRST
FIGURE 8-2: PROGRAMMING MODE
ENTRY – VPP FIRST
FIGURE 8-3: PROGRAMMING MODE
EXIT – VPP LAST
FIGURE 8-4: PROGRAMMING MODE
EXIT – VDD LAST
TPINT Internally timed programming operation time
2.5
5
ms
ms
Program memory
Configuration Words
TPEXT Externally timed programming pulse 1.0 2.1 ms Note 1
TDIS Time delay from program to compare
(HV discharge time) 300 — s
TEXIT Time delay when exiting Program/Verify mode 1 s
Note 1: Externally timed writes are not supported for Configuration and Calibration bits.
TABLE 8-1: AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY
AC/DC CHARACTERISTICS Standard Operating Conditions
Production tested at 25°C
Sym. Characteristics Min. Typ. Max. Units Conditions/Comments
VPP
TENTH
VDD
TENTS
ICSPDAT
ICSPCLK
VIHH
VIL
TENTH
ICSPDAT
ICSPCLK
VDD
TENTS
VPP
VIHH
VIL
TEXIT
VPP
VDD
ICSPDAT
ICSPCLK
VIHH
VIL
TEXIT
VPP
VDD
ICSPDAT
ICSPCLK
VIHH
VIL
2010-2011 Microchip Technology Inc. Advance Information DS41442B-page 37
PIC16(L)F151X/152X
FIGURE 8-5: CLOCK AND DATA
TIMING
FIGURE 8-6: WRITE COMMAND-PAYLOAD TIMING
FIGURE 8-7: READ COMMAND-PAYLOAD TIMING
as
ICSPCLK
TCKH TCKL
TDH
TDS
ICSPDAT
output
TCO
ICSPDAT
ICSPDAT
ICSPDAT
TLZD
THZD
input
as
from input
from output
to input
to output
12345612 15 16
X0LSb MSb 0
TDLY
Command Next
Command
Payload
ICSPCLK
ICSPDAT
XXXXX
1234561
215 16
X
TDLY
Command Next
Command
Payload
ICSPCLK
ICSPDAT
XXXXX
(from Programmer)
LSb MSb 0
ICSPDAT
(from Device)
x
MCLR
PIC16(L)F151X/152X
DS41442B-page 38 Advance Information 2010-2011 Microchip Technology Inc.
FIGURE 8-8: LVP ENTRY (POWERED)
FIGURE 8-9: LVP ENTRY (POWERING UP)
TCKLTCKH
33 clocks
012... 31
TDH
TDS
TENTH
LSb of Pattern MSb of Pattern
VDD
MCLR
ICSPCLK
ICSPDAT
TENTS
TCKH TCKL
33 Clocks
Note 1: Sequence matching can start with no edge on MCLR first.
0 1 2 ... 31
TDH
TDS
TENTH
LSb of Pattern MSb of Pattern
VDD
MCLR
ICSPCLK
ICSPDAT
2010-2011 Microchip Technology Inc. Advance Information DS41442B-page 39
PIC16(L)F151X/152X
APPENDIX A: REVISION HISTORY
Revision A (08/2010)
Original release of this document.
Revision B (09/2011)
Added PIC16(L)F1512/1513 devices; Added new
Figures 3-1 and 3-2; Updated Registers 3-1, 3-2 and 3-
3 to new format; Updated Register 3-3 to add 2 kW and
4 kW Flash memory; Added Notes to Examples 7-1 to
7-4; Updated Table 8-1; Other minor corrections.
PIC16(L)F151X/152X
DS41442B-page 40 Advance Information 2010-2011 Microchip Technology Inc.
NOTES:
QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV = ISO/TS 169492009: (2
2010-2011 Microchip Technology Inc. Advance Information DS41442B-page 41
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
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OTHERWISE, RELATED TO THE INFORMATION,
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Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
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FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
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Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, chipKIT,
chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,
FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,
Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,
MPLINK, mTouch, Omniscient Code Generation, PICC,
PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,
rfLAB, Select Mode, Total Endurance, TSHARC,
UniWinDriver, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
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SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
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© 2010-2011, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-61341-635-8
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
’8‘ MICROCHIP AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE
DS41442B-page 42 Advance Information 2010-2011 Microchip Technology Inc.
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