SM802109 Datasheet by Microchip Technology

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SM802109
ClockWorks PCI-e Quad 100MHz
Ultra-Low Jitter, HCSL
Frequency Synthesizer
ClockWorks is a trademark of Micrel, Inc
RotaryWave is a registered trademark of Multigig, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
September 2011 M9999-092911-B
hbwhelp@micrel.com or (408) 955-1690
ber of the ClockWorks
3.3V or 2.5V pow
and synthesizes four HCSL output cloc
SM802109 accepts a 25MHz crystal or
reference clock.
support documentation can be found on
Micrel’s web site at: www.micrel.com
General Description
The SM802109 is a mem family of
devices from Micrel and provides an extreme
timing solution for PCI-Express clock signals.
on a unique patented RotaryWave® archite
ly low-noise
It is based
cture that
provides very-low phase noise.
The device operates from a er supply
ks at 100MHz. The
LVCMOS
Data sheets and
Features
.
ock outputs at 100MHz
ge
00MHz
(1.875MHz to 20MHz): 105fs
Industrial temperature range (–40°C to +85°C)
Green, RoHS, and PFOS compliant
Available in 24-pin 4mm × 4mm QFN package
Applications
PCI-Express
Block Diagram
Generates four HCSL cl
perating ran 2.5V or 3.3V o
Typical phase jitter @ 1
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g Inf ion(1)
arki Shipping Temperature R Package
Orderin ormat
Part Number M ng ange
SM802109UMG 802109 Tube –40°C to +85°C 24-Pin QFN
SM802109UMGTR 802109 Tape and Reel –40°C to +85°C 24-Pin QFN
Note:
1. Devices are Green, RoHS, and PFOS compliant.
Pin Configuration
2
(
Pin Description
Pin Number Nam Pin
4-Pin QFN
Top View)
Pin e Type Pin Level Pin Function
16, 17 /Q0, Q0
1, Q1 O, (DIF) ck Outputs from Bank 1 100MHz
20, 21 /Q HCSL Differential Clo
23, 24
3, 4
/Q2, Q2
/Q3, Q3 O, (DIF) HCSL Differential Clock Outputs from Bank 2 100MHz
1 VDDO2 PWR Power Supply for Output Bank 2
2 VSSO2 PWR Power Supply Ground for Output Bank 2
5 PLL_BYPASS I, (SE) LVCMOS
PLL Bypass, Selects Output Source
0 = Normal PLL Operation
1 = Output from Input Reference Clock or Crystal
45K pulldown
6 XTAL_SEL I, (SE) LVCMOS
Selects PLL Input Reference Source
0 = REF_IN, 1 = XTAL, 45K pullup
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iption (Con
ber me Pin Typ Level Pin Function
Pin Descr tinued)
Pin Num Pin Na e Pin
7, 12, 15, 19 TEST Factory Test pins, Do not connect anything to these
pins.
8 D PWR pply VD Core Power Su
13, 14 VSS
osed Pa PWR pply Ground. The exposed pad must
e connected to the VSS ground plane.
(Exp d)
Core Power Su
b
18 PWR t Bank 1 VDDO1 Power Supply for Outpu
22 VSSO1 PWR Power Supply Ground for Output Bank 1
9 F_IN I, (SRE E) LVCMOS Reference Clock Input
10 XTAL_IN I, (SE) Crystal
Crystal Reference Input, no load caps needed (see
Figure 5).
11 XTAL_OUT (SE) rystal
Crystal Reference Output, no load caps needed (see
Figure 5).
O, C
Truth Table
PLL_BYPASS XTAL_SEL INPUT OUTPUT
0 PLL
1 XTAL/REF_IN
0 REF_IN
1 XTAL
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.....
o V
.........
Case Temperature ..................................................... 1
Storage Temperature (Ts) ......................... 65°C to +150°C
tage (VDD, VDDO1/2)............... +2.375V to +3.465V
–40°C to +85°C
Still-Air......................................................... 50°C/W
QFN (ψJB)
Junction-to-Board ....................................... 30°C/W
acteri (4)
O ±5
±5% or 2.5V ±5%
= 40°C
rameter ion Min. Typ. Max. Units
Absolute Maximum Ratings(1)
Supply Voltage (VDD, VDDO1/2) ............................ .....+4.6V Supply Vol
Input Voltage (V ) .............................. 0.50V t
IN
Lead Temperature (soldering, 20s)...................
DD + 0.5V
260°C
15°C QFN (θJA)
Operating Ratings(2)
Ambient Temperature (TA)..........................
Junction Thermal Resistance(3)
DC Electrical Char stics
VDD = VDD 1/2 = 3.3V ±5% or 2.5V %
VDD = 3.3V ±5%, VDDO1/2 = 3.3V
TA to +85°C.
Symbol Pa Condit
VDD, VDDO1 o .37 2.5 2.625 V
/2 2.5V Operating V ltage 2 5
VDD, VDDO1/2 3.3V Operating Voltage 3.135 3.3 3.465 V
IDD XTAL_SEL = 0
Outputs 50 to VSS 140 175 mA
REF_IN Supply current VDD + VDDO
IDD Supply current VDD +
XTAL VDDO
XTAL_SEL = 1
Outputs 50 to VSS 150 185 mA
HCSL D ha acteristics(4)
± ±
in Typ. Max. Units
C Electrical C r
V = V
DD DDO1/2 = 3.3V 5% or 2.5V 5%
VDD = 3.3V ±5%, VDDO1/2 = 3.3V ±5% or 2.5V ±5%
TA = 40°C to +85°C. RL = 50 to VSS
Symbol Parameter Condition M
VOH Output High Voltage 660 700 850 mV
VOL Output Low Voltage -150 0 27 mV
VCROSS Crossing Point Voltage 250 350 550 mV
Notes:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied
at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB.
4. The circuit is designed to meet the AC and DC specifications shown in the above table(s) after thermal equilibrium has been established.
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TAL_SEL) DC Electrical Characteristics(4)
D±5% A40°C to +85°C.
ymbo Condition Min. Ty Max. Units
LVCMOS (PLL_BYPASS, X
VD = 3.3V ±5%, or 2.5V , T =
S l Parameter p.
VIH o 2 VDD + 0.3 V
Input High V ltage
VIL o 0.3 0.8 V
Input Low V ltage
IIH Input High Current VDD = VIN = 3.465V 150
μA
IIL Input Low Current VDD = 3.465V, VIN = 0V 150
μA
REF_IN DC Electrical Characteristics(4)
VDD = 3.3V ±5%, or 2.5V ±
Symbol Pa ter Min. Ty Max. Units
5%, TA = 40°C to +85°C.
rame Condition p.
VIH Input High Voltage 1.1 VDD + 0.3 V
VIL Input Low Voltage 0.3 0.6 V
XTAL_SEL = VIL, VIN = 0V D 5
μA
to VD5
I
IN Input Current
VIH, VIN = VDD 20 µA
XTAL_SEL =
Crystal Characteristics
Parameter Condition Min. Typ. Max. Units
Mode of Oscillation 10pF to 12pF Load Fundamental, Parallel Resonant
Frequency 25 MHz
Equivalent Series Resistance (ESR) 50
Shunt Capacitor, C0 1 5 pF
Correlation Drive Level 10 100 µW
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tics(4, 5)
.3V ±5%, .3V ±5% or 2.5V ±5%
40 0 to VS
mbol Pa Condition Typ. Max. Units
AC El ical Charectr acteris
.5V ±5% VDD = VDDO1/2 = 3.3V ±5% or 2
VDD = 3 VDDO1/2 = 3
TA = °C to +85°C. RL = 5 S
Sy rameter Min.
FOUT uency 100 MHz Output Freq
FREF t Freque 25 MHz Reference Inpu ncy
TR/TF Output Rise/Fall Time 20% – 80% 150 300 450 ps LVPECL
ODC Output Duty Cycle 48 50 52 %
TSKEW utput Skew 45 ps Output-to-O Note 6
TLOCK PLL Lock Time 20 ms
Tjit() RMS Phase Jitter Integration Ran
(7)
100MHz
ge (1.875MHz – 20MHz)
105
250
fs
Integration Range (12kHz – 20MHz)
Spurious Noise Components 25MHz 95 dBc
Notes:
5. All phase noise measurements were taken with an Agilent 5052B phase noise system.
6. Defined as skew between outputs at the same supply voltage and with equal load conditions; measured at the output differential crossing points.
7. Measured using 25MHz crystal as the input reference source. If using an external reference input, use a low phase noise source. With an external
reference, the phase noise will follow the input source phase noise up to about 1MHz.
hbwhe\g_@micrel.com ation at: hbwhelg@mxcrel.com
Micrel, Inc. SM802109
September 2011 7 M9999-092911-B
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ormation
ting with a crystal input reference, do not
ut
as p ssible
plies
al load capacitance is built inside the die no
Selecting a
Family of
Precision Synthesizers application note for
details.
Contact Micrel’s HBW applications group if you need
assistance on selecting a suitable crystal fo our
application at: hbwhelp@micrel.com
Application Inf
Input Reference
When opera
apply a switching signal to REF_IN.
Crystal Layo
Keep the layers under the crystal as open
and do not place switching signals or noisy sup
under the crystal.
Cryst
o
so
external capacitance is needed. See the
Quartz crystal for the Clockworks Flex I
further
r y
.
ed with 50 to VSS. For
oad all outputs. If you want to AC-
couple or change the termination, contact Micrel’s
application group: hbwhelp@micrel.com
HCSL Outputs
HCSL outputs are to be terminat
best performance l
.
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Phase Noise Plots
Phase Noise Plot: 100MHz, 1.875MHz 20MHz 104fS
Phase Noise Plot: 100MHz, 12kHz 20MHz 242fS
one: Lxmm T 80W 20W TR Tr RMS PHASE NOISE/J ITTER PHASE NOISE PLOT / NOISE POWER PHASE NOISE MASK I r‘ r2 OFFSET FREQUENCY RMS JITTER =qAREA UNDER THE MASKED PHASE NOISE PLOT hbwhelg_@micrel,com
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Figure 1. Duty Cycle Timing Figure 2. All Outputs Rise/Fall Time
Figure 3. RMS Phase/Noise Jitter
VDDO OSCILLOSCOPE Q I) I 20 = 509 IQ J 500 VSS XTALilN I: 10pF TO 12pF PARALLE L CRYSTAL XTALioUT hbwhelg_@micrel,com
Micrel, Inc. SM802109
September 2011 10 M9999-092911-B
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Figure 4. HCSL Output Load and Test Circuit
Figure 5. Crystal Input Interface
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Micrel, Inc. SM802109
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Package Information
24-Pin Package Type
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408 08) 474-1000 WEB http://www.micrel.com) 944-0800 FAX +1 (4
Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This
information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry,
specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Micrel’s terms and conditions of sale for such products, Micrel assumes no liability
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© 2011 Micrel, Incorporated.

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