L6391 Datasheet by STMicroelectronics

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This is information on a product in full production.
September 2015 DocID17892 Rev 3 1/23
L6391
High voltage high and low-side driver
Datasheet - production data
Features
High voltage rail up to 600 V
dV/dt immunity ± 50 V/nsec in full temperature
range
Driver current capability:
290 mA source
430 mA sink
Switching times 75/35 nsec rise/fall with 1 nF
load
3.3 V, 5 V TTL/CMOS inputs with hysteresis
Integrated bootstrap diode
Comparator for fault protections
Smart shutdown function
Adjustable deadtime
Interlocking function
Compact and simplified layout
Bill of material reduction
Effective fault protection
Flexible, easy and fast design
Applications
Motor driver for home appliances, factory
automation, industrial drives and fans
HID ballasts, power supply units
Description
The L6391 is a high voltage device manufactured
with the BCD™ “OFF-LINE” technology. It is a
single-chip half-bridge gate driver for N-channel
power MOSFET or IGBT.
The high-side (floating) section is designed to
stand a voltage rail up to 600 V. The logic inputs
are CMOS/TTL compatible down to 3.3 V for easy
interfacing the microcontroller/DSP.
An integrated comparator is available for
protections against overcurrent, overtemperature,
etc.
www.st.com
Contents L6391
2/23 DocID17892 Rev 3
Contents
1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.1 AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.2 DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6 Waveform definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7 Smart shutdown function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
8 Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
9 Bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
CBOOT selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
10 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
SO-14 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
11 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DocID17892 Rev 3 3/23
L6391 Block diagram
23
1 Block diagram
Figure 1. Block diagram
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Pin connection L6391
4/23 DocID17892 Rev 3
2 Pin connection
Figure 2. Pin connection (top view)
Table 1. Pin description
Pin
number Pin name Type Function
1 LIN I Low-side driver logic input (active low)
2 SD/OD (1) I/O Shutdown logic input (active low)/open-drain
comparator output
3 HIN I High-side driver logic input (active high)
4 VCC P Lower section supply voltage
5 DT I Deadtime setting
6 NC Not connected
7 GND P Ground
8 CP- I Comparator negative input
9 CP+ I Comparator positive input
10 LVG(1)
1. The circuit guarantees less than 1 V on the LVG and HVG pins (at Isink = 10 mA), with VCC > 3 V. This
allows omitting the “bleeder” resistor connected between the gate and the source of the external MOSFET
normally used to hold the pin low; the gate driver assures low impedance also in SD condition.
O Low-side driver output
11 NC Not connected
12 OUT P High-side (floating) common voltage
13 HVG(1) O High-side driver output
14 BOOT P Bootstrapped supply voltage
LIN
HIN
LVG
HVG
DTLH DTHL
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
INTERLOCKING
INTERLOCKING
G
IN
EDGE
DEADTIME
INTERLOCKING
INTERLOCKING
G
I
G
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
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DocID17892 Rev 3 5/23
L6391 Truth table
23
3 Truth table
Table 2. Truth table
Input Output
SD LIN HIN LVG HVG
LX
(1)
1. X: don't care.
X(1) LL
HHL L L
HLHLL
HLLHL
HHHLH
Electrical data L6391
6/23 DocID17892 Rev 3
4 Electrical data
4.1 Absolute maximum ratings
4.2 Thermal data
Table 3. Absolute maximum ratings
Symbol Parameter
Value
Unit
Min. Max.
Vcc Supply voltage -0.3 21 V
Vout Output voltage Vboot - 21 Vboot + 0.3 V
Vboot Bootstrap voltage -0.3 620 V
Vhvg High-side gate output voltage Vout - 0.3 Vboot + 0.3 V
Vlvg Low-side gate output voltage -0.3 Vcc + 0.3 V
Vcp- Comparator negative input voltage -0.3 Vcc + 0.3 V
Vcp+ Comparator positive input voltage -0.3 Vcc + 0.3 V
Vi Logic input voltage -0.3 15 V
VOD Open-drain voltage -0.3 15 V
dvout / dt Allowed output slew rate 50 V/ns
Ptot Total power dissipation (TA = 25 °C) 800 mW
TJJunction temperature 150 °C
Tstg Storage temperature -50 150 °C
ESD Human body model 2 kV
Table 4. Thermal data
Symbol Parameter SO-14 Unit
R
th(JA)
Thermal resistance junction to ambient 120 °C/W
DocID17892 Rev 3 7/23
L6391 Electrical data
23
4.3 Recommended operating conditions
Table 5. Recommended operating conditions
Symbol Pin Parameter Test conditions Min. Max. Unit
Vcc 4 Supply voltage 12.5 20 V
VBO(1)
1. VBO = VBOOT - VOUT
.
14 - 12 Floating supply voltage 12.4 20 V
Vout 12 DC output voltage - 9(2)
2. LVG off. Vcc = 12.5 V. Logic is operational if VBOOT > 5 V.
580 V
VCP- 8Comparator negative
input voltage VCP+ [2.5 V] VCC(3)
3. At least one of the comparator's inputs must be lower than 2.5 V to guarantee proper operation.
V
VCP+ 9Comparator positive
input voltage VCP- [2.5 V] VCC(3) V
fsw Switching frequency HVG, LVG load CL = 1 nF 800 kHz
TJJunction temperature -40 125 °C
Electrical characteristics L6391
8/23 DocID17892 Rev 3
5 Electrical characteristics
5.1 AC operation
Table 6. AC operation electrical characteristics (VCC = 15 V; TJ = +25 °C)
Symbol Pin Parameter Test conditions Min. Typ. Max. Unit
ton
1 vs. 10
3 vs. 13
High/low-side driver turn-on
propagation delay Vout = 0 V
Vboot = Vcc
CL = 1 nF
Vi = 0 to 3.3 V
see Figure 3
50 125 200 ns
toff
High/low-side driver turn-off
propagation delay 50 125 200 ns
tsd 2 vs. 10,
13
Shutdown to high/low-side
driver propagation delay 50 125 200 ns
tisd
Comparator triggering to
high/low-side driver turn-off
propagation delay
Measured applying a voltage step from
0 V to 3.3 V to pin CP+; CP- = 0.5 V 200 250 ns
MT Delay matching, HS and LS
turn-on/off 30 ns
DT 5 Deadtime setting range(1)
RDT = 0 , CL = 1 nF 0.1 0.18 0.25 µs
RDT = 37 k, CL = 1 nF, CDT = 100 nF 0.48 0.6 0.72 µs
RDT = 136 k, CL = 1 nF, CDT = 100 nF 1.35 1.6 1.85 µs
RDT = 260 k, CL = 1 nF, CDT = 100 nF 2.6 3.0 3.4 µs
MDT Matching deadtime(2)
RDT = 0 , CL = 1 nF 80 ns
RDT = 37 k, CL = 1 nF, CDT = 100 nF 120 ns
RDT = 136 k, CL = 1 nF, CDT = 100 nF 250 ns
RDT = 260 k, CL = 1 nF, CDT = 100 nF 400 ns
tr10,13
Rise time CL = 1 nF 75 120 ns
tf Fall time CL = 1 nF 35 70 ns
1. See Figure 4.
2. MDT = | DTLH - DTHL | (see Figure 5 on page 12).
DocID17892 Rev 3 9/23
L6391 Electrical characteristics
23
Figure 3. Timing
Figure 4. Typical deadtime vs. DT resistor value
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0.5
1
1.5
2
2.5
3
3.5
0 50 100 150 200 250 300
Rdt (kOhm)
DT (us)
Approximated formula for
Rdt calculation (typ.):
Rdt[kΩ] = 92.2 · DT[µs] - 16.6
AM16763v1
Electrical characteristics L6391
10/23 DocID17892 Rev 3
5.2 DC operation
Table 7. DC operation electrical characteristics (VCC = 15 V; TJ = + 25 °C)
Symbol Pin Parameter Test conditions Min. Typ. Max. Unit
Vcc_hys
4
Vcc UV hysteresis 1.2 1.5 1.8 V
Vcc_thON Vcc UV turn-ON threshold 11.5 12 12.5 V
Vcc_thOFF Vcc UV turn-OFF threshold 10 10.5 11 V
I
qccu
Undervoltage quiescent supply
current
Vcc = 9.5 V
SD = 5 V; LIN = 5 V;
HIN = GND; RDT = 0 ;
CP+ = GND; CP- = 5 V
100 150 A
I
qcc
Quiescent current
V
cc
= 15 V
SD = 5 V; LIN = 5 V;
HIN = GND; RDT = 0 ;
CP+ = GND; CP- = 5 V
500 1000 A
Bootstrapped supply voltage section(1)
VBO_hys
14 - 12
VBO UV hysteresis 1.2 1.5 1.8 V
VBO_thON VBO UV turn-ON threshold 10.6 11.5 12.4 V
VBO_thOFF VBO UV turn-OFF threshold 9.1 10 10.9 V
I
QBOU
Undervoltage VBO quiescent
current
V
BO
= 9 V
SD = 5 V; LIN and
HIN = 5 V; RDT = 0 ;
CP+ = GND; CP- = 5 V
70 110 A
I
QBO
VBO quiescent current
V
BO
= 15 V
SD = 5 V; LIN and
HIN = 5 V; RDT = 0 ;
CP+ = GND; CP- = 5 V
200 240 A
ILK High voltage leakage current Vhvg = Vout = Vboot = 600 V 10 A
R
DS(on)
Bootstrap driver on resistance(2) LVG ON 120 W
Driving buffer section
I
so
10, 13
High/low-side source short-circuit
current V
IN
= V
ih
(t
p
< 10 s) 200 290 mA
I
si
High/low-side sink short-circuit
current V
IN
= V
il
(tp < 10 s) 250 430 mA
Logic inputs
V
il
1, 2, 3
Low level logic threshold 0.8 1.1 V
V
ih
High level logic threshold voltage 1.9 2.25 V
Vil_S
1, 3 Single input voltage LIN and HIN connected
together and floating 0.8 V
DocID17892 Rev 3 11/23
L6391 Electrical characteristics
23
I
HINh
3
HIN logic “1” input bias current HIN = 15 V 110 175 260 A
I
HINl
HIN logic “0” input bias current HIN = 0 V 1 A
ILINl 1
LIN logic “0” input bias current LIN = 0 V 3 6 20 A
ILINh LIN logic “1” input bias current LIN = 15 V 1 A
I
SDh
2
SD logic “1” input bias current SD = 15 V 10 40 100 A
I
SDl
SD logic “0” input bias current SD = 0 V 1 A
1. VBO = VBOOT - VOUT
.
2. RDS(on) is tested in the following way: RDS(on) = [(VCC - VBOOT1) - (VCC - VBOOT2)] / [I1(VCC,VBOOT1) - I2(VCC,VBOOT2)]
where I1 is pin 14 current when VBOOT = VBOOT1, I2 when VBOOT = VBOOT2.
Table 8. Sense comparator(1) (VCC = 15 V, TJ = +25 °C)
Symbol Pin Parameter Test conditions Min. Typ. Max. Unit
Vio 8, 9 Input offset voltage -15 15 mV
Iib 8, 9 Input bias current VCP+ = 1 V, VCP - = 0.5 V 1 A
V
ol
2Open-drain low level
output voltage
Iod = - 3 mA VCP+ = 1 V;
VCP- = 0.5 V; 0.5 V
t
d_comp
Comparator delay
Rpull = 100 k to 5 V on
SD/OD pin; VCP- = 0.5 V;
voltage step on CP+ = 0 to
3.3 V
90 130 ns
SR 2 Slew rate CL = 180 pF; Rpu = 5 k60 V/s
1. Comparator is disabled when Vcc is in UVLO condition.
Table 7. DC operation electrical characteristics (VCC = 15 V; TJ = + 25 °C) (continued)
Symbol Pin Parameter Test conditions Min. Typ. Max. Unit
Waveform definitions L6391
12/23 DocID17892 Rev 3
6 Waveform definitions
Figure 5. Deadtime and interlocking waveform definitions
LIN
HIN
LVG
HVG
LIN
HIN
LVG
HVG
LIN
HIN
LVG
HVG
LIN
HIN
LVG
HVG
DT
LH
DT
HL
DT
LH
DT
HL
DT
LH
DT
HL
DT
LH
DT
HL
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
INTERLOCKING
INTERLOCKING
G
IN
CONTROL SIGNAL EDGE
OVERLAPPED:
INTERLOCKING + DEADTIME
CONTROL SIGNAL EDGE
SYNCHRONOUS (*):
DEADTIME
CONTROL SIGNAL EDGE
NOT OVERLAPPED,
BUT INSIDE THE DEADTIME:
DEADTIME
CONTROL SIGNAL EDGE
NOT OVERLAPPED,
OUTSIDE THE DEADTIME:
DIRECT DRIVING
(*) HIN and LIN can be connected togheter and driven by just one control signal
INTERLOCKING
INTERLOCKING
G
I
G
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
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DocID17892 Rev 3 13/23
L6391 Smart shutdown function
23
7 Smart shutdown function
The L6391 device integrates a comparator committed to the fault sensing function. Both
comparator's inputs are available on pins 8 and 9. For example, applying a voltage
reference to CP- and connecting the CP+ to an external shunt resistor, a simple overcurrent
detection function can be implemented.
The output signal of the comparator is fed to an integrated MOSFET with the open-drain
output available on the pin 2, shared with the SD input. When the comparator triggers, the
device is set in shutdown state and both its outputs are set to low level leaving the half-
bridge in tristate.
Figure 6. Smart shutdown timing waveforms
SD/OD
FROM/TO
CONTROLLER
V
BIAS
CSD
RSD
SMART
SD
LOGIC
R
ON_OD
SHUTDOWN CIRCUIT
R
PD_SD
An approximation of the disable time is given by:
where:
HIN/LIN
HVG/LVG
open-drain gate
(internal)
CP+
CP-
PROTECTION
Fast shutdown :
the driver outputs are set in SD state immediately after the comparator
triggering even if the SD signal has not yet reached the lower input threshold
disable time
SD/OD
AM16755v1
Smart shutdown function L6391
14/23 DocID17892 Rev 3
In common overcurrent protection architectures, the comparator output is usually connected
to the SD input and an RC network is connected to this SD/OD line in order to provide
a monostable circuit, which implements a protection time following the fault condition.
Differently from the common fault detection systems, the L6391 smart shutdown
architecture allows immediate turn-off of the output gate driver in case of fault, by minimizing
the propagation delay between the fault detection event and the current output switch-off. In
fact the time delay between the fault and the output turn-off is no longer dependent on the
RC value of the external network connected to the SD/OD pin. In the smart shutdown
circuitry, the fault signal has a preferential path which directly switches off the outputs after
the comparator triggering. At the same time, the internal logic turns on the open-drain output
and holds it on until the SD voltage goes below the SD logic input lower threshold. When
such threshold is reached, the open-drain output is turned off, allowing the external pull-up
to recharge the capacitor. The driver outputs restart following the input pins as soon as the
voltage at the SD/OD pin reaches the higher threshold of the SD logic input. The smart
shutdown system gives the possibility to increase the time constant of the external RC
network (that determines the disable time after the fault event) up to very large values
without increasing the delay time of the protection.
Any external signal provided to the SD pin is not latched and can be used as control signal
in order to perform, for instance, PWM chopping through this pin. In fact when a PWM signal
is applied to the SD input and the logic inputs of the gate driver are stable, the outputs
switch from the low level to the state defined by the logic inputs and vice versa.
In some applications, it may be useful to latch the driver in the shutdown condition for an
arbitrary time, until the controller decides to reset it to normal operation. This may, for
example, be achieved by a circuit as the one shown in Figure 7. When the open-drain starts
pulling down the SD/OD pin, the external latch turns on and keeps the pin to GND,
preventing it from being pulled up again once the SD logic input lower threshold is reached
and the internal open-drain turns off. One pin of the controller is used to release the external
latch, and one to externally force a shutdown condition and also to read the status of the
SD/OD pin.
Figure 7. Protection latching circuit
In applications using only one L6391 for the protection of different legs (such as a single-
shunt inverter, for example), the resistor divider, shown in Figure 8, can be implemented.
This simple network allows the SD pins of the other devices to reach a voltage lower than
L6391 Vil, so that each device can get its low logic level regardless of part to part variations
of the thresholds.
SD_sense
SD_force
GND
VDD
μC
VDD
VCC
R1
9*R
R3
2*R
HVG
OUT
LVG
VBOOT
CP-
OPOUT
DT
CP+
L6391
SD/OD
GND
VCC
HIN
LIN
+
+
-
VCC
HV BUS
L639x
L639x
SD/OD SD/OD
C2 C3
C1
C2, C3: small noise filtering capacitors
C1: disable time setting capacitor
R2
R
V
BIAS
AM16756v1
DocID17892 Rev 3 15/23
L6391 Smart shutdown function
23
Figure 8. SD level shifting circuit
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Typical application diagram L6391
16/23 DocID17892 Rev 3
8 Typical application diagram
Figure 9. Application diagram
UV
DETECTION
LEVEL
SH I FTER
BOOTSTRAP DRIVER
S
V
CC
LVG
DRIV ER
HIN
LIN
HVG
DRIVER
HVG
OUT
LVG
BOOT
UV
DETECTION
GND
SD/OD
DT DEAD
TIM E
R
LOGIC
SHOOT
THR OUGH
PREVE NTI ON
FLOATI NG STRUCTURE
CO M PA RATO R
CP+
1
210
14
7
5
3
4
9
from LVG
VCC
5V
+
-
5V
CP -
8
12
13
H.V.
TO LOAD
Cboot
V
BIAS
V
CC
+
FROM CONTROLLER
FROM CONTROLLER
FROM / TO
CONTROLLER
V
BIAS
SM A RT
SD
AM02458v1
DocID17892 Rev 3 17/23
L6391 Bootstrap driver
23
9 Bootstrap driver
A bootstrap circuitry is needed to supply the high voltage section. This function is usually
accomplished by a high voltage fast recovery diode (Figure 10). In the L6391 device
a patented integrated structure replaces the external diode. It is realized by a high voltage
DMOS, driven synchronously with the low-side driver (LVG), with diode in series, as shown
in Figure 11. An internal charge pump (Figure 11) provides the DMOS driving voltage.
CBOOT selection and charging
To choose the proper C
BOOT
value the external MOS can be seen as an equivalent
capacitor. This capacitor C
EXT
is related to the MOS total gate charge:
Equation 1
The ratio between the capacitors C
EXT
and C
BOOT
is proportional to the cyclical voltage loss.
It has to be:
Equation 2
if Q
gate
is 30 nC and V
gate
is 10 V, C
EXT
is 3 nF. With C
BOOT
= 100 nF the drop is 300 mV.
If HVG has to be supplied for a long time, the C
BOOT
selection has also to take into account
the leakage and quiescent losses.
HVG steady-state consumption is lower than 240 A, so if HVG T
ON
is 5 ms, C
BOOT
has to
supply C
EXT
with
1.2 C. This charge on a 1 F capacitor means a voltage drop of 1.2 V.
The internal bootstrap driver gives a great advantage: the external fast recovery diode can
be avoided (it usually has great leakage current).
This structure can work only if V
OUT
is close to GND (or lower) and in the meanwhile the
LVG is on. The charging time (T
charge
) of the C
BOOT
is the time in which both conditions are
fulfilled and it has to be long enough to charge the capacitor.
The bootstrap driver introduces a voltage drop due to the DMOS R
DS(on)
(typical value:
120 ). At low frequency this drop can be neglected. Anyway, the rise of frequency has to
take into account.
The following equation is useful to compute the drop on the bootstrap DMOS:
Equation 3
where Q
gate
is the gate charge of the external power MOS, R
DS(on)
is the on resistance of
the bootstrap DMOS and T
charge
is the charging time of the bootstrap capacitor.
CEXT
Qgate
Vgate
--------------=
CBOOT>>>CEXT
Vdrop Ich earg RDS on Vdrop
Qgate
Tch earg
------------------ RDS on
==
Bootstrap driver L6391
18/23 DocID17892 Rev 3
For example: using a power MOS with a total gate charge of 30 nC the drop on the
bootstrap DMOS is about 1 V, if the T
charge
is 5 s. In fact:
Equation 4
V
drop
has to be taken into account when the voltage drop on C
BOOT
is calculated: if this drop
is too high, or the circuit topology doesn’t allow a sufficient charging time, an external diode
can be used.
Figure 10. Bootstrap driver with high voltage fast recovery diode
Figure 11. Bootstrap driver with internal charge pump
Vdrop
30nC
5s
---------------1200.7V=
TO LOAD
H.V.
HVG
LVG
C
BOOT
DBOOT
BOOT
VCC
OUT
HVG
LVG
TO LOAD
H.V.
C
BOOT
V
CC
OUT
BOOT
hx45‘ > A1 EUZHZHZLJZHZLJZU SEAT‘NG PLANE 025 mm GAGE PLANE \
DocID17892 Rev 3 19/23
L6391 Package information
23
10 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
SO-14 package information
Figure 12. SO-14 package outline
0016019_E
Package information L6391
20/23 DocID17892 Rev 3
Figure 13. SO-14 footprint
Table 9. SO-14 package mechanical data
Symbol
Dimensions (mm )
Min. Typ. Max.
A 1.35 1.75
A1 0.10 0.25
A2 1.10 1.65
B 0.33 0.51
C 0.19 0.25
D 8.55 8.75
E 3.80 4.00
e 1.27
H 5.80 6.20
h 0.25 0.50
L 0.40 1.27
K 0 8
e0.40
ddd 0.10




".
DocID17892 Rev 3 21/23
L6391 Order codes
23
11 Order codes
Table 10. Order codes
Order code Package Packaging
L6391D SO-14 Tube
L6391DTR SO-14 Tape and reel
Revision history L6391
22/23 DocID17892 Rev 3
12 Revision history
Table 11. Document revision history
Date Revision Changes
14-Dec-2010 1 First release.
10-May-2013 2
Added HBM parameter to Table 3.
Added IQBO max. value to Tab le 7.
Changed Vil and Vih min. and max. values in Table 7.
Added note to Table 8.
Updated Section 7 and Section .
Changed Figure 6 and added Figure 7 and Figure 8.
Updated SO-14 mechanical data.
Updated DIP-14 mechanical data.
11-Sep-2015 3
Removed DIP-14 package from the entire document.
Updated Table 4 on page 6 (updated R
th(JA)
value).
Moved Table 10 on page 21 (moved from page 1 to page 21, updated
titles.
Updated Table 3 on page 6 (updated ESD parameter and value).
Updated note 1.and 2. below Table 7 on page 10 (minor
modifications, replaced VCBOOTx by VBOOTx ).
Added Figure 13 on page 20.
Updated cross-references throughout document.
Minor modifications throughout document.
DocID17892 Rev 3 23/23
L6391
23
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