AOZ1031AI Datasheet by Alpha & Omega Semiconductor Inc.

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ALPPLA & OMEGA SEMICONDUCTOR W Green Prod-m iii—41 if P
Rev. 1.6 March 2010 www.aosmd.com Page 1 of 15
AOZ1031AI
EZBuck™ 3A Synchronous Buck Regulator
General Description
The AOZ1031A is a high efficiency, easy to use, 3A
synchronous buck regulator. The AOZ1031A works from
4.5V to 18V input voltage range, and provides up to 3A of
continuous output current with an output voltage adjust-
able down to 0.8V.
The AOZ1031A comes in a SO-8 package and is rated
over a -40°C to +85°C operating ambient temperature
range.
Features
z4.5V to 18V operating input voltage range
zSynchronous Buck: 80mΩ internal high-side switch
and 30mΩ internal low-side switch with integrated
schottky diode
zHigh efficiency: up to 95%
zInternal soft start
zOutput voltage adjustable to 0.8V
z3A continuous output current
zFixed 600kHz PWM operation
zPulse skipping at light load for high efficiency over
entire load range
zCycle-by-cycle current limit
zPre-bias start-up
zShort-circuit protection
zThermal shutdown
zSO-8 package
Applications
zPoint of load DC/DC converters
zLCD TV
zSet top boxes
zDVD/Blu-ray players/recorders
zCable modems
zPCIe graphics cards
zTelecom/Networking/Datacom equipment
Typical Application
Figure 1. 3.3V 3A Synchronous Buck Regulator
LX
VIN
VIN
VOUT
FB
PGND
EN
COMP
AGND
C2, C3
22µF
R1
R2
C
C
R
C
C1
22µF
L1 4.7µH
AOZ1031
ALPIlAlzGMEG/l MM/rmwmc ma 6' Green
Rev. 1.6 March 2010 www.aosmd.com Page 2 of 15
AOZ1031AI
Ordering Information
AOS Green Products use reduced levels of Halogens, and are also RoHS compliant.
Please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information.
Pin Configuration
Pin Description
Part Number Ambient Temperature Range Package Environmental
AOZ1031AI -40°C to +85°C SO-8 RoHS Compliant
Green Product
Pin Number Pin Name Pin Function
1 PGND Power ground. PGND needs to be electrically connected to AGND.
2 VIN Supply voltage input. When VIN rises above the UVLO threshold and EN is logic high, the
device starts up.
3 AGND Analog ground. AGND is the reference point for controller section. AGND needs to be
electrically connected to PGND.
4 FB Feedback input. The FB pin is used to set the output voltage via a resistive voltage divider
between the output and AGND.
5 COMP External loop compensation pin. Connect a RC network between COMP and AGND to
compensate the control loop.
6 EN Enable pin. Pull EN to logic high to enable the device. Pull EN to logic low to disable the
device. Do not leave it open.
7, 8 LX Switching node. PWM output connection to inductor.
LX
LX
EN
COMP
1
2
3
4
PGND
VIN
AGND
FB
SO-8
(Top View)
8
7
6
5
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AOZ1031AI
Rev. 1.6 March 2010 www.aosmd.com Page 3 of 15
Block Diagram
Absolute Maximum Ratings
Exceeding the Absolute Maximum ratings may damage the
device.
Note:
1. Devices are inherently ESD sensitive, handling precautions are
required. Human body model rating: 1.5kΩ in series with 100pF.
Recommend Operating Ratings
The device is not guaranteed to operate beyond the Maximum
Operating Ratings.
600kHz
AGND PGND
VIN
EN
FB
COMP
LX
OTP
Internal
+5V
ILimit
PWM
Control
Logic
5V LDO
Regulator
UVLO
& POR
Softstart
Reference
& Bias
0.8V
Q1
Q2
PWM
Comp
Level
Shifter
+
FET
Driver
ISen
EAmp
0.2V
+
+
+
+
+
Frequency
Foldback
Comparator
+
Over-Voltage
Protection
Comparator
0.96V
Parameter Rating
Supply Voltage (VIN)20V
LX to AGND -0.7V to VIN+0.3V
LX to AGND -3V for 20 nS
EN to AGND -0.3V to VIN+0.3V
FB to AGND -0.3V to 6V
COMP to AGND -0.3V to 6V
PGND to AGND -0.3V to +0.3V
Junction Temperature (TJ) +150°C
Storage Temperature (TS) -65°C to +150°C
ESD Rating(1) 2.0kV
Parameter Rating
Supply Voltage (VIN) 4.5V to 18V
Output Voltage Range 0.8V to VIN
Ambient Temperature (TA) -40°C to +85°C
Package Thermal Resistance
SO-8 (ΘJA)
SO-8 (ΘJC) 87°C/W
30°C/W
Package Power Dissipation (PD) @
25°C Ambient
SO-8 1.15W
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AOZ1031AI
Rev. 1.6 March 2010 www.aosmd.com Page 4 of 15
Electrical Characteristics
TA = 25°C, VIN = VEN = 12V, VOUT = 3.3V unless otherwise specified.(3)
Notes:
3. The device is not guaranteed to operate beyond the Maximum Operating ratings.
Symbol Parameter Conditions Min. Typ. Max. Units
VIN Supply Voltage 4.5 18 V
VUVLO Input under-voltage lockout
threshold VIN rising
VIN falling 4.1
3.7 V
V
IIN Supply current (Quiescent) IOUT = 0, VFB = 1.2V, VEN >1.2V 1.6 2.5 mA
IOFF Shutdown supply current VEN = 0V 110μA
VFB Feedback Voltage TA = 25°C 0.788 0.8 0.812 V
Load regulation 0.5 %
Line regulation 1%
IFB Feedback voltage input current 200 nA
VEN EN input threshold Off threshold
On threshold 20.6 V
V
VHYS EN input hysteresis 100 mV
MODULATOR
fOFrequency 500 600 700 kHz
DMAX Maximum Duty Cycle 100 %
DMIN Minimum Duty Cycle 9%
Error amplifier voltage gain 500 V / V
Error amplifier transconductance 200 μA / V
PROTECTION
ILIM Current Limit 4.0 5.0 A
VOVP Over-Voltage Protection Off threhsold
On threshold 960
860 mV
mV
Over-temperature shutdown limit TJ rising
TJ falling 150
100 °C
°C
tSS Soft Start Interval 2.2 ms
OUTPUT STAGE
High-side switch on-resistance VIN = 12V
VIN = 5V 80
130 100
180 mΩ
mΩ
Low-side switch on-resistance VIN = 12V
VIN = 5V 30
56 36
70 mΩ
mΩ
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AOZ1031AI
Rev. 1.6 March 2010 www.aosmd.com Page 5 of 15
Typical Performance Characteristics
Circuit of Figure 1. TA = 25°C, VIN = VEN = 12V, VOUT = 3.3V unless otherwise specified.
Light Load (DCM) Operation
1us/div
Start Up to Full Load
1ms/div
50% to 100% Load Transient
100us/div
Full Load (CCM) Operation
1us/div
Short Circuit Protection
4ms/div
Short Circuit Recovery
10ms/div
ALPIlAlzGMEG/l MM/rmwmc ma
AOZ1031AI
Rev. 1.6 March 2010 www.aosmd.com Page 6 of 15
Efficiency
Thermal Derating
AOZ1031AI Efficiency
100
90
80
70
60
50
40
30
20
10
0
0 0.5 1.0 1.5 2.0 2.5 3.0
IOUT (A)
0 0.5 1.0 1.5 2.0 2.5 3.0
IOUT (A)
Efficiency (%)
100
90
80
70
60
50
40
30
20
10
0
Efficiency (%)
Efficiency (VIN = 12V) vs. Load Current Efficiency (VIN = 5V) vs. Load Current
VO = 1.2V
VO = 1.8V
VO = 3.3V
VO = 5V
VO = 1.2V
VO = 1.8V
VO = 3.3V
Derating Curves at 5V/6V Input
Ambient Temperature (TA)
Output Current (IO)
Derating Curves at 12V Input
1.2V, 1.8V Output
3.3V Output
Thermal de-rating curves for SO-8 package part under typical input and output condition based on the evaluation board.
25°C ambient temperature and natural convection (air speed < 50LFM) unless otherwise specified.
5
4
3
2
1
0
25 35 45 55 65 75 85
Ambient Temperature (TA)
Output Current (IO)
1.2V, 1.8V, 3.3V, 5.0V Output
5
4
3
2
1
0
25 35 45 55 65 75 85
ALPHA a. OMEGA SEMICOND uc TOR
AOZ1031AI
Rev. 1.6 March 2010 www.aosmd.com Page 7 of 15
Detailed Description
The AOZ1031A is a current-mode step down regulator
with integrated high-side PMOS switch and a low-side
NMOS switch. It operates from a 4.5V to 18V input volt-
age range and supplies up to 3A of load current. The
duty cycle can be adjusted from 6% to 100% allowing a
wide range of output voltage. Features include enable
control, Power-On Reset, input under voltage lockout,
output over voltage protection, active high power good
state, fixed internal soft-start and thermal shut down.
The AOZ1031A is available in SO-8 package.
Enable and Soft Start
The AOZ1031A has internal soft start feature to limit
in-rush current and ensure the output voltage ramps up
smoothly to regulation voltage. A soft start process
begins when the input voltage rises to 4.1V and voltage
on EN pin is HIGH. In soft start process, the output volt-
age is ramped to regulation voltage in typically 2.2ms.
The 2.2ms soft start time is set internally.
The EN pin of the AOZ1031A is active high. Connect the
EN pin to VIN if enable function is not used. Pull it to
ground will disable the AOZ1031A. Do not leave it open.
The voltage on EN pin must be above 2V to enable the
AOZ1031A. When voltage on EN pin falls below 0.6V, the
AOZ1031A is disabled. If an application circuit requires
the AOZ1031A to be disabled, an open drain or open col-
lector circuit should be used to interface to EN pin.
Steady-State Operation
Under steady-state conditions, the converter operates
in fixed frequency and Continuous-Conduction Mode
(CCM).
The AOZ1031A integrates an internal P-MOSFET as the
high-side switch. Inductor current is sensed by amplifying
the voltage drop across the drain to source of the high
side power MOSFET. Output voltage is divided down by
the external voltage divider at the FB pin. The difference
of the FB pin voltage and reference is amplified by the
internal transconductance error amplifier. The error volt-
age, which shows on the COMP pin, is compared against
the current signal, which is sum of inductor current signal
and ramp compensation signal, at PWM comparator
input. If the current signal is less than the error voltage,
the internal high-side switch is on. The inductor current
flows from the input through the inductor to the output.
When the current signal exceeds the error voltage, the
high-side switch is off. The inductor current is freewheel-
ing through the internal low-side N-MOSFET switch to
output. The internal adaptive FET driver guarantees no
turn on overlap of both high-side and
low-side switch.
Comparing with regulators using freewheeling Schottky
diodes, the AOZ1031A uses freewheeling NMOSFET to
realize synchronous rectification. It greatly improves the
converter efficiency and reduces power loss in the
low-side switch.
The AOZ1031A will enter the discontinuous conduction
mode at light load. Several pulses may be skipped in
between switching cycles at very light load, it further
improving light load efficiency.
The AOZ1031A uses a P-Channel MOSFET as the
high-side switch. It saves the bootstrap capacitor nor-
mally seen in a circuit which is using an NMOS switch. It
allows 100% turn-on of the high-side switch to achieve
linear regulation mode of operation. The minimum volt-
age drop from VIN to VO is the load current times DC
resistance of MOSFET plus DC resistance of buck induc-
tor. It can be calculated by equation below:
where;
VO_MAX is the maximum output voltage;,
VIN is the input voltage from 4.5V to 18V,
IO is the output current from 0A to 3A, and
RDS(ON) is the on resistance of internal MOSFET. The value is
between 97mΩ and 200mΩ depending on input voltage and
junction temperature.
Switching Frequency
The AOZ1031A switching frequency is fixed and set by
an internal oscillator. The practical switching frequency
could range from 500kHz to 700kHz due to device varia-
tion.
Output Voltage Programming
Output voltage can be set by feeding back the output to
the FB pin by using a resistor divider network. In the
application circuit shown in Figure 1. The resistor divider
network includes R1 and R2. Usually, a design is started
by picking a fixed R2 value and calculating the required
R1 with equation below.
Some standard value of R1, R2 and most used output
voltage values are listed in Table 1 on the next page.
VO_MAX VIN IORDS ON()
×=
VO0.8 1 R1
R2
-------
+
⎝⎠
⎜⎟
⎛⎞
×=
ALPHA I: OMEGA SEMICONDUCTOR
AOZ1031AI
Rev. 1.6 March 2010 www.aosmd.com Page 8 of 15
Table 1.
The combination of R1 and R2 should be large enough to
avoid drawing excessive current from the output, which
will cause power loss.
Since the switch duty cycle can be as high as 100%, the
maximum output voltage can be set as high as the input
voltage minus the voltage drop on upper PMOS and
inductor.
Protection Features
The AOZ1031A has multiple protection features to pre-
vent system circuit damage under abnormal conditions.
Over Current Protection (OCP)
The sensed inductor current signal is also used for over
current protection. Since the AOZ1031A employs peak
current mode control, the COMP pin voltage is propor-
tional to the peak inductor current. The COMP pin volt-
age is limited to be between 0.4V and 2.5V internally.
The peak inductor current is automatically limited cycle
by cycle.
When the output is shorted to ground under fault condi-
tions, the inductor current decays very slow during a
switching cycle because of Vo=0V. To prevent cata-
strophic failure, AOZ1031A detects the duration the over-
current condition occurs. If the over-current condition
occurs for certain period, AOZ1013A totally turns off for a
period of time, then restarts. If the fault is still there, then
the chip will be off again. The converter will initiate a soft
start once the over-current condition disappears.
Power-On Reset (POR)
A power-on reset circuit monitors the input voltage. When
the input voltage exceeds 4.1V, the converter starts oper-
ation. When input voltage falls below 3.7V, the converter
will be shut down.
Thermal Protection
An internal temperature sensor monitors the junction
temperature. It shuts down the internal control circuit and
high side PMOS if the junction temperature exceeds
150°C. The regulator will restart automatically under the
control of soft-start circuit when the junction temperature
decreases to 100°C.
Application Information
The basic AOZ1031A application circuit is show in
Figure 1. Component selection is explained below.
Input Capacitor
The input capacitor must be connected to the VIN pin and
PGND pin of AOZ1031A to maintain steady input voltage
and filter out the pulsing input current. The voltage rating
of input capacitor must be greater than maximum input
voltage plus ripple voltage.
The input ripple voltage can be approximated by equa-
tion below:
Since the input current is discontinuous in a buck con-
verter, the current stress on the input capacitor is another
concern when selecting the capacitor. For a buck circuit,
the RMS value of input capacitor current can be calcu-
lated by:
if we let m equal the conversion ratio:
The relation between the input capacitor RMS current
and voltage conversion ratio is calculated and shown in
Figure 2 on the next page. It can be seen that when VO is
half of VIN, CIN is under the worst current stress. The
worst current stress on CIN is 0.5 x IO.
Vo (V) R1 (kΩ)R2 (kΩ)
0.8 1.0 open
1.2 4.99 10
1.5 10 11.5
1.8 12.7 10.2
2.5 21.5 10
3.3 31.1 10
5.0 52.3 10
ΔVIN
IO
fC
IN
×
----------------- 1VO
VIN
---------
⎝⎠
⎜⎟
⎛⎞
VO
VIN
---------
××=
ICIN_RMS IO
VO
VIN
---------1VO
VIN
---------
⎝⎠
⎜⎟
⎛⎞
×=
VO
VIN
---------m=
ALPHA a. OMEGA JEMICOND Uc TOR
AOZ1031AI
Rev. 1.6 March 2010 www.aosmd.com Page 9 of 15
Figure 2. ICIN vs. Voltage Conversion Ratio
For reliable operation and best performance, the input
capacitors must have current rating higher than ICIN_RMS
at worst operating conditions. Ceramic capacitors are
preferred for input capacitors because of their low ESR
and high current rating. Depending on the application cir-
cuits, other low ESR tantalum capacitor may also be
used. When selecting ceramic capacitors, X5R or X7R
type dielectric ceramic capacitors should be used for
their better temperature and voltage characteristics. Note
that the ripple current rating from capacitor manufactures
are based on certain amount of life time. Further
de-rating may be necessary in practical design.
Inductor
The inductor is used to supply constant current to output
when it is driven by a switching voltage. For given input
and output voltage, inductance and switching frequency
together decide the inductor ripple current, which is:
The peak inductor current is:
High inductance gives low inductor ripple current but
requires larger size inductor to avoid saturation. Low rip-
ple current reduces inductor core losses. It also reduces
RMS current through inductor and switches, which
results in less conduction loss. Usually, peak to peak rip-
ple current on inductor is designed to be 20%
to 30% of output current.
When selecting the inductor, make sure it is able to han-
dle the peak current without saturation even at the high-
est operating temperature.
The inductor takes the highest current in a buck circuit.
The conduction loss on inductor need to be checked for
thermal and efficiency requirements.
Surface mount inductors in different shape and styles are
available from Coilcraft, Elytone and Murata. Shielded
inductors are small and radiate less EMI noise. But they
cost more than unshielded inductors. The choice
depends on EMI requirement, price and size.
Output Capacitor
The output capacitor is selected based on the DC output
voltage rating, output ripple voltage specification and rip-
ple current rating.
The selected output capacitor must have a higher rated
voltage specification than the maximum desired output
voltage including ripple. De-rating needs to be consid-
ered for long term reliability.
Output ripple voltage specification is another important
factor for selecting the output capacitor. In a buck con-
verter circuit, output ripple voltage is determined by
inductor value, switching frequency, output capacitor
value and ESR. It can be calculated by the equation
below:
where;
CO is output capacitor value, and
ESRCO is the Equivalent Series Resistor of output capacitor.
When low ESR ceramic capacitor is used as output
capacitor, the impedance of the capacitor at the switching
frequency dominates. Output ripple is mainly caused by
capacitor value and inductor ripple current. The output
ripple voltage calculation can be simplified to:
If the impedance of ESR at switching frequency domi-
nates, the output ripple voltage is mainly decided by
capacitor ESR and inductor ripple current. The output rip-
ple voltage calculation can be further simplified to:
For lower output ripple voltage across the entire operat-
ing temperature range, X5R or X7R dielectric type of
ceramic, or other low ESR tantalum are recommended to
be used as output capacitors.
0
0.1
0.2
0.3
0.4
0.5
0 0.5 1
m
I
CIN_RMS
(m)
I
O
ΔIL
VO
fL×
-----------1VO
VIN
---------
⎝⎠
⎜⎟
⎛⎞
×=
ILpeak IO
ΔIL
2
--------
+=
ΔVOΔILESRCO 1
8fC
O
××
-------------------------
+
⎝⎠
⎛⎞
×=
ΔVOΔIL1
8fC
O
××
-------------------------
×=
ΔVOΔILESRCO
×=
ALPHA a. OMEGA SEMICOND uc TOR
AOZ1031AI
Rev. 1.6 March 2010 www.aosmd.com Page 10 of 15
In a buck converter, output capacitor current is continu-
ous. The RMS current of output capacitor is decided by
the peak to peak inductor ripple current. It can be calcu-
lated by:
Usually, the ripple current rating of the output capacitor is
a smaller issue because of the low current stress. When
the buck inductor is selected to be very small and induc-
tor ripple current is high, output capacitor could be over-
stressed.
Loop Compensation
The AOZ1031A employs peak current mode control for
easy use and fast transient response. Peak current mode
control eliminates the double pole effect of the output
L&C filter. It greatly simplifies the compensation loop
design.
With peak current mode control, the buck power stage
can be simplified to be a one-pole and one-zero system
in frequency domain. The pole is dominant pole can be
calculated by:
The zero is a ESR zero due to output capacitor and its
ESR. It is can be calculated by:
where;
CO is the output filter capacitor,
RL is load resistor value, and
ESRCO is the equivalent series resistance of output capacitor.
The compensation design is actually to shape the con-
verter control loop transfer function to get desired gain
and phase. Several different types of compensation net-
work can be used for the AOZ1031A. For most cases, a
series capacitor and resistor network connected to the
COMP pin sets the pole-zero and is adequate for a stable
high-bandwidth control loop.
In the AOZ1031A, FB pin and COMP pin are the inverting
input and the output of internal error amplifier. A series R
and C compensation network connected to COMP pro-
vides one pole and one zero. The pole is:
where;
GEA is the error amplifier transconductance, which is
200 x 10-6 A/V,
GVEA is the error amplifier voltage gain, which is 500 V/V, and
C2 is compensation capacitor in Figure 1.
The zero given by the external compensation network,
capacitor C2 and resistor R3, is located at:
To design the compensation circuit, a target crossover
frequency fC for close loop must be selected. The system
crossover frequency is where control loop has unity gain.
The crossover is the also called the converter bandwidth.
Generally a higher bandwidth means faster response to
load transient. However, the bandwidth should not be too
high because of system stability concern. When design-
ing the compensation loop, converter stability under all
line and load condition must be considered.
Usually, it is recommended to set the bandwidth to be
equal or less than 1/10 of switching frequency. The
AOZ1031A operates at a frequency range from 500kHz
to 700kHz. It is recommended to choose a crossover fre-
quency equal or less than 40kHz.
The strategy for choosing RC and CC is to set the cross
over frequency with RC and set the compensator zero
with CC. Using selected crossover frequency, fC, to calcu-
late RC:
where;
fC is desired crossover frequency. For best performance, fC is
set to be about 1/10 of switching frequency,
VFB is 0.8V,
GEA is the error amplifier transconductance, which is
200 x 10-6 A/V, and
GCS is the current sense circuit transconductance, which is 6.68
A/V.
The compensation capacitor CC and resistor RC together
make a zero. This zero is put somewhere close to the
dominate pole fP1 but lower than 1/5 of selected cross-
over frequency. CC can is selected by:
ICO_RMS
ΔIL
12
----------
=
fP11
2πCORL
××
-----------------------------------
=
fZ11
2πCOESRCO
××
------------------------------------------------
=
fP2
GEA
2πCCGVEA
××
-------------------------------------------
=
fZ21
2πCCRC
××
-----------------------------------
=
fC40kHz=
RCfC
VO
VFB
---------- 2πC2
×
GEA GCS
×
------------------------------
××=
CC1.5
2πRCfP1
××
-----------------------------------
=
ALPHA a. OMEGA SEMICOND uc TOR www.acsmd.com
AOZ1031AI
Rev. 1.6 March 2010 www.aosmd.com Page 11 of 15
Equation above can also be simplified to:
An easy-to-use application software which helps to
design and simulate the compensation loop can be found
at www.aosmd.com.
Thermal Management and Layout
Consideration
In the AOZ1031A buck regulator circuit, high pulsing cur-
rent flows through two circuit loops. The first loop starts
from the input capacitors, to the VIN pin, to the LX pins,
to the filter inductor, to the output capacitor and load, and
then return to the input capacitor through ground. Current
flows in the first loop when the high side switch is on. The
second loop starts from inductor, to the output capacitors
and load, to the low side NMOSFET. Current flows in the
second loop when the low side NMOSFET is on.
In PCB layout, minimizing the two loops area reduces the
noise of this circuit and improves efficiency. A ground
plane is strongly recommended to connect input capaci-
tor, output capacitor, and PGND pin of the AOZ1031A.
In the AOZ1031A buck regulator circuit, the major power
dissipating components are the AOZ1031A and the out-
put inductor. The total power dissipation of converter cir-
cuit can be measured by input power minus output
power.
The power dissipation of inductor can be approximately
calculated by output current and DCR of inductor.
The actual junction temperature can be calculated with
power dissipation in the AOZ1031A and thermal imped-
ance from junction to ambient.
The maximum junction temperature of AOZ1031A is
150°C, which limits the maximum load current capability.
Please see the thermal de-rating curves for maximum
load current of the AOZ1031A under different ambient
temperature.
The thermal performance of the AOZ1031A is strongly
affected by the PCB layout. Extra care should be taken
by users during design process to ensure that the IC will
operate under the recommended environmental condi-
tions.
The AOZ1031A is standard SO-8 package. Several lay-
out tips are listed below for the best electric and thermal
performance. Figure 3 on the next page illustrates a PCB
layout example of AOZ1031A.
1. The LX pins are connected to internal PFET and
NFET drains. They are low resistance thermal con-
duction path and most noisy switching node. Con-
nected a large copper plane to LX pin to help thermal
dissipation.
2. Do not use thermal relief connection to the VIN and
the PGND pin. Pour a maximized copper area to the
PGND pin and the VIN pin to help thermal dissipa-
tion.
3. Input capacitor should be connected to the VIN pin
and the PGND pin as close as possible.
4. A ground plane is preferred. If a ground plane is not
used, separate PGND from AGND and connect them
only at one point to avoid the PGND pin noise cou-
pling to the AGND pin.
5. Make the current trace from LX pins to L to Co to the
PGND as short as possible.
6. Pour copper plane on all unused board area and
connect it to stable DC nodes, like VIN, GND or
VOUT.
7. Keep sensitive signal trace far away form the LX
pins.
CC
CORL
×
RC
---------------------
=
Ptotal_loss VIN IIN VOIO
××=
Pinductor_loss IO2Rinductor 1.1××=
Tjunction Ptotal_loss Pinductor_loss
()Θ
JA
×=
AREA 4: OMEGA :EMICOND Uc TOR
AOZ1031AI
Rev. 1.6 March 2010 www.aosmd.com Page 12 of 15
Figure 3. AOZ1031A (SO-8) PCB layout
W SEMICONDUCTOR
Rev. 1.6 March 2010 www.aosmd.com Page 13 of 15
AOZ1031AI
Package Dimensions, SO-8L
Notes:
1. All dimensions are in millimeters.
2. Dimensions are inclusive of plating
3. Package body sizes exclude mold flash and gate burrs. Mold flash at the non-lead sides should be less than 6 mils.
4. Dimension L is measured in gauge plane.
5. Controlling dimension is millimeter, converted inch dimensions are not necessarily exact.
Symbols
A
A1
A2
b
c
D
E1
e
E
h
L
θ
Dimensions in millimeters
Min.
1.35
0.10
1.25
0.31
0.17
4.80
3.80
5.80
0.25
0.40
0°
D
C
L
h x 45°
7° (4x)
b
2.20
5.74
0.80
Unit: mm
1.27
A1
A2 A
0.1
θ
Gauge Plane Seating Plane
0.25
e
8
1
E1E
Nom.
1.65
1.50
4.90
3.90
1.27 BSC
6.00
Max.
1.75
0.25
1.65
0.51
0.25
5.00
4.00
6.20
0.50
1.27
8°
Symbols
A
A1
A2
b
c
D
E1
e
E
h
L
θ
Dimensions in inches
Min.
0.053
0.004
0.049
0.012
0.007
0.189
0.150
0.228
0.010
0.016
0°
Nom.
0.065
0.059
0.193
0.154
0.050 BSC
0.236
Max.
0.069
0.010
0.065
0.020
0.010
0.197
0.157
0.244
0.020
0.050
8°
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Rev. 1.6 March 2010 www.aosmd.com Page 14 of 15
AOZ1031AI
Tape and Reel Dimensions
SO-8 Carrier Tape
SO-8 Reel
SO-8 Tape
Leader/Trailer
& Orientation
Tape Size
12mm
Reel Size
ø330
M
ø330.00
±0.50
Package
SO-8
(12mm)
A0
6.40
±0.10
B0
5.20
±0.10
K0
2.10
±0.10
D0
1.60
±0.10
D1
1.50
±0.10
E
12.00
±0.10
E1
1.75
±0.10
E2
5.50
±0.10
P0
8.00
±0.10
P1
4.00
±0.10
P2
2.00
±0.10
T
0.25
±0.10
N
ø97.00
±0.10
K0
Unit: mm
B0
G
M
W1
S
K
H
N
W
V
R
Trailer Tape
300mm min. or
75 empty pockets
Components Tape
Orientation in Pocket
Leader Tape
500mm min. or
125 empty pockets
A0
P1
P2
See Note 5
See Note 3
See Note 3
Feeding Direction
P0
E2
E1
E
D0
T
D1
W
13.00
±0.30
W1
17.40
±1.00
H
ø13.00
+0.50/-0.20
K
10.60
S
2.00
±0.50
G
R
V
ALPHA a. OMEGA JEMICOND Uc TOR Hflflfl i Z1031A| EAXWLI O LIUJU
Rev. 1.6 March 2010 www.aosmd.com Page 15 of 15
AOZ1031AI
AOZ1031 Package Marking
Z1031AI
FAY Part Number Code
Assembly Lot Code
Year & Week Code
WLT
Fab & Assembly Location
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of
the user.
2. A critical component in any component of a life
support, device, or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
This datasheet contains preliminary data; supplementary data may be published at a later date.
Alpha & Omega Semiconductor reserves the right to make changes at any time without notice.
LIFE SUPPORT POLICY
ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.

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