SY89838U Datasheet by Microchip Technology

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® - Precision 1:8 LVDS Clock Fanout Buffer = with 2:1 Runt Pulse Eliminator Input MUX \ + 1 documentation 0 : www.micremom. Precwsmn Edge is a reglsiered irademark oi Micrel, Inc hbwheig@micrel com
SY89838U
Precision 1:8 LVDS Clock Fanout Buffer
with 2:1 Runt Pulse Eliminator Input MUX
May 2008 M9999-051308-D
hbwhelp@micrel.com or (408) 955-1690
Precision Edge is a registered trademark of Micrel, Inc
General Description
The SY89838U is a low jitter, low skew, high-speed
1:8 fanout buffer with a unique, 2:1 differential input
multiplexer (MUX) optimized for redundant source
switchover applications. Unlike standard multiplexers,
the SY89838U unique 2:1 Runt Pulse Eliminator
(RPE) MUX prevents any short cycles or “runt” pulses
during switchover. In addition, a unique fail-safe input
protection prevents metastable conditions when the
selected input clock fails to a DC voltage (voltage
between the pins of the differential input drops below
200mV). The SY89838U distributes clock frequencies
from 1kHz to 1.5GHz, guaranteed, over temperature
and voltage.
The differential input includes Micrel’s unique, 3-pin
input termination architecture that allows customers to
interface to any differential signal (AC- or DC-coupled)
as small as 200mV (400MvPP) without any level
shifting or termination resistor networks in the signal
path. The outputs are 350mV compatible LVDS with
fast rise/fall times guaranteed to be less than 150ps.
The SY89838U operates from a 2.5V ±5% supply and
is guaranteed over the full industrial temperature range
of 40°C to +85°C. For applications that require
800mV LVPECL outputs, consider the SY89837U. The
SY89838U is part of Micrel’s high-speed, Precision
Edge® product line.
All support documentation can be found on Micrel’s
web site at: www.micrel.com.
Precision Edge®
Features
Selects between two clocks, and provides 8
precision, low skew LVDS output copies
2:1 MUX input provides a glitch-free, stable LVDS
output
Guaranteed AC performance over temperature and
supply voltage:
Wide operating frequency: 1kHz to >1.5GHz
<150ps tr/tf
<40ps output-to-output skew
Unique patent-pending input isolation design
minimizes crosstalk
Fail-safe input prevents oscillation
Ultra-low jitter design:
150fs RMS phase jitter
<0.7psRMS MUX crosstalk induced jitter
Unique patent-pending input termination and VT pin
accepts DC- and AC-coupled inputs (CML, PECL,
LVDS)
350mV LVDS output swing
Power supply 2.5V +5%
40°C to +85°C industrial temperature range
Available in 32-pin (5mm x 5mm) QFN package
Applications
Redundant clock switchover
Failsafe clock protection
Markets
LAN/WAN
Enterprise Servers
ATE
Test and Measurements
United States Patent No. RE44,134
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Typical Application
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Ordering Information(1)
Part Number Package
Type
Operating
Range
Package Marking Lead
Finish
SY89838UMG QFN-32 Industrial SY89838U with bar line
Pb-Free indicator
NiPdAu
Pb-Free
SY89838UMGTR(2) QFN-32 Industrial SY89838U with bar line
Pb-Free indicator
NiPdAu
Pb-Free
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = +25°C, DC Electrical only.
2. Tape and Reel.
Pin Configuration
32-Pin QFN
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Pin Description
Pin Number Pin Name Pin Function
1, 3,
6, 8
IN0, /IN0,
IN1, /IN1
Differential Inputs: These input pairs are the differential signal inputs to the
device. These inputs accept AC or DC-coupled signals
as small as 100mV
(200mVPP). Each pin of a pair internally terminates to a VT pin through 50.
Please refer to the “Input Interface Applications” section for more details.
2, 7 VT0, VT1
Input Termination Center-Tap: Each side of the differential input pair terminates
to a VT pin. The VT0 and VT1 pins provide a center-tap to a termination network
for maximum interface flexibility. See the
“Input Interface Applications” section
for more details.
31 SEL
This single-ended TTL/CMOS-compatible input selects th
e inputs to the
multiplexer. Note that this input is internally connected to a 25k pull-up resistor
and will default to a logic HIGH state if left open. Input threshold is VCC/2.
9, 19, 22, 32 VCC
Positive Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitors as close
to VCC pins as possible.
30, 28, 26, 24,
18, 16, 14, 12,
29, 27, 25, 23,
17, 15, 13, 11
Q0 Q7,
/Q0 /Q7
Differential Outputs: These LVDS output pairs are a logic function of the IN0,
IN1, and SEL inputs. Please refer to the truth table below for details. Unused
output pairs must be terminated with 100 across the pair.
20, 21 GND,
Exposed Pad
Ground: Ground pin and exposed pad must be connected to the same ground
plane.
10 CAP
Power-
On Reset (POR) Initialization capacitor. When using the multiplexer with
RPE capability, this pin is tied to a capacitor to VCC. The purpose is to ensure
the internal RPE logic starts up in a known state. See “Power-On Rest (POR)
Description” section for more de
tails regarding capacitor selection. If this pin is
tied directly to VCC, the RPE function will be disabled and the multiplexer will
function as a normal multiplexer. The CAP pin should never be left open.
4, 5 VREF-AC0
VREF-AC1
Reference Voltage: These outputs bias to VCC–1.2V. They are used for AC-
coupling inputs (IN, /IN). Connect VREF_AC directly to the VT pin. Bypass with
0.01µF low ESR capacitor to VCC. See “Input Interface Applications” section.
Maximum sink/source current is ±1.5mA.
Truth Table
Inputs Outputs
IN0 /IN0 IN1 /IN1 SEL Q /Q
0 1 X X 0 0 1
1 0 X X 0 1 0
X X 0 1 1 0 1
X X 1 0 1 1 0
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Absolute Maximum Ratings(1)
Supply Voltage (VCC) ........................... -0.5V to +4.0V
Input Voltage (VIN) .................................. -0.5V to VCC
Input Current
Source or sink current on IN, /IN .............. ±50mA
Termination Current
Source or sink current on VT .................. ±100mA
VREF-AC Source or sink current .......................... ±2mA
Lead Temperature (soldering, 20 sec.) .......... +260°C
Storage Temperature (Ts) .................. 65°C to 150°C
Operating Ratings(2)
Supply Voltage (VCC) .................. +2.375V to +2.625V
Ambient Temperature (TA) ................ 40°C to +85°C
Package Thermal Resistance(3)
QFN (θJA)
Still-Air ..................................................... 35°C/W
QFN (ψJB)
Junction-to-Board .................................... 16°C/W
DC Electrical Characteristics(4)
TA = 40°C to +85°C, unless otherwise stated.
Symbol Parameter Condition Min Typ Max Units
VCC Power Supply 2.375 2.5 2.625 V
ICC Power Supply Current No load, max. VCC 250 350 mA
RIN Input Resistance
(IN-to-VT)
45 50 55
RDIFF_IN Differential Input Resistance
(IN-to-/IN)
90 100 110
VIH Input High Voltage
(IN, /IN)
1.2 VCC V
VIL Input Low Voltage
(IN, /IN)
0 VIH0.2 V
VIN Input Voltage Swing
(IN, /IN)
See Figure 1a. Note 5 0.2 VCC V
VDIFF_IN Differential Input Voltage Swing
|IN-/IN|
See Figure 1b. 0.4 V
VIN_FSI Input Voltage Threshold that
Triggers FSI
30 100 mV
VT_IN IN-to-VT
(IN, /IN)
1.8 V
VREF-AC Output Reference Voltage VCC1.3 VCC1.2 VCC1.1 V
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. This is a stress rating only and functional operation
is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings
conditions for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Package Thermal Resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. θJA
and ψJB values are determined for a 4-layer board in still air, unless otherwise stated.
4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
5. VIN (max) is specified when VT is floating.
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LVDS Outputs DC Electrical Characteristics(6)
VCC = +2.5V ±5%; TA = 40°C to + 85°C; RL = 100Ω across output pair, or equivalent, unless otherwise stated.
Symbol Parameter Condition Min Typ Max Units
VOUT Output Voltage Swing
(Q, /Q)
See Figure 1a and 4a 250 325 mV
VDIFF-OUT Differential Output Voltage Swing
|Q - /Q|
See Figure 1b 500 650 mV
VOCM Output Common Mode Voltage See Figure 4b 1.125 1.275 V
VOCM Change in Common Mode Voltage See Figure 4b 50 +50 mV
LVTTL/CMOS DC Electrical Characteristics(6)
VCC = +2.5V ±5%; TA = 40°C to + 85°C, unless otherwise stated.
Symbol Parameter Condition Min Typ Max Units
VIH Input HIGH Voltage 2.0 V
VIL Input LOW Voltage 0.8 V
IIH Input HIGH Current 125 30 µA
IIL Input LOW Current 300 µA
Note:
1. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
RMS Phase Jitter hbwhe\g@m\crel com
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AC Electrical Characteristics(6)
VCC = +2.5V ±5%; TA = 40°C to +85°C, RPE enabled, Input tr/tf 600ps (20% to 80%), RL = 100, unless otherwise stated.
Symbol Parameter Condition Min Typ Max Units
fMAX Maximum Operating Frequency RPE enabled 1.5 2.0 GHz
tpd Differential Propagation Delay
IN-to-Q
VIN 250mV, Note 7
500
700
950
ps
SEL-to-Q RPE enabled, see Timing Diagram 17 Cycles
SEL-to-Q RPE disabled (VIN = VCC/2) 1000 ps
tpd
Tempco
Differential Propagation Delay
Temperature Coefficient
115 fs/oC
tskew Output-to-Output Skew Note 8 20 40 ps
Part-to-Part Skew Note 9 200 ps
tJitter
RMS Phase Jitter
Output = 622MHz
Integration range: 12kHz 20MHz
150 fs
Crosstalk-Induced Jitter Note 10
0.7 psRMS
tR, tF Output Rise/Fall Time (20% to 80%) At full output swing. 40 80 150 ps
Notes:
6. High-frequency AC-parameters are guaranteed by design and characterization.
7. Propagation delay is a function of rise and fall time at IN. See “Typical Operating Characteristics” for more details.
8. Output-to-output skew is measured between two different outputs under identical transitions.
9. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at
the respective inputs.
10. Crosstalk is measured at the output while applying two similar differential clock frequencies that are asynchronous with respect to each
other at the inputs.
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Functional Description
RPE MUX and Fail-Safe Input
The SY89838U is optimized for clock switchover
applications where switching from one clock to another
clock without runt pulses (short cycles) is required. It
features two unique circuits:
Runt-Pulse Eliminator (RPE) Circuit:
The RPE MUX provides a “glitchless” switchover
between two clocks and prevents any runt pulses from
occurring during the switchover transition. The design
of both clock inputs is identical (i.e., the switchover
sequence and protection is symmetrical for both input
pair, IN0 or IN1. Thus, either input pair may be
defined as the primary input). If not required, the RPE
function can be permanently disabled to allow the
switchover between inputs to occur immediately. If the
CAP pin is tied directly to VCC, the RPE function will be
disabled and the multiplexer will function as a normal
multiplexer.
Fail-Safe Input (FSI) Circuit:
The FSI function provides protection against a
selected input pair that drops below the minimum
amplitude requirement. If the selected input pair drops
sufficiently below the 100mV minimum single-ended
input amplitude limit (VIN), or 200mV differentially
(VDIFF_IN), the output will latch to the last valid clock
state.
RPE and FSI Functionality
The basic operation of the RPE MUX and FSI
functionality is described with the following four case
descriptions. All descriptions are related to the true
inputs and outputs. The primary (or selected) clock is
called CLK1; the secondary (or alternate) clock is
called CLK2. Due to the totally asynchronous relation
of the IN and SEL signals and an additional internal
protection against metastability, the number of pulses
required for the operations described in cases 1-4 can
vary within certain limits. Refer to “Timing Diagrams
for more detailed information.
Case #1 Two Normal Clocks and RPE Enabled
In this case the frequency difference between the two
running clocks IN0 and IN1 must not be greater than
1.5:1. For example, if the IN0 clock is 500MHz, the IN1
clock must be within the range of 334MHz to 750MHz.
If the SEL input changes state to select the alternate
clock, the switchover from CLK1 to CLK2 will occur in
three stages.
Stage 1: The output will continue to follow CLK1 for
a limited number of pulses.
Stage 2: The output will remain LOW for a limited
number of pulses of CLK2.
Stage 3: The output follows CLK2.
Stage 2
Select CLK 1
Select CLK 2
CLK1
CLK2
SEL
OUTPUT
Runt pulse eliminated
from output
Stage 3
3 to 5 falling edges
of CLK1
4 to 5 falling edges of CLK2
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Case #2 Input Clock Failure: Switching from a selected
clock stuck HIGH to a valid clock (RPE enabled)
If CLK1 fails HIGH before the RPE MUX selects CLK2
(using the SEL pin), the switchover will occur in three
stages.
Stage 1: The output will remain HIGH for a limited
number of pulses of CLK2.
Stage 2: The output will switch to LOW and then
remain LOW for a limited number of falling edges of
CLK2.
1. Stage 3: The output will follow CLK2.
Case #3 Input Clock Failure: Switching from a
selected clock stuck Low to a valid clock (RPE
enabled)
If CLK1 fails LOW before the RPE MUX selects
CLK2 (using the SEL pin), the switchover will occur
in two stages.
Stage 1: The output will remain LOW for a
limited number of falling edges of CLK2.
Stage 2: The output will follow CLK2.
Stage 2
Stage 1
OUTPUT
CLK1
CLK2
SEL
Select CLK 1
Select CLK 2
Runt pulse eliminated
from output
Stage 3
14 to 16 falling edges of CLK2
Note: Output shows extended clock cycle during switchover. Pulse width for both high and low of this cycle will
always be greater than 50% of the CLK2 period.
Stage 1
CLK1
CLK2
SEL
Select CLK 1
Select CLK 2
Stage 2
13 to 17 falling edges of CLK2
SEL Se‘ec: CLK‘ Se‘ect CLK 2 OUTPUT _ as in case #2 _ _ _ _ as m case #3 1 (my) 1 2an LuF 10 hbwhe‘ mwcrel com
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Case #4 Input Clock Failure: Switching from the
selected clock input stuck in an undetermined state to
a valid clock input (RPE enabled)
If CLK1 fails to an undetermined state (e.g., amplitude
falls below the 100mV (VIN) minimum single-ended
input limit, or 200mV differentially) before the RPE
MUX selects CLK2 (using the SEL pin), the switchover
to the valid clock CLK2 will occur either following Case
#2 or Case #3, depending on the last valid state at the
CLK1.
If the selected input clock fails to a floating, static, or
extremely low signal swing, including 0mV, the FSI
function will eliminate any metastable condition and
guarantee a stable output signal. No ringing and no
undetermined state will occur at the output under
these conditions.
Please note that the FSI function will not prevent duty
cycle distortions or runt pulses in case of a slowly
deteriorating (but still toggling) input signal. Due to the
FSI function, the propagation delay will depend on rise
and fall time of the input signal and on its amplitude.
Refer to Typical Operating Characteristics” for more
detailed information.
Power-On Reset (POR) Description
The SY89838U includes an internal power-on reset
(POR) function to ensure the RPE logic starts-up in a
known logic state once the power-supply voltage is
stable. An external capacitor connected between VCC
and the CAP pin (pin 10) controls the delay for the
power-on reset function.
Calculation of the required capacitor value is based on
the time the system power supply needs to power up
to a minimum of 2.3V. The time constant for the
internal power-on-reset must be greater than the time
required for the power supply to ramp up to a minimum
of 2.3V.
The following formula describes this relationship:
C(µF) ≥
)/(12
)(
Fms
mst
dPS
µ
As an example, if the time required for the system
power supply to power up past 2.3V is 12ms, the
required capacitor value on pin 10 would be:
C(µF) ≥
)/(12
12
Fms
ms
µ
C(µF) ≥
F
µ
1
CLK1
CLK2
SEL
Select CLK 1
Select CLK 2
OUTPUT
as in case #2
as in case #3
Output Swlng VI. Frequency PROPAGATION DELAV (ps) 0 500 1000 1500 FREQUENCV (MHz) 2000 FHUF’AGA‘HON DELAV (ps) PROPAGATION DELAV (ps) 11 hbwhe‘ mwcrel com
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Typical Operating Characteristics
VCC = 2.5V, GND = 0V, VIN ≥ 250mVpk, tr/tf ≤ 300ps, RL = 100Ω across output pair; TA = 25°C, unless otherwise stated.
0
100
200
300
400
500
600
700
800
900
1000
0100 200 300 400 500 600
INPUT RISE/FALL TIME (ps)
Propagation Delay Variation
vs. Input Rise/Fall Time
tpd (min)
tpd (max)
VIN = 200mVPK
0
100
200
300
400
500
600
700
800
900
1000
0100 200 300 400 500 600
INPUT RISE/FALL TIME (ps)
Propagation Delay Variation
vs. Input Rise/Fall Time
tpd (min)
tpd (max)
VIN = 400mVPK
0
100
200
300
400
500
600
700
800
900
1000
0100 200 300 400 500 600
INPUT RISE/FALL TIME (ps)
Propagation Delay Variation
vs. Input Rise/Fall Time
tpd (min)
tpd (max)
VIN = 800mVPK
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Singled-Ended and Differential Swings
Figure 1a. Singled-Ended Voltage Swing
Figure1b. Differential Voltage Swing
Input Stage
Figure 2. Simplified Differential Input Stage
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Input Interface Applications
Figure 3a. LVPECL Interface
(DC-Coupled)
Figure 3b. LVPECL Interface
(AC-coupled)
option: may connect VT to VCC
Figure 3c. CML Interface
(DC-Coupled)
Figure 3d. CML Interface
(AC-Coupled)
Figure 3e. LVDS Interface
(DC-Coupled)
Figure 4a LVDS Differential Measurement Figure 4b. LVDS Common Mode Measurement www.mwcreiLom/groducHnfo/groducts/sulumons shtml 14 hbwheig@m\crel com
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LVDS Output Interface Applications
LVDS specifies a small swing of 325mV typical, on a
nominal 1.2V common mode above ground. The
common mode voltage has tight limits to permit large
variations in ground between an LVDS driver and
receiver. Also, change in common mode voltage, as a
function of data input, is kept to a minimum, to keep
EMI low.
Figure 4a. LVDS Differential Measurement
Figure 4b. LVDS Common Mode Measurement
Related Product and Support Documentation
Part Number
Function
Data Sheet Link
SY89837U Presision 1:8 LVPECL Fanout Buffer with
2:1 Runt Pulse Eliminator Input Mux
www.micrel.com/_PDF/HBW/SY89837u.pdf
HBW Solutions New Products and Applications www.micrel.com/product-info/products/solutions.shtml
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Package Information
32-Pin (5mm x 5mm) QFN
i Package EPr Expused Pad Due CompSwde \s‘and \ x x o o 3 x x o o o x x c o 3 , \ Hem Dwss‘pahon Heat Dlswpahun - K Va _ Heavycapperwane ‘ th Heavy CoDDer mane MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA rel on of a ended ed. 16 hbwhe\g@m\crel com
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PCB Thermal Consideration for 32-Pin QFN Package
(Always solder, or equivalent, the exposed pad to the PCB)
Package Notes:
1. Package meets Level 2 qualification.
2. All parts are dry-packaged before shipment.
3. Exposed pads must be soldered to a ground for proper thermal management.
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel
for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the custome
r.
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IC CLK BUFFER 2:8 2GHZ 32MLF
IC CLK BUFFER 2:8 2GHZ 32MLF
IC CLK BUFFER 2:8 2GHZ 32MLF
IC CLK BUFFER 2:8 2GHZ 32MLF