SY10E016, SY100E016 Datasheet by Microchip Technology

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1
SY10E016
SY100E016
Micrel, Inc.
M9999-032006
hbwhelp@micrel.com or (408) 955-1690
Pin Function
P0-P7Parallel Data (Preset) Inputs
Q0-Q7Data outputs
CE Count Enable Control Input
PE Parallel Load Enable Control Input
MR Master Reset
CLK Clock
TC Terminal Count Output
TCLD TC-Load Control Input
VCCO VCC to Output
700MHz min. count frequency
Extended 100E VEE range of –4.2V to –5.5V
1000ps CLK to Q, TC
Internal, gated TC feedback
8 bits wide
Fully synchronous counting and TC generation
Asynchronous Master Reset
Fully compatible with industry standard 10KH,
100K I/O levels
Internal 75K input pulldown resistors
Fully compatible with Motorola MC10E/100E016
Available in 28-pin PLCC package
The SY10/100E016 are high-speed synchronous,
presettable and cascadable 8-bit binary counters designed
for use in new, high-performance ECL systems. Architecture
and operation are the same as the Motorola MC10H016 in
the MECL 10KH family, extended to 8 bits, as shown in the
logic diagram.
The counters feature internal feedback of TC, gated by
the TCLD (terminal count load) pin. When TCLD is LOW,
the TC feedback is disabled and counting proceeds
continuously, with TC going LOW to indicate an all-HlGH
state. When TCLD is HIGH, the TC feedback causes the
counter to automatically reload upon TC = LOW, thus
functioning as a programmable counter.
8-BIT SYNCHRONOUS
BINARY UP COUNTER SY10E016
SY100E016
FEATURES DESCRIPTION
PIN NAMES
Rev.: G Amendment: /0
Issue Date:
March 2006
‘ a :::::::
2
SY10E016
SY100E016
Micrel, Inc.
M9999-032006
hbwhelp@micrel.com or (408) 955-1690
PACKAGE/ORDERING INFORMATION
Ordering Information(1)
Package Operating Package Lead
Part Number Type Range Marking Finish
SY10E016JI J28-1 Industrial SY10E016JI Sn-Pb
SY10E016JITR(2) J28-1 Industrial SY10E016JI Sn-Pb
SY100E016JI J28-1 Industrial SY100E016JI Sn-Pb
SY100E016JITR(2) J28-1 Industrial SY100E016JI Sn-Pb
SY10E016JC J28-1 Commercial SY10E016JC Sn-Pb
SY10E016JCTR(2) J28-1 Commercial SY10E016JC Sn-Pb
SY100E016JC J28-1 Commercial SY100E016JC Sn-Pb
SY100E016JCTR(2) J28-1 Commercial SY100E016JC Sn-Pb
SY10E016JY(3) J28-1 Industrial SY10E016JY with Matte-Sn
Pb-Free bar-line indicator
SY10E016JYTR(2, 3) J28-1 Industrial SY10E016JYwith Matte-Sn
Pb-Free bar-line indicator
SY100E016JY(3) J28-1 Industrial SY100E016JY with Matte-Sn
Pb-Free bar-line indicator
SY100E016JYTR(2, 3) J28-1 Industrial SY100E016JY with Matte-Sn
Pb-Free bar-line indicator
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only.
2. Tape and Reel.
3. Pb-Free package is recommended for new designs.
28-Pin PLCC (J28-1)
VEE
MR
CLK
P0
NC
VCCO
26
27
28
1
2
3
4
18
17
16
15
14
13
12
25 24 23 22 21 20 19
567891011
P1
TCLD
Q2
Q1
Q7
P5
PLCC
TOP VIEW
J28-1
TC
CE
PE
P6
P7
Q6
VCC
Q5
VCCO
Q4
Q3
Q0
VCCO
P4
P3
P2
4L __________ TJ: fig 4 g %7 ,,JJJJ,, ' , / 7L. / /s/ ____________ _'_. 4L""'B""TJ:V L§% _______ 9 2i , 43 AA
3
SY10E016
SY100E016
Micrel, Inc.
M9999-032006
hbwhelp@micrel.com or (408) 955-1690
BLOCK DIAGRAM
BIT 7
BIT 2 – BIT 6
BIT 1
Q0Q1Q2Q3Q4Q5Q6
CE
P7
P1
CE
SLAVE
MASTER
Q0MQ0M
Q0
BIT 0
5
5
5
5
5
5
P0
TC
Q7
Q0
Q1
Q2 – Q6
TCLD MR CLK
PE CE
4
SY10E016
SY100E016
Micrel, Inc.
M9999-032006
hbwhelp@micrel.com or (408) 955-1690
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = –40°CTA = 0°CTA = +25°CTA = +85°C
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
IIH Input HIGH Current 150 150 150 150 µA
IEE Power Supply Current mA
10E — 151 181 — 151 181 — 151 181 — 151 181
100E — 151 181 — 151 181 — 151 181 — 174 208
TRUTH TABLE(1)
CE PE TCLD MR CLK Function
X L X L Z Load Parallel (Pn to Qn)
L H L L Z Continuous Count
L H H L Z Count; Load Parallel on TC = LOW
H H X L Z Hold
X X X L ZZ Master respond, Slaves Hold
X X X H Z Reset (Qn : = LOW, TC : = HIGH)
NOTE:
1. Z = Clock Pulse (LOW-to-HIGH), ZZ = Clock Pulse (HIGH-to-LOW)
DC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = –40°CTA = 0°CTA = 25°CTA = +85°C
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
fCOUNT Max. Count Frequency 700 900 700 900 700 900 700 900 MHz
tPD Propagation Delay to Output ps
CLK to Q 600 725 1000 600 725 1000 600 725 1000 600 725 1000
MR to Q 600 775 1000 600 775 1000 600 775 1000 600 775 1000
CLK to TC (Qs loaded)(1) 550 775 1050 550 775 1050 550 775 1050 550 775 1050
CLK to TC (Qs unloaded)(1) 550 700 900 550 700 900 550 700 900 550 700 900
MR to TC 625 775 1000 625 775 1000 625 775 1000 625 775 1000
tSSet-up Time ps
Pn 150 –30 150 –30 150 –30 150 –30
CE 600 400 600 400 600 400 600 400
PE 600 400 600 400 600 400 600 400
TCLD 500 300 500 300 500 300 500 300
tHHold Time ps
Pn 250 30 250 30 250 30 250 30
CE 0 –400 0 –400 0 –400 0 –400
PE 0 –400 0 –400 0 –400 0 –400
TCLD 100 –300 100 –300 100 –300 100 –300
tRR Reset Recovery Time 900 700 900 700 900 700 900 700 ps
tWP Minimum Pulse Width 400 400 400 400 ps
CLK, MR
trRise/Fall Times 300 510 800 300 510 800 300 510 800 300 510 800 ps
tf20% to 80%
NOTE:
1. CLK to TC propagation delay is dependent on the loading of the Q outputs. With all of the Q outputs loaded, the noise generated in going from a IIII IIII
state to a 0000 0000 state causes the CLk to TC+ delay to increase.
AC ELECTRICAL CHARACTERISTICS
5
SY10E016
SY100E016
Micrel, Inc.
M9999-032006
hbwhelp@micrel.com or (408) 955-1690
FUNCTION TABLE
Function PE CE MR TCLD CLK P7–P4P3P2P1P0Q7–Q4Q3Q2Q1Q0TC
Load L X L X Z H H H L L H H H L L H
Count H L L L Z XXXXXHHHLHH
HLLLZ XXXXXHHHHLH
HLLLZ XXXXXHHHHHL
HLLLZ XXXXXLLLLLH
Load L X L X Z H H H L L H H H L L H
Hold H H L X Z XXXXXHHHLLH
HHLXZ XXXXXHHHLLH
Load On H L L H Z H L H H L H H H L H H
Terminal H L L H Z H L H H L HHHHLH
Count H L L H Z H L H H L HHHHHL
HLLHZ HLHHLHLHHLH
HL LHZ HLHHLHLHHHH
HLLHZ HLHHLHHLLLH
Reset X X H X X XXXXXLLLLLH
6
SY10E016
SY100E016
Micrel, Inc.
M9999-032006
hbwhelp@micrel.com or (408) 955-1690
APPLICATIONS INFORMATION
Cascading Multiple E016 Devices
For applications which call for larger than 8-bit counters,
multiple E016s can be tied together to achieve very wide bit
width counters. The active low terminal count (TC) output and
count enable input (CE) greatly facilitate the cascading of
E016 devices. Two E016s can be cascaded without the need
for external gating; however, for counters wider than 16 bits,
external OR gates are necessary for cascade implementations.
Figure 1, below, pictorially illustrates the cascading of 4
E016s to build a 32-bit high frequency counter. Note the E101
gates used to OR the terminal count outputs of the lower order
E016s to control the counting operation of the higher order
bits. When the terminal count of the preceding device (or
devices) goes low (the counter reaches an all 1s state), the
more significant E016 is set in its count mode and will count
one binary digit upon the next positive clock transition. In
addition, the preceding devices will also count one bit, thus
sending their terminal count outputs back to a high state,
disabling the count operation of the more significant counters
and placing them back into hold modes. Therefore, for an
E016 in the chain to count all of the lower order terminal count
outputs, it must be in the low state. The bit width of the counter
can be increased or decreased by simply adding or subtracting
E016 devices from Figure 1 and maintaining the logic pattern
illustrated in the same figure.
The maximum frequency of operation for the cascaded
counter chain is set by the propagation delay of the TC output
and the necessary set-up time of the CE input and the
propagation delay through the OR gate controlling it (for 16-
bit counters the limitation is only the TC propagation delay and
the CE set-up time). Figure 1 shows E101 gates used to
control the count enable inputs; however, if the frequency of
operation is lower, a slower ECL OR gate can be used. Using
the worst case guarantees for these parameters from the
ECLinPS data book, the maximum count frequency for a
greater than 16-bit counter is 475MHz and that for a 16-bit
counter is 625MHz. Note that this assumes the trace delay
between the TC outputs and the CE inputs are negligible. If
this is not the case, estimates of these delays need to be
added to the calculations.
Figure 1. 32-Bit Cascaded E016 Counter
Q
0
Q
7
P
0
P
7
CE PE
TC
CLK
E016
LSB
TCCLK
E016
TCCLK
E016
TCCLK
E016
MSB
LOAD
"LO"
CLOCK
E101
Q
0
Q
7
Q
0
Q
7
Q
0
Q
7
P
0
P
7
P
0
P
7
P
0
P
7
CE PE CE PE CE PE
E101
MM M2
7
SY10E016
SY100E016
Micrel, Inc.
M9999-032006
hbwhelp@micrel.com or (408) 955-1690
Programmable Divider
The E016 has been designed with a control pin which
makes it ideal for use as an 8-bit programmable divider. The
TCLD pin (load on terminal count), when asserted, reloads the
data present at the parallel input pin (Pn's) upon reaching
terminal count (an all 1s state on the outputs). Because this
feedback is built internal to the chip, the programmable
division operation will run at very nearly the same frequency
as the maximum counting frequency of the device. Figure 2
below illustrates the input conditions necessary for utilizing
the E016 as a programmable divider set up to divide by 113.
To determine what value to load into the device to accomplish
the desired division, the designer simply subtracts the binary
equivalent of the desired divide ratio for the binary value for
256. As an example for a divide ration of 113:
PN's = 256 113 = 8F16 = 1000 1111
where
P0 = LSB and P7 = MSB
Forcing this input condition, as per the set-up in Figure 2, will
result in the waveforms of Figure 3. Note that the TC output
HLL HHLHH
P7P6P5P4P3P2P1P0
PE
CE
TCLD
CLK
Q7Q6Q5Q4Q3Q2Q1Q0
TC
H
L
H
Figure 2. Mod 2 to 256 Programmable Divider
Figure 3. Divide by 113 E016 Programmable Divider Waveforms
CLOCK
PE
TC
LOAD 1001 0000 1001 0001 1111 1100 1111 1101 1111 1110 1111 1111 LOAD
Divide by 113
8
SY10E016
SY100E016
Micrel, Inc.
M9999-032006
hbwhelp@micrel.com or (408) 955-1690
is used as the divide output and the pulse duration is equal to
a full clock period. For even divide ratios twice the desired
divide ratio can be loaded into the E016 and the TC output can
feed the clock input of a toggle flip-flop to create a signal
divided as desired with a 50% duty cycle.
A single E016 can be used to divide by any ratio from 2 to
256, inclusive. If divide ratios of greater than 256 are needed,
multiple E016s can be cascaded in a manner similar to that
already discussed. When E016s are cascaded to build larger
dividers, the TCLD pin will no longer provide a means for
loading on terminal count. Because one does not want to
reload the counters until all of the devices in the chain have
reached terminal count, external gating of the TC pins must be
used for multiple E016 divider chains.
Figure 4 on the following page shows a typical block
diagram of a 32-bit divider chain. Once again, the maximize
the frequency of operation, E101 OR gates were used. For
lower frequency applications, a slower OR gate could replace
the E101. Note that for a 16-bit divider, the OR function
feeding the PE (program enable) input CANNOT be replaced
by a wire OR tie as the TC output of the least significant E016
must also feed the CE input of the most significant E016. If the
two TC outputs were OR tied, the cascaded count operation
would not operate properly. Because in the cascaded form
the PE feedback is external and requires external gating, the
maximum frequency of operation will be significantly less than
the same operation in a single device.
Maximizing E016 Count Frequency
The E016 device produces nine fast transitioning single-
ended outputs; thus, VCC noise can become significant in
situations where all of the outputs switch simultaneously in the
same direction. This VCC noise can negatively impact the
maximum frequency of operation of the device. Since the
device does not need to have the Q outputs terminated to
count properly, it is recommended that, if the outputs are not
going to be used in the rest of the system, they should be left
unterminated. In addition, if only a subset of the Q outputs are
used in the system, only those outputs should be terminated.
Not terminating the unused outputs will not only cut down the
VCC noise generated, but will also save in total system power
dissipation. Following these guidelines will allow designers to
either be more aggressive in their designs, or provide them
Divide Preset Data Inputs
Ratio P7P6P5P4P3P2P1P0
2HHHHHHHL
3 H H HHH H L H
4 H H HHH H L L
5 H H HHH L H H
••••• • ••
••••• • ••
112 H L L H L L L L
113 H L L L H H H H
114 H L L L H H H L
••••• • ••
••••• • ••
254 L L L L L L H L
255 L L L L L L L H
256 L L L L L L L L
Table 1. Preset Values for Various Divide Ratios
9
SY10E016
SY100E016
Micrel, Inc.
M9999-032006
hbwhelp@micrel.com or (408) 955-1690
Figure 4. 32-Bit Cascaded E016 Programmable Divider
Q
0
Q
7
P
0
P
7
CE PE
TC
CLK
E016
LSB
Q
0
Q
7
P
0
P
7
E016
Q
0
Q
7
P
0
P
7
E016
Q
0
Q
7
P
0
P
7
E016
MSB
"LO"
CLOCK
E101 E101
E101
CE PE CE PE CE PE
TC
CLK TC
CLK TC
CLK
w um «.JL m ‘ :45 ‘ 22 ‘ w; ‘ _,- \ «, m ’ V WHK m? Fn'r
10
SY10E016
SY100E016
Micrel, Inc.
M9999-032006
hbwhelp@micrel.com or (408) 955-1690
28-PIN PLCC (J28-1)
Rev. 03
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use.
Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into
the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchasers
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Micrel for any damages resulting from such use or sale.
© 2006 Micrel, Incorporated.

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