SSM2212 Datasheet by Analog Devices Inc.

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ANALOG DEVICES 133:: I‘ll—\TH—I LILHJLI {E
Audio, Dual-Matched
NPN Transistor
Data Sheet SSM2212
Rev. C Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2010–2015 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
Very low voltage noise: 1 nV/√Hz maximum at 100 Hz
Excellent current gain match: 0.5%
Low offset voltage (VOS): 200 μV maximum (SOIC)
Outstanding offset voltage drift: 0.03 μV/°C
High gain bandwidth product: 200 MHz
PIN CONNECTIONS
C
11
B
12
E
13
NIC
4
C
2
8
B
2
7
E
2
6
NIC
5
SSM2212
09043-001
NOTES
1. NIC = NO INTERNAL CONNECTION.
Figure 1. 8-Lead SOIC_N
09043-020
12
11
10
1
3
49
2
6
5
7
8
16
15
14
13
SSM2212
E
1A
E
1B
E
2B
E
2A
NIC
C
1
NIC
B
1
NIC
C
2
NIC
NIC
NIC
B
2
NIC
NIC
NOTES
1. NIC = NO INTERNAL CONNECTION.
Figure 2. 16-Lead LFCSP_WQ
GENERAL DESCRIPTION
The SSM2212 is a dual, NPN-matched transistor pair that is
specifically designed to meet the requirements of ultralow noise
audio systems.
With its extremely low input base spreading resistance (rbb' is
typically 28 Ω) and high current gain (hFE typically exceeds 600 at
IC = 1 mA), the SSM2212 can achieve outstanding signal-to-noise
ratios. The high current gain results in superior performance
compared to systems incorporating commercially available
monolithic amplifiers.
Excellent matching of the current gain (ΔhFE) to approximately
0.5% and low VOS of less than 10 μV typical make the SSM2212
ideal for symmetrically balanced designs, which reduce high-
order amplifier harmonic distortion.
Stability of the matching parameters is guaranteed by protection
diodes across the base-emitter junction. These diodes prevent
degradation of beta and matching characteristics due to reverse
biasing of the base-emitter junction.
The SSM2212 is also an ideal choice for accurate and reliable
current biasing and mirroring circuits. Furthermore, because
the accuracy of a current mirror degrades exponentially with
mismatches of VBE between transistor pairs, the low VOS of the
SSM2212 does not need offset trimming in most circuit
applications.
The SSM2212 SOIC performance and characteristics are
guaranteed over the extended temperature range of −40°C to
+85°C.
The SSM2212 is available in 8-lead SOIC and 16-lead LFCSP
packages.
SSM2212 Data Sheet
Rev. C | Page 2 of 12
TABLE OF CONTENTS
Features .............................................................................................. 1
Pin Connections ............................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical CharacteristicsSOIC Package ................................ 3
Electrical CharacteristicsLFCSP Package .............................. 4
Absolute Maximum Rating ............................................................. 5
Thermal Resistance .......................................................................5
ESD Caution...................................................................................5
Typical Performance Characteristics ..............................................6
Pin Configurations and Function Descriptions ............................9
Applications Information .............................................................. 10
Fast Logarithmic Amplifier ....................................................... 10
Outline Dimensions ....................................................................... 11
Ordering Guide .......................................................................... 11
REVISION HISTORY
6/15Rev. B to Rev. C
Added LFCSP Package ....................................................... Universal
Changes to Features Section and General Description Section ....... 1
Changed Pin Configuration Section to Pin Connections Section .. 1
Added Figure 2; Renumbered Sequentially ....................................... 1
Added Electrical CharacteristicsLFCSP Package Section and
Table 2; Renumbered Sequentially ...................................................... 4
Changes to Table 4 .................................................................................. 5
Added Pin Configurations and Function Descriptions Section,
Figure 17, Table 5, Figure 18, and Table 6 .......................................... 9
Added Figure 21 .................................................................................... 11
Updated Outline Dimensions ............................................................ 11
Changes to Ordering Guide ................................................................ 11
7/10Rev. A to Rev. B
Changes to Figure 1 .......................................................................... 1
6/10Rev. 0 to Rev. A
Changes to Fast Logarithmic Amplifier Section .......................... 8
6/10Revision 0: Initial Version
Table L
Data Sheet SSM2212
Rev. C | Page 3 of 12
SPECIFICATIONS
ELECTRICAL CHARACTERISTICSSOIC PACKAGE
VCB = 15 V, IO = 10 µA, TA = 25°C, unless otherwise specified.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
DC AND AC CHARACTERISTICS
Current Gain1 hFE
IC = 1 mA 300 605
−40°C ≤ TA ≤ +85°C 300
IC = 10 µA 200 550
−40°C ≤ TA ≤ +85°C 200
Current Gain Match2 ΔhFE 10 µA ≤ IC ≤ 1 mA 0.5 5 %
Noise Voltage Density3 eN IC = 1 mA, VCB = 0 V
fO = 10 Hz 1.6 2 nV/√Hz
fO = 100 Hz 0.9 1 nV/√Hz
fO = 1 kHz 0.85 1 nV/√Hz
fO = 10 kHz 0.85 1 nV/√Hz
Low Frequency Noise (0.1 Hz to 10 Hz) eN p-p IC = 1 mA 0.4 µV p-p
Offset Voltage VOS VCB = 0 V, IC = 1 mA 10 200 µV
−40°C ≤ T
A
≤ +85°C
220
µV
Offset Voltage Change vs. VCB ΔVOS/ΔVCB 0 V ≤ VCB ≤ VMAX4,1 µA ≤ IC ≤ 1 mA5 10 50 µV
Offset Voltage Change vs. IC ΔVOS/ΔIC 1 µA ≤ IC 1 mA5, VCB = 0 V 5 70 µV
Offset Voltage Drift ΔVOS/ΔT 40°C ≤ TA ≤ +85°C 0.08 1 µV/°C
−40°C ≤ TA +85°C, VOS trimmed to 0 V 0.03 0.3 µV/°C
Breakdown Voltage
BV
CEO
40
V
Gain Bandwidth Product fT IC = 10 mA, VCE = 10 V 200 MHz
Collector-to-Base Leakage Current ICBO VCB = VMAX 25 500 pA
−40°C ≤ TA ≤ +85°C 3 nA
Collector-to-Collector Leakage Current ICC VCC = VMAX6, 7 35 500 pA
−40°C ≤ TA ≤ +85°C 4 nA
Collector-to-Emitter Leakage Current ICES VCE = VMAX, VBE = 0 V6, 7 35 500 pA
−40°C ≤ TA ≤ +85°C 4 nA
Input Bias Current IB IC = 10 µA 50 nA
−40°C ≤ TA ≤ +85°C 50 nA
Input Offset Current IOS IC = 10 µA 6.2 nA
−40°C ≤ TA ≤ +85°C 13 nA
Input Offset Current Drift
ΔI
OS
/ΔT
I
C
= 10 µA
6
, −40°C ≤ T
A
≤ +85°C
40
150
pA/°C
Collector Saturation Voltage VCE (SAT) IC = 1 mA, IB = 100 µA 0.05 0.2 V
Output Capacitance COB VCB = 15 V, IE = 0 µA 23 pF
Bulk Resistance RBE 10 µA ≤ IC ≤ 10 mA6 0.3 1.6
Collector-to-Collector Capacitance CCC VCC = 0 V 35 pF
1 Current gain is guaranteed with collector-to-base voltage (VCB) swept from 0 V to VMAX at the indicated collector currents.
2 Current gain match (ΔhFE) is defined as follows: ΔhFE = (100(ΔIB)(hFE min)/IC).
3 Noise voltage density is guaranteed, but not 100% tested.
4 This is the maximum change in VOS as VCB is swept from 0 V to 40 V.
5 Measured at IC = 10 µA and guaranteed by design over the specified range of IC.
6 Guaranteed by design.
7 ICC and ICES are verified by measurement of ICBO.
Table 2‘
SSM2212 Data Sheet
Rev. C | Page 4 of 12
ELECTRICAL CHARACTERISTICSLFCSP PACKAGE
VCB = 15 V, IO = 100 µA, TA = 25°C, unless otherwise specified.
Table 2.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
DC AND AC CHARACTERISTICS
Current Gain1 hFE
IC = 1 mA, VCB = 15 V 300 1800 2400
IC = 1 mA, VCB = 0 V 200 1300 2200
IC = 100 µA, VCB = 15 V 350 2100 2500
IC = 100 µA, VCB = 0 V 250 1500 2300
Current Gain Match2 ΔhFE 100 µA ≤ IC ≤ 1 mA 0.5 5 %
Noise Voltage Density3 eN IC = 1 mA, VCB = 0 V
fO = 10 Hz 1.6 2 nV/√Hz
fO = 100 Hz 0.9 1 nV/√Hz
fO = 1 kHz 0.85 1 nV/√Hz
fO = 10 kHz 0.85 1 nV/√Hz
Low Frequency Noise (0.1 Hz to 10 Hz) eN p-p IC = 1 mA 0.4 µV p-p
Offset Voltage VOS VCB = 0 V, IC = 1 mA 25 250 µV
VCB = 0 V, IC = 100 µA 10 250 µV
Gain Bandwidth Product
f
T
I
C
= 10 mA, V
CE
= 10 V
200
MHz
Input Bias Current IB IC = 100 µA 200 nA
Input Offset Current IOS IC = 100 µA 10 nA
Output Capacitance COB VCB = 15 V, IE = 0 µA 23 pF
Collector-to-Collector Capacitance CCC VCC = 0 V 35 pF
1 Current gain is guaranteed with collector-to-base voltage (VCB) swept from 0 V to VMAX at the indicated collector currents.
2 Current gain match (ΔhFE) is defined as follows: ΔhFE = (100(ΔIB)(hFE min)/IC).
3 Noise voltage density is guaranteed, but not 100% tested.
Table 3‘ Am ESD [:Iemosmic disKhargl) sensitiv: de (havged devmes and ("cm board; (an amnayge wuhom dewecnon Akhough ms pmduu feawves pmmed 0v pmpnemy pmaman ("(umy. damage may cum on dewce: xub‘ened w mgn enevgy ESD Therefove, pmpev [SD pvmumng :hculd he (aken m avmd perfovmanze degvadanon or ‘05: of funcuonamy
Data Sheet SSM2212
Rev. C | Page 5 of 12
ABSOLUTE MAXIMUM RATING
Table 3.
Parameter Rating
Breakdown Voltage of
Collector-to-Base Voltage (BVCBO)
40 V
Breakdown Voltage of
Collector-to-Emitter Voltage (BVCEO)
40 V
Breakdown Voltage of
Collector-to-Collector Voltage (BVCC)
40 V
Breakdown Voltage of
Emitter-to-Emitter Voltage (BVEE)
40 V
Collector Current (IC) 20 mA
Emitter Current (IE) 20 mA
Storage Temperature Range 65°C to +150°C
Operating Temperature Range −40°C to +85°C
Junction Temperature Range
−65°C to +150°C
Lead Temperature (Soldering, 60 sec) 300°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
θ
JA
θ
JC
Unit
8-Lead SOIC (R-8) 120 45 °C/W
16-Lead LFCSP (CP-16-22) 75 4.4 °C/W
ESD CAUTION
SSM2212 Data Sheet
Rev. C | Page 6 of 12
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VCE = 5 V, unless otherwise specified.
CH1 2.00V M4.00s A CH1 15.8V
1
CH1 4.92V p-p
0
9043-002
Figure 3. Low Frequency Noise (0.1 Hz to 10 Hz), IC = 1 mA, Gain = 10,000,000
1k
0.1
1
10
100
0.1 1 10 100 1k 10k 100k
NOISE VOLTAGE DENSITY (nV/ Hz)
FREQUENCY (Hz)
I
C
= 1mA TEST
I
C
= 10µA TEST
I
C
= 1µA TEST
09043-003
Figure 4. Noise Voltage Density vs. Frequency
100
0
20
40
60
80
0.001 10.10.01
TOTAL NOISE (nV/ Hz)
COLLECTOR CURRENT, I
C
(mA)
R
S
= 100k
R
S
= 10k
R
S
= 1k
09043-004
Figure 5. Total Noise vs. Collector Current, f = 1 kHz
900
800
700
600
500
400
300
200
100
0.001 10.10.01
CURRENT GAIN (h
FE
)
COLLECTOR CURRENT (mA)
T
A
=+25°C
T
A
= –55°C
T
A
= +125°C
09043-005
Figure 6. Current Gain vs. Collector Current (VCB = 0 V)
900
800
700
600
500
400
300
200
0
100
–100 –50 0 50 100 150
CURRENT GAIN (h
FE
)
TEMPERATURE (°C)
1mA
A
09043-006
Figure 7. Current Gain vs. Temperature (Excludes ICBO)
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0.35
0.30
0.001 0.01 0.1 1 10
BASE EMITTER VOLTAGE, VBE (V)
COLLECTOR CURRENT, IC (mA)
VCE = 5V
09043-008
Figure 8. Base Emitter Voltage vs. Collector Current
Data Sheet SSM2212
Rev. C | Page 7 of 12
100
10
1
0.1
0.01
0.001
0.001 0.01 0.1 110
INPUT RESISTANCE, h
IE
(MΩ)
COLLECTOR CURRENT, I
C
(mA)
V
CE
= 5V
09043-009
Figure 9. Small Signal Input Resistance vs. Collector Current
1m
0.1m
0.01m
0.1µ
0.01µ
0.001 10001001010.10.01
CONDUCTANCE, h
OE
(mho)
COLLECTOR CURRENT, I
C
(mA)
V
CE
= 5V
09043-010
Figure 10. Small Signal Output Conductance vs. Collector Current
0.01
0.1
1
10
100
00.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
COLLECTOR CURRENT, I
C
(mA)
SATURATION VOLTAGE, V
SAT
(V)
T
A
= –55°C
T
A
= +125°C
T
A
= +25°C
09043-017
Figure 11. Collector Current vs. Saturation Voltage
1000
100
10
1
0.1
0.0125 50 75 100 125
CURRENT, I
CBO
(nA)
TEMPERATURE (°C)
09043-012
Figure 12. Collector-to-Base Leakage Current vs. Temperature
40
35
30
25
20
15
10
5
0010 20 30 40 50
CAPACITANCE, CCB (pF)
REVERSE BIAS VOLTAGE (V)
09043-013
Figure 13. Collector-to-Base Capacitance vs. Reverse Bias Voltage
40
35
30
25
20
15
10
5
0010 20 30 40 50
CAPACITANCE, CCC (pF)
COLLECTOR-TO-SUBSTRATE VOLTAGE (V)
09043-014
Figure 14. Collector-to-Collector Capacitance vs.
Collector-to-Substrate Voltage
SSM2212 Data Sheet
Rev. C | Page 8 of 12
1000
100
10
1
0.1
0.0125 50 75 100 125
CURRENT, I
CC
(nA)
TEMPERATURE (°C)
09043-015
Figure 15. Collector-to-Collector Leakage Current vs. Temperature
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0010 20 30 40 50
CAPACITANCE, CCC (pF)
REVERSE BIAS VOLTAGE (V)
09043-016
Figure 16. Collector-to-Collector Capacitance vs. Reverse Bias Voltage
jjjj DUDE
Data Sheet SSM2212
Rev. C | Page 9 of 12
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
C
11
B
12
E
13
NIC
4
C
2
8
B
2
7
E
2
6
NIC
5
SSM2212
TOP VIEW
(Not to Scale)
09043-021
NOTES
1. NIC = NO INTERNAL CONNECTION.
Figure 17. SOIC Pin Configuration
Table 5. SOIC Pin Function Descriptions
Pin No. Mnemonic Description
1 C1 Collector of Channel 1.
2 B1 Base of Channel 1.
3 E1 Emitter of Channel 1.
4, 5 NIC No Internal Connection.
6 E2 Emitter of Channel 2.
7 B2 Base of Channel 2.
8 C2 Collector of Channel 2.
09043-022
12
11
10
1
3
49
2
6
5
7
8
16
15
14
13
E
1A
E
1B
E
2B
E
2A
NIC
C
1
NIC
B
1
NIC
C
2
NIC
NIC
NIC
B
2
NIC
NIC
NOTES
1. NIC = NO INTERNAL CONNECTION.
2. EXPOSED PAD. THE EXPOSED PAD MUST BE
CONNECTED TO THE LOWEST POTENTIAL.
SSM2212
TOP VIEW
(Not to Scale)
Figure 18. LFCSP Pin Configuration
Table 6. LFCSP Pin Function Descriptions
Pin No. Mnemonic Description
1 E1A Emitter of Channel 1. Must be connect to E1B.
2 E1B Emitter of Channel 1. Must be connect to E1A.
3 E2B Emitter of Channel 2. Must be connect to E2A.
4 E2A Emitter of Channel 2. Must be connect to E2B.
5, 7, 8, 9, 10, 12, 14, 16 NIC No Internal Connection.
6 B2 Base of Channel 2.
11 C2 Collector of Channel 2.
13 C1 Collector of Channel 1.
15 B1 Base of Channel 1.
EPAD Exposed Pad. The exposed pad must be connected to the lowest potential.
“1 4m
SSM2212 Data Sheet
Rev. C | Page 10 of 12
APPLICATIONS INFORMATION
FAST LOGARITHMIC AMPLIFIER
The circuit in Figure 19 is a modification of a standard
logarithmic amplifier configuration. Running the SSM2212 at
2.5 mA per side (full scale) allows a fast response with a wide
dynamic range. The circuit has a 7 decade current range and a
5 decade voltage range, and it is capable of 2.5 µs settling time to
1% with a 1 V to 10 V step. The output follows the equation:
IN
REF
O
V
V
q
kT
R
RR
Vln
2
23 +
=
To compensate for the temperature dependence of the kT/q term, a
resistor with a positive 0.35%/°C temperature coefficient is chosen
for R2. The output is inverted with respect to the input and is
nominally −1 V/decade using the component values indicated.
1
4
3
28
7
5
6
–15V
330pF
R
3
7.5kΩ
R
2
500Ω
R
2
= TEL LABS QB1E (+0.35%/°C)
330pF
V
O
+15V
R
S
4kΩ
R
1
4kΩ
4kΩ
V
IN
(0V TO 10V)
V
REF
10V
1/2
AD8512
SSM2212
1/2
AD8512
09043-018
Figure 19. Fast Logarithmic Amplifier
, 5.00 10.1 m) HHHH’ ORDERING GUIDE
Data Sheet SSM2212
Rev. C | Page 11 of 12
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AA
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
8 5
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 20. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters (and inches)
3.10
3.00 SQ
2.90
0.30
0.23
0.18
1.75
1.60 SQ
1.45
08-16-2010-E
1
0.50
BSC
BOTTOM VIEWTOP VIEW
16
5
8
9
12
13
4
EXPOSED
PAD
PIN 1
INDICATOR
0.50
0.40
0.30
SEATING
PLANE
0.05 MAX
0.02 NOM
0.20 REF
0.25 MIN
COPLANARITY
0.08
PIN 1
INDICATOR
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.80
0.75
0.70
COMPLIANT
TO
JEDEC STANDARDS MO-220-WEED-6.
Figure 21. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
3 mm × 3 mm Body, Very Very Thin Quad
(CP-16-22)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option Branding
SSM2212RZ 40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
SSM2212RZ-R7 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
SSM2212RZ-RL −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
SSM2212CPZ-R7
−40°C to +85°C
16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
CP-16-22
A3F
SSM2212CPZ-RL −40°C to +85°C 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-16-22 A3F
1 Z = RoHS Compliant Part.
momilms Analug Dam, mun vigmx .mmd.1ndemukx ind ANALOG DEVICES www.analog.cnm
SSM2212 Data Sheet
Rev. C | Page 12 of 12
NOTES
©20102015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09043-0-6/15(C)

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