MAT12 Datasheet by Analog Devices Inc.

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ANALOG DEVICES
Audio, Dual-Matched
NPN Transistor
Data Sheet MAT12
Rev. A Document Feedbac
k
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2010–2014 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
Very low voltage noise: 1 nV/√Hz maximum at 100 Hz
Excellent current gain match: 0.5% typical
Low offset voltage (VOS): 200 μV maximum
Outstanding offset voltage drift: 0.03 μV/°C typical
High gain bandwidth product: 200 MHz
PIN CONFIGURATION
NOTE
1. SUBSTRATE IS CONNECTED
TO CASE ON TO-78 PACKAGE.
2
. SUBSTRATE IS NORMALLY
CONNECTED TO THE MOS
T
NEGATIVE CIRCUIT POTENTIAL,
BUT CAN BE FLOATED.
09044-001
C
1
E
1
B
1
C
2
E
2
B
2
16
25
34
Figure 1. 6-Lead TO-78
GENERAL DESCRIPTION
The MAT12 is a dual, NPN-matched transistor pair that is
specifically designed to meet the requirements of ultralow
noise audio systems.
With its extremely low input base spreading resistance (rbb'
is typically 28 Ω) and high current gain (hFE typically exceeds
600 at IC = 1 mA), the MAT12 can achieve outstanding signal-
to-noise ratios. The high current gain results in superior
performance compared to systems incorporating commercially
available monolithic amplifiers.
Excellent matching of the current gain (ΔhFE) to about 0.5%
and low VOS of less than 10 μV typical make the MAT12 ideal
for symmetrically balanced designs, which reduce high-order
amplifier harmonic distortion.
Stability of the matching parameters is guaranteed by protection
diodes across the base emitter junction. These diodes prevent
degradation of beta and matching characteristics due to reverse
biasing of the base emitter junction.
The MAT12 is also an ideal choice for accurate and reliable
current biasing and mirroring circuits. Furthermore, because
the accuracy of a current mirror degrades exponentially with
mismatches of VBE between transistor pairs, the low VOS of
the MAT12 does not need offset trimming in most circuit
applications.
The MAT12 is a good replacement for the MAT02, and its
performance and characteristics are guaranteed over the
extended temperature range of −40°C to +85°C.
MAT12 Data Sheet
Rev. A | Page 2 of 12
TABLE OF CONTENTS
Features .............................................................................................. 1
Pin Configuration ............................................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics ............................................................. 3
Absolute Maximum Ratings ............................................................ 4
Thermal Resistance .......................................................................4
ESD Caution...................................................................................4
Typical Performance Characteristics ..............................................5
Applications Information .................................................................8
Fast Logarithmic Amplifier ..........................................................8
Outline Dimensions ....................................................................... 10
Ordering Guide .......................................................................... 10
REVISION HISTORY
1/14—Re v. 0 to Re v. A
Change to Gain Bandwidth Product Parameter ........................... 3
7/10—Revision 0: Initial Version
Data Sheet MAT12
Rev. A | Page 3 of 12
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VCB = 15 V, IO = 10 µA, TA = 25°C, unless otherwise specified.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
DC AND AC CHARACTERISTICS
Current Gain1 hFE IC = 1 mA 300 605
−40°C ≤ TA ≤ +85°C 300
I
C
= 10 µA
200
550
−40°C ≤ TA ≤ +85°C 200
Current Gain Match2 ΔhFE 10 µA ≤ IC ≤ 1 mA 0.5 5 %
Noise Voltage Density3 eN IC = 1 mA, VCB = 0 V
fO = 10 Hz 1.6 2 nV/√Hz
fO = 100 Hz 0.9 1 nV/√Hz
fO = 1 kHz 0.85 1 nV/√Hz
fO = 10 kHz 0.85 1 nV/√Hz
Low Frequency Noise (0.1 Hz to 10 Hz) eN p-p IC = 1 mA 0.4 µV p-p
Offset Voltage VOS VCB = 0 V, IC = 1 mA 10 200 µV
−40°C ≤ TA ≤ +85°C 220 µV
Offset Voltage Change vs. V
CB
ΔV
OS
/ΔV
CB
0 V ≤ V
CB
≤ V
MAX
4,1 µA ≤ I
C
≤ 1 mA5
10
µV
Offset Voltage Change vs. IC ΔVOS/ΔIC 1 µA ≤ IC ≤ 1 mA5, VCB = 0 V 5 70 µV
Offset Voltage Drift ΔVOS/ΔT −40°C ≤ TA ≤ +85°C 0.08 1 µV/°C
−40°C ≤ TA +85°C, VOS trimmed to 0 V 0.03 0.3 µV/°C
Breakdown Voltage, Collector to Emitter BVCEO 40 V
Gain Bandwidth Product fT IC = 10 mA, VCE = 10 V 200 MHz
Collector-to-Base Leakage Current ICBO VCB = VMAX 25 500 pA
−40°C ≤ TA ≤ +85°C 3 nA
Collector-to-Collector Leakage Current6, 7 ICC VCC = VMAX 35 500 pA
−40°C ≤ TA ≤ +85°C 4 nA
Collector-to-Emitter Leakage Current6, 7 ICES VCE = VMAX, VBE = 0 V 35 500 pA
−40°C ≤ T
A
≤ +85°C
4
nA
Input Bias Current IB IC = 10 µA 50 nA
−40°C ≤ TA ≤ +85°C 50 nA
Input Offset Current IOS IC = 10 µA 6.2 nA
−40°C ≤ TA ≤ +85°C 13 nA
Input Offset Current Drift6 ΔIOS/ΔT IC = 10 µA, −40°C ≤ TA ≤ +85°C 40 150 pA/°C
Collector Saturation Voltage
V
CE (S AT )
I
C
= 1 mA, I
B
= 100 µA
0.05
V
Output Capacitance COB VCB = 15 V, IE = 0 µA 23 pF
Bulk Resistance6 RBE 10 µA ≤ IC ≤ 10 mA 0.3 1.6 Ω
Collector-to-Collector Capacitance CCC VCC = 0 V 35 pF
1 Current gain is guaranteed with collector-to-base voltage (VCB) swept from 0 V to VMAX at the indicated collector currents.
2 Current gain match (ΔhFE) is defined as follows: ΔhFE = (100(ΔIB)(hFE min)/IC).
3 Noise voltage density is guaranteed, but not 100% tested.
4 This is the maximum change in VOS as VCB is swept from 0 V to 40 V.
5 Measured at IC = 10 µA and guaranteed by design over the specified range of IC.
6 Guaranteed by design.
7 ICC and ICES are verified by the measurement of ICBO.
m ESD [electrostatic dinharge) sensitive device, Charged devizes and mm beards (an distharge wuhoui deiemon Aimaugh (his praduu €eamres paiemeg or pmprieiavy pmiemgn (Irwiivy, damage may new on devi
MAT12 Data Sheet
Rev. A | Page 4 of 12
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Breakdown Voltage of
Collector-to-Base Voltage (BVCBO)
40 V
Breakdown Voltage of
Collector-to-Emitter Voltage (BVCEO)
40 V
Breakdown Voltage of
Collector-to-Collector Voltage (BVCC)
40 V
Breakdown Voltage of
Emitter-to-Emitter Voltage (BVEE)
40 V
Collector Current (IC) 20 mA
Emitter Current (IE) 20 mA
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +85°C
Junction Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 60 sec) 300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type θJA θJC Unit
6-Lead TO-78 150 45 °C/W
ESD CAUTION
WWW % cm 1 W k ( 5=1akfl ns=1m =5»!
Data Sheet MAT12
Rev. A | Page 5 of 12
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VCE = 5 V, unless otherwise specified.
CH1 2.00V M4.00s
A CH1 15.8V
1
CH1 4.92V p-p
09044-002
Figure 2. Low Frequency Noise (0.1 Hz to 10 Hz), IC = 1 mA, Gain = 10,000,000
1k
0.1
1
10
100
0.1 110 100 1k 10k 100k
NOISE VOLTAGE DENSITY (nV/ Hz)
FREQUENCY (Hz)
I
C
= 1mA TEST
I
C
= 10µA TEST
I
C
= 1µA TEST
09044-003
Figure 3. Noise Voltage Density vs. Frequency
100
0
20
40
60
80
0.001 10.10.01
TOTAL NOISE (nV/ Hz)
COLLECTOR CURRENT, I
C
(mA)
R
S
= 100kΩ
R
S
= 10kΩ
R
S
= 1kΩ
09044-004
Figure 4. Total Noise vs. Collector Current, f = 1 kHz
900
800
700
600
500
400
300
200
100
0.001 10.10.01
CURRENT GAIN (hFE)
COLLECTOR CURRENT (mA)
TA = +25°C
TA = –55°C
TA = +125°C
09044-005
Figure 5. Current Gain vs. Collector Current (VCB = 0 V)
900
800
700
600
500
400
300
200
0
100
–100 –50 050 100 150
CURRENT GAIN (hFE)
TEMPERATURE (°C)
1mA
A
09044-006
Figure 6. Current Gain vs. Temperature (Excludes ICBO)
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0.35
0.30
0.001 0.01 0.1 110
BASE EMITTER VOLTAGE, V
BE
(V)
COLLECTOR CURRENT, I
C
(mA)
V
CE
= 5V
09044-007
Figure 7. Base Emitter Voltage vs. Collector Current
MAT12 Data Sheet
Rev. A | Page 6 of 12
100
10
1
0.1
0.01
0.001
0.001 0.01 0.1 110
INPUT RESISTANCE, h
IE
(MΩ)
COLLECTOR CURRENT, I
C
(mA)
V
CE
= 5V
09044-008
Figure 8. Small Signal Input Resistance vs. Collector Current
1m
0.1m
0.01m
0.1µ
0.01µ
0.001 10001001010.10.01
CONDUCTANCE, h
OE
(mho)
COLLECTOR CURRENT, I
C
(mA)
V
CE
= 5V
09044-009
Figure 9. Small Signal Output Conductance vs. Collector Current
0.01
0.1
1
10
100
00.1 0.2 0.30.4 0.5 0.6 0.7 0.8 0.9
COLLECTOR CURRENT, I
C
(mA)
SATURATION VOLTAGE, V
SAT
(V)
TA
= –55°C
TA
= +125°C
TA
= +25°C
09044-018
Figure 10. Collector Current vs. Saturation Voltage
1000
100
10
1
0.1
0.0125 50 75 100 125
CURRENT, ICBO (nA)
TEMPERATURE (°C)
09044-010
Figure 11. Collector-to-Base Leakage Current vs. Temperature
40
35
30
25
20
15
10
5
0010 20 30 40 50
CAPACITANCE, C
CB
(pF)
REVERSE BIAS VOLTAGE (V)
09044-011
Figure 12. Collector-to-Base Capacitance vs. Reverse Bias Voltage
40
35
30
25
20
15
10
5
0010 20 30 40 50
CAPACITANCE, C
CC
(pF)
COLLECTOR-TO-SUBSTRATE VOLTAGE (V)
09044-012
Figure 13. Collector-to-Collector Capacitance vs.
Collector-to-Substrate Voltage
Data Sheet MAT12
Rev. A | Page 7 of 12
1000
100
10
1
0.1
0.0125 50 75 100 125
COLLECTOR-TO-COLLECTOR
LEAKAGE CURRENT, I
CC
(nA)
TEMPERATURE (°C)
09044-013
Figure 14. Collector-to-Collector Leakage Current vs. Temperature
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0010 20 30 40 50
COLLECTOR-TO-COLLECTOR
CAPACITANCE, C
CC
(pF)
REVERSE BIAS VOLTAGE (V)
09044-014
Figure 15. Collector-to-Collector Capacitance vs. Reverse Bias Voltage
«n .usv
MAT12 Data Sheet
Rev. A | Page 8 of 12
APPLICATIONS INFORMATION
FAST LOGARITHMIC AMPLIFIER
The circuit of Figure 16 is a modification of a standard logarith-
mic amplifier configuration. Running the MAT12 at 2.5 mA per
side (full scale) allows for a fast response with a wide dynamic
range. The circuit has a seven decade current range and a five
decade voltage range, and it is capable of 2.5 µs settling time to
1% with a 1 V to 10 V step. The output follows the equation:
IN
REF
2
23
O
V
V
q
kT
R
RR
Vln
+
=
To compensate for the temperature dependence of the kT/q term, a
resistor with a positive 0.35%/°C temperature coefficient is selected
for R2. The output is inverted with respect to the input and is
nominally −1 V/decade using the component values indicated.
1
4
3
28
7
5
6
–15V
330pF
R
3
7.5kΩ
R
2
500Ω
R
2
= 0.35%/°C
330pF
V
O
+15V
R
S
4kΩ
R
1
4kΩ
4kΩ
V
IN
(0V TO 10V)
V
REF
10V
AD8512
MAT12
1/2
AD8512
09044-015
Figure 16. Fast Logarithmic Amplifier
Data Sheet MAT12
Rev. A | Page 9 of 12
LOG CONFORMANCE TESTING
The log conformance of the MAT12 is tested using the circuit
shown in Figure 18. The circuit employs a dual transdiode
logarithmic converter operating at a fixed ratio of collector
currents that are swept over a 10:1 range. The output of each
transdiode converter is the VBE of the transistor plus an error
term, which is the product of the collector current and rBE, the
bulk emitter resistance. The difference of the VBE is amplified at
a gain of ×100 by the AMP02 instrumentation amplifier. The
differential emitter base voltage (∆VBE) consists of a temperature-
dependent dc level plus an ac error voltage, which is the deviation
from true log conformity as the collector currents vary.
The output of the transdiode logarithmic converter comes from
the following idealized intrinsic transistor equation (for silicon)
S
C
BE I
I
q
kT
Vln=
(1)
where:
k is Boltzmanns constant (1.38062 × 1023 J/K).
q is the unit electron charge (1.60219 × 1019°C).
T is the absolute temperature, K (= °C + 273.2).
IS is the extrapolated current for VBE → 0 (VBE tending to zero).
IC is the collector current.
An error term must be added to Equation 1 to allow for the
bulk resistance (rBE) of the transistor. Error due to the op amp
input current is limited by use of the AD8512 dual op amp. The
resulting AMP02 input is:
BE2
C2
BE1
C1
C2
C1
BE rI
rI
I
I
q
kT
V
+=
=ln
(2)
A ramp function that sweeps from 1 V to 10 V is converted by
the op amps to a collector current ramp through each transistor.
Because IC1 is made equal to 10 IC2, and assuming TA = 25°C,
Equation 2 becomes
∆VBE = 59 mV + 0.9 IC1 rBE (∆rBE ~ 0)
As viewed on an oscilloscope, the change in ∆VBE for a 10:1
change in IC is shown in Figure 17.
09044-016
61.5
61.0
60.5
60.0
59.5
59.0
58.5
110 100
COLLECTOR CURRENT (mA)
LOGGING ERROR,ΔV
BE
(mV)
Figure 17. Emitter Base, Log Conformity
With the oscilloscope ac-coupled, the temperature dependent
term becomes a dc offset and the trace represents the deviation
from true log conformity. The bulk resistance can be calculated
from the voltage deviation, ∆VO, and the change in collector
current (9 mA):
100
1
mA9
×
=
O
BE
V
r
(3)
This procedure solves for rBE for Side A. Switching R1 and R2
provides the rBE for Side B. Differential rBE is found by making
R1 = R2.
–15V
+15V
AMP02 V
OUT
= 100ΔV
BE
A
V
= 100
–15V
100pF
+15V
500
1N914
V
BE
V
BE
1kI
C1
I
C2
SIDE A DUT
Q1
V
CC
–15V
100pF
+15V
+
500
1N914
1/2
AD8512
1/2
AD8512
1k
SIDE B DUT
Q2
V
CC
+
09044-017
Figure 18. Log Conformance Circuit
MAT12 Data Sheet
Rev. A | Page 10 of 12
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONSARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
0.250 (6.35) MIN
0.750 (19.05)
0.500 (12.70)
0.185 (4.70)
0.165 (4.19)
REFERENCE PLANE
0.050 (1.27) MAX
0.019 (0.48)
0.016 (0.41)
0.021 (0.53)
0.016 (0.41)
0.045 (1.14)
0.010 (0.25)
0.040 (1.02) MAX
BASE & SEATING PLANE
0.335 (8.51)
0.305 (7.75)
0.370 (9.40)
0.335 (8.51)
0.034 (0.86)
0.027 (0.69)
0.160 (4.06)
0.110 (2.79)
0.100 (2.54) BSC
5
2
6
4
3
1
0.200
(5.08)
BSC
0.100
(2.54)
BSC
45°
BSC
0.045 (1.14)
0.027 (0.69)
022306-A
Figure 19. 6-Pin Metal Header Package [TO-78]
(H-06)
Dimensions shown in inches and (millimeters)
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
MAT12AHZ 40°C to +85°C 6-Pin Metal Header Package [TO-78] H-06
1 Z = RoHS Compliant Part.
Data Sheet MAT12
Rev. A | Page 11 of 12
NOTES
ANALOG DEVICES www.analug.cum
MAT12 Data Sheet
Rev. A | Page 12 of 12
NOTES
©20102014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09044-0-1/14(A)

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