STM32W108HB,CC,CB,CZ Datasheet by STMicroelectronics

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This is information on a product still in production but not recommended for new designs.
March 2015 DocID16252 Rev 16 1/289
STM32W108HB STM32W108CB
STM32W108CC STM32W108CZ
High-performance, IEEE 802.15.4 wireless system-on-chip with up
to 256 Kbyte of embedded Flash memory
Datasheet - not recommended for new design
Features
Complete system-on-chip
32-bit ARM® Cortex®-M3 processor
2.4 GHz IEEE 802.15.4 transceiver and
lower MAC
128/192/256-Kbyte Flash, 8/12/16-Kbyte
RAM memory
AES128 encryption accelerator
Flexible ADC, SPI/UART/I2C serial
communications, and general-purpose
timers
24 highly configurable GPIOs with Schmitt
trigger inputs
Industry-leading ARM® Cortex®-M3 processor
Leading 32-bit processing performance
Highly efficient Thumb®-2 instruction set
Operation at 6, 12 or 24 MHz
Flexible nested vectored interrupt controller
Low power consumption, advanced
management
Receive current (w/ CPU): 27 mA
Transmit current (w/ CPU, +3 dBm TX):
31 mA
Low deep sleep current, with retained RAM
and GPIO: 400 nA/800 nA with/without
sleep timer
Low-frequency internal RC oscillator for
low-power sleep timing
High-frequency internal RC oscillator for
fast (100 µs) processor start-up from sleep
Exceptional RF performance
Normal mode link budget up to 102 dB;
configurable up to 107 dB
-99 dBm normal RX sensitivity;
configurable to -100 dBm (1% PER,
20 byte packet)
+3 dB normal mode output power;
configurable up to +8 dBm
Robust WiFi and Bluetooth coexistence
Innovative network and processor debug
Non-intrusive hardware packet trace
Serial wire/JTAG interface
Standard ARM debug capabilities: Flash
patch and breakpoint; data watchpoint and
trace; instrumentation trace macrocell
Application flexibility
Single voltage operation: 2.1-3.6 V with
internal 1.8 V and 1.25 V regulators
Optional 32.768 kHz crystal for higher timer
accuracy
Low external component count with single
24 MHz crystal
Support for external power amplifier
Small 7x7 mm 48-pin VFQFPN and
UFQFPN packages or 6x6 mm 40-pin
VFQFPN package
Applications
Smart energy
Building automation and control
Home automation and control
Security and monitoring
ZigBee® Pro wireless sensor networking
RF4CE products and remote controls
VFQFPN46 (6 x 6 mm)
UFQFPN48 (7 x 7 mm)
VFQFPN48 (7 x 7 mm)
www.st.com
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Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.1 Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.2.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.2.2 ARM® Cortex®-M3 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2 Documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3 Pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4 Embedded memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.1 Memory organization and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.2 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.3 Random-access memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.3.1 Direct memory access (DMA) to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.3.2 RAM memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.3.3 Memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.3.4 Memory controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.4 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5 Radio frequency module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.1 Receive (Rx) path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.1.1 Rx baseband . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.1.2 RSSI and CCA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.2 Transmit (Tx) path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.2.1 Tx baseband . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.2.2 TX_ACTIVE and nTX_ACTIVE signals . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.3 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.4 Integrated MAC module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.5 Packet trace interface (PTI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.6 Random number generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6 System modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
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6.1 Power domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.1.1 Internally regulated power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.1.2 Externally regulated power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.2 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.2.1 Reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.2.2 Reset recording . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.2.3 Reset generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.2.4 Reset register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.3 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.3.1 High-frequency internal RC oscillator (HSI) . . . . . . . . . . . . . . . . . . . . . . 55
6.3.2 High-frequency crystal oscillator (HSE OSC) . . . . . . . . . . . . . . . . . . . . 55
6.3.3 Low-frequency internal RC oscillator (LSI10K) . . . . . . . . . . . . . . . . . . . 55
6.3.4 Low-frequency crystal oscillator (LSE OSC) . . . . . . . . . . . . . . . . . . . . . 55
6.3.5 Clock switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.3.6 Clock switching registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.4 System timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.4.1 MAC timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.4.2 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.4.3 Sleep timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.4.4 Event timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.4.5 Slow timer (MAC timer, Watchdog, and Sleeptimer) control and status
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.5 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.5.1 Wake sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.5.2 Basic sleep modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.5.3 Further options for deep sleep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.5.4 Use of debugger with sleep modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.5.5 Power management registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.6 Security accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
7 Integrated voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
8 General-purpose input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
8.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
8.1.1 GPIO ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
8.1.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
8.1.3 Forced functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
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8.1.4 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
8.1.5 nBOOTMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
8.1.6 GPIO modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
8.1.7 Wake monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
8.2 External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
8.3 Debug control and status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
8.4 GPIO alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
8.5 General-purpose input/output (GPIO) registers . . . . . . . . . . . . . . . . . . . 101
8.5.1 Port x configuration register (Low) (GPIOx_CRL) . . . . . . . . . . . . . . . . 101
8.5.2 Port x configuration register (High) (GPIOx_CRH) . . . . . . . . . . . . . . . 102
8.5.3 Port x input data register (GPIOx_IDR) . . . . . . . . . . . . . . . . . . . . . . . . 103
8.5.4 Port x output data register (GPIOx_ODR) . . . . . . . . . . . . . . . . . . . . . . 103
8.5.5 Port x output set register (GPIOx_BSR) . . . . . . . . . . . . . . . . . . . . . . . 104
8.5.6 Port x output clear register (GPIOx_BRR) . . . . . . . . . . . . . . . . . . . . . . 104
8.5.7 External interrupt pending register (EXTI_PR) . . . . . . . . . . . . . . . . . . 105
8.5.8 External interrupt x trigger selection register (EXTIx_TSR) . . . . . . . . . 105
8.5.9 External interrupt x configuration register (EXTIx_CR) . . . . . . . . . . . . 106
8.5.10 PC TRACE or debug select register (GPIO_PCTRACECR) . . . . . . . . 106
8.5.11 GPIO debug configuration register (GPIO_DBGCR) . . . . . . . . . . . . . . 107
8.5.12 GPIO debug status register (GPIO_DBGSR) . . . . . . . . . . . . . . . . . . . 107
8.5.13 General-purpose input/output (GPIO) register map . . . . . . . . . . . . . . . 108
9 Serial interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
9.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
9.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
9.3 SPI master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
9.3.1 Setup and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
9.3.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
9.3.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
9.4 SPI slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
9.4.1 Setup and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
9.4.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
9.4.3 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
9.4.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
9.5 Inter-integrated circuit interfaces (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . .119
9.5.1 Setup and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
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9.5.2 Constructing frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
9.5.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
9.6 Universal asynchronous receiver/transmitter (UART) . . . . . . . . . . . . . . 123
9.6.1 Setup and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
9.6.2 FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
9.6.3 RTS/CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
9.6.4 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
9.6.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
9.7 Direct memory access (DMA) channels . . . . . . . . . . . . . . . . . . . . . . . . . 127
9.8 Serial controller common registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
9.8.1 Serial controller interrupt status register (SCx_ISR) . . . . . . . . . . . . . . 129
9.8.2 Serial controller interrupt enable register (SCx_IER) . . . . . . . . . . . . . . 131
9.8.3 Serial controller interrupt control register 1 (SCx_ICR) . . . . . . . . . . . . 133
9.8.4 Serial controller data register (SCx_DR) . . . . . . . . . . . . . . . . . . . . . . . 134
9.8.5 Serial controller control register 2 (SCx_CR) . . . . . . . . . . . . . . . . . . . . 134
9.8.6 Serial controller clock rate register 1 (SCx_CRR1) . . . . . . . . . . . . . . . 135
9.8.7 Serial controller clock rate register 2 (SCx_CRR2) . . . . . . . . . . . . . . . 135
9.9 Serial controller: Serial peripheral interface (SPI) registers . . . . . . . . . . 136
9.9.1 Serial controller SPI status register (SCx_SPISR) . . . . . . . . . . . . . . . . 136
9.9.2 Serial controller SPI control register (SCx_SPICR) . . . . . . . . . . . . . . . 137
9.10 Serial controller: Inter-integrated circuit (I2C) registers . . . . . . . . . . . . . 138
9.10.1 Serial controller I2C status register (SCx_I2CSR) . . . . . . . . . . . . . . . . 138
9.10.2 Serial controller I2C control register 1 (SCx_I2CCR1) . . . . . . . . . . . . 139
9.10.3 Serial controller I2C control register 2 (SCx_I2CCR2) . . . . . . . . . . . . 140
9.11 Serial controller: Universal asynchronous receiver/
transmitter (UART) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
9.11.1 Serial controller UART status register (SC1_UARTSR) . . . . . . . . . . . 141
9.11.2 Serial controller UART control register (SC1_UARTCR) . . . . . . . . . . . 142
9.11.3 Serial controller UART baud rate register 1 (SC1_UARTBRR1) . . . . . 143
9.11.4 Serial controller UART baud rate register 2 (SC1_UARTBRR2) . . . . . 144
9.12 Serial controller: Direct memory access (DMA) registers . . . . . . . . . . . . 145
9.12.1 Serial controller receive DMA begin address channel A register
(SCx_DMARXBEGADDAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
9.12.2 Serial controller receive DMA end address channel A register
(SCx_DMARXENDADDAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
9.12.3 Serial controller receive DMA begin address channel B register
(SCx_ DMARXBEGADDBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
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9.12.4 Serial controller receive DMA end address channel B register
(SCx_DMARXENDADDBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
9.12.5 Serial controller transmit DMA begin address channel A register
(SCx_DMATXBEGADDAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
9.12.6 Serial controller transmit DMA end address channel A register
(SCx_DMATXENDADDAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
9.12.7 Serial controller transmit DMA begin address channel B register
(SCx_DMATXBEGADDBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
9.12.8 Serial controller transmit DMA end address channel B register
(SCx_DMATXENDADDBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
9.12.9 Serial controller receive DMA counter channel A register
(SCx_DMARXCNTAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
9.12.10 Serial controller receive DMA count channel B register
(SCx_DMARXCNTBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
9.12.11 Serial controller transmit DMA counter register
(SCx_DMATXCNTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
9.12.12 Serial controller DMA status register (SCx_DMASR) . . . . . . . . . . . . . 151
9.12.13 Serial controller DMA control register (SCx_DMACR) . . . . . . . . . . . . . 153
9.12.14 Serial controller receive DMA channel A first error register
(SCx_DMARXERRAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
9.12.15 Serial controller receive DMA channel B first error register
(SCx_DMARXERRBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
9.12.16 Serial controller receive DMA saved counter channel B register
(SCx_DMARXCNTSAVEDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
9.12.17 Serial interface (SC1/SC2) register map . . . . . . . . . . . . . . . . . . . . . . . 155
10 General-purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
10.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
10.1.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
10.1.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
10.1.3 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
10.1.4 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
10.1.5 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
10.1.6 PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
10.1.7 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
10.1.8 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
10.1.9 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
10.1.10 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
10.1.11 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
10.1.12 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
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10.1.13 Timers and external trigger synchronization . . . . . . . . . . . . . . . . . . . . 186
10.1.14 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
10.1.15 Timer signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
10.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
10.3 General-purpose timers 1 and 2 registers . . . . . . . . . . . . . . . . . . . . . . . 197
10.3.1 Timer x interrupt and status register (TIMx_ISR) . . . . . . . . . . . . . . . . . 197
10.3.2 Timer x interrupt missed register (TIMx_MISSR) . . . . . . . . . . . . . . . . . 198
10.3.3 Timer x interrupt enable register (TIMx_IER) . . . . . . . . . . . . . . . . . . . . 198
10.3.4 Timer x control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . 199
10.3.5 Timer x control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . 201
10.3.6 Timer x slave mode control register (TIMx_SMCR) . . . . . . . . . . . . . . . 202
10.3.7 Timer x event generation register (TIMx_EGR) . . . . . . . . . . . . . . . . . . 205
10.3.8 Timer x capture/compare mode register 1 (TIMx_CCMR1) . . . . . . . . . 206
10.3.9 Timer x capture/compare mode register 2 (TIMx_CCMR2) . . . . . . . . . 210
10.3.10 Timer x capture/compare enable register (TIMx_CCER) . . . . . . . . . . . 214
10.3.11 Timer x counter register (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . 215
10.3.12 Timer x prescaler register (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . 215
10.3.13 Timer x auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . . . . 216
10.3.14 Timer x capture/compare 1 register (TIMx_CCR1) . . . . . . . . . . . . . . . 216
10.3.15 Timer x capture/compare 2 register (TIMx_CCR2) . . . . . . . . . . . . . . . 217
10.3.16 Timer x capture/compare 3 register (TIMx_CCR3) . . . . . . . . . . . . . . . 217
10.3.17 Timer x capture/compare 4 register (TIMx_CCR4) . . . . . . . . . . . . . . . 218
10.3.18 Timer 1 option register (TIM1_OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
10.3.19 Timer 2 option register (TIM2_OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
10.3.20 General-purpose timers 1 and 2 (TIM1/TIM2) register map . . . . . . . . 220
11 Analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
11.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
11.1.1 Setup and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
11.1.2 GPIO usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
11.1.3 Voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
11.1.4 Offset/gain correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
11.1.5 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
11.1.6 ADC configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
11.1.7 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
11.1.8 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
11.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
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11.3 Analog-to-digital converter (ADC) registers . . . . . . . . . . . . . . . . . . . . . . 233
11.3.1 ADC interrupt status register (ADC_ISR) . . . . . . . . . . . . . . . . . . . . . . 233
11.3.2 ADC interrupt enable register (ADC_IER) . . . . . . . . . . . . . . . . . . . . . . 233
11.3.3 ADC control register (ADC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
11.3.4 ADC offset register (ADC_OFFSETR) . . . . . . . . . . . . . . . . . . . . . . . . . 235
11.3.5 ADC gain register (ADC_GAINR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
11.3.6 ADC DMA control register (ADC_DMACR) . . . . . . . . . . . . . . . . . . . . . 236
11.3.7 ADC DMA status register (ADC_DMASR) . . . . . . . . . . . . . . . . . . . . . . 236
11.3.8 ADC DMA memory start address register (ADC_DMAMSAR) . . . . . . 237
11.3.9 ADC DMA number of data to transfer register (ADC_DMANDTR) . . . 237
11.3.10 ADC DMA memory next address register (ADC_DMAMNAR) . . . . . . 238
11.3.11 ADC DMA count number of data transferred register
(ADC_DMACNDTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
11.3.12 Analog-to-digital converter (ADC) register map . . . . . . . . . . . . . . . . . . 239
12 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
12.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 241
12.2 Management interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
12.2.1 Management interrupt source register (MGMT_ISR) . . . . . . . . . . . . . 243
12.2.2 Management interrupt mask register (MGMT_IER) . . . . . . . . . . . . . . . 244
12.2.3 Management interrupt (MGMT) register map . . . . . . . . . . . . . . . . . . . 244
13 Debug support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
13.1 STM32W108 JTAG TAP connection . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
14 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
14.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
14.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
14.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
14.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
14.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
14.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
14.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
14.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
14.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
14.3.2 Operating conditions at power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
14.3.3 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 250
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14.4 SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
14.5 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
14.6 Clock frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
14.6.1 High frequency internal clock characteristics . . . . . . . . . . . . . . . . . . . . 259
14.6.2 High frequency external clock characteristics . . . . . . . . . . . . . . . . . . . 259
14.6.3 Low frequency internal clock characteristics . . . . . . . . . . . . . . . . . . . . 260
14.6.4 Low frequency external clock characteristics . . . . . . . . . . . . . . . . . . . 260
14.7 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
14.8 Digital I/O specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
14.9 Non-RF system electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 267
14.10 RF electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
14.10.1 Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
14.10.2 Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
14.10.3 Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
15 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
15.1 VFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
15.2 VFQFPN40 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
15.3 UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
16 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
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List of tables
Table 1. Description of abbreviations used for bit field access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 2. Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 3. STM32W108xx peripheral register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 4. Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 5. MEM register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 6. Generated resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 7. RST register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 8. System clock modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 9. CLK register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 10. MACTMR, WDG, and SLPTMR register map and reset values . . . . . . . . . . . . . . . . . . . . . 73
Table 11. PWR register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 12. 1.8 V integrated voltage regulator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 13. GPIO configuration modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 14. Timer 2 output configuration controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 15. GPIO forced functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 16. IRQC/D GPIO selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 17. GPIO signal assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 18. GPIO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 19. SC1 GPIO usage and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 20. SC2 GPIO usage and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 21. SPI master GPIO usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 22. SPI master mode formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 23. SPI slave GPIO usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 24. SPI slave mode formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 25. I2C Master GPIO Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 26. I2C clock rate programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 27. I2C master frame segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 28. UART GPIO usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 29. UART baud rate divisors for common baud rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 30. UART RTS/CTS flow control configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Table 31. SC1/SC2 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 32. Timer GPIO use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 33. EXTRIGSEL clock signal selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Table 34. Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Table 35. Timer signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Table 36. TIM1/TIM2 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Table 37. ADC GPIO pin usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Table 38. ADC inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Table 39. Typical ADC input configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Table 40. ADC sample times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Table 41. ADC gain and offset correction equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Table 42. ADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Table 43. NVIC exception table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Table 44. MGMT register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Table 45. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Table 46. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Table 47. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Table 48. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
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Table 49. POR HV thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Table 50. POR LVcore thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Table 51. POR LVmem thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Table 52. Reset filter specification for RSTB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Table 53. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Table 54. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Table 55. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Table 56. ADC module key parameters for 1 MHz sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Table 57. ADC module key parameters for input buffer disabled
and 6 MHz sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Table 58. ADC module key parameters for input buffer enabled
and 6MHz sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Table 59. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Table 60. High-frequency RC oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Table 61. High-frequency crystal oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Table 62. Low-frequency RC oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Table 63. Low-frequency crystal oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Table 64. DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Table 65. Digital I/O characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Table 66. Non-RF system electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Table 67. Receive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Table 68. Transmit characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Table 69. Synthesizer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Table 70. VFQFPN48 - 48-pin, 7x7 mm, 0.5 mm pitch very thin profile fine pitch quad
flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Table 71. VFQFPN40 - 40-pin, 6x6 mm, 0.5 mm pitch very thin profile fine pitch quad
flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Table 72. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Table 73. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
List of figures STM32W108HB STM32W108CB STM32W108CC STM32W108CZ
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List of figures
Figure 1. STM32W108xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 2. 48-pin VFQFPN pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 3. 40-pin VFQFPN pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 4. STM32W108xB memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 5. STM32W108CC and STM32W108CZ memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 6. System module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 7. Clocks block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 8. Power management state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 9. GPIO block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 10. Serial controller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 11. I2C segment transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 12. UART character frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 13. UART FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 14. RTS/CTS flow control connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 15. General-purpose timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Figure 16. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 163
Figure 17. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Figure 18. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Figure 19. Counter timing diagram, update event when ARPE = 0
(TIMx_ARR not buffered) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Figure 20. Counter timing diagram, update event when ARPE = 1 (TIMx_ARR buffered) . . . . . . . . 166
Figure 21. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 22. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 23. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . . . . . . . . . . . 168
Figure 24. Counter timing diagram, update event with ARPE = 1
(counter underflow) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Figure 25. Counter timing diagram, update event with ARPE = 1
(counter overflow) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Figure 26. Control circuit in Normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . 170
Figure 27. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 28. Control circuit in External Clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 29. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Figure 30. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Figure 31. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . 173
Figure 32. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Figure 33. Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Figure 34. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 35. Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Figure 36. Edge-aligned PWM waveforms (ARR = 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Figure 37. Center-aligned PWM waveforms (ARR = 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Figure 38. Example of one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Figure 39. Example of counter operation in encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . 184
Figure 40. Example of encoder interface mode with IC1FP1 polarity inverted . . . . . . . . . . . . . . . . . 185
Figure 41. Control circuit in Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Figure 42. Control circuit in Gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Figure 43. Control circuit in Trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Figure 44. Control circuit in External clock mode 2 + Trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . 189
Figure 45. Master/slave timer example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
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Figure 46. Gating Timer 2 with OC1REF of Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Figure 47. Gating Timer 2 with enable of Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Figure 48. Triggering timer 2 with update of Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Figure 49. Triggering Timer 2 with enable of Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Figure 50. Triggering Timers 1 and 2 with Timer 1 TI1 input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Figure 51. ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Figure 52. SWJ block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Figure 53. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Figure 54. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Figure 55. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Figure 56. SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Figure 57. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Figure 58. Transmit power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Figure 59. Transmit output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Figure 60. VFQFPN48 - 48-pin, 7x7 mm, 0.5 mm pitch very thin profile fine pitch quad
flat package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Figure 61. VFQFPN48 - 48-pin, 7x7 mm, 0.5 mm pitch very thin profile fine pitch quad
flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Figure 62. VFQFPN40 - 40-pin, 6x6 mm, 0.5 mm pitch very thin profile fine pitch quad
flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Figure 63. VFQFPN40 - 40-pin, 6x6 mm, 0.5 mm pitch very thin profile fine pitch quad
flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Figure 64. VFQFPN40 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Figure 65. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Figure 66. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Figure 67. UFQFPN48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Description STM32W108HB STM32W108CB STM32W108CC STM32W108CZ
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1 Description
The STM32W108xx is a fully integrated system-on-chip that integrates a 2.4 GHz, IEEE
802.15.4-compliant transceiver, 32-bit ARM® Cortex®-M3 microprocessor, Flash and RAM
memory, and peripherals of use to designers of 802.15.4-based systems.
The transceiver utilizes an efficient architecture that exceeds the dynamic range
requirements imposed by the IEEE 802.15.4-2003 standard by over 15 dB. The integrated
receive channel filtering allows for robust co-existence with other communication standards
in the 2.4 GHz spectrum, such as IEEE 802.11 and Bluetooth. The integrated regulator,
VCO, loop filter, and power amplifier keep the external component count low. An optional
high performance radio mode (boost mode) is software-selectable to boost dynamic range.
The integrated 32-bit ARM® Cortex®-M3 microprocessor is highly optimized for high
performance, low power consumption, and efficient memory utilization. Including an
integrated MPU, it supports two different modes of operation: Privileged mode and
Unprivileged mode. This architecture could be used to separate the networking stack from
the application code and prevent unwanted modification of restricted areas of memory and
registers resulting in increased stability and reliability of deployed solutions.
The STM32W108xx has 128/192/256 Kbyte of embedded Flash memory and 8/12/16 Kbyte
of integrated RAM for data and program storage. The STM32W108xx HAL software
employs an effective wear-leveling algorithm that optimizes the lifetime of the embedded
Flash.
To maintain the strict timing requirements imposed by the ZigBee and IEEE 802.15.4-2003
standards, the STM32W108xx integrates a number of MAC functions into the hardware.
The MAC hardware handles automatic ACK transmission and reception, automatic backoff
delay, and clear channel assessment for transmission, as well as automatic filtering of
received packets. A packet trace interface is also integrated with the MAC, allowing
complete, non-intrusive capture of all packets to and from the STM32W108xx.
The STM32W108xx offers a number of advanced power management features that enable
long battery life. A high-frequency internal RC oscillator allows the processor core to begin
code execution quickly upon waking. Various deep sleep modes are available with less than
1 µA power consumption while retaining RAM contents. To support user-defined
applications, on-chip peripherals include UART, SPI, I2C, ADC and general-purpose timers,
as well as up to 24 GPIOs. Additionally, an integrated voltage regulator, power-on-reset
circuit, and sleep timer are available.
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1.1 Development tools
The STM32W108xx implements both the ARM Serial Wire and JTAG debug interfaces.
These interfaces provide real time, non-intrusive programming and debugging capabilities.
Serial Wire and JTAG provide the same functionality, but are mutually exclusive. The Serial
Wire interface uses two pins; the JTAG interface uses five. Serial Wire is preferred, since it
uses fewer pins.
The STM32W108xx also integrates the standard ARM system debug components: Flash
Patch and Breakpoint (FPB), Data Watchpoint and Trace (DWT), and Instrumentation Trace
Macrocell (DWT).
Figure 1. STM32W108xx block diagram
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Description STM32W108HB STM32W108CB STM32W108CC STM32W108CZ
16/289 DocID16252 Rev 16
1.2 Overview
1.2.1 Functional description
The STM32W108xx radio receiver is a low-IF, super-heterodyne receiver. The architecture
has been chosen to optimize co-existence with other devices in the 2.4 GHz band (namely,
WIFI and Bluetooth), and to minimize power consumption. The receiver uses differential
signal paths to reduce sensitivity to noise interference. Following RF amplification, the
signal is downconverted by an image-rejecting mixer, filtered, and then digitized by an ADC.
The radio transmitter uses an efficient architecture in which the data stream directly
modulates the VCO frequency. An integrated power amplifier (PA) provides the output
power. Digital logic controls Tx path and output power calibration. If the STM32W108xx is to
be used with an external PA, use the TX_ACTIVE or nTX_ACTIVE signal to control the
timing of the external switching logic.
The integrated 4.8 GHz VCO and loop filter minimize off-chip circuitry. Only a 24 MHz
crystal with its loading capacitors is required to establish the PLL local oscillator signal.
The MAC interfaces the on-chip RAM to the Rx and Tx baseband modules. The MAC
provides hardware-based IEEE 802.15.4 packet-level filtering. It supplies an accurate
symbol time base that minimizes the synchronization effort of the software stack and meets
the protocol timing requirements. In addition, it provides timer and synchronization
assistance for the IEEE 802.15.4 CSMA-CA algorithm.
The STM32W108xx integrates an ARM® Cortex®-M3 microprocessor, revision r1p1. This
industry-leading core provides 32 bit performance and is very power efficient. It has
excellent code density using the ARM® Thumb 2 instruction set. The processor can be
operated at 12 MHz or 24 MHz when using the crystal oscillator, or at 6 MHz or 12 MHz
when using the integrated high frequency RC oscillator.
The STM32W108xx has 128/192/256 Kbyte of Flash memory, 8/12/16 Kbyte of SRAM on-
chip, and the ARM configurable memory protection unit (MPU).
The STM32W108xx contains 24 GPIO pins shared with other peripheral or alternate
functions. Because of flexible routing within the STM32W108xx, external devices can use
the alternate functions on a variety of different GPIOs. The integrated Serial Controller SC1
can be configured for SPI (master or slave), I2C (master-only), or UART operation, and the
Serial Controller SC2 can be configured for SPI (master or slave) or I2C (master-only)
operation.
The STM32W108xx has a general purpose ADC which can sample analog signals from six
GPIO pins in single-ended or differential modes. It can also sample the regulated supply
VDD_PADSA, the voltage reference VREF, and GND. The ADC has two selectable voltage
ranges: 0 V to 1.2 V for the low voltage (input buffer disabled) and 0.1 V to VDD_PADS
minus 0.1 V for the high voltage supply (input buffer enabled). The ADC has a DMA mode to
capture samples and automatically transfer them into RAM. The integrated voltage
reference for the ADC, VREF, can be made available to external circuitry. An external
voltage reference can also be driven into the ADC.
The STM32W108xx contains four oscillators: a high frequency 24 MHz external crystal
oscillator (24 MHz HSE OSC), a high frequency 12 MHz internal RC oscillator (12 MHz HSI
RC), an optional low frequency 32.768 kHz external crystal oscillator (32 kHz HSE OSC),
and a 10 kHz internal RC oscillator (10 kHz LSI RC).
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The STM32W108xx has an ultra low power, deep sleep state with a choice of clocking
modes. The sleep timer can be clocked with either the external 32.768 kHz crystal oscillator
or with a 1 kHz clock derived from the internal 10 kHz LSI RC oscillator. Alternatively, all
clocks can be disabled for the lowest power mode. In the lowest power mode, only external
events on GPIO pins will wake up the chip. The STM32W108xx has a fast startup time
(typically 100 µs) from deep sleep to the execution of the first ARM® Cortex®-M3 instruction.
The STM32W108xx contains three power domains. The always-on high voltage supply
powers the GPIO pads and critical chip functions. Regulated low voltage supplies power the
rest of the chip. The low voltage supplies are be disabled during deep sleep to reduce power
consumption. Integrated voltage regulators generate regulated 1.25 V and 1.8 V voltages
from an unregulated supply voltage. The 1.8 V regulator output is decoupled and routed
externally to supply analog blocks, RAM, and Flash memories. The 1.25 V regulator output
is decoupled externally and supplies the core logic.
The digital section of the receiver uses a coherent demodulator to generate symbols for the
hardware-based MAC. The digital receiver also contains the analog radio calibration
routines and controls the gain within the receiver path.
In addition to 2 general-purpose timers, the STM32W108xx also contains a watchdog timer
to ensure protection against software crashes and CPU lockup, a 32-bit sleep timer
dedicated to system timing and waking from sleep at specific times and an ARM® standard
system event timer in the NVIC.
The STM32W108xx integrates hardware support for a Packet Trace module, which allows
robust packet-based debug.
Note: The STM32W108xx is not pin-compatible with the previous generation chip, the SN250,
except for the RF section of the chip. Pins 1-11 and 45-48 are compatible, to ease migration
to the STM32W108xx.
1.2.2 ARM® Cortex®-M3 core
The STM32W108xx integrates the ARM® Cortex®-M3 microprocessor, revision r1p1,
developed by ARM Ltd, making the STM32W108xx a true system-on-a-chip solution. The
ARM® Cortex®-M3 is an advanced 32-bit modified Harvard architecture processor that has
separate internal program and data buses, but presents a unified program and data address
space to software. The word width is 32 bits for both the program and data sides. The ARM®
Cortex®-M3 allows unaligned word and half-word data accesses to support efficiently-
packed data structures.
The ARM® Cortex®-M3 clock speed is configurable to 6 MHz, 12 MHz, or 24 MHz. For
normal operation 12 MHz is preferred over 24 MHz due to its lower power consumption. The
6 MHz operation can only be used when radio operations are not required since the radio
requires an accurate 12 MHz clock.
The ARM® Cortex®-M3 in the STM32W108xx has also been enhanced to support two
separate memory protection levels. Basic protection is available without using the MPU, but
the usual operation uses the MPU. The MPU protects unimplemented areas of the memory
map to prevent common software bugs from interfering with software operation. The
architecture could also separate the networking stack from the application code using a fine
granularity RAM protection module. Errant writes are captured and details are reported to
the developer to assist in tracking down and fixing issues.
Documentation conventions STM32W108HB STM32W108CB STM32W108CC STM32W108CZ
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2 Documentation conventions
Table 1. Description of abbreviations used for bit field access
Abbreviation Description(1)
1. The conditions under which the hardware (core) sets or clears this field are explained in details in the bit
field description, as well as the events that may be generated by writing to the bit.
Read/Write (rw) Software can read and write to these bits.
Read-only (r) Software can only read these bits.
Write only (w) Software can only write to this bit. Reading returns the reset value.
Read/Write in (MPU)
Privileged mode only (rws)
Software can read and write to these bits only in Privileged mode. For
more information, please refer to RAM memory protection on page 37
and Memory protection unit on page 42.
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DocID16252 Rev 16 19/289
STM32W108HB STM32W108CB STM32W108CC STM32W108CZ Pinout and pin description
286
3 Pinout and pin description
Figure 2. 48-pin VFQFPN pinout
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Pinout and pin description STM32W108HB STM32W108CB STM32W108CC STM32W108CZ
20/289 DocID16252 Rev 16
Figure 3. 40-pin VFQFPN pinout
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        
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DLE
Table 2. Pin descriptions
48-Pin
Package
Pin no.
40-Pin
Package
Pin no. Signal Direction Description
1 40 VDD_24MHZ Power 1.8V high-frequency oscillator supply
2 1 VDD_VCO Power 1.8V VCO supply
3 2 RF_P I/O Differential (with RF_N) receiver input/transmitter output
4 3 RF_N I/O Differential (with RF_P) receiver input/transmitter output
5 4 VDD_RF Power 1.8V RF supply (LNA and PA)
6 5 RF_TX_ALT_P O Differential (with RF_TX_ALT_N) transmitter output (optional)
7 6 RF_TX_ALT_N O Differential (with RF_TX_ALT_P) transmitter output (optional)
8 7 VDD_IF Power 1.8V IF supply (mixers and filters)
9 8 BIAS_R I Bias setting resistor
DocID16252 Rev 16 21/289
STM32W108HB STM32W108CB STM32W108CC STM32W108CZ Pinout and pin description
286
10 9 VDD_PADSA Power Analog pad supply (1.8V)
11 10
PC5 I/O Digital I/O
TX_ACTIVE O
Logic-level control for external Rx/Tx switch. The
STM32W108xx baseband controls TX_ACTIVE and drives it
high (VDD_PADS) when in Tx mode.
Select alternate output function with GPIOC_CRH[7:4]
12 11 nRESET I Active low chip reset (internal pull-up)
13
PC6 I/O Digital I/O
OSC32_IN I/O 32.768 kHz crystal oscillator
Select analog function with GPIOC_CRH[11:8]
nTX_ACTIVE O Inverted TX_ACTIVE signal (see PC5)
Select alternate output function with GPIOC_CRH[11:8]
14
PC7 I/O Digital I/O
OSC32_OUT I/O 32.768 kHz crystal oscillator.
Select analog function with GPIOC_CRH[15:12]
OSC32_EXT I Digital 32 kHz clock input source
15 12 VREG_OUT Power Regulator output (1.8 V while awake, 0 V during deep sleep)
16 13 VDD_PADS Power Pads supply (2.1-3.6 V)
17 14 VDD_CORE Power 1.25 V digital core supply decoupling
18
PA7
I/O
High
current
Digital I/O. Disable REG_EN with GPIO_DBGCR[4]
TIM1_CH4
O
Timer 1 Channel 4 output
Enable timer output with TIM1_CCER
Select alternate output function with GPIOA_CRH[15:12]
Disable REG_EN with GPIO_DBGCR[4]
I Timer 1 Channel 4 input. (Cannot be remapped.)
REG_EN O External regulator open drain output. (Enabled after reset.)
Table 2. Pin descriptions (continued)
48-Pin
Package
Pin no.
40-Pin
Package
Pin no. Signal Direction Description
Pinout and pin description STM32W108HB STM32W108CB STM32W108CC STM32W108CZ
22/289 DocID16252 Rev 16
19 15
PB3 I/O Digital I/O
TIM2_CH3
(see Pin 22)
O
Timer 2 channel 3 output
Enable remap with TIM2_OR[6]
Enable timer output in TIM2_CCER
Select alternate output function with GPIOB_CRL[15:12]
I Timer 2 channel 3 input. Enable remap with TIM2_OR[6].
UART_CTS I
UART CTS handshake of Serial Controller 1
Enable with SC1_UARTCR[5]
Select UART with SC1_CR
SC1SCLK
O
SPI master clock of Serial Controller 1
Either disable timer output in TIM2_CCER or disable remap
with TIM2_OR[6]
Enable master with SC1_SPICR[4]
Select SPI with SC1_CR
Select alternate output function with GPIOB_CRL[15:12]
I
SPI slave clock of Serial Controller 1
Enable slave with SC1_SPICR[4]
Select SPI with SC1_CR
20 16
PB4 I/O Digital I/O
TIM2_CH4
(see also
Pin 24)
O
Timer 2 channel 4 output
Enable remap with TIM2_OR[7]
Enable timer output in TIM2_CCER
Select alternate output function with GPIOB_CRH[3:0]
I Timer 2 channel 4 input. Enable remap with TIM2_OR[7].
UART_RTS O
UART RTS handshake of Serial Controller 1
Either disable timer output in TIM2_CCER or disable remap
with TIM2_OR[7]
Enable with SC1_UARTCR[5]
Select UART with SC1_CR
Select alternate output function with GPIOB_CRH[3:0]
SC1nSSEL I
SPI slave select of Serial Controller 1
Enable slave with SC1_SPICR[4]
Select SPI with SC1_CR
Table 2. Pin descriptions (continued)
48-Pin
Package
Pin no.
40-Pin
Package
Pin no. Signal Direction Description
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STM32W108HB STM32W108CB STM32W108CC STM32W108CZ Pinout and pin description
286
21 17
PA0 I/O Digital I/O
TIM2_CH1
(see also
Pin 30)
O
Timer 2 channel 1 output
Disable remap with TIM2_OR[4]
Enable timer output in TIM2_CCER
Select alternate output function with GPIOA_CRL[3:0]
I Timer 2 channel 1 input. Disable remap with TIM2_OR[4].
SC2MOSI
O
SPI master data out of Serial Controller 2
Either disable timer output in TIM2_CCER or enable remap
with TIM2_OR[4]
Enable master with SC2_SPICR[4]
Select SPI with SC2_CR
Select alternate output function with GPIOA_CRL[3:0]
I
SPI slave data in of Serial Controller 2
Enable slave with SC2_SPICR[4]
Select SPI with SC2_CR
22 18
PA1 I/O Digital I/O
TIM2_CH3
(see also
Pin 19)
O
Timer 2 channel 3 output
Disable remap with TIM2_OR[6]
Enable timer output in TIM2_CCER
Select alternate output function with GPIOA_CRL[7:4]
I Timer 2 channel 3 input. Disable remap with TIM2_OR[6].
SC2SDA I/O
I2C data of Serial Controller 2
Either disable timer output in TIM2_CCER or enable remap
with TIM2_OR[6]
Select I2C with SC2_CR
Select alternate open-drain output function with
GPIOA_CRL[7:4]
SC2MISO
O
SPI slave data out of Serial Controller 2
Either disable timer output in TIM2_CCER or enable remap
with TIM2_OR[6]
Enable slave with SC2_SPICR[4]
Select SPI with SC2_CR
Select alternate output function with GPIOA_CRL[7:4]
I
SPI master data in of Serial Controller 2
Enable slave with SC2_SPICR[4]
Select SPI with SC2_CR
23 19 VDD_PADS Power Pads supply (2.1-3.6V)
Table 2. Pin descriptions (continued)
48-Pin
Package
Pin no.
40-Pin
Package
Pin no. Signal Direction Description
Pinout and pin description STM32W108HB STM32W108CB STM32W108CC STM32W108CZ
24/289 DocID16252 Rev 16
24 20
PA2 I/O Digital I/O
TIM2_CH4
(see also
Pin 20)
O
Timer 2 channel 4 output
Disable remap with TIM2_OR[7]
Enable timer output in TIM2_CCER
Select alternate output function with GPIOA_CRL[11:8]
I Timer 2 channel 4 input. Disable remap with TIM2_OR[7].
SC2SCL I/O
I2C clock of Serial Controller 2
Either disable timer output in TIM2_CCER or enable remap
with TIM2_OR[7]
Select I2C with SC2_CR
Select alternate open-drain output function with
GPIOA_CRL[11:8]
SC2SCLK
O
SPI master clock of Serial Controller 2
Either disable timer output in TIM2_CCER or enable remap
with TIM2_OR[7]
Enable master with SC2_SPICR[4]
Select SPI with SC2_CR
Select alternate output function with GPIOA_CRL[11:8]
I
SPI slave clock of Serial Controller 2
Enable slave with SC2_SPICR[4]
Select SPI with SC2_CR
25 21
PA3 I/O Digital I/O
SC2nSSEL I
SPI slave select of Serial Controller 2
Enable slave with SC2_SPICR[4]
Select SPI with SC2_CR
TRACECLK
(see also Pin
36)
O
Synchronous CPU trace clock
Either disable timer output in TIM2_CCER or enable remap
with TIM2_OR[5]
Enable trace interface in ARM core
Select alternate output function with GPIOA_CRL[15:12]
TIM2_CH2
(see also Pin
31)
O
Timer 2 channel 2 output
Disable remap with TIM2_OR[5]
Enable timer output in TIM2_CCER
Select alternate output function with GPIOA_CRL[15:12]
I Timer 2 channel 2 input. Disable remap with TIM2_OR[5].
Table 2. Pin descriptions (continued)
48-Pin
Package
Pin no.
40-Pin
Package
Pin no. Signal Direction Description
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STM32W108HB STM32W108CB STM32W108CC STM32W108CZ Pinout and pin description
286
26 22
PA4 I/O Digital I/O
ADC4 Analog ADC Input 4. Select analog function with GPIOA_CRH[3:0].
PTI_EN O
Frame signal of Packet Trace Interface (PTI).
Disable trace interface in ARM core.
Select alternate output function with GPIOA_CRH[3:0].
TRACEDATA2 O
Synchronous CPU trace data bit 2.
Select 4-wire synchronous trace interface in ARM core.
Enable trace interface in ARM core.
Select alternate output function with GPIOA_CRH[3:0].
27 23
PA5 I/O Digital I/O
ADC5 Analog ADC Input 5. Select analog function with GPIOA_CRH[7:4].
PTI_DATA O
Data signal of Packet Trace Interface (PTI).
Disable trace interface in ARM core.
Select alternate output function with GPIOA_CRH[7:4].
nBOOTMODE I
Embedded serial bootloader activation out of reset.
Signal is active during and immediately after a reset on NRST.
See Section 6.2: Resets on page 48 for details.
TRACEDATA3 O
Synchronous CPU trace data bit 3.
Select 4-wire synchronous trace interface in ARM core.
Enable trace interface in ARM core.
Select alternate output function with GPIOA_CRH[7:4]
28 24 VDD_PADS Power Pads supply (2.1-3.6 V)
29
PA6
I/O
High
current
Digital I/O
TIM1_CH3
O
Timer 1 channel 3 output
Enable timer output in TIM1_CCER
Select alternate output function with GPIOA_CRH[11:8]
I Timer 1 channel 3 input (Cannot be remapped.)
Table 2. Pin descriptions (continued)
48-Pin
Package
Pin no.
40-Pin
Package
Pin no. Signal Direction Description
Pinout and pin description STM32W108HB STM32W108CB STM32W108CC STM32W108CZ
26/289 DocID16252 Rev 16
30 25
PB1 I/O Digital I/O
SC1MISO O
SPI slave data out of Serial Controller 1
Either disable timer output in TIM2_CCER or disable remap
with TIM2_OR[4]
Select SPI with SC1_CR
Select slave with SC1_SPICR
Select alternate output function with GPIOB_CRL[7:4]
SC1MOSI O
SPI master data out of Serial Controller 1
Either disable timer output in TIM2_CCER or disable remap
with TIM2_OR[4]
Select SPI with SC1_CR
Select master with SC1_SPICR
Select alternate output function with GPIOB_CRL[7:4]
SC1SDA I/O
I2C data of Serial Controller 1
Either disable timer output in TIM2_CCER,
or disable remap with TIM2_OR[4]
Select I2C with SC1_CR
Select alternate open-drain output function with
GPIOB_CRL[7:4]
SC1TXD O
UART transmit data of Serial Controller 1
Either disable timer output in TIM2_CCER or disable remap
with TIM2_OR[4]
Select UART with SC1_CR
Select alternate output function with GPIOB_CRL[7:4]
TIM2_CH1
(see also
Pin 21)
O
Timer 2 channel 1 output
Enable remap with TIM2_OR[4]
Enable timer output in TIM2_CCER
Select alternate output function with GPIOA_CRL[7:4]
I Timer 2 channel 1 input. Disable remap with TIM2_OR[4].
Table 2. Pin descriptions (continued)
48-Pin
Package
Pin no.
40-Pin
Package
Pin no. Signal Direction Description
DocID16252 Rev 16 27/289
STM32W108HB STM32W108CB STM32W108CC STM32W108CZ Pinout and pin description
286
31 26
PB2 I/O Digital I/O
SC1MISO I
SPI master data in of Serial Controller 1
Select SPI with SC1_CR
Select master with SC1_SPICR
SC1MOSI I
SPI slave data in of Serial Controller 1
Select SPI with SC1_CR
Select slave with SC1_SPICR
SC1SCL I/O
I2C clock of Serial Controller 1
Either disable timer output in TIM2_CCER,
or disable remap with TIM2_OR[5]
Select I2C with SC1_CR
Select alternate open-drain output function with
GPIOB_CRL[11:8]
SC1RXD I UART receive data of Serial Controller 1
Select UART with SC1_CR
TIM2_CH2
(see also Pin
25)
O
Timer 2 channel 2 output
Enable remap with TIM2_OR[5]
Enable timer output in TIM2_CCER
Select alternate output function with GPIOB_CRL[11:8]
I Timer 2 channel 2 input. Enable remap with TIM2_OR[5].
32 27
SWCLK I/O
Serial Wire clock input/output with debugger
Selected when in Serial Wire mode (see JTMS description,
Pin 35)
JTCK I
JTAG clock input from debugger
Selected when in JTAG mode (default mode, see JTMS
description, Pin 35)
Internal pull-down is enabled
33 28
PC2 I/O Digital I/O
Enable with GPIO_DBGCR[5]
JTDO O
JTAG data out to debugger
Selected when in JTAG mode (default mode, see JTMS
description, Pin 35)
SWO O
Serial Wire Output asynchronous trace output to debugger
Select asynchronous trace interface in ARM core
Enable trace interface in ARM core
Select alternate output function with GPIOC_CRL[11:8]
Enable Serial Wire mode (see JTMS description, Pin 35)
Internal pull-up is enabled
Table 2. Pin descriptions (continued)
48-Pin
Package
Pin no.
40-Pin
Package
Pin no. Signal Direction Description
Pinout and pin description STM32W108HB STM32W108CB STM32W108CC STM32W108CZ
28/289 DocID16252 Rev 16
34 29
PC3 I/O
Digital I/O
Either Enable with GPIO_DBGCR[5],
or enable Serial Wire mode (see JTMS description)
JTDI I
JTAG data in from debugger
Selected when in JTAG mode (default mode, see JTMS
description, Pin 35)
Internal pull-up is enabled
35 30
PC4 I/O Digital I/O
Enable with GPIO_DBGCR[5]
JTMS I
JTAG mode select from debugger
Selected when in JTAG mode (default mode)
JTAG mode is enabled after power-up or by forcing NRST low
Select Serial Wire mode using the ARM-defined protocol
through a debugger
Internal pull-up is enabled
SWDIO I/O
Serial Wire bidirectional data to/from debugger
Enable Serial Wire mode (see JTMS description)
Select Serial Wire mode using the ARM-defined protocol
through a debugger
Internal pull-up is enabled
36
PB0 I/O Digital I/O
VREF Analog O ADC reference output.
Enable analog function with GPIOB_CRL[3:0].
VREF Analog I
ADC reference input.
Enable analog function with GPIOB_CRL[3:0].
Enable reference output with an ST system function.
IRQA I External interrupt source A.
TRACECLK
(see also Pin
25)
O
Synchronous CPU trace clock.
Enable trace interface in ARM core.
Select alternate output function with GPIOB_CRL[3:0].
TIM1CLK I Timer 1 external clock input.
TIM2MSK I Timer 2 external clock mask input.
37 VDD_PADS Power Pads supply (2.1 to 3.6 V).
Table 2. Pin descriptions (continued)
48-Pin
Package
Pin no.
40-Pin
Package
Pin no. Signal Direction Description
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STM32W108HB STM32W108CB STM32W108CC STM32W108CZ Pinout and pin description
286
38 31
PC1 I/O Digital I/O
ADC3 Analog ADC Input 3
Enable analog function with GPIOC_CRL[7:4]
SWO
(see also Pin
33)
O
Serial Wire Output asynchronous trace output to debugger
Select asynchronous trace interface in ARM core
Enable trace interface in ARM core
Select alternate output function with GPIOC_CRL[7:4]
TRACEDATA0 O
Synchronous CPU trace data bit 0
Select 1-, 2- or 4-wire synchronous trace interface in ARM
core
Enable trace interface in ARM core
Select alternate output function with GPIOC_CRL[7:4]
39 32 VDD_MEM Power 1.8 V supply (Flash, RAM)
40 33
PC0
I/O
High
current
Digital I/O
Either enable with GPIO_DBGCR[5],
or enable Serial Wire mode (see JTMS description, Pin 35)
and disable TRACEDATA1
JRST I
JTAG reset input from debugger
Selected when in JTAG mode (default mode, see JTMS
description) and TRACEDATA1 is disabled
Internal pull-up is enabled
IRQD (1) I Default external interrupt source D
TRACEDATA1 O
Synchronous CPU trace data bit 1
Select 2- or 4-wire synchronous trace interface in ARM core
Enable trace interface in ARM core
Select alternate output function with GPIOC_CRL[3:0]
41 34
PB7
I/O
High
current
Digital I/O
ADC2 Analog ADC Input 2
Enable analog function with GPIOB_CRH[15:12]
IRQC (1) I Default external interrupt source C
TIM1_CH2
O
Timer 1 channel 2 output
Enable timer output in TIM1_CCER
Select alternate output function with GPIOB_CRH[15:12]
I Timer 1 channel 2 input (Cannot be remapped)
Table 2. Pin descriptions (continued)
48-Pin
Package
Pin no.
40-Pin
Package
Pin no. Signal Direction Description
Pinout and pin description STM32W108HB STM32W108CB STM32W108CC STM32W108CZ
30/289 DocID16252 Rev 16
42 35
PB6
I/O
High
current
Digital I/O
ADC1 Analog ADC Input 1
Enable analog function with GPIOB_CRH[11:8]
IRQB I External interrupt source B
TIM1_CH1
O
Timer 1 channel 1 output
Enable timer output in TIM1_CCER
Select alternate output function with GPIOB_CRH[11:8]
I Timer 1 channel 1 input (Cannot be remapped)
43
PB5 I/O Digital I/O
ADC0 Analog ADC Input 0
Enable analog function with GPIOB_CRH[7:4]
TIM2CLK I Timer 2 external clock input
TIM1MSK I Timer 2 external clock mask input
44 36 VDD_CORE Power 1.25 V digital core supply decoupling
45 37 VDD_PRE Power 1.8 V prescaler supply
46 VDD_SYNTH Power 1.8 V synthesizer supply
47 38 OSC_IN I/O 24 MHz HSE OSC or left open when using external clock
input on OSC_OUT
48 39 OSC_OUT I/O 24 MHz HSE OSC or external clock input
49 41 GND Ground Ground supply pad in the bottom center of the package.
1. IRQC and IRQD external interrupts can be mapped to any digital I/O pin using the EXTIC_CR and EXTID_CR registers.
Table 2. Pin descriptions (continued)
48-Pin
Package
Pin no.
40-Pin
Package
Pin no. Signal Direction Description
DocID16252 Rev 16 31/289
STM32W108HB STM32W108CB STM32W108CC STM32W108CZ Embedded memory
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4 Embedded memory
4.1 Memory organization and memory map
The bytes are coded in the memory in Little Endian format. The lowest numbered byte in a
word is considered the word’s least significant byte and the highest numbered byte the most
significant.
For detailed mapping of peripheral registers, please refer to the relevant section.
All the memory areas that are not allocated to on-chip memories and peripherals are
considered “Reserved”).
Refer to Figure 4: STM32W108xB memory mapping, Figure 5: STM32W108CC and
STM32W108CZ memory mapping, and Table 3: STM32W108xx peripheral register
boundary addresses for the register boundary addresses of the peripherals available in all
STM32W108xx devices.
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32/289 DocID16252 Rev 16
Figure 4. STM32W108xB memory mapping
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STM32W108HB STM32W108CB STM32W108CC STM32W108CZ Embedded memory
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Figure 5. STM32W108CC and STM32W108CZ memory mapping
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Embedded memory STM32W108HB STM32W108CB STM32W108CC STM32W108CZ
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Table 3. STM32W108xx peripheral register boundary addresses
Bus Boundary address Peripheral Register map
APB
0x4000 F000 - 0x4000 FFFF General-purpose timer 2
(TIM2)
Table 10.3.20: General-
purpose timers 1 and 2
(TIM1/TIM2) register
map
0x4000 E000 - 0x4000 EFFF General-purpose timer 1
(TIM1)
Table 10.3.20: General-
purpose timers 1 and 2
(TIM1/TIM2) register
map
0x4000 D025 - 0x4000 DFFF Reserved -
0x4000 D000 - 0x4000 D024 Analog-to-digital converter
(ADC)
Table 11.3.12: Analog-
to-digital converter
(ADC) register map
0x4000 C871 - 0x4000 CFFF Reserved -
0x4000 C800 - 0x4000 C870 Serial interface
(SC1)
Table 9.12.17: Serial
interface (SC1/SC2)
register map
0x4000 C071 - 0x4000 C7FF Reserved -
0x4000 C000 - 0x4000 C070 Serial interface
(SC2)
Table 9.12.17: Serial
interface (SC1/SC2)
register map
0x4000 B000 - 0x4000 BFFF
General-purpose
input/output
(GPIO)
Table 8.5.13: General-
purpose input/output
(GPIO) register map
0x4000 A000 - 0x4000 AFFF Management interrupt
(MGMT)
Table 12.2.3:
Management interrupt
(MGMT) register map
0x4000 6025 - 0x4000 9FFF Reserved -
0x4000 600C - 0x4000 6024 Sleeptimer
(SLPTMR)
MAC timer
(MACTMR)/Watchdog
(WDG)/Sleeptimer(SLP
TMR) register map
0x4000 6009 - 0x4000 600B Reserved -
0x4000 6000 - 0x4000 6008 Watchdog
(WDG)
MAC timer
(MACTMR)/Watchdog
(WDG)/Sleeptimer(SLP
TMR) register map
0x4000 5000 - 0x4000 5FFF Memory controller
(MEM)
Memory controller
(MEM) register map
0x4000 4021 - 0x4000 4FFF Reserved -
0x4000 4000 - 0x4000 4020 Clock switching
(CLK)
Clock switching (CLK)
register map
0x4000 3000 - 0x4000 3FFF Reserved -
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4.2 Flash memory
The STM32W108 provides Flash memory in four separate blocks as follows:
Main Flash Block (MFB)
Fixed Information Block (FIB)
Fixed Information Block Extension (FIB-EXT)
Customer Information Block (CIB)
The size of these blocks and associated page size is described in Table 4.
The smallest erasable unit is one page and the smallest writable unit is an aligned 16-bit
half-word. The Flash is guaranteed to have 10k write/erase cycles. The Flash cell has been
qualified for a data retention time of >100 years at room temperature.
APB
0x4000 2000 - 0x4000 2FFF MAC timer
(MACTMR)
MAC timer
(MACTMR)/Watchdog
(WDG)/Sleeptimer(SLP
TMR) register map
0x4000 1000 - 0x4000 1FFF Reserved -
0x4000 0000 - 0x4000 0FFF Power management
(PWR)
Power management
(PWR) register map
0x2000 4000 - 0x3FFF FFFF Reserved -
0x2000 0000 - 0x2000 3FFF SRAM -
0x0804 0000 - 0x1FFF FFFF Reserved -
0x0800 0000 - 0x0803 FFFF Main Flash memory
(256 Kbyte) -
Table 3. STM32W108xx peripheral register boundary addresses (continued)
Bus Boundary address Peripheral Register map
Table 4. Flash memory
STM32W108xB STM32W108CC STM32W108CZ Unit
Size Page size Size Page size Size Page size
MFB 128 1 256 2 192 2 Kbyte
FIB 222222Kbyte
CIB 0.50.52222Kbyte
FIB-EXT 0N/A162162Kbyte
Total 130.5 276 212 Kbyte
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36/289 DocID16252 Rev 16
Flash may be programmed either through the Serial Wire/JTAG interface or through
bootloader software. Programming Flash through Serial Wire/JTAG requires the assistance
of RAM-based utility code. Programming through a bootloader requires specific software for
over-the-air loading or serial link loading. A simplified, serial-link-only bootloader is also
available preprogrammed into the FIB.
4.3 Random-access memory
The STM32W108xx has 8/12/16 Kbyte of static RAM on-chip. The start of RAM is mapped
to address 0x20000000. Although the ARM® Cortex®-M3 allows bit band accesses to this
address region, the standard MPU configuration does not permit use of the bit-band feature.
The RAM is physically connected to the AHB System bus and is therefore accessible to
both the ARM® Cortex®-M3 microprocessor and the debugger. The RAM can be accessed
for both instruction and data fetches as bytes, half words, or words. The standard MPU
configuration does not permit execution from the RAM, but for special purposes, such as
programming the main Flash block, the MPU may be disabled. To the bus, the RAM
appears as 32-bit wide memory and in most situations has zero wait state read or write
access. In the higher CPU clock mode the RAM requires two wait states. This is handled by
hardware transparent to the user application with no configuration required.
4.3.1 Direct memory access (DMA) to RAM
Several of the peripherals are equipped with DMA controllers allowing them to transfer data
into and out of RAM autonomously. This applies to the radio (802.15.4 MAC), general
purpose ADC, and both serial controllers. In the case of the serial controllers, the DMA is full
duplex so that a read and a write to RAM may be requested at the same time. Thus there
are six DMA channels in total.
The STM32W108xx integrates a DMA arbiter that ensures fair access to the microprocessor
as well as the peripherals through a fixed priority scheme appropriate to the memory
bandwidth requirements of each master. The priority scheme is as follows, with the top
peripheral being the highest priority:
1. General Purpose ADC
2. Serial Controller 2 Receive
3. Serial Controller 2 Transmit
4. MAC
5. Serial Controller 1 Receive
6. Serial Controller 1 Transmit
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4.3.2 RAM memory protection
The STM32W108xx integrates two memory protection mechanisms. The first memory
protection mechanism is through the ARM® Cortex®-M3 Memory Protection Unit (MPU)
described in the Memory Protection Unit section. The MPU may be used to protect any area
of memory. MPU configuration is normally handled by software. The second memory
protection mechanism is through a fine granularity RAM protection module. This allows
segmentation of the RAM into blocks where any block can be marked as write protected. An
attempt to write to a protected RAM block using a user mode write results in a bus error
being signaled on the AHB System bus. A system mode write is allowed at any time and
reads are allowed in either mode. The main purpose of this fine granularity RAM protection
module is to notify the stack of erroneous writes to system areas of memory. RAM protection
is configured using a group of registers that provide a bit map. Each bit in the map
represents a 32-byte block of RAM for STM32W108xB and 64 bytes of RAM for
STM32W108CC and STM32W108CZ.When the bit is set the block is write protected.
The fine granularity RAM memory protection mechanism is also available to the peripheral
DMA controllers. A register bit is provided to enable the memory protection to include DMA
writes to protected memory. If a DMA write is made to a protected location in RAM, a
management interrupt is generated. At the same time the faulting address and the
identification of the peripheral is captured for later debugging. Note that only peripherals
capable of writing data to RAM, such as received packet data or a received serial port
character, can generate this interrupt.
4.3.3 Memory controller
The STM32W108xx allows the RAM and DMA protection to be controlled using the memory
controller interface. The chip contains eight RAM protection registers and two DMA
protection registers. In addition, the chip contains a register, RAM_CR, for enabling the
protection of the memory.
Embedded memory STM32W108HB STM32W108CB STM32W108CC STM32W108CZ
38/289 DocID16252 Rev 16
4.3.4 Memory controller registers
RAM is divided into 32 byte pages. Each page has a register bit that, when set, protects it
from being written in user mode. The protection registers (MEM_PROT) are arranged in the
register map as a 256-bit vector. Bit 0 of this vector protects page 0 which begins at location
0x2000 0000 and ends at 0x2000 001F. Bit 255 of this vector protects the top page which
starts at 0x20001FE0 and ends at 0x2000 1FFF.
Memory RAM protection register x (RAM_PROTRx)
Address: 0x 4000 5000 (RAM_PROTR1), 0x 4000 5004 (RAM_PROTR2),
0x 4000 5008 (RAM_PROTR3), 0x 4000 500C (RAM_PROTR4),
0x 4000 5010 (RAM_PROTR5), 0x 4000 5014 (RAM_PROTR6),
0x 4000 5018(RAM_PROTR7), and 0x 4000 501C (RAM_PROTR8).
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Memory page protection x[31:16
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
1514131211109876543210
Memory page protection x[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:0 Memory page protection x[31:0]:
Bit 0 in the RAM_PROTR1 protects page 0
Bit 31 in the RAM_PROTR1 protects page 31
Bit 0 in the RAM_PROTR2 protects page 32
Bit 31 in the RAM_PROTR2 protects page 63
Bit 0 in the RAM_PROTR3 protects page 64
Bit 31 in the RAM_PROTR3 protects page 95
Bit 0 in the RAM_PROTR4 protects page 96
Bit 31 in the RAM_PROTR4 protects page 127
Bit 0 in the RAM_PROTR5 protects page 128
Bit 31 in the RAM_PROTR5 protects page 159
Bit 0 in the RAM_PROTR6 protects page 160
Bit 31 in the RAM_PROTR6 protects page 191
Bit 0 in the RAM_PROTR7 protects page 192
Bit 31 in the RAM_PROTR7 protects page 223
Bit 0 in the RAM_PROTR8 protects page 224
….
Bit 31 in the RAM_PROTR8 protects page 255
E]
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Memory DMA protection register 1 (DMA_PROTR1)
Address: 0x 4000 5020
Reset value: 0x2000 0000
Memory DMA protection register 2 (DMA_PROTR2)
Address: 0x 4000 5024
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Offset[18:3]
r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Offset[2:0] Address[11:0]
Reserved
r r r r r r r r r r r r r r r
Bits 31:13 Offset[18:0]:
Offset in RAM
Bits 12:1 Offset[11:0]:
DMA protection fault, faulting address.
Bit 0 Reserved, must be kept at reset value
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Channel[2:0]
r r r
Bits 31:3 Reserved, must be kept at reset value
Bits 2:0 Channel[2:0]: Channel encoding
7: Not used
6: Not used
5: SC2_RX
4: Not used
3: ADC
2: Not used
1: SC1_RX
0: Not used
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Memory RAM control register (RAM_CR)
Address: 0x 4000 5028
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
WEN
Reserved
rw
Bits 31:3 Reserved, must be kept at reset value
Bit 2 WEN: Makes all RAM writes appear as user mode
Bits 1:0 Reserved, must be kept at reset value
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Memory controller (MEM) register map
Table 5 gives the MEM register map and reset values.
Refer to Figure 4: STM32W108xB memory mapping, Figure 5: STM32W108CC and
STM32W108CZ memory mapping, and Table 3: STM32W108xx peripheral register
boundary addresses for the register boundary addresses of the peripherals available in all
STM32W108xx devices.
Table 5. MEM register map and reset values
Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x5000 RAM_PROTR1 Memory page protection 1[31:0]
Reset value 00000000000000000000000000000000
0x5004 RAM_PROTR2 Memory page protection 2[31:0]
Reset value 00000000000000000000000000000000
0x5008 RAM_PROTR3 Memory page protection 3[31:0]
Reset value 00000000000000000000000000000000
0x500C RAM_PROTR4 Memory protection 4[31:0]
Reset value 00000000000000000000000000000000
0x5010 RAM_PROTR5 Memory protection 5[31:0]
Reset value 00000000000000000000000000000000
0x5014 RAM_PROTR6 Memory protection 6[31:0]
Reset value 00000000000000000000000000000000
0x5018 RAM_PROTR7 Memory protection 7[31:0]
Reset value 00000000000000000000000000000000
0x501C RAM_PROTR8 Memory protection 8[31:0]
Reset value 00000000000000000000000000000000
0x5020 DMA_PROTR1 Offset[18:0] Address[11:0]
Res.
Reset value 0010000000000000000000000000000
0x5024 DMA_PROTR2
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Channel[2:0]
Reset value 0000
0x5028 RAM_CR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
WEN
Res.
Res.
Reset value 0
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4.4 Memory protection unit
The STM32W108xx includes the ARM® Cortex®-M3 Memory Protection Unit, or MPU. The
MPU controls access rights and characteristics of up to eight address regions, each of
which may be divided into eight equal sub-regions. Refer to the ARM® Cortex®-M3
Technical Reference Manual (DDI 0337A) for a detailed description of the MPU.
ST software configures the MPU in a standard configuration and application software should
not modify it. The configuration is designed for optimal detection of illegal instruction or data
accesses. If an illegal access is attempted, the MPU captures information about the access
type, the address being accessed, and the location of the offending software. This simplifies
software debugging and increases the reliability of deployed devices. As a consequence of
this MPU configuration, accessing RAM and register bit-band address alias regions is not
permitted, and generates a bus fault if attempted.
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5 Radio frequency module
The radio module consists of an analog front end and digital baseband as shown in
Figure 1: STM32W108xx block diagram.
5.1 Receive (Rx) path
The Rx path uses a low-IF, super-heterodyne receiver that rejects the image frequency
using complex mixing and polyphase filtering. In the analog domain, the input RF signal
from the antenna is first amplified and mixed down to a 4 MHz IF frequency. The mixers'
output is filtered, combined, and amplified before being sampled by a 12 Msps ADC. The
digitized signal is then demodulated in the digital baseband. The filtering within the Rx path
improves the STM32W108xx's co-existence with other 2.4 GHz transceivers such as IEEE
802.15.4, IEEE 802.11g, and Bluetooth radios. The digital baseband also provides gain
control of the Rx path, both to enable the reception of small and large wanted signals and to
tolerate large interferers.
5.1.1 Rx baseband
The STM32W108xx Rx digital baseband implements a coherent demodulator for optimal
performance. The baseband demodulates the O-QPSK signal at the chip level and
synchronizes with the IEEE 802.15.4-defined preamble. An automatic gain control (AGC)
module adjusts the analog gain continuously every ¼ symbol until the preamble is detected.
Once detected, the gain is fixed for the remainder of the packet. The baseband despreads
the demodulated data into 4-bit symbols. These symbols are buffered and passed to the
hardware-based MAC module for packet assembly and filtering.
In addition, the Rx baseband provides the calibration and control interface to the analog Rx
modules, including the LNA, Rx baseband filter, and modulation modules. The ST RF
software driver includes calibration algorithms that use this interface to reduce the effects of
silicon process and temperature variation.
5.1.2 RSSI and CCA
The STM32W108xx calculates the RSSI over every 8-symbol period as well as at the end of
a received packet. The linear range of RSSI is specified to be at least 40 dB over
temperature. At room temperature, the linear range is approximately 60 dB (-90 dBm to -30
dBm input signal).
The STM32W108xx Rx baseband provides support for the IEEE 802.15.4-2003 RSSI CCA
method, Clear channel reports busy medium if RSSI exceeds its threshold.
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5.2 Transmit (Tx) path
The STM32W108xx Tx path produces an O-QPSK-modulated signal using the analog front
end and digital baseband. The area- and power-efficient Tx architecture uses a two-point
modulation scheme to modulate the RF signal generated by the synthesizer. The modulated
RF signal is fed to the integrated PA and then out of the STM32W108xx.
5.2.1 Tx baseband
The STM32W108xx Tx baseband in the digital domain spreads the 4-bit symbol into its
IEEE 802.15.4-2003-defined 32-chip sequence. It also provides the interface for software to
calibrate the Tx module to reduce silicon process, temperature, and voltage variations.
5.2.2 TX_ACTIVE and nTX_ACTIVE signals
For applications requiring an external PA, two signals are provided called TX_ACTIVE and
nTX_ACTIVE. These signals are the inverse of each other. They can be used for external
PA power management and RF switching logic. In transmit mode the Tx baseband drives
TX_ACTIVE high, as described in Table 17: GPIO signal assignments on page 99. In
receive mode the TX_ACTIVE signal is low. TX_ACTIVE is the alternate function of PC5,
and nTX_ACTIVE is the alternate function of PC6. See Section 8: General-purpose
input/output on page 92 for details of the alternate GPIO functions.
5.3 Calibration
The ST RF software driver calibrates the radio using dedicated hardware resources.
5.4 Integrated MAC module
The STM32W108xx integrates most of the IEEE 802.15.4 MAC requirements in hardware.
This allows the ARM® Cortex®-M3 CPU to provide greater bandwidth to application and
network operations. In addition, the hardware acts as a first-line filter for unwanted packets.
The STM32W108xx MAC uses a DMA interface to RAM to further reduce the overall ARM®
Cortex®-M3 CPU interaction when transmitting or receiving packets.
When a packet is ready for transmission, the software configures the Tx MAC DMA by
indicating the packet buffer RAM location. The MAC waits for the backoff period, then
switches the baseband to Tx mode and performs channel assessment. When the channel is
clear the MAC reads data from the RAM buffer, calculates the CRC, and provides 4-bit
symbols to the baseband. When the final byte has been read and sent to the baseband, the
CRC remainder is read and transmitted.
The MAC is in Rx mode most of the time. In Rx mode various format and address filters
keep unwanted packets from using excessive RAM buffers, and prevent the CPU from
being unnecessarily interrupted. When the reception of a packet begins, the MAC reads 4-
bit symbols from the baseband and calculates the CRC. It then assembles the received data
for storage in a RAM buffer. Rx MAC DMA provides direct access to RAM. Once the packet
has been received additional data, which provides statistical information on the packet to the
software stack, is appended to the end of the packet in the RAM buffer space.
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The primary features of the MAC are:
CRC generation, appending, and checking
Hardware timers and interrupts to achieve the MAC symbol timing
Automatic preamble and SFD pre-pending on Tx packets
Address recognition and packet filtering on Rx packets
Automatic acknowledgement transmission
Automatic transmission of packets from memory
Automatic transmission after backoff time if channel is clear (CCA)
Automatic acknowledgement checking
Time stamping received and transmitted messages
Attaching packet information to received packets (LQI, RSSI, gain, time stamp, and
packet status)
IEEE 802.15.4 timing and slotted/unslotted timing
5.5 Packet trace interface (PTI)
The STM32W108xx integrates a true PHY-level PTI for effective network-level debugging. It
monitors all the PHY Tx and Rx packets between the MAC and baseband modules without
affecting their normal operation. It cannot be used to inject packets into the PHY/MAC
interface. This 500 kbps asynchronous interface comprises the frame signal (PTI_EN, PA4)
and the data signal (PTI_DATA, PA5).
5.6 Random number generator
Thermal noise in the analog circuitry is digitized to provide entropy for a true random
number generator (TRNG). The TRNG produces 16-bit uniformly distributed numbers. The
Software can use the TRNG to seed a pseudo random number generator (PNRG). The
TRNG is also used directly for cryptographic key generation.
STM32W108HB STM32W1OBCB STM32W 2W1 odules ncompass power, resets, clocks, system timers, p nt 6shows these modules and how they imeract. Figure 6. System module block diagram E .MS nMMFl) m w vwzcjws my V: m suvw mm) m Lyme BB
System modules STM32W108HB STM32W108CB STM32W108CC STM32W108CZ
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6 System modules
System modules encompass power, resets, clocks, system timers, power management, and
encryption. Figure 6 shows these modules and how they interact.
Figure 6. System module block diagram
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6.1 Power domains
The STM32W108xx contains three power domains:
An "always on domain" containing all logic and analog cells required to manage the
STM32W108xx's power modes, including the GPIO controller and sleep timer. This
domain must remain powered.
A "core domain" containing the CPU, Nested Vectored Interrupt Controller (NVIC), and
peripherals. To save power, this domain can be powered down using a mode called
deep sleep.
A "memory domain" containing the RAM and Flash memories. This domain is managed
by the power management controller. When in deep sleep, the RAM portion of this
domain is powered from the always-on domain supply to retain the RAM contents while
the regulators are disabled. During deep sleep the Flash portion is completely powered
down.
6.1.1 Internally regulated power
The preferred and recommended power configuration is to use the internal regulated power
supplies to provide power to the core and memory domains. The internal regulators
(VREG_1V25 and VREG_1V8) generate nominal 1.25 V and 1.8 V supplies. The 1.25 V
supply is internally routed to the core domain and to an external pin. The 1.8 V supply is
routed to an external pin where it can be externally routed back into the chip to supply the
memory domain. The internal regulators are described in Section 7: Integrated voltage
regulator on page 90.
When using the internal regulators, the always-on domain must be powered between 2.1 V
and 3.6 V at all four VDD_PADS pins.
When using the internal regulators, the VREG_1V8 regulator output pin (VREG_OUT) must
be connected to the VDD_MEM, VDD_PADSA, VDD_VCO, VDD_RF, VDD_IF, VDD_PRE,
and VDD_SYNTH pins.
When using the internal regulators, the VREG_1V25 regulator output and supply requires a
connection between both VDD_CORE pins.
6.1.2 Externally regulated power
Optionally, the on-chip regulators may be left unused, and the core and memory domains
may instead be powered from external supplies. For simplicity, the voltage for the core
domain can be raised to nominal 1.8 V, requiring only one external regulator. Note that if the
core domain is powered at a higher voltage (1.8 V instead of 1.25 V) then power
consumption increases. A regulator enable signal, REG_EN, is provided for control of
external regulators. This is an open-drain signal that requires an external pull-up resistor. If
REG_EN is not required to control external regulators it can be disabled (see Section 8.1.3:
Forced functions on page 95).
Using an external regulator requires the always-on domain to be powered between 1.8 V
and 3.6 V at all four VDD_PADS pins.
When using an external regulator, the VREG_1V8 regulator output pin (VREG_OUT) must
be left unconnected.
When using an external regulator, this external nominal 1.8 V supply has to be connected to
both VDD_CORE pins and to the VDD_MEM, VDD_PADSA, VDD_VCO, VDD_RF, VDD_IF,
VDD_PRE and VDD_SYNTH pins.
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6.2 Resets
The STM32W108xx resets are generated from a number of sources. Each of these reset
sources feeds into central reset detection logic that causes various parts of the system to be
reset depending on the state of the system and the nature of the reset event.
6.2.1 Reset sources
For power-on reset (POR HV and POR LV) thresholds, see Section 14.3.2: Operating
conditions at power-up on page 249.
Watchdog reset
The STM32W108xx contains a watchdog timer (see also the Watchdog Timer section) that
is clocked by the internal 1 kHz timing reference. When the timer expires it generates the
reset source WATCHDOG_RESET to the Reset Generation module.
Software reset
The ARM® Cortex®-M3 CPU can initiate a reset under software control. This is indicated
with the reset source SYSRESETREQ to the Reset Generation module.
Note: When using certain external debuggers, the chip may lock up require a pin reset or power
cycle if the debugger asserts SYSRESETREQ. It is recommended not to write to the
SCS_AIRCR register directly from application code. The ST software provides a reset
function that should be used instead. This reset function ensures that the chip is in a safe
clock mode prior to triggering the reset.
Option byte error
The Flash memory controller contains a state machine that reads configuration information
from the information blocks in the Flash at system start time. An error check is performed on
the option bytes that are read from Flash and, if the check fails, an error is signaled that
provides the reset source OPT_BYTE_ERROR to the Reset Generation module.
If an option byte error is detected, the system restarts and the read and check process is
repeated. If the error is detected again the process is repeated but stops on the 3rd failure.
The system is then placed into an emulated deep sleep where recovery is possible. In this
state, Flash memory readout protection is forced active to prevent secure applications from
being compromised.
Debug reset
The Serial Wire/JTAG Interface (SWJ) provides access to the SWJ Debug Port (SWJ-DP)
registers. By setting the register bit CDBGRSTREQ in the SWJ-DP, the reset source
CDBGRSTREQ is provided to the Reset Generation module.
JTAG reset
One of the STM32W108xx's pins can function as the JTAG reset, conforming to the
requirements of the JTAG standard. This input acts independently of all other reset sources
and, when asserted, does not reset any on-chip hardware except for the JTAG TAP. If the
STM32W108xx is in the Serial Wire mode or if the SWJ is disabled, this input has no effect.
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Deep sleep reset
The Power Management module informs the Reset Generation module of entry into and exit
from the deep sleep states. The deep sleep reset is applied in the following states: before
entry into deep sleep, while removing power from the memory and core domain, while in
deep sleep, while waking from deep sleep, and while reapplying power until reliable power
levels have been detect by POR LV.
The Power Management module allows a special emulated deep sleep state that retains
memory and core domain power while in deep sleep.
6.2.2 Reset recording
The STM32W108xx records the last reset condition that generated a restart to the system.
The reset conditions recorded are:
PWRHV Always-on domain power supply failure
PWRLV Core or memory domain power supply failure
RSTB NRST pin asserted
WDG Watchdog timer expired
SWRST Software reset by SYSERSETREQ from ARM® Cortex®-M3
CPU
WKUP Wake-up from deep sleep
OBFAIL Error check failed when reading option bytes from Flash
memory
The Reset status register (RST_SR) is used to read back the last reset event. All bits are
mutually exclusive except the OBFAIL bit which preserves the original reset event when set.
Note: While CPU Lockup is marked as a reset condition in software, CPU Lockup is not
specifically a reset event. CPU Lockup is set to indicate that the CPU entered an
unrecoverable exception. Execution stops but a reset is not applied. This is so that a
debugger can interpret the cause of the error. We recommend that in a live application (i.e.
no debugger attached) the watchdog be enabled by default so that the STM32W108xx can
be restarted.
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6.2.3 Reset generation
The Reset Generation module responds to reset sources and generates the following reset
signals:
PORESET Reset of the ARM® Cortex®-M3 CPU and ARM® Cortex®-M3
System Debug components (Flash Patch and Breakpoint,
Data Watchpoint and Trace, Instrumentation Trace Macrocell,
Nested Vectored Interrupt Controller). ARM defines
PORESET as the region that is reset when power is applied.
SYSRESET Reset of the ARM® Cortex®-M3 CPU without resetting the
Core Debug and System Debug components, so that a live
system can be reset without disturbing the debug
configuration.
DAPRESET Reset to the SWJ's AHB Access Port (AHB-AP).
PRESETHV Peripheral reset for always-on power domain, for peripherals
that are required to retain their configuration across a deep
sleep cycle.
PRESETLV Peripheral reset for core power domain, for peripherals that
are not required to retain their configuration across a deep
sleep cycle.
Table 6 shows which reset sources generate certain resets.
Table 6. Generated resets
Reset source Reset generation
PORESET SYSRESET DAPRESET PRESETHV PRESETLV
POR HV XXXXX
POR LV (in deep sleep) X X X - X
POR LV (not in deep
sleep) XXXXX
RSTB X X - X X
Watchdog reset - X - X X
Software reset - X - X X
Option byte error X X - - X
Normal deep sleep X X X - X
Emulated deep sleep - X - - X
Debug reset - X - - -
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6.2.4 Reset register
Reset status register (RST_SR)
Address offset: 0x4000 002C
Reset value: 0x0000 0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
LKUP OBFAIL WKUP SWRST WDG PIN PWRLV PWRHV
rr r rrrr r
Bits 31:8 Reserved, must be kept at reset value
Bit 7 LKUP:
When set to ‘1’, the reset is due to core lockup.
Bit 6 OBFAIL:
When set to ‘1’, the reset is due to an Option byte load failure (may be set with other bits).
Bit 5 WKUP:
When set to ‘1’, the reset is due to a wake-up from deep sleep.
Bit 4 SWRST:
When set to ‘1’, the reset is due to a software reset.
Bit 3 WDG:
When set to ‘1’, the reset is due to watchdog expiration.
Bit 2 PIN:
When set to ‘1’, the reset is due to an external reset pin signal.
Bit 1 PWRLV:
When set to ‘1’, the reset is due to the application of a Core power supply (or previously
failed).
Bit 0 PWRHV:
Always set to ‘1’, Normal power applied.
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Reset (RST) register map
Table 7 gives the RST register map and reset values.
Refer to Figure 4: STM32W108xB memory mapping, Figure 5: STM32W108CC and
STM32W108CZ memory mapping, and Table 3: STM32W108xx peripheral register
boundary addresses for the register boundary addresses of the peripherals available in all
STM32W108xx devices.
Table 7. RST register map and reset values
Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
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OBFAIL
WKUP
SWRST
WDG
PIN
PWRLV
PWRHV
Reset value 00000000
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6.3 Clocks
The STM32W108xx integrates four oscillators:
High frequency RC oscillator (HSI)
24 MHz crystal oscillator (HSE)
10 kHz LSI RC oscillator (LSI10K)
32.768 kHz crystal oscillator (LSE)
Note: The LSI1K clock is generated from the 10 kHz LSI RC oscillator (LSI10K). The default value
is a divide by 10 for a nominal 1 kHz output clock.
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Figure 7 shows a block diagram of the clocks in the STM32W108xx. This simplified view
shows all the clock sources and the general areas of the chip to which they are routed.
Figure 7. Clocks block diagram
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6.3.1 High-frequency internal RC oscillator (HSI)
The high-frequency RC oscillator (HSI) is used as the default system clock source when
power is applied to the core domain. The nominal frequency coming out of reset is 12 MHz.
Most peripherals, excluding the radio peripheral, are fully functional using the HSI clock
source. Application software must be aware that peripherals are clocked at different speeds
depending on whether HSI or HSE OSC is being used. Since the frequency step of HSI is
0.5 MHz and the high-frequency crystal oscillator is used for calibration, the calibrated
accuracy of HSI is ±250 kHz ±40 ppm. The UART and ADC peripherals may not be usable
due to the lower accuracy of the HSI frequency.
See also Section 14.6.1: High frequency internal clock characteristics on page 259.
6.3.2 High-frequency crystal oscillator (HSE OSC)
The high-frequency crystal oscillator (HSE OSC) requires an external 24 MHz crystal with
an accuracy of ±40 ppm. Based upon the application's bill of materials and current
consumption requirements, the external crystal may cover a range of ESR requirements.
The crystal oscillator has a software-programmable bias circuit to minimize current
consumption. ST software configures the bias circuit for minimum current consumption.
All peripherals including the radio peripheral are fully functional using the HSE OSC clock
source. Application software must be aware that peripherals are clocked at different speeds
depending on whether HSI or HSE OSC is being used.
If the 24 MHz crystal fails, a hardware failover mechanism forces the system to switch back
to the high-frequency RC oscillator as the main clock source, and a non-maskable interrupt
(NMI) is signaled to the ARM® Cortex®-M3 NVIC.
See also Section 14.6.2: High frequency external clock characteristics on page 259.
6.3.3 Low-frequency internal RC oscillator (LSI10K)
A low-frequency RC oscillator (LSI10K) is provided as an internal timing reference. The
nominal frequency coming out of reset is 10 kHz, and ST software calibrates this clock to
10 kHz. From the tuned 10 kHz oscillator (LSI10K) ST software calibrates a fractional-N
divider to produce a 1 kHz reference clock, LSI1K.
See also Section 14.6.3: Low frequency internal clock characteristics on page 260.
6.3.4 Low-frequency crystal oscillator (LSE OSC)
A low-frequency 32.768 kHz crystal oscillator (LSE OSC) is provided as an optional timing
reference for on-chip timers. This oscillator is designed for use with an external watch
crystal.
See also Section 14.6.4: Low frequency external clock characteristics on page 260.
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6.3.5 Clock switching
The STM32W108xx has two switching mechanisms for the main system clock, providing
four clock modes.
The register bit SW1 in the CLK_HSECR2 register switches between the high-frequency RC
oscillator (HSI) and the high-frequency crystal oscillator (HSE OSC) as the main system
clock (SCLK). The peripheral clock (PCLK) is always half the frequency of SCLK.
The register bit SW2 in the CLK_CPUCR register switches between PCLK and SCLK to
produce the ARM® Cortex®-M3 CPU clock (FCLK). The default and preferred mode of
operation is to run the CPU at the lower PCLK frequency, 12 MHz, but the higher SCLK
frequency, 24 MHz, can be selected to give higher processing performance at the expense
of an increase in power consumption.
In addition to these modes, further automatic control is invoked by hardware when Flash
programming is enabled. To ensure accuracy of the Flash controller's timers, the FCLK
frequency is forced to 12 MHz during Flash programming and erase operations.
Table 8. System clock modes
SW1 CLK_CPUCR SCLK PCLK
fCLK
Flash
Program/
Erase Inactive
Flash
Program/
Erase Active
0 (HSI) 0 (Normal CPU) 12 MHz 6 MHz 6 MHz 12 MHz
0 (HSI) 1 (Fast CPU) 12 MHz 6 MHz 12 MHz 12 MHz
1 (HSE OSC) 0 (Normal CPU) 24 MHz 12 MHz 12 MHz 12 MHz
1 (HSE OSC) 1 (Fast CPU) 24 MHz 12 MHz 24 MHz 12 MHz
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6.3.6 Clock switching registers
Clock sleep mode control register (CLK_SLEEPCR)
The sleep timer controls the low power clock gated modes.
Clearing the LSI10KEN bit in the CLK_SLEEPCR register before executing WFI with the
SLEEPDEEP bit set to '1' in the SCB_SCR register (for more details refer to the Cortex-M3
Programming manual PM0056) causes deep sleep 2 mode to be entered. Setting the
LSI10KEN bit in the CLK_SLEEPCR register causes deep sleep 1 mode to be entered.
Address: 0x4000 0008
Reset value: 0x0000 0002
Low-speed internal 10 KHz clock (LSI10K) control register (CLK_LSI10KCR)
Address: 0x4000 000C
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
LSI10KEN LSEEN
rw rw
Bits 31:2 Reserved, must be kept at reset value
Bit 1 LSI10KEN:
1: Enables 10 kHz internal RC during deep sleep mode.
2: Disables 10 kHz internal RC during deep sleep mode
Bit 0 LSEEN:
1: Enables 32 kHz external oscillator during deep sleep mode.
2: Disables 32 kHz external oscillator during deep sleep mode.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
TUNE[3:0]
rw rw rw rw
Bits 1:4 Reserved, must be kept at reset value
Bits 3:0 TUNE[3:0]:
Tunes the value for the HSI clock.
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Low-speed internal 1 KHz clock control register (CLK_LSI1KCR)
Address: 0x4000 0010
Reset value: 0x0000 5000
High-speed external clock control register 1 (CLK_HSECR1)
Address: 0x4000 4004
Reset value: 0x0000 000F
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALINT[4:0] CLKFRAC[10:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:16 Reserved, must be kept at reset value
Bits 15:11 CALINT[4:0]:
Divider value integer portion.
Bits 10:0 CALINT[10:0]:
Divider value fractional portion.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
BIASTRIM[3:0]
rw rw rw rw
Bits 31:4 Reserved, must be kept at reset value
Bits 3:0 BIASTRIM[3:0]:
Bias trim setting for 24-MHz oscillator. Reset to full bias power up. May be overwritten in
software.
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High-speed internal clock control register (CLK_HSICR)
Address: 0x4000 4008
Reset value: 0x0000 0017
High-speed external clock comparator register (CLK_HSECOMPR)
Address: 0x4000 400C
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
TUNE[4:0]
rw rw rw rw rw
Bits 31:5 Reserved, must be kept at reset value
Bits 4:0 TUNE[4:0]:
Frequency trim setting for the high-speed internal oscillator.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
HLEVEL LLEVEL
rr
Bits 31:2 Reserved, must be kept at reset value
Bit 1 HLEVEL: High-level comparator output
1: High-level comparator output set.
0: High-level comparator output reset.
Bit 0 LLEVEL: Low-level comparator output
1: Low-level comparator output set.
0: Low-level comparator output reset.
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Clock period control register (CLK_PERIODCR)
Address: 0x4000 4010
Reset value: 0x0000 0000
Clock period status register (CLK_PERIODSR)
Address: 0x4000 4014
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
MODE[1:0]
rw rw
Bits 31:2 Reserved, must be kept at reset value
Bits 1:0 MODE[1:0]: Sets the clock to be measured by CLK_PERIOD
3: Not used
2: Measures TUNE_FILTER_RESULT
1: Measures HSI
0: Measures LSI
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PERIOD[15:0]
rrrrrrr r r r r rr r r r
Bits 31:16 Reserved, must be kept at reset value
Bits 15:0 PERIOD[15:0]: Measures the number of 12-MHz clock cycles in 16 or 256 periods (depending
on the MODE bits in the CLK_PERIODCR register) of the selected clock.
16 x 12 MHz clock period in LSI10K mode or 256 x 12 MHz clock period in HSI mode.
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Clock dither control register (CLK_DITHERCR)
Address: 0x4000 4018
Reset value: 0x0000 0000
High-speed external clock control register 2 (CLK_HSECR2)
Address: 0x4000 401C
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
DIS
rws
Bits 31:1 Reserved, must be kept at reset value
Bit 0 DIS: Dither disable
1: Dither enable
0: Dither disable
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
EN SW1
rws rws
Bits 31:2 Reserved, must be kept at reset value
Bit 1 EN: External high-speed clock enable
When set to “1”, the main clock is 24-MHz HSE OSC.
1: Enables the 24-MHz HSE OSC.
0: Disables the 24-MHz HSE OSC.
Bit 0 SW1: System clock switch
1: HSE (external high-speed clock) is selected.
0: HSI (internal high-speed clock) is selected.
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CPU clock control register (CLK_CPUCR)
Address: 0x4000 4020
Reset value: 0x0000 0000
Note: Clock selection determines if the RAM controller is running at the same speed as the PCLK
(SW2 = ‘1’) or double speed of PCLK (SW2 = ‘0’).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
SW2
rws
Bits 31:1 Reserved, must be kept at reset value
Bit 0 SW2: Switch clock 2
1: 24-MHz CPU clock selected
0: 12-MHz CPU clock selected
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Clock switching (CLK) register map
Table 9 gives the CLK register map and reset values.
Refer to Figure 4: STM32W108xB memory mapping, Figure 5: STM32W108CC and
STM32W108CZ memory mapping, and Table 3: STM32W108xx peripheral register
boundary addresses for the register boundary addresses of the peripherals available in all
STM32W108xx devices.
Table 9. CLK register map and reset values
Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0008 CLK_SLEEPCR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
LSI10KEN
LSEEN
Reset value 10
0x000C CLK_LSI10KCR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TUNE[3:0]
Reset value 0000
0x0010 CLK_LSI1KCR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CALINT[4:0] CLKFRAC[10:0]
Reset value 0101000000000000
0x0014-
0x4000
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0x4004 CLK_HSECR1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
BIASTRIM
[3:0]
Reset value 1111
0x4008 CLK_HSICR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TUNE[4:0]
Reset value 01111
0x400C CLK_HSECOMPR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
HLEVEL
LLEVEL
Reset value 00
0x4010 CLK_PERIODCR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
MODE[1:0]
Reset value 00
0x4014 CLK_PERIODSR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PERIOD[15:0]
Reset value 0000000000000000
0x4018 CLK_DITHERCR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DIS
Reset value 0
0x401C CLK_HSECR2
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
EN
SW1
Reset value 00
0x4020 CLK_CPUCR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SW2
Reset value 0
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6.4 System timers
6.4.1 MAC timer
The STM32W108 devices integrate a 20-bit counter (MACTMR_CNTR register) dedicated
to the MAC timer. The counting mode of the MAC timer is controlled using the
MACTMR_CR register. This register (MACTMR_CR) integrates two bits: one to enable the
counting mode and the other to reset the value of the counter (MACTMR_CNTR register).
6.4.2 Watchdog timer
The STM32W108xx integrates a watchdog timer which can be enabled to provide protection
against software crashes and ARM® Cortex®-M3 CPU lockup. By default, it is disabled at
power up of the always-on power domain. The watchdog timer uses the calibrated 1 kHz
clock (LSI1K) as its reference and provides a nominal 2.048 s timeout. A low water mark
interrupt occurs at 1.792 s and triggers an NMI to the ARM® Cortex®-M3 NVIC as an early
warning. When enabled, periodically reset the watchdog timer by writing to the
WDG_KICKSR register before it expires.
The watchdog timer can be paused when the debugger halts the ARM® Cortex®-M3. To
enable this functionality, set the bit DBGP bit in the SLPTMR_CR register.
If the low-frequency internal RC oscillator (LSI10K) is turned off during deep sleep, LSI1K
stops. As a consequence the watchdog timer stops counting and is effectively paused
during deep sleep.
The watchdog enable/disable bits are protected from accidental change by requiring a two
step process. To enable the watchdog timer the application must first write the enable code
0xEABE to the WDG_KR register and then set the WDGEN register bit. To disable the timer
the application must write the disable code 0xDEAD to the WDG_KR register and then set
the WDGDIS register bit.
6.4.3 Sleep timer
The STM32W108xx integrates a 32-bit timer dedicated to system timing and waking from
sleep at specific times. The sleep timer can use either the calibrated 1 kHz
reference(LSI1K), or the 32 kHz crystal clock (LSE). The default clock source is the internal
1 kHz clock. The sleep timer clock source is chosen with the CLKSEL bit in the
SLPTMR_CR register.
The sleep timer has a prescaler, a divider of the form 2^N, where N can be programmed
from 1 to 2^15. This divider allows for very long periods of sleep to be timed. The timer
provides two compare outputs and wrap detection, all of which can be used to generate an
interrupt or a wake up event.
The sleep timer is paused when the debugger halts the ARM® Cortex®-M3. No additional
register bit must be set.
To save current during deep sleep, the low-frequency internal RC oscillator (LSI10K) can be
turned off. If LSI10K is turned off during deep sleep and a low-frequency 32.768 kHz crystal
oscillator is not being used, then the sleep timer will not operate during deep sleep and
sleep timer wake events cannot be used to wakeup the STM32W108xx.
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6.4.4 Event timer
The SysTick timer is an ARM® standard system timer in the NVIC. The SysTick timer can be
clocked from either the FCLK (the clock going into the CPU) or the Sleep Timer clock. FCLK
is either the SCLK or PCLK as selected by CLK_CPUCR (see Section 6.3.5: Clock
switching on page 56).
6.4.5 Slow timer (MAC timer, Watchdog, and Sleeptimer) control and status
registers
These registers are powered from the always-on power domain.
All registers are only writable when in System mode
MACTimer counter register (MACTMR_CNTR)
Address: 0x4000 2038
Reset value: 0x0000 0000
MACTimer counter register (MACTMR_CR)
Address: 0x4000 208C
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
CNT[19:16]
rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:20 Reserved, must be kept at reset value
Bits 19:0 CNT[19:0]: MAC timer counter value
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
RST EN
rw rw
Bits 31:2 Reserved, must be kept at reset value
Bit 1 RST: MAC timer reset
Bit 0 EN: MAC timer enable
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Watchdog control register (WDG_CR)
Register bits for general top level chip functions and protection.
Watchdog bits can only be written after first writing the appropriate code to the WDG_KR
register.
Address: 0x4000 6000
Reset value: 0x0000 0002
Watchdog key register (WDG_KR)
Requires magic number write to arm the watchdog enable or disable function.
Address: 0x4000 6004
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
WDG
DIS
WDG
EN
rw rw
Bits 31:2 Reserved, must be kept at reset value
Bit 1 WDGDIS: Watchdog disable
Bit 0 WDGEN: Watchdog enable
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY[15:0]
wwwwww w w w w w ww w w w
Bits 31:16 Reserved, must be kept at reset value
Bits 15:0 KEY[15:0]:
Write 0xDEAD to disable or 0xEABE to enable.
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Watchdog kick-start register (WDG_KICKSR)
Write any value to this register to kick-start the watchdog.
Address: 0x4000 6008
Reset value: 0x0000 0000
Sleep timer configuration register (SLPTMR_CR)
This register sets the various options for the Sleep timer.
Address: 0x4000 600C
Reset value: 0x0000 0400
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KS[15:0]
wwwwww w w w w w ww w w w
Bits 31:16 Reserved, must be kept at reset value
Bits 15:0 KS[15:0]:
Watchdog kick-start value: write any value to restart the watchdog.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
REVERSE EN DBGP
Reserved
PSC[3:0]
Reserved
CLK
SEL
rw rw rw rw rw rw rw rw
Bits 31:13 Reserved, must be kept at reset value
Bit 12 REVERSE:
0: Count forward
1: Count backwards
Only changes when EN is set to ‘0’
Bit 11 EN:
0: Disable sleep timer
1: Enable sleep timer
To change other register bits (REVERSE, PSC, CLKSEL), this bit must be set to ‘0’.
Enabling/Disabling latency can be up 2 to 3 clock-periods of selected clock.
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Sleep timer count high register (SLPTMR_CNTH)
Address: 0x4000 6010
Reset value: 0x0000 0000
Bit 10 DBGP: Debug pause
0: The timer continues working in Debug mode.
1: The timer is paused in Debug mode when the CPU is halted.
Bits 9:8 Reserved, must be kept at reset value
Bits 7:4 PSC[3:0]: Sleep timer prescaler setting
Divides clock by 2N where N = 0 to 15.
Can only be changed when the EN is set to ‘0’.
Bits 3:1 Reserved, must be kept at reset value
Bit 0 CLKSEL: Clock select
0: Calibrated 1kHz RC clock (default); 1: 32kHz.
Can only be changed when the EN is set to ‘0’.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNTH[15:0]
rrrrrr r r r r r rr r r r
Bits 31:16 Reserved, must be kept at reset value
Bits 15:0 CNTH[15:0]: Sleep timer counter high value
Reading this register updates the SLEEP_CNTL for subsequent reads.
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Sleep timer count low register (SLPTMR_CNTL)
Address: 0x4000 6014
Reset value: 0x0000 0000
Sleep timer compare A high register (SLPTMR_CMPAH)
Address: 0x4000 6018
Reset value: 0x0000 FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNTL[15:0]
rrrrrr r r r r r rr r r r
Bits 31:16 Reserved, must be kept at reset value
Bits 15:0 CNTL[15:0]: Sleep timer counter low value
This register is only valid following a read of the SLPTMR_CNTH register.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMPAH[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:16 Reserved, must be kept at reset value
Bits 15:0 CMPAH[15:0]: Sleep timer compare A high value
Sleep timer compare value - writing to this register updates the SLPTMR_CMPAH register
directly and updates the SLPTMR_CMPAL register from the hold register. This value can
only be changed when the sleep timer is disabled (EN bit set to 0 in the SLPTMR_CR
register). If the value is changed when the sleep timer is enabled (EN bit set to ‘1’ in the
SLPTMR_CR register), a spurious interrupt may be generated. Therefore it is recommended
to disable sleep timer interrupts before changing this register.
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Sleep timer compare A low register (SLPTMR_CMPAL)
Address: 0x4000 601C
Reset value: 0x0000 FFFF
Sleep timer compare B high register (SLPTMR_CMPBH)
Address: 0x4000 6020
Reset value: 0x0000 FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMPAL[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:16 Reserved, must be kept at reset value
Bits 15:0 CMPAL[15:0]: Sleep timer compare A low value
Writing to this register puts the value in the hold register until a write to the SLPTMR_CMPAH
register. The value can only be changed when the sleep timer is disabled (EN bit set to ‘0’ in
the SLPTMR_CR register). If the value is changed when the sleep timer is enabled (EN bit
set to ‘1’ in the SLPTMR_CR register) a spurious interrupt may be generated. Therefore it is
recommended to disable interrupts before changing this register.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMPBH[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:16 Reserved, must be kept at reset value
Bits 15:0 CMPBH[15:0]: Sleep timer compare B high value
Sleep timer compare value - writing to this register updates the SLPTMR_CMPBH register
directly and updates the SLPTMR_CMPBL register from the hold register. This value can
only be changed when the EN (bit 11 of SLPTMR_CR register) is set to ‘0’. If the value is
changed when the EN bit is set to ‘1’, a spurious interrupt may be generated. Therefore it is
recommended to disable interrupts before changing this register.
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Sleep timer compare B low register (SLPTMR_CMPBL)
Address: 0x4000 6024
Reset value: 0x0000 FFFF
Sleep timer interrupt source register (SLPTMR_ISR)
Address: 0x4000 A014
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMPBL[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:16 Reserved, must be kept at reset value
Bits 15:0 CMPBL[15:0]: Sleep timer compare B low value
Writing to this register puts the value in the hold register until a write to the SLPTMR_CMPBH
register. The value can only be changed when the sleep timer is enabled (EN bit set to ‘0’ in
the SLPTMR_CR register) is set to ‘0’. If the value is changed when the sleep timer is
enabled (EN bit set to ‘1’ in the SLPTMR_CR register), a spurious interrupt may be
generated. Therefore it is recommended to disable interrupts before changing this register.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
CMPB CMPA WRAP
rw rw rw
Bits 31:3 Reserved, must be kept at reset value
Bit 2 CMPB: Sleep timer compare B
Bit 1 CMPA: Sleep timer compare A
Bit 0 WRAP: Sleep timer wrap
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Sleep timer force interrupt register (SLPTMR_IFR)
Address: 0x4000 A020
Reset value: 0x0000 0000
Sleep timer interrupt enable register (SLPTMR_IER)
Address: 0x4000 A054
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
CMPB CMPA WRAP
rw rw rw
Bits 31:3 Reserved, must be kept at reset value
Bit 2 CMPB: Force sleep timer compare B interrupt
Bit 1 CMPA: Force sleep timer compare A interrupt
Bit 0 WRAP: Force sleep timer wrap interrupt
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
CMPB CMPA WRAP
rw rw rw
Bits 31:3 Reserved, must be kept at reset value
Bit 2 CMPB: Sleep timer compare B
Bit 1 CMPA: Sleep timer compare A
Bit 0 WRAP: Sleep timer wrap
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MAC timer (MACTMR)/Watchdog (WDG)/Sleeptimer(SLPTMR) register map
Table 10 gives the MACTMR, WDG, and SLPTMR register map and reset values.
Table 10. MACTMR, WDG, and SLPTMR register map and reset values
Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x2038 MACTMR_CNTR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CNT[19:0]
Reset value 00000000000000000000
0x208C MACTMR_CR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
RST
EN
Reset value 00
0x6000 WDG_CR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
WDGDIS
WDGEN
Reset value 10
0x6004 WDG_KR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
KEY[15:0]
Reset value 0000000000000000
0x6008 WDG_KICKSR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
KS[15:0]
Reset value 0000000000000000
0x600C SLPTMR_CR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
REVERSE
EN
DBGP
Res.
Res.
PSC[3:0]
Res.
Res.
Res.
CLKSEL
Reset value 001 0000 0
0x6010 SLPTMR_CNTH
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CNTH[15:0]
Reset value 0000000000000000
0x6014 SLPTMR_CNTL
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CNTL[15:0]
Reset value 0000000000000000
0x6018 SLPTMR_CMPAH
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CMPAH[15:0]
Reset value 0000000000000000
0x601C SLPTMR_CMPAL
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CMPAL[15:0]
Reset value 0000000000000000
0x6020 SLPTMR_CMPBH
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CMPBH[15:0]
Reset value 0000000000000000
0x6024 SLPTMR_CMPBL
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CMPBL[15:0]
Reset value 0000000000000000
0xA014 SLPTMR_ISR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CMPB
CMPA
WRAP
Reset value 000
0xA020 SLPTMR_IFR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CMPB
CMPA
WRAP
Reset value 000
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Refer to Figure 4: STM32W108xB memory mapping, Figure 5: STM32W108CC and
STM32W108CZ memory mapping, and Table 3: STM32W108xx peripheral register
boundary addresses for the register boundary addresses of the peripherals available in all
STM32W108xx devices.
6.5 Power management
The STM32W108xx's power management system is designed to achieve the lowest deep
sleep current consumption possible while still providing flexible wakeup sources, timer
activity, and debugger operation. The STM32W108xx has four main sleep modes:
Idle Sleep: Puts the CPU into an idle state where execution is suspended until any
interrupt occurs. All power domains remain fully powered and nothing is reset.
Deep sleep 1: The primary deep sleep state. In this state, the core power domain is
fully powered down and the sleep timer is active
Deep sleep 2: The same as deep sleep 1 except that the sleep timer is inactive to save
power. In this mode the sleep timer cannot wakeup the STM32W108xx.
Deep sleep 0 (also known as emulated deep sleep): The chip emulates a true deep
sleep without powering down the core domain. Instead, the core domain remains
powered and all peripherals except the system debug components (ITM, DWT, FPB,
NVIC) are held in reset. The purpose of this sleep state is to allow STM32W108xx
software to perform a deep sleep cycle while maintaining debug configuration such as
breakpoints.
6.5.1 Wake sources
When in deep sleep the STM32W108xx can be returned to the running state in a number of
ways, and the wake sources are split depending on deep sleep 1 or deep sleep 2.
0xA054 SLPTMR_IER
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CMPB
CMPA
WRAP
Reset value 000
Table 10. MACTMR, WDG, and SLPTMR register map and reset values (continued)
Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
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The following wake sources are available in both deep sleep 1 and 2.
Wake on GPIO activity: Wake due to change of state on any GPIO.
Wake on serial controller 1: Wake due to a change of state on GPIO Pin PB2.
Wake on serial controller 2: Wake due to a change of state on GPIO Pin PA2.
Wake on IRQD: Wake due to a change of state on IRQD. Since IRQD can be
configured to point to any GPIO, this wake source is another means of waking on any
GPIO activity.
Wake on setting of CDBGPWRUPREQ: Wake due to setting the CDBGPWRUPREQ
bit in the debug port in the SWJ.
Wake on setting of CSYSPWRUPREQ: Wake due to setting the CSYSPWRUPREQ bit
in the debug port in the SWJ.
The following sources are only available in deep sleep 1 since the sleep timer is not active in
deep sleep 2.
Wake on sleep timer compare A.
Wake on sleep timer compare B.
Wake on sleep timer wrap.
The following source is only available in deep sleep 0 since the SWJ is required to write
memory to set this wake source and the SWJ only has access to some registers in deep
sleep 0.
Wake on write to the COREWAKE bit in the PWR_WAKECR2 register.
The Wakeup Recording module monitors all possible wakeup sources. More than one
wakeup source may be recorded because events are continually being recorded (not just in
deep-sleep), since another event may happen between the first wake event and when the
STM32W108xx wakes up.
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6.5.2 Basic sleep modes
The power management state diagram in Figure 8 shows the basic operation of the power
management controller.
Figure 8. Power management state diagram
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In normal operation an application may request one of two low power modes through
program execution:
Idle Sleep is achieved by executing a WFI instruction whilst the SLEEPDEEP bit in the
Cortex System Control register (SCS_SCR) is clear (for more details refer to the
Cortex-M3 Programming manual PM0056). This puts the CPU into an idle state where
execution is suspended until an interrupt occurs. This is indicated by the state at the
bottom of the diagram. Power is maintained to the core logic of the STM32W108xx
during the Idle Sleeping state.
Deep sleep is achieved by executing a WFI instruction whilst the SLEEPDEEP bit in
the Cortex System Control register (SCS_SCR) is set (for more details refer to the
Cortex-M3 Programming manual PM0056). This triggers the state transitions around
the main loop of the diagram, resulting in powering down the STM32W108xx's core
logic, and leaving only the always-on domain powered. Wake up is triggered when one
of the pre-determined events occurs.
If a deep sleep is requested the STM32W108xx first enters a pre-deep sleep state. This
state prevents any section of the chip from being powered off or reset until the SWJ goes
idle (by clearing CSYSPWRUPREQ). This pre-deep sleep state ensures debug operations
are not interrupted.
In the deep sleep state the STM32W108xx waits for a wake up event which will return it to
the running state. In powering up the core logic the ARM® Cortex®-M3 is put through a reset
cycle and ST software restores the stack and application state to the point where deep sleep
was invoked.
6.5.3 Further options for deep sleep
By default, the low-frequency internal RC oscillator (LSI10K) is running during deep sleep
(known as deep sleep 1).
To conserve power, LSI10K can be turned off during deep sleep. This mode is known as
deep sleep 2. Since the LSI10K is disabled, the sleep timer and watchdog timer do not
function and cannot wake the chip unless the low-frequency 32.768 kHz crystal oscillator is
used. Non-timer based wake sources continue to function. Once a wake event occurs, the
LSI10K restarts and becomes enabled.
6.5.4 Use of debugger with sleep modes
The debugger communicates with the STM32W108xx using the SWJ.
When the debugger is connected, the CDBGPWRUPREQ bit in the debug port in the SWJ
is set, the STM32W108xx will only enter deep sleep 0 (the emulated deep sleep state). The
CDBGPWRUPREQ bit indicates that a debug tool is connected to the chip and therefore
there may be debug state in the system debug components. To maintain the state in the
system debug components only deep sleep 0 may be used, since deep sleep 0 will not
cause a power cycle or reset of the core domain. The CSYSPWRUPREQ bit in the debug
port in the SWJ indicates that a debugger wants to access memory actively in the
STM32W108xx. Therefore, whenever the CSYSPWRUPREQ bit is set while the
STM32W108xx is awake, the STM32W108xx cannot enter deep sleep until this bit is
cleared. This ensures the STM32W108xx does not disrupt debug communication into
memory.
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Clearing both CSYSPWRUPREQ and CDBGPWRUPREQ allows the STM32W108xx to
achieve a true deep sleep state (deep sleep 1 or 2). Both of these signals also operate as
wake sources, so that when a debugger connects to the STM32W108xx and begins
accessing the chip, the STM32W108xx automatically comes out of deep sleep. When the
debugger initiates access while the STM32W108xx is in deep sleep, the SWJ intelligently
holds off the debugger for a brief period of time until the STM32W108xx is properly powered
and ready.
For more information regarding the SWJ and the interaction of debuggers with deep sleep,
contact ST support for Application Notes and ARM® CoreSight documentation.
6.5.5 Power management registers
Power deep sleep control register 1 (PWR_DSLEEPCR1)
Address: 0x4000 0004
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
LVFREEZ
EReserved
rw
Bits 31:2 Reserved, must be kept at reset value
Bit 1 LVFREEZE: LV freeze state
1: Enables LV freeze output states
0: Disables GPIO freeze
Bit 0 Reserved, must be kept at reset value
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Power deep sleep control register 2 (PWR_DSLEEPCR2)
Address: 0x4000 0014
Reset value: 0x0000 0001
Power voltage regulator control register (PWR_VREGCR)
Address: 0x4000 0018
Reset value: 0x0000 0204
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
MODE
rw
Bits 31:1 Reserved, must be kept at reset value
Bit 0 MODE: This bit is used only when the debugger is attached to enable deep sleep mode 0.
1: Enables deep sleep mode 0 when the debugger is attached (default condition).
0: Disables deep sleep mode 0 when the debugger is attached (the CPU is in deep sleep
mode 1 or 2).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
1V8EN
Reserved
1V8TRIM[2:0]
Reserved
1V2EN
Reserved
1V2TRIM[2:0]
rws rw rw rw rws rw rw rw
Bits 31:12 Reserved, must be kept at reset value
Bit 11 1V8EN: 1V8 direct control of regulator on/off
1: 1V8 regulator on
0: 1V8 regulator off
Bit 10 Reserved, must be kept at reset value
Bits 9:7 1V8TRIM: 1V8 regulator trim value
Bits 6:5 Reserved, must be kept at reset value
Bit 4 1V2EN: 1V2 direct control of regulator on/off
1: 1V2 regulator on
0: 1V2 regulator off
Bit 3 Reserved, must be kept at reset value
Bits 2:0 1V2TRIM: 1V2 regulator trim value
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Power wakeup event control register 1 (PWR_WAKECR1)
Address: 0x4000 0020
Reset value: 0x0000 0200
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
CRYSP
WRUP
REQ
CPWR
RUP
REQ
CORE WRAP COMPB COMP
AIRQD SC2 SC1 WAK
EEN
rw rw rw rw rw rws rw rw rw rw
Bits 31:10 Reserved, must be kept at reset value
Bit 9 CSYSPWRUPREQ: Wakeup on the CSYSPWRUPREQ event (move to running from deep
sleep 0).
1: Enables wakeup on CSYSPWRUPREQ event
0: Disables Wakeup on CSYSPWRUPREQ event
Bit 8 CPWRRUPREQ: Wakeup on the CPWRUPREQ event (move to running from deep sleep 0)
1: Enables wakeup on CPWRUPREQ event
0: Disables wakeup on CPWRUPREQ event
Bit 7 CORE: Wakeup on write to WAKE_CORE bit
1: Enables wakeup on write to WAKE_CORE bit
0: Disables wakeup on write to WAKE_CORE bit
Bit 6 WRAP: Wakeup on sleep timer compare wrap/overflow event
1: Enables wakeup on sleep timer compare wrap/overflow event
0: Disables wakeup on sleep timer compare wrap/overflow event
Bit 5 COMPB: Wake up on sleep timer compare B event
1: Enables wakeup on sleep timer compare B event
0: Disables wakeup on sleep timer compare B event
Bit 4 COMPA: Wakeup on sleep timer compare A event
1: Enables wakeup on sleep timer compare A event
0: Disables wakeup on sleep timer compare A event
Bit 3 IRQD: Wakeup on IRQD event
1: Enables wakeup on IRQD event
0: Disables wakeup on IRQD event
Bit 2 SC2: Wakeup on SC2 event
1: Enables wakeup on SC2 event
0: Disables wakeup on SC2 event
Bit 1 SC1: Wakeup on SC1 event
1: Enables wakeup on SC1 event
0: Disables wakeup on SC1 event
Bit 0 WAKEEN: Enable GPIO wakeup monitoring
1: Enables GPIO wakeup monitoring
0: Disables GPIO wakeup monitoring
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Power wakeup event control register 2 (PWR_WAKECR2)
Address: 0x4000 0024
Reset value: 0x0000 0000
Power wakeup event status register (PWR_WAKESR)
Address: 0x4000 0028
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
CORE
WAKE Reserved
w
Bits 31:10 Reserved, must be kept at reset value
Bit 5 COREWAKE: Power-up controlled by debug port activity. Write to this bit to wake core from
deep sleep 0.
Bits 4:0 Reserved, must be kept at reset value
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
CRYSP
WRUP
REQ
CPWR
RUP
REQ
CORE WRAP COMPB COMP
AIRQD SC2 SC1 GPIO
PIN
rw rw rw rw rw rw rw rw rw rw
Bits 31:10 Reserved, must be kept at reset value
Bit 9 CSYSPWRUPREQ: Indicates that a Debug Access Port (DAP) access to the SYS registers
triggered the wake event.
0: Wakeup on CSYSPWRUPREQ event not detected
1: Wakeup on CSYSPWRUPREQ event detected
Bit 8 CPWRRUPREQ: Wake indicates that a DAP access to the DBG registers triggered the wake
event.
0: Wakeup on CPWRRUPREQ event not detected
1: Wakeup on CPWRRUPREQ event detected
Bit 7 CORE: Wakeup on debug port activity
0: Wakeup on CORE event not detected
1: Wakeup on CORE event detected
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Power CPWRUPREQ status register (PWR_CPWRUPREQSR)
Address: 0x4000 0034
Reset value: 0x0000 0000
Bit 6 WRAP: Sleep timer wrap
0: Wakeup on WRAP event not detected
1: Wakeup on WRAP event detected
Bit 5 COMPB: Sleep timer compare B
0: Wakeup on COMPB event not detected
1: Wakeup on COMPB event detected
Bit 4 COMPA: Sleep timer compare A
0: Wake up on COMPA event not detected
1: Wake up on COMPA event detected
Bit 3 IRQD: Change of GPIO pin for external interrupt IRQD
0: Wakeup on IRQD event not detected
1: Wakeup on IRQD event detected
Bit 2 SC2: Serial control 2
0: Wakeup on SC2 event not detected
1: Wakeup on SC2 event detected
Bit 1 SC1: Serial control 1
0: Wakeup on SC1 event not detected
1: Wakeup on SC1 event detected
Bit 0 GPIOPIN: Change of programmable GPIO pin (programmable with GPIO wakeup monitoring)
0: Wakeup on GPIO pin not detected
1: Wakeup on GPIO pin detected
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
REQ
r
Bits 31:1 Reserved, must be kept at reset value
Bit 0 REQ: Status of the SPWRUPREQ
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Power CSYSPWRUPREQ status register (PWR_CSYSPWRUPREQSR)
Address: 0x4000 0038
Reset value: 0x0000 0000
Power CSYSPWRUPACK status register (PWR_CSYSPWRUPACKSR)
Address: 0x4000 003C
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
REQ
r
Bits 31:1 Reserved, must be kept at reset value
Bit 0 REQ: Status of the CSYSPWRUPREQ
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
ACK
r
Bits 31:1 Reserved, must be kept at reset value
Bit 0 ACK: Status of the CSYSPWRUPACK
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Power CSYSPWRUPACK control register (PWR_CSYSPWRUPACKCR)
Address: 0x4000 0040
Reset value: 0x0000 0000
Power GPIO wakeup monitoring port A register (PWR_WAKEPAR)
Address: 0x4000 BC08
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
INHIBIT
rw
Bits 31:1 Reserved, must be kept at reset value
Bit 0 INHIBIT: Value of CSYSPWRUPACK_INHIBIT (cleared by the power management state
machine as part of power-down sequence).
1: Inhibits CSYSPWRUPACK
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
rw rw rw rw rw rw rw rw
Bits 31:8 Reserved, must be kept at reset value
Bit 7 PA7
1: Enables GPIO wakeup on pin GPIO[ 7] changing state
0: Disables GPIO wakeup on pin GPIO[ 7] changing state
Bit 6 PA6
1: Enables GPIO wakeup on pin GPIO[ 6] changing state
0: Disables GPIO wakeup on pin GPIO[ 6] changing state
Bit 5 PA5
1: Enables GPIO wakeup on pin GPIO[ 5] changing state
0: Disables GPIO wakeup on pin GPIO[ 5] changing state
Bit 4 PA4
1: Enables GPIO wakeup on pin GPIO[ 4] changing state
0: Disables GPIO wakeup on pin GPIO[ 4] changing state
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Power GPIO wakeup monitoring port B register (PWR_WAKEPBR)
Address: 0x4000 BC0C
Reset value: 0x0000 0000
Bit 3 PA3
1: Enables GPIO wakeup on pin GPIO[ 3] changing state
0: Disables GPIO wakeup on pin GPIO[ 3] changing state
Bit 2 PA2
1: Enables GPIO wakeup on pin GPIO[ 2] changing state
0: Disables GPIO wakeup on pin GPIO[ 2] changing state
Bit 1 PA1
1: Enables GPIO wakeup on pin GPIO[ 1] changing state
0: Disables GPIO wakeup on pin GPIO[ 1] changing state
Bit 0 PA0
1: Enables GPIO wakeup on pin GPIO[ 0] changing state
0: Disables GPIO wakeup on pin GPIO[ 0] changing state
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
rw rw rw rw rw rw rw rw
Bits 31:8 Reserved, must be kept at reset value
Bit 7 PB7
1: Enables GPIO wakeup on pin GPIO[ 7] changing state
0: Disables GPIO wakeup on pin GPIO[ 7] changing state
Bit 6 PB6
1: Enables GPIO wakeup on pin GPIO[ 6] changing state
0: Disables GPIO wakeup on pin GPIO[ 6] changing state
Bit 5 PB5
1: Enables GPIO wakeup on pin GPIO[ 5] changing state
0: Disables GPIO wakeup on pin GPIO[ 5] changing state
Bit 4 PB4
1: Enables GPIO wakeup on pin GPIO[ 4] changing state
0: Disables GPIO wakeup on pin GPIO[ 4] changing state
Bit 3 PB3
1: Enables GPIO wakeup on pin GPIO[ 3] changing state
0: Disables GPIO wakeup on pin GPIO[ 3] changing state
Bit 2 PB2
1: Enables GPIO wakeup on pin GPIO[ 2] changing state
0: Disables GPIO wakeup on pin GPIO[ 2] changing state
System modules STM32W108HB STM32W108CB STM32W108CC STM32W108CZ
86/289 DocID16252 Rev 16
Power GPIO wakeup monitoring port C register (PWR_WAKEPCR)
Address: 0x4000 BC10
Reset value: 0x0000 0000
Bit 1 PB1
1: Enables GPIO wakeup on pin GPIO[ 1] changing state
0: Disables GPIO wakeup on pin GPIO[ 1] changing state
Bit 0 PB0
1: Enables GPIO wakeup on pin GPIO[ 0] changing state
0: Disables GPIO wakeup on pin GPIO[ 0] changing state
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
rw rw rw rw rw rw rw rw
Bits 31:8 Reserved, must be kept at reset value
Bit 7 PC7
1: Enables GPIO wakeup on pin GPIO[ 7] changing state
0: Disables GPIO wakeup on pin GPIO[ 7] changing state
Bit 6 PC6
1: Enables GPIO wakeup on pin GPIO[ 6] changing state
0: Disables GPIO wakeup on pin GPIO[ 6] changing state
Bit 5 PC5
1: Enables GPIO wakeup on pin GPIO[ 5] changing state
0: Disables GPIO wakeup on pin GPIO[ 5] changing state
Bit 4 PC4
1: Enables GPIO wakeup on pin GPIO[ 4] changing state
0: Disables GPIO wakeup on pin GPIO[ 4] changing state
Bit 3 PC3
1: Enables GPIO wakeup on pin GPIO[ 3] changing state
0: Disables GPIO wakeup on pin GPIO[ 3] changing state
Bit 2 PC2
1: Enables GPIO wakeup on pin GPIO[ 2] changing state
0: Disables GPIO wakeup on pin GPIO[ 2] changing state
Bit 1 PC1
1: Enables GPIO wakeup on pin GPIO[ 1] changing state
0: Disables GPIO wakeup on pin GPIO[ 1] changing state
Bit 0 PC0
1: Enables GPIO wakeup on pin GPIO[ 0] changing state
0: Disables GPIO wakeup on pin GPIO[ 0] changing state
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Power wakeup filter register (PWR_WAKEFILTR)
Address: 0x4000 BC1C
Reset value: 0x0000 000F
Power management (PWR) register map
Table 11 gives the PWR register map and reset values.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
IRQD SC2 SC1 GPIO
PIN
rw rw rw rw
Bits 31:4 Reserved, must be kept at reset value
Bit 3 IRQD_WAKE_FILTER: Enables filter on GPIO wakeup source IRQD
Bit 2 SC2_WAKE_FILTER: Enables filter on GPIO wakeup source SC2 (PA2)
Bit 1 SC1_WAKE_FILTER: Enables filter on GPIO wakeup source SC1 (PB2)
Bit 0 GPIO_WAKE_FILTER: Enables filter on GPIO wakeup sources enabled by the
PWR_WAKEPAR, PWR_WAKEPBR, and PWR_WAKEPCR registers.
Table 11. PWR register map and reset values
Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0004 PWR_DSLEEPCR1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
LVFREEZE
Res.
Reset value 0
0x0008-
0x0010
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0x0014 PWR_DSLEEPCR2
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
MODE
Reset value 0
0x0018 PWR_VREGCR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
1V8EN
Res.
1V8TRIM
[2:0]
Res.
Res.
1V2EN
Res.
1V2TRIM
[2:0]
Reset value 0100 0111
0x001C
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
System modules STM32W108HB STM32W108CB STM32W108CC STM32W108CZ
88/289 DocID16252 Rev 16
0x0020 PWR_WAKECR1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CSYSPWRUPREQ
CPWRRUPREQ
CORE
WRAP
COMPB
COMPA
IRQD
SC2
SC1
WAKEEN
Reset value 1000000000
0x0024 PWR_WAKECR2
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
COREWAKE
Res.
Res.
Res.
Res.
Res.
Reset value 0
0x0028 PWR_WAKESR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CSYSPWRUPREQ
CPWRRUPREQ
CORE
WRAP
COMPB
COMPA
IRQD
SC2
SC1
GPIOPIN
Reset value 0000000000
0x002C-
0x0030
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0x0034
PWR_CPWRUP
REQSR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
REQ
Reset value 0
0x0038
PWR_CSYSPWRUP
REQSR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
REQ
Reset value 0
0x003C
PWR_CSYSPWRUP
ACKSR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ACK
Reset value 0
0x0040
PWR_CSYSPWRUP
ACKCR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
INHIBIT
Reset value 0
0x0044-
0xBC04
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0xBC08 PWR_WAKEPAR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Reset value 00000000
0xBC0C PWR_WAKEPBR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
Reset value 00000000
0xBC10 PWR_WAKEPCR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
Reset value 00000000
0xBC14-
0xBC18
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0xBC1C PWR_WAKEFILTR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
IRQD
SC2
SC1
GPIOPIN
Reset value 0000
Table 11. PWR register map and reset values (continued)
Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
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Refer to Figure 4: STM32W108xB memory mapping, Figure 5: STM32W108CC and
STM32W108CZ memory mapping, and Table 3: STM32W108xx peripheral register
boundary addresses for the register boundary addresses of the peripherals available in all
STM32W108xx devices.
6.6 Security accelerator
The STM32W108xx contains a hardware AES encryption engine accessible from the ARM®
Cortex®-M3. NIST-based CCM, CCM, CBC-MAC, and CTR modes are implemented in
hardware. These modes are described in the IEEE 802.15.4-2003 specification, with the
exception of CCM, which is described in the ZigBee Security Services Specification 1.0.
Integrated voltage regulator STM32W108HB STM32W108CB STM32W108CC STM32W108CZ
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7 Integrated voltage regulator
The STM32W108xx integrates two low dropout regulators to provide 1.8 V and 1.25 V
power supplies. The 1V8 regulator supplies the analog and memories, and the 1V25
regulator supplies the digital core. In deep sleep the voltage regulators are disabled.
When enabled, the 1V8 regulator steps down the pads supply voltage (VDD_PADS) from a
nominal 3.0 V to 1.8 V. The regulator output pin (VREG_OUT) must be decoupled externally
with a suitable capacitor. VREG_OUT should be connected to the 1.8 V supply pins VDDA,
VDD_RF, VDD_VCO, VDD_SYNTH, VDD_IF, and VDD_MEM. The 1V8 regulator can
supply a maximum of 50 mA.
When enabled, the 1V25 regulator steps down VDD_PADS to 1.25 V. The regulator output
pin (VDD_CORE, (Pin 17) must be decoupled externally with a suitable capacitor. It should
connect to the other VDD_CORE pin (Pin 44). The 1V25 regulator can supply a maximum of
10 mA.
The regulators are controlled by the digital portion of the chip as described in Section 6:
System modules.
Table 12. 1.8 V integrated voltage regulator specifications
Parameter Min. Typ. Max. Units Comments
Supply range for regulator 2.1 3.6 V VDD_PADS
1V8 regulator output -5% 1.8 +5% V Regulator output after
initialization
1V8 regulator output after reset -5% 1.75 +5% V Regulator output after
reset
1V25 regulator output -5% 1.25 +5% V Regulator output after
initialization
1V25 regulator output after reset -5% 1.45 +5% V Regulator output after
reset
1V8 regulator capacitor - 2.2 - µF
Low ESR tantalum
capacitor
ESR greater than 2 Ω
ESR less than 10 Ω
De-coupling less than100
nF ceramic
1V25 regulator capacitor - 1.0 - µF Ceramic capacitor (0603)
1V8 regulator output current 0 - 50 mA Regulator output current
1V25 regulator output current 0 - 10 mA Regulator output current
No load current - 600 - µA No load current
(bandgap and regulators)
1V8 regulator current limit - 200 - mA Short circuit current limit
1V25 regulator current limit - 25 - mA Short circuit current limit
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An external 1.8 V regulator may replace both internal regulators. The STM32W108xx can
control external regulators during deep sleep using open-drain GPIO PA7, as described in
Section 8: General-purpose input/output. The STM32W108xx drives PA7 low during deep
sleep to disable the external regulator and an external pull-up is required to release this
signal to indicate that supply voltage should be provided. Current consumption increases
approximately 2 mA when using an external regulator. When using an external regulator the
internal regulators should be disabled through software.
1V8 regulator start-up time - 50 - µs 0 V to POR threshold 2.2
µF capacitor
1V25 regulator start-up time - 50 - µs 0 V to POR threshold 1.0
µF capacitor
Table 12. 1.8 V integrated voltage regulator specifications (continued)
Parameter Min. Typ. Max. Units Comments
fig? E~ +7 .— p7 ewe» WAKER
General-purpose input/output STM32W108HB STM32W108CB STM32W108CC STM32W108CZ
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8 General-purpose input/output
The STM32W108xx has 24 multi-purpose GPIO pins that may be individually configured as:
General purpose output
General purpose open-drain output
Alternate output controlled by a peripheral device
Alternate open-drain output controlled by a peripheral device
Analog
General purpose input
General purpose input with pull-up or pull-down resistor
The basic structure of a single GPIO is illustrated in Figure 9.
Figure 9. GPIO block diagram
A Schmitt trigger converts the GPIO pin voltage to a digital input value. The digital input
signal is then always routed to the GPIOx_IDR register; to the alternate inputs of associated
peripheral devices; to wake detection logic if wake detection is enabled; and, for certain
pins, to interrupt generation logic. Configuring a pin in analog mode disconnects the digital
input from the pin and applies a high logic level to the input of the Schmitt trigger.
Only one device at a time can control a GPIO output. The output is controlled in normal
output mode by the GPIOx_ODR register and in alternate output mode by a peripheral
device. When in input mode or analog mode, digital output is disabled.
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8.1 Functional description
8.1.1 GPIO ports
The 24 GPIO pins are grouped into three ports: PA, PB, and PC. Individual GPIOs within a
port are numbered 0 to 7 according to their bit positions within the GPIO registers.
Note: Because GPIO port registers' functions are identical, the notation x is used here to refer to
A, B, or C. For example, GPIOx_IDR refers to the registers GPIOA_IDR, GPIOB_IDR, and
GPIOC_IDR.
Each of the three GPIO ports has the following registers whose low-order eight bits
correspond to the port's eight GPIO pins:
GPIOx_IDR (input data register) returns the pin level (unless in analog mode).
GPIOx_ODR (output data register) controls the output level in normal output mode.
GPIOx_BRR (clear output data register) clears bits in GPIOx_ODR.
GPIOx_BSR (set output data register) sets bits in GPIOx_ODR.
PWR_WAKEPxR (wake monitor register) specifies the pins that can wake the
STM32W108xx.
In addition to these registers, each port has a pair of configuration registers, GPIOx_CRH
and GPIOx_CRL. These registers specify the basic operating mode for the port's pins.
GPIOx_CRL configures the pins CNFMODE3[3:0], CNFMODE2[3:0], CNFMODE1[3:0], and
CNFMODE0[3:0]. GPIOx_CRH configures the pins CNFMODE7[3:0], CNFMODE6[3:0],
CNFMODE5[3:0], and CNFMODE4[3:0]. Henceforth, the notation GPIOx_CRH/L is used to
refer to the pair of configuration registers.
Five GPIO pins (PA6, PA7, PB6, PB7 and PC0) can sink and source higher current than
standard GPIO outputs. Refer to Table 65: Digital I/O characteristics on page 266 for more
information.
General-purpose input/output STM32W108HB STM32W108CB STM32W108CC STM32W108CZ
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8.1.2 Configuration
Each pin has a 4-bit configuration value in the GPIOx_CRH/L register. The various GPIO
modes and their 4 bit configuration values are shown in Table 13.
If a GPIO has two peripherals that can be the source of alternate output mode data, then
other registers in addition to GPIOx_CRH/L determine which peripheral controls the output.
Several GPIOs share an alternate output with Timer 2 and the Serial Controllers. Bits in
Timer 2's TIM2_OR register control routing Timer 2 outputs to different GPIOs. Bits in Timer
2's TIM2_CCER register enable Timer 2 outputs. When Timer 2 outputs are enabled they
override Serial Controller outputs. Table 14 indicates the GPIO mapping for Timer 2 outputs
depending on the bits in the register TIM2_OR. Refer to Section 10: General-purpose timers
on page 160 for complete information on timer configuration.
For outputs assigned to the serial controllers, the serial interface mode registers (SCx_CR)
determine how the GPIO pins are used.
Table 13. GPIO configuration modes
GPIO mode GPIOx_CRH/L Description
Analog 0x0 Analog input or output. When in analog mode, the
digital input (GPIOx_IDR) always reads 1.
Input (floating) 0x4 Digital input without an internal pull up or pull down.
Output is disabled.
Input (pull-up or pull-down) 0x8
Digital input with an internal pull up or pull down. A
set bit in GPIOx_ODR selects pull up and a cleared
bit selects pull down. Output is disabled.
Output (push-pull) 0x1 Push-pull output. GPIOx_ODR controls the output.
Output (open-drain) 0x5 Open-drain output. GPIOx_ODR controls the
output. If a pull up is required, it must be external.
Alternate Output (push-pull) 0x9 Push-pull output. An onboard peripheral controls
the output.
Alternate Output
(open-drain) 0xD
Open-drain output. An onboard peripheral controls
the output. If a pull up is required, it must be
external.
Alternate Output (push-pull)
SPI SCLK Mode 0xB Push-pull output mode only for SPI master mode
SCLK pins.
Table 14. Timer 2 output configuration controls
Timer 2 output Option register bit GPIO mapping selected by TIM2_OR bit
01
TIM2_CH1 TIM2_OR[4] PA0 PB1
TIM2_CH2 TIM2_OR[5] PA3 PB2
TIM2_CH3 TIM2_OR[6] PA1 PB3
TIM2_CH4 TIM2_OR[7] PA2 PB4
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The alternate outputs of PA4 and PA5 can either provide packet trace data (PTI_EN and
PTI_DATA), or synchronous CPU trace data (TRACEDATA2 and TRACEDATA3).
If a GPIO does not have an associated peripheral in alternate output mode, its output is set
to 0.
8.1.3 Forced functions
For some GPIOs the GPIOx_CRH/L configuration may be overridden. Table 15 shows the
GPIOs that can have different functions forced on them regardless of the GPIOx_CRH/L
registers.
Note: The DEBUG_DIS bit in the GPIO_DBGCR register can disable the Serial Wire/JTAG
debugger interface. When this bit is set, all debugger-related pins (PC0, PC2, PC3, PC4)
behave as standard GPIO.
8.1.4 Reset
A full chip reset is one due to power on (low or high voltage), the NRST pin, the watchdog,
or the SYSRESETREQ bit. A full chip reset affects the GPIO configuration as follows:
The GPIOx_CRH/L configurations of all pins are configured as floating inputs.
The EXTREGEN bit is set in the GPIO_DBGCR register, which overrides the normal
configuration for PA7.
The DBGDIS bit in the GPIO_DBGCR register is cleared, allowing Serial Wire/JTAG
access to override the normal configuration of PC0, PC2, PC3, and PC4.
Table 15. GPIO forced functions
GPIO Override condition Forced function Forced signal
PA7 EXTREGEN bit set in the GPIO_DBGCR
register Open-drain output REG_EN
PC0 Debugger interface is active in JTAG mode Input with pull up JRST
PC2 Debugger interface is active in JTAG mode Push-pull output JTDO
PC3 Debugger interface is active in JTAG mode Input with pull up JDTI
PC4 Debugger interface is active in JTAG mode Input with pull up JTMS
PC4 Debugger interface is active in Serial Wire
mode
Bidirectional (push-pull
output or floating input)
controlled by debugger
interface
SWDIO
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8.1.5 nBOOTMODE
nBOOTMODE is a special alternate function of PA5 that is active only during a pin reset
(NRST) or a power-on-reset of the always-powered domain (POR_HV). If nBOOTMODE is
asserted (pulled or driven low) when coming out of reset, the processor starts executing an
embedded serial boot loader instead of its normal program.
While in reset and during the subsequent power-on-reset startup delay (512 high-frequency
RC oscillator periods), PA5 is automatically configured as an input with a pull-up resistor. At
the end of this time, the STM32W108xx samples nBOOTMODE: a high level selects normal
startup, and a low level selects the boot loader. After nBOOTMODE has been sampled, PA5
is configured as a floating input. The BOOTMODE bit in the GPIO_DBGSR register
captures the state of nBOOTMODE so that software may act on this signal if required.
Note: To avoid inadvertently asserting nBOOTMODE, PA5's capacitive load should not exceed
252 pF.
8.1.6 GPIO modes
Analog mode
Analog mode enables analog functions, and disconnects a pin from the digital input and
output logic. Only the following GPIO pins have analog functions:
PA4, PA5, PB5, PB6, PB7, and PC1 can be analog inputs to the ADC.
PB0 can be an external analog voltage reference input to the ADC, or it can output the
internal analog voltage reference from the ADC.
PC6 and PC7 can connect to an optional 32.768 kHz crystal.
Note: When an external timing source is required, a 32.768 kHz crystal is commonly connected to
PC6 and PC7. Alternatively, when PC7 is configured as a digital input, PC7 can accept a
digital external clock input.
When configured in analog mode:
The output drivers are disabled.
The internal pull-up and pull-down resistors are disabled.
The Schmitt trigger input is connected to a high logic level.
Reading GPIOx_IDR returns a constant 1.
Input mode
Input mode is used both for general purpose input and for on-chip peripheral inputs. Input
floating mode disables the internal pull-up and pull-down resistors, leaving the pin in a high-
impedance state. Input pull-up or pull-down mode enables either an internal pull-up or pull-
down resistor based on the GPIOx_ODR register. Setting a bit to 0 in GPIOx_ODR enables
the pull-down and setting a bit to 1 enables the pull up.
When configured in input mode:
The output drivers are disabled.
An internal pull-up or pull-down resistor may be activated depending on GPIOx_CRH/L
and GPIOx_ODR.
The Schmitt trigger input is connected to the pin.
Reading GPIOx_IDR returns the input at the pin.
The input is also available to on-chip peripherals.
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Output mode
Output mode provides a general purpose output under direct software control. Regardless
of whether an output is configured as push-pull or open-drain, the GPIO's bit in the
GPIOx_ODR register controls the output. The GPIOx_BSR and GPIOx_BRR registers can
atomically set and clear bits within GPIOx_ODR register. These set and clear registers
simplify software using the output port because they eliminate the need to disable interrupts
to perform an atomic read-modify-write operation of GPIOx_ODR.
When configured in output mode:
The output drivers are enabled and are controlled by the value written to GPIOx_ODR:
In open-drain mode: 0 activates the N-MOS current sink; 1 tri-states the pin.
In push-pull mode: 0 activates the N-MOS current sink; 1 activates the P-MOS current
source.
The internal pull-up and pull-down resistors are disabled.
The Schmitt trigger input is connected to the pin.
Reading GPIOx_IDR returns the input at the pin.
Reading GPIOx_ODR returns the last value written to the register.
Note: Depending on configuration and usage, GPIOx_ODR and GPIOx_IDR may not have the
same value.
Alternate output mode
In this mode, the output is controlled by an on-chip peripheral instead of GPIOx_ODR and
may be configured as either push-pull or open-drain. Most peripherals require a particular
output type - I2C requires an open-drain driver, for example - but since using a peripheral
does not by itself configure a pin, the GPIOx_CRH/L registers must be configured properly
for a peripheral's particular needs. As described in Section 8.1.2: Configuration on page 94,
when more than one peripheral can be the source of output data, registers in addition to
GPIOx_CRH/L determine which to use.
When configured in alternate output mode:
The output drivers are enabled and are controlled by the output of an on-chip
peripheral:
In open-drain mode: 0 activates the N-MOS current sink; 1 tri-states the pin.
In push-pull mode: 0 activates the N-MOS current sink; 1 activates the P-MOS current
source.
The internal pull-up and pull-down resistors are disabled.
The Schmitt trigger input is connected to the pin.
Reading GPIOx_IDR returns the input to the pin.
Note: Depending on configuration and usage, GPIOx_ODR and GPIOx_IDR may not have the
same value.
Alternate output SPI SCLK mode
SPI master mode SCLK outputs, PB3 (SC1SCLK) or PA2 (SC2SCLK), use a special output
push-pull mode reserved for those signals. Otherwise this mode is identical to alternate
output mode.
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8.1.7 Wake monitoring
The PWR_WAKEPxR registers specify which GPIOs are monitored to wake the processor.
If a GPIO's wake enable bit is set in PWR_WAKEPxR, then a change in the logic value of
that GPIO causes the STM32W108xx to wake from deep sleep. The logic values of all
GPIOs are captured by hardware upon entering sleep. If any GPIO's logic value changes
while in sleep and that GPIO's PWR_WAKEPxR bit is set, then the STM32W108xx will
wake from deep sleep. (There is no mechanism for selecting a specific rising-edge, falling-
edge, or level on a GPIO: any change in logic value triggers a wake event.) Hardware
records the fact that GPIO activity caused a wake event, but not which specific GPIO was
responsible. Instead, software should read the state of the GPIOs on waking to determine
the cause of the event.
The register PWR_WAKEFILTR contains bits to enable digital filtering of the external
wakeup event sources: the GPIO pins, SC1 activity, SC2 activity, and IRQD. The digital filter
operates by taking samples based on the (nominal) 10 kHz LSI RC oscillator. If three
samples in a row all have the same logic value, and this sampled logic value is different from
the logic value seen upon entering sleep, the filter outputs a wakeup event.
In order to use GPIO pins to wake the STM32W108xx from deep sleep, the GPIO_SEL bit in
the EXTIx_CR register must be set. Waking up from GPIO activity does not work with pins
configured for analog mode since the digital logic input is always set to 1 when in analog
mode. Refer to Section 6: System modules on page 46 for information on the
STM32W108xx's power management and sleep modes.
8.2 External interrupts
The STM32W108xx can use up to four external interrupt sources (IRQA, IRQB, IRQC, and
IRQD), each with its own top level NVIC interrupt vector. Since these external interrupt
sources connect to the standard GPIO input path, an external interrupt pin may
simultaneously be used by a peripheral device or even configured as an output. Analog
mode is the only GPIO configuration that is not compatible with using a pin as an external
interrupt.
External interrupts have individual triggering and filtering options selected using the
registers EXTIA_TSR, EXTIB_TSR, EXTIC_TSR, and EXTID_TSR. The bit field INTMOD of
the EXTIx_TSR register enables IRQx's second level interrupt and selects the triggering
mode: 0 is disabled; 1 for rising edge; 2 for falling edge; 3 for both edges; 4 for active high
level; 5 for active low level. The minimum width needed to latch an unfiltered external
interrupt in both level- and edge-triggered mode is 80 ns. With the digital filter enabled (the
FILTEN bit in the EXTIx_TSR register is set), the minimum width needed is 450 ns.
The register EXTI_PR is the second-level interrupt flag register that indicates pending
external interrupts. Writing 1 to a bit in the EXTI_PR register clears the flag while writing 0
has no effect. If the interrupt is level-triggered, the flag bit is set again immediately after
being cleared if its input is still in the active state.
Two of the four external interrupts, IRQA and IRQB, have fixed pin assignments. The other
two external interrupts, IRQC and IRQD, can use any GPIO pin. The EXTIC_CR and
EXTID_CR registers specify the GPIO pins assigned to IRQC and IRQD, respectively.
Table 16 shows how the EXTIC_CR and EXTID_CR register values select the GPIO pin
used for the external interrupt.
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In some cases, it may be useful to assign IRQC or IRQD to an input also in use by a
peripheral, for example to generate an interrupt from the slave select signal (nSSEL) in an
SPI slave mode interface.
Refer to Section 12: Interrupts on page 241 for further information regarding the
STM32W108xx interrupt system.
8.3 Debug control and status
Two GPIO registers are largely concerned with debugger functions. GPIO_DBGCR can
disable debugger operation, but has other miscellaneous control bits as well.
GPIO_DBGSR, a read-only register, returns status related to debugger activity
(FORCEDBG and SWEN), as well a flag (BOOTMODE) indicating whether nBOOTMODE
was asserted at the last power-on or NRST-based reset.
8.4 GPIO alternate functions
Table 17 lists the GPIO alternate functions.
Table 16. IRQC/D GPIO selection
EXTIx_CR GPIO EXTIx_CR GPIO EXTIx_CR GPIO
0 PA0 8 PB0 16 PC0
1 PA1 9 PB1 17 PC1
2 PA2 10 PB2 18 PC2
3 PA3 11 PB3 19 PC3
4 PA4 12 PB4 20 PC4
5 PA5 13 PB5 21 PC5
6 PA6 14 PB6 22 PC6
7 PA7 15 PB7 23 PC7
Table 17. GPIO signal assignments
GPIO Analog Alternate function Input Output current
drive
PA0 - TIM2_CH1(1),
SC2MOSI
TIM2_CH1(1),
SC2MOSI Standard
PA1 - TIM2_CH3(1),
SC2MISO, SC2SDA
TIM2_CH3(1),
SC2MISO, SC2SDA Standard
PA2 - TIM2_CH4(1),
SC2SCLK, SC2SCL
TIM2_CH4(1),
SC2SCLK Standard
PA3 - TIM2_CH2(1),
TRACECLK
TIM2_CH2(1),
SC2nSSEL Standard
PA4 ADC4 PTI_EN, TRACEDATA2 - Standard
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PA5 ADC5 PTI_DATA,
TRACEDATA3 nBOOTMODE(2) Standard
PA6 - TIM1_CH3 TIM1_CH3 High
PA7 - TIM1_CH4, REG_EN
(3) TIM1_CH4 High
PB0 VREF TRACECLK TIM1CLK, TIM2MSK,
IRQA Standard
PB1 -
TIM2_CH1(4), SC1TXD,
SC1MOSI, SC1MISO,
SC1SDA
TIM2_CH1(4), SC1SDA Standard
PB2 - TIM2_CH2(4),
SC1SCLK
TIM2_CH2(4),
SC1MISO, SC1MOSI,
SC1SCL, SC1RXD
Standard
PB3 - TIM2_CH3(4),
SC1SCLK
TIM2_CH3(4),
SC1SCLK, UART_CTS Standard
PB4 - TIM2_CH4(4),
UART_RTS
TIM2_CH4(4),
SC1nSSEL Standard
PB5 ADC0 - TIM2CLK, TIM1MSK Standard
PB6 ADC1 TIM1_CH1 TIM1_CH1, IRQB High
PB7 ADC2 TIM1_CH2 TIM1_CH2