LTC2924 Datasheet by Analog Devices Inc.

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L7 LINE I “2 LTC2924 TECHNOLOGY L7 LJUW 1
LTC2924
1
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For more information www.linear.com/LTC2924
Typical applicaTion
FeaTures DescripTion
Quad Power Supply
Sequencer
The LT C
®
2924 is a power supply sequencer designed for
use with external N-channel MOSFETs or power supplies
with shutdown pins. Four power supplies can be fully
sequenced by a single LTC2924 and up to five supplies
can be sequenced to a sixth master supply. The LTC2924
requires a minimum of external components, using only
two feedback resistors per sequenced power supply and
a single resistor to set hysteresis.
An internally regulated charge pump provides gate drive
voltages for external logic and sub-logic-level MOSFETs.
Adding a single capacitor enables an adjustable time delay
between power supplies during both Power On and Power
Off sequencing. A second capacitor can be added to enable
a power good timer for detecting the failure of any power
supply to turn on within the selected time. Errors in power
supply sequencing and the control input are detected and
reported at the FAULT output. The LTC2924 features pre-
cision input comparators which can provide 1% accuracy
in monitoring power supply voltages.
Multiple LTC2924s may be easily cascaded to sequence
a virtually unlimited number of power supplies.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
applicaTions
n Fully Sequence and Monitor Four Supplies
n Six with Minimal External Circuitry
n Cascadable for Additional Supplies
n Power Off in Reverse Order or Simultaneously
n Charge Pump Drives External MOSFETs
n Drives Power Supply Shutdown Pins with No Exter-
nal Pull-Up Resistors
n 10µA Output Current Allows Soft-Starting of Supplies
n Done Indicator for Both Power On and Power Off
n Adjustable Time Delay Between Power Supplies
n Power Good Timer
n Power Supply Voltage Monitoring and Power Se-
quence Error Detection and Reporting
n Available in a 16-Lead Narrow SSOP Package
n Sequenced Power Supplies for ASICs with Multiple
I/O and Core Voltages
n Latch-Up Prevention in Systems with Multiple Power
Supplies
Power-Up Sequence
OUT1
OUT2
OUT3
OUT4
ON
DONE
FAULT
TMR
PGT
IN1
IN2
IN3
IN4
HYS/CFG
LTC2924
VCC
GND
150nF
2924 TA01a
SYSTEM
CONTROLLER
150nF
1.69k
6.04k
0.1µF
Q1
Q2
100k 1.62k 66.5k
18.2k 3.09k
Q1-Q4: IRL3714S
ALL RESISTORS 1%
20k
V
ON
= 2.64V
VOFF = 1.98V
VON = 0.93V
VOFF
= 0.915V
VON = 3.97V
VOFF = 2.97V
VON = 2.79V
VOFF = 2.73V
49.9k
10k 10k
5V
3V
1V
3.3V
SHDN
5V
SHDN
5V EARLY
2V/DIV
2V/DIV
10ms/DIV
2924 TA01b
5V
3V
1V
3.3V
ON
TMR
DONE
5V/DIV
5V/DIV
2V/DIV
2V/DIV
10ms/DIV
2924 TA01c
5V
3V
1V
3.3V
ON
TMR
DONE
5V/DIV
5V/DIV
Power-Down Sequence
LTC2924 TOP VIEW flflflflflflflfl UUUUUUUU GN PACKAGE VEVLEAD PLAS'HC SSOP
LTC2924
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pin conFiguraTionabsoluTe MaxiMuM raTings
Supply Voltage (VCC) ................................ 0.3V to 6.5V
Input Voltages
ON, IN1-IN4 .................................0.3V to VCC + 0.3V
PGT, TMR, HYS/CFG ....................0.3V to VCC + 0.3V
Open-Drain Output Voltages
FA U LT, DONE ...............................0.3V to VCC + 0.3V
Output Voltages
(OUT1 - OUT4) (Note 5) .............. 0.3V to VCC + 4.5V
Operating Temperature Range
LTC2924C ................................................ 0°C to 70°C
LTC2924I .............................................40°C to 85°C
Storage Temperature Range .................. 65°C to 150°C
Lead Temperature (Soldering, 10 sec) ................... 300°C
(Note 1)
GN PACKAGE
16-LEAD PLASTIC SSOP
1
2
3
4
5
6
7
8
TOP VIEW
16
15
14
13
12
11
10
9
IN1
IN2
IN3
IN4
OUT1
OUT2
OUT3
OUT4
ON
HYS/CFG
TMR
GND
PGT
VCC
DONE
FAULT
TJMAX = 125°C, θJA = 130°C/W
orDer inForMaTion
Lead Free Finish
TUBE TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2924CGN#PBF LTC2924CGN#TRPBF 2924 16-Lead Plastic SSOP 0°C to 70°C
LTC2924IGN#PBF LTC2924IGN#TRPBF 2924I 16-Lead Plastic SSOP –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
(http://www.linear.com/product/LTC2924#orderinfo)
LTC2924 L7 LJUW 3
LTC2924
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SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Supply
VCC Input Supply Range l3 6 V
ICC Input Supply Current l1.5 3 mA
ON Threshold
VON(TH) ON, Low to High Threshold l0.6000 0.6060 0.6121 V
VOFF(TH) ON, High to Low Threshold l0.6014 0.6074 0.6135 V
IN1-IN4 Threshold
VON(TH) IN1-IN4 Low to High Threshold l0.6020 0.6081 0.6142 V
VOFF(TH) IN1-IN4 High to Low Threshold l0.6026 0.6087 0.6148 V
ON, IN1-IN4 Characteristics
VFAULT ON, IN1-IN4 High Speed Low Fault Threshold l0.33 0.4 0.48 V
ION(HYS) ON, IN1-IN4 Hysteresis Current Range VON ≥ VON(TH) (Note 2) l0.5 50 µA
ION(ERROR) ON, IN1-IN4 Hysteresis Current Error 1 – (ION(HYS)/(0.5/RHYS)), VON(TH) = 1V
0.5µA ≤ ION < 25µA
25µA ≤ ION ≤ 50µA
l
l
±22
±10
%
%
ILEAK ON, IN1-IN4 Leakage (Below Threshold) VON(TH) = 0.5V l2 ±100 nA
VON(HYS) ON, IN1-IN4 Minimum Hysteresis Voltage IHYS RIN (Note 6) l4 mV
OUT1-OUT4 Characteristics
VOUT(EN) OUT1-OUT4 Gate Drive Voltage IOUTn = 0 VCC + 4.5 VCC + 6 V
IOUT(EN) OUT1-OUT4 On Current OUTn On, VOUT = (VCC + 4V) l8.6 10 11.2 µA
ROUT(OFF) OUT1-OUT4 Off Resistance to GND OUTn Off, IOUT = 2mA l240 Ω
HYS Characteristics
RHYS HYS Current Programming Resistor Range (Notes 2, 3) 10k 1M Ω
VHYS HYS Programming Voltage RHYS Tied to GND
RHYS Tied to VCC
0.5
VCC – 0.5
V
V
TMR Characteristics
ITMR Timer Pin Output Current Timer On, VTMR ≤ 0.9V l4 5 6 µA
VTH(HI) Timer High Voltage Threshold VCC = 5V 0.93 1 1.07 V
PGT Characteristics
IPGT Power Good Timer Pin Output Current Power Good Timer On, VPGT ≤ 0.9V l4 5 6 µA
VPGT Power Good Timer Fault Detected Voltage
Threshold
VCC = 5V 0.93 1 1.07 V
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 3V to 6V, unless otherwise noted.
LTC2924 4 L7LJ1W
LTC2924
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elecTrical characTerisTics
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Hysteresis current must be 500nA minimum. Hysteresis current
may exceed 50µA, but accuracy is not guaranteed.
Note 3: HYS/CFG pin must be pulled to GND or VCC with an external
resistor. See Applications Information for details.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
DONE Characteristics
RD(LO) DONE Pin Pull-Down Resistance to GND DONE = Low, I = 2mA l100 Ω
ID(HI) DONE Pin Off Leakage Current DONE = High l15 µA
FAULT Characteristics
RFAULT (LO) FAULT Pin Pull-Down Resistance to GND FAULT Being Pulled Low Internally,
I = 2mA
l400 Ω
IFAULT(HI) FAULT Pin Off Leakage Current FAULT High l2 µA
VFAULT(HI) Voltage Above Which an Externally Generated
FAULT Condition Will Not be Detected
l1.6 V
VFAULT(LO) Voltage Below Which an Externally Generated l0.6 V
FAULT Condition Will be Detected
RF(EXT) External Pull-Up Resistance l10 kΩ
tFAULT Externally Commanded FAULT Below VFAULT(LO)
to OUT1-OUT4 Pull-Down On Delay
l1 µs
tFAULT(MIN) Externally Commanded FAULT Minimum Time
Below VFAULT(LO)
(Note 4) 1 µs
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 3V to 6V, unless otherwise noted.
Note 4: Determined by design, not production tested. External circuits
pulling down on the FAULT pin must maintain the signal below VFAULT(LO)
for ≥1µs.
Note 5: Internal circuits may drive the OUTn pins higher than the Absolute
Maximum Ratings.
Note 6: RIN is the parallel combination of the two resistors forming the
resistive divider connected to the ON and IN1-IN4 pins.
LTC2924 23 I 3 (mA) V MM 55 E AT 2mA (m n 45 cc (mm 'AT 2mA (m H (mm ‘2 V MM zoo 35 L7 LJUW
LTC2924
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Typical perForMance characTerisTics
RDONE vs VCC RFAULT vs VCC
OUTn (Off) ISAT vs Temperature OUTn (Off) ISAT vs VCC
ICC vs VCC VOUT(EN) vs IOUT VOUT(EN) vs VCC
V
CC
(V)
3
2.3
2.1
1.9
1.7
1.5
1.3
1.1
0.9 4.5 5.5
2924 G01
3.5 4 5
6
I
CC
(mA)
IOUT1-4 = –10µA
RHYS = 51k
ON HIGH
ON LOW
I
OUT
(µA)
0
14
12
10
8
6
4
2
06 10
2924 G02
2 4 8
12
V
OUT
(V)
VCC = 6V
ONE OUTPUT DRIVING CURRENT
VCC = 3V
V
(V)
2
OUT
9
10
2924 G03
8
7345
11
IOUT1-4 < 1µA
VCC (V)
3
R
DONE
AT 2mA (Ω)
40
45
2924 G04
35
30 45
6
55
50
TEMPERATURE (°C)
–60 –40
I
SAT
(mA)
30
35
40
60
2924 G06
25
20
–20 0 20 40 80
100
15
10
45
VOUT = 5V
VCC = 6V
VCC = 3V
VCC (V)
3
R
FAULT
AT 2mA (Ω)
120
140
2924 G05
100
80 45
6
200
180
160
VCC (V)
2.5
I
SAT
(mA)
25
30
35
4 5
6.5
2924 G07
20
15
10
3 3.5 4.5 5.5 6
VOUT = 5V
LTC2924 6 L7LJ1‘JW
LTC2924
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pin FuncTions
IN1-IN4 (Pins 1, 2, 3, 4): Sequenced Power Supply Moni-
tor Input. Connect this pin to an external resistive divider
between each sequenced power supply and GND. During
Power On sequencing, 0.61V (typ) at this pin indicates
that the sequenced power supply (enabled with each of
the OUT1-OUT4 pins) has reached the desired Power On
sequence voltage. A hysteresis current (programmed by
the HYS pin) is sourced out of each of the IN1-IN4 pins
after the 0.61V threshold is detected. During the Power Off
sequence, 0.61V at this pin indicates that the sequenced
power supply has reached the desired Power Off voltage.
The hysteresis current is removed after the 0.61V thresh-
old is detected.
OUT1-OUT4 (Pins 5, 6, 7, 8): Sequenced Power Supply
Enable. Connect this pin to the shutdown pin or an external
series N-channel MOSFET gate for each power supply being
sequenced. (A low at this pin means the sequenced power
supply is commanded to turn off.) When disabled, each
output is connected to GND with a resistance of <240Ω.
When enabled, each output is connected to an internally
generated charge pump supply (nominally VCC + 5V) via
an internal 10µA (typ) current source.
FAULT (Pin 9): Fault Pin. Pull this pin high with an external
10k resistor. The LTC2924 will pull this pin low if a fault
condition is detected (see Applications Information for
details). Pulling this pin low externally causes a simulta-
neous unsequenced Power Off.
DONE (Pin 10): Done Pin. Pull this pin to VCC with an
external 10k resistor. This open-drain output pulls low at
the completion of the Power-On sequence. At the end of
the Power Off sequence, the LTC2924 floats this pin. For
cascading multiple LTC2924s, see Application Information
for connecting the DONE pin.
VCC (Pin 11): LTC2924 Power Supply Input. All internal
circuits are powered from this pin. VCC should be con-
nected to a low noise power supply voltage and should
be bypassed with at least a 0.1µF capacitor to the GND
pin in close proximity to the LTC2924.
PGT (Pin 12): Power Good Timer. The PGT pin sets the time
allowed for a power supply to turn on after being enabled
with the OUT1-OUT4 pins. Connecting a capacitor between
this pin and ground programs a 200mS/µF dura tion. The
PGT pin is reset before each of the OUT1-OUT4 pins are
asserted. If the voltage at the PGT pin reaches 1V, a fault
condition is asserted. The PGT pin must be con nected
directly to ground to disable the power good timer func-
tion. Keep the ratio CPGT/CTMR between 1 and 100.
GND (Pin 13): Ground. All internal circuits are returned to
the GND pin. Connect this pin to the ground of the power
supplies that are being sequenced.
TMR (Pin 14): Timer. A capacitor connected between
this pin and ground sets the time delay between a supply
ready (IN1-IN4) signal and the enabling of the next power
supply in the sequence (OUT1-OUT4), with a 200mS/µF
duration. The TMR pin may be left floating if no delay is
required between supplies being sequenced on or off. The
PGT pin should be grounded if the TMR pin is left floating.
If an internal fault condition occurs, TMR will indicate so
by going to VCC until the fault condition is cleared. Do not
connect any other circuits to the TMR pin.
HYS/CFG (Pin 15): Hysteresis Current Setting and Cas-
cade Configuration. Connecting a resistor between this
pin and GND programs a 0.5/REXT (typ) hysteresis cur-
rent which is sourced out of each IN and ON pin. When
multiple LTC2924s are cascaded, the HYS/CFG pin is also
used to configure the position of the first LTC2924. See
Applica tions Information for details.
ON (Pin 16): On Pin. Commands the LTC2924 to sequence
the power supplies up (Power On sequence) or down
(Power Off sequence). Typically connected to a system
controller. Hysteresis current is applied to this pin when
above 0.61V (typ). This pin has a precision 0.61V thresh old
and can be used to sense a nonsequenced power supply’s
voltage to start the Power On sequence. See Applications
Information for details. For cascading mul tiple LTC2924s,
see Applications Information for connect ing the ON pin.
LTC2924
LTC2924
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FuncTional DiagraM
+
0.61V
ON
+
0.61V
IN1
+
0.61V
IN2
+
0.61V
IN3
+
+
IH
0.61V
0.5V
HYS/CFG
IN4
VCP
10µA
OUT1
VCC
VCP
10µA
OUT2
VCP
10µA
OUT3
VCP
10µA
OUT4
DONE
VCP
FAULT
2924 BD
LAST
1V
+
1V
TMR
PGT GND
FIRST
DETECT
LOGIC
CHARGE
PUMP
5
CLOCK
UVLO
1V
0.5V
0.61V
INTERNAL
REFERENCE
IH
IH
IH
IH
IH
5µA 5µA
16
1
2
3
4
15
14
12 13
11
9
10
8
7
6
5
4
LTC2924 H m m 4 A u u m 8 L7LJ1‘JW
LTC2924
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The LTC2924 is a power supply sequencer designed for
use with external N-channel MOSFETs or power supplies
with shutdown pins. Four power supplies can be fully
sequenced by a single LTC2924 (see Figure 1). An inter-
nally regulated charge pump provides (VCC + 5V) gate
voltages for driving external logic-level and sub-logic level
MOSFETs. Adding a single capacitor enables an adjustable
time delay between power supplies during both Power
On and Power Off sequencing. A second capacitor can
be added to enable a power good timer which detects the
failure of any power supply to turn on within the set time.
The ON pin signal is used to command the LTC2924
to start the Power On and Power Down sequences. To
command the Power On sequence, the ON pin is pulled
above 0.61V by a system controller or a resistive divider
from a power supply. A voltage comparator senses the
ON command and signals the sequencing logic to start
the Power On sequence.
When the Power On sequence starts, the TMR grounding
switch is released and a 5µA current source charges an
external capacitor, CTMR (see Figure 2). When the voltage
on this capacitor exceeds 1V, a comparator signals the
Figure 1. Power On and Power Off Sequence for Four Supplies
Figure 2. On Sequence for Four Supplies
operaTion
DONE *TMR IS CAPACITOR ADJUSTABLE
0V
ON
TMR*
VPS2(ON)
VPS3(ON)
VPS4(ON)
VPS1(ON)
PS1
PS3
PS2
PS4
VPS4(OFF)
VPS3(OFF)
VPS2(OFF)
2924 F01
VPS1(OFF)
ON
TMR
OUT1
0.61V
0.61V
1V
OUT2
OUT3
OUT4
IN1
IN2
IN3
IN4
DONE
0.61V
0.61V
0.61V
2924 F02
LTC2924 L7 LJUW 9
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operaTion
logic, which starts the charge pump and enables OUT1
to turn on the first power supply. The power good timer
circuit is also enabled by turning off the switch that is
shorting the external capacitor to ground and enabling a
5µA current source to charge the CPGT capacitor.
The output circuit responds by opening a switch, which
is shorting the OUT1 pin to ground and enabling a 10µA
current source, which is connected to the charge pump.
The OUT1 pin can be connected to either the shutdown pin
of a power supply or the gate of a N-channel MOSFET that
is in series with the output of the sequenced power supply.
As the power supply turns on, the resistive divider con-
nected to the IN1 pin starts to drive up the voltage at the
IN1 pin. When the voltage at this pin exceeds 0.61V, the
comparator signals the logic that the first power supply
is on. At this time a current is sourced out of the IN1
pin which serves as the hysteresis current for the input
comparator. This allows the application to choose a lower
Power Off voltage sense during the Power Off sequence.
The power good timer (PGT) circuit is signaled and resets
the PGT capacitor. The timer circuit is enabled and the
cycle repeats until the last power supply has turned on.
When the last power supply has turned on, the DONE pin
pull-down switch is turned on to signal that the Power On
sequence has completed.
If a power supply fails to turn on after it is enabled and the
voltage at the PGT pin exceeds 1V, the LTC2924 will disable
all power supplies by pulling all OUT pins to ground. A fault
condition will be indicated by the FAULT pin pulling low.
The hysteresis current sourced at the ON pin and each IN
pin is set at the HYS/CFG pin. The current is determined
by an external resistor nominally pulled to ground. The
hysteresis current is 0.5V/RHYS.
The Power Off sequence is initiated by pulling the ON pin
below 0.61V after a Power On sequence has completed
(see Figure 3). The Power Off sequence turns off the power
supplies in the reverse order of the Power On sequence.
OUT4 is turned off first. The timer function is used between
each supply being sequenced down. The PGT is not used.
The end of the Power Off sequence is indicated by the
LTC2924 floating the DONE pin.
Figure 3. 4-Power Supply Power Off Sequence
ON
TMR
OUT4
0.61V
0.61V
OUT3
OUT2
OUT1
IN4
IN3
IN2
IN1
DONE
0.61V
0.61V
0.61V
2924 F03
LTc2924
LTC2924
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applicaTions inForMaTion
Up to five supplies can be sequenced to a sixth master
supply by a single LTC2924 (Figure 4). The turn on of the
first power supply is sensed by the ON pin. Power supplies
two through five are enabled by the OUT1 through OUT4
pins, and their turn on sensed by the IN1 through IN4 pins
respectively. The last power supply is enabled by the DONE
pin, which is generally connected through an in verter. This
application is used where power supplies are sequentially
sequenced on and the turn off is simulta neous. Multiple
LTC2924s can be cascaded to facilitate sequencing of
eight or more power supplies. See the Cascading Multiple
LTC2924s section.
Selecting the Hysteresis Current and IN Pin Feedback
Resistors
The IN1-IN4 pins are connected to a sequenced power
supply with a resistive divider. The resistors are calculated
by first selecting a hysteresis current, IHYS, and calculat-
ing RHYS:
RHYS =
0.5V
I
HYS
; 0.5µA IHYS 50µA
For each sequenced power supply, choose a voltage
when the power supply is considered to be On during
Figure 4. 6-Power Supply Sequencer Block Diagram
OUT1
OUT2
OUT3
OUT4
DONE
FAULT
ON
IN1
IN2
IN3
IN4
LTC2924
VCC
GND 2924 F04
SHDN VOUT
PS1
SHDN VOUT
PS2
SHDN VOUT
PS3
SHDN VOUT
PS4
SHDN VOUT
PS5
SHDN
*VCC EARLY MUST BE ON BEFORE
SEQUENCING SUPPLIES
VOUT
PS6
TURN OFF
VCC EARLY*
SYSTEM
CONTROLLER
VON ’VOFF %: LTC2924 0.5V 2.2V70.61V (VON VOFF) A ( ) 9.2k9 + 24k§2 L7 LJUW ‘I‘I
LTC2924
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applicaTions inForMaTion
a Power On sequence (VON) and Off during a Power Off
sequence (VOFF).
Referring to Figures 5 and 6, each set of resistors can
then be calculated by:
RB=
V
ON
V
OFF
IHYS
RA=RB0.61V
V
ON
– 0.61V
In the following example (Figure 5) IHYS is 50µA. This
corresponds to a RHYS resistor of:
RHYS =
0.5V
50µA =10kΩ
In Figure 5, VON = 2.2V and VOFF = 1V. Using the equations
provided above:
RB=
2.2V – 1V
50µA =24kΩ
RA=24kΩ0.61V
2.2V 0.61V
=9.2kΩ
Hysteresis Voltage Check
After calculating the resistors RB and RA, check to make
sure the hystersis voltage at the ON and IN1-IN4 pins is
greater than 4mV. Use the following equation:
V
HYS =VON VOFF
( )
RA
RA+RB
For this example :
V
HYS =2.2V – 1V
( )
9.2kΩ
9.2kΩ + 24kΩ
=0.33V
which is greater than 4mV.
Figure 5. Designing IHYS, Feedback Resistors
Figure 6. Typical Power Supply Sequencer
+
IN
RB
VPS
RA
0.61V
IRB
VON = 2.2V
VOFF = 1V
IFB = IRB + I
HYS
2924 F05
IHYS
IHYS
150nF
2924 TA03
SYSTEM
CONTROLLER
150nF
POWER SUPPLY 4
POWER SUPPLY 3
POWER SUPPLY 2
POWER SUPPLY 1
V
ON
3.01V
VOFF 2.68V
VON 4.49V
VOFF 3.99V
VON 1.43V
VOFF 1.27V
VON 2.25V
VOFF 2V
33.2k
9.31k
24.9k
0.1µF
15.8k 49.9k
11.81k 7.87k 8.45k
49.9k
2.5V
SHDN
1.6V
SHDN
5V
SHDN
3.3V
SHDN
10k
5V EARLY*
10k
*5V EARLY MUST BE ON BEFORE
SEQUENCING SUPPLIES
OUT1
OUT2
OUT3
OUT4
ON
DONE
FAULT
TMR
PGT
IN1
IN2
IN3
IN4
HYS/CFG
VCC
GND
LTC2924
LTC2924 2.2V70.61V 24k 0.61 12 L7LJCUEN2
LTC2924
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For more information www.linear.com/LTC2924
applicaTions inForMaTion
Minimize stray capacitance on the ON and IN1-IN4 pins.
As a practical matter, lay out these resistors as close to
the LTC2924 as possible.
Details of Resistor Calculations
In this example, the voltage at the IN pins is 0.61V when
the LTC2924 detects that the power supply is On during a
Power On sequence or Off during a Power Off sequence.
The delta voltage, ΔV, represents the difference:
ΔV = 2.2V – 1V = 1.2V
This delta voltage on RB will be equal to the product of
hysteresis current IHYS and RB. Therefore:
RB=Δ
V
IHYS
=
1.2V
50µA =24kΩ
The current IRB at the Power On voltage of 2.2V is:
IRB =
2.2V 0.61V
24k
=66µA
During the Power On sequence, IHYS = 0, so IFB is equal
to IRB and RA is:
RA=
0.61
66µA =9.2k
VOFF Precaution
Use caution if designs call for VOFF voltages less than ~0.8V.
Many loads stop using significant current at this level, and
the power supply may take a long time to go below this
voltage. If VOFF voltages at or less than this voltage are
necessary, consider adding an extra resistive load at the
output of the power supply to ensure it discharges in a
reasonable amount of time.
Selecting the Timing Capacitor
During the Power On sequence, the timer is used to cre-
ate a delay between the time one supply reaches the On
threshold and the next supply is enabled. During the Power
Off sequence, the timer is used to create a delay between
the time one supply reaches the Off threshold and the
next supply is disabled. Select the timing capaci tor with
the following equation:
CTMR [µF] = tDELAY 5µF/s
Leaving the TMR pin unconnected will generate the mini-
mum delay. If the TMR pin is unconnected then the PGT
pin should be grounded. The accuracy of the time delay will
be affected by the capacitor leakage (the nominal charge
current is 5µA) and capacitor tolerance. A low leakage
ceramic capacitor is recommended.
Selecting the Power Good Timer (PGT) Capacitor
During the Power On sequence, the PGT can be used to
detect the failure of a power supply to reach the desired
On voltage. The PGT is enabled each time a power supply
is enabled by the OUT1-OUT4 pins. The PGT is reset each
time an IN1-IN4 pin detects that a power supply is at the
desired On voltage. Select the PGT timeout capacitor with
the following equation:
CPGT [µF] = tPGT 5µF/s
If no PGT is desired, the PGT pin must be shorted to
ground. The accuracy of the PGT timeout will be affected
by the capacitor leakage (the nominal charge current is
5µA) and capacitor tolerance. A low leakage ceramic ca-
pacitor is recommended. The ratio of CPGT/CTMR should
be kept between 1 and 100. If a CPGT value is required
that exceeds the maximum ratio of CPGT/CTMR then CTMR
should be increased appropriately.
LTC2924 ”J I W Tl I |||| g< w="" l7hejwegr="" 1="" 3="">
LTC2924
13
2924fc
For more information www.linear.com/LTC2924
Cascading Multiple LTC2924s
Two or more LTC2924s may be cascaded to fully se quence
8,12 or more power supplies. Figures 7 and 8 show how
to configure the LTC2924 to sequence 8 and 12 power
supplies. To sequence more power supplies, use the circuit
in Figure 8 and add more LTC2924s in the middle.
Notice that the last LTC2924 in the cascade string must
have a pull-up resistor on the DONE pin. Any LTC2924
that is not the first in the cascade string should have the
hysteresis current setting resistor, RHYS, pulled to VCC
instead of ground. The value of the RHYS resistor remains
unchanged. The FAULT pins should all be connected to-
gether and pulled up with a single 10k resistor.
Care should be taken when designing a circuit cascading
multiple LTC2924s. Use the following guidelines:
Figure 8. Cascading Three LTC2924s to Fully Sequence Up to 12 Power Supplies
All VCC and ground pins for the LTC2924s in the cascade
chain must be connected to the same power supply.
The ground pins should be connected via a ground
plane.
Cascaded LTC2924s communicate using a combination
of levels and pulses which do not look like the normal
output of a DONE pin nor input to an ON pin. Do not
connect any other components to the node between
the DONE and ON pins. Keep the parasitic capacitance
on this node below 75pF. Care should be taken when
routing a circuit trace between DONE and ON. If pos-
sible, run the trace adjacent to the ground plane, and/
or shield the trace with a ground trace on either side.
Leakage currents must be maintained below 2µA on
this node.
applicaTions inForMaTion
Figure 7. Cascading Two LTC2924s to Fully Sequence Up to Eight Power Supplies
TMR
HYS/CFG
ON
IN1
IN2
IN3
IN4
VCC
GND
PGT
OUT1
OUT2
OUT3
OUT4
DONE
LTC2924
V
CC
FAULT
VCC
VCC
DONE
10k
10k
FAULT
2924 F07
TMR
HYS/CFG
ON
IN1
IN2
IN3
IN4
VCC
GND
PGT
OUT1
OUT2
OUT3
OUT4
DONE
LTC2924ON
R
HYS
RHYS
FAULT
TMR
HYS/CFG
ON
IN1
IN2
IN3
IN4
VCC
GND
PGT
OUT1
OUT2
OUT3
OUT4
DONE
LTC2924
V
CC
FAULT
VCC
VCC
DONE
10k
10k
FAULT
2924 F08
TMR
HYS/CFG
ON
IN1
IN2
IN3
IN4
VCC
GND
PGT
OUT1
OUT2
OUT3
OUT4
DONE
LTC2924
RHYS RHYS
FAULT
TMR
HYS/CFG
ON
IN1
IN2
IN3
IN4
VCC
GND
PGT
OUT1
OUT2
OUT3
OUT4
DONE
LTC2924ON
R
HYS
FAULT
LTc2924
LTC2924
14
2924fc
For more information www.linear.com/LTC2924
Connecting Unused OUT and IN Pins
Figure 9 shows how to connect unused OUT and IN pins
on the LTC2924. Unused OUT-IN pairs must be connected
together to ensure proper operation.
Fault Detection
The LTC2924 has sophisticated fault detection which can
detect:
Power On and Power Off sequence errors
System controller command errors
Power On timeout failure (with the power good timer
enabled)
Externally commanded faults (FAULT pin pulled low)
If any of the above faults are detected, the LTC2924
immediately pulls the OUT1-OUT4 pins low turning off
all of the power supplies. If the fault condition is detected
in one of the supplies controlled by the LTC2924 (an “in-
ternally generated” fault), the FAULT pin is immediately
pulled low indicating the fault condition.
Clearing the Fault Condition
In order to clear the fault condition within the LTC2924,
the following conditions must exist:
All four IN pins must be below 0.61V
The ON pin must be below 0.61V
In the case of an externally generated fault, the FAULT
pin must not be pulled down.
Fault Condition Indicator
If the LTC2924 receives a commanded fault (a cascaded
LTC2924 or an external source pulls down on the FAULT
pin) the LTC2924 will pull the TMR pin low. If the LTC2924
has detected the fault itself (from its internal fault detec-
tion circuits) it will indicate so by raising the TMR pin to
VCC. This internal/external fault indicator can be especially
helpful while searching for the source of a fault condition
when multiple LTC2924s are cascaded.
If a fault occurs when the ON pin is high, the fault status
indication on the TMR pin will remain valid until the ON
pin goes low.
Figure 9. Connecting Unused OUT and IN Pins
applicaTions inForMaTion
IN1
IN2
IN3
IN4
OUT1
OUT2
OUT3
OUT4
LTC2924
2924 F09
PS2
PS1
LTC2924 L7HEJWEGR 1 5
LTC2924
15
2924fc
For more information www.linear.com/LTC2924
Note that the TMR pin may take a while to reach the VCC
voltage. The pin is pulled to VCC with the same 5µA current
source used for the TMR function. The larger the timer
capacitor, the longer this will take. To estimate the amount
of time required for the TMR pin to reach VCC in a fault
condition, multiply the normal timer duration by VCC (in
Volts). See Figures 7 and 8 for FAULT pin connections
when two or more LTC2924 chips are cascaded.
Sequence Errors
The LTC2924 keeps track of power supplies that should
be on during the Power On sequence and the Power Off
sequence. The LTC2924 also monitors each IN pin after
all of the power supplies have sequenced on. If a power
supply (as monitored at the IN1-IN4 pins) goes low when
it should be high, a fault condition is detected. All four OUT
pins are pulled low and the FAULT pin will be pulled low.
The precision voltage threshold for detection of a se quence
error at any of the IN1-IN4 pins is the same as the normal
threshold (~0.61V). The precision voltage com parators
used in the LTC2924 employ a sampled tech nique to im-
prove accuracy. The sample time is approximately 20µs.
To improve the speed of detection for a sequence error, a
second high speed comparator is used for detecting a low
power supply. The voltage threshold for the high speed
comparators is approximately 0.4V (VON(FAULT)). Voltages
sensed below this threshold when a power supply should
be ON will cause a fault in ~1µs.
System Controller ON Command Errors
Once the LTC2924 receives the Power On command via
the ON pin, the ON pin must remain above 0.61V until
the Power On sequence has completed (e.g. DONE is as-
serted). Removing the ON command before the LTC2924
Power On sequence has completed is considered a fault
condition. All of the OUT1-OUT4 pins that are already high
will be pulled low and the FAULT pin will be pulled low.
The same is true for the Power Off sequence. If the
LTC2924 has completed the Power On sequence and the
ON pin goes low, the ON pin must remain below 0.61V
until the Power Off sequence has completed. Raising the
ON pin above 0.61V before the Power Off sequence has
com pleted is considered a fault condition. Any OUTn pins
that are still high will immediately be pulled low and the
FAULT pin will be pulled low.
Power On Timeout Errors
If the LTC2924 PGT is being used (not tied to ground) a
fault condition will be detected when the PGT pin goes
above ~1V. If this occurs during Power On, all of the
OUT1 -OUT4 pins that are already high will be pulled low
and the FAULT pin will be pulled low.
Externally Commanded Faults
If an external circuit pulls the FAULT pin low, an external
fault condition is detected and all OUT pins will be pulled
low. After sensing the Externally Commanded Fault, the
LTC2924 will also pull down on the FAULT pin until the
conditions for clearing the fault condition exist (see Clear-
ing the Fault Condition).
applicaTions inForMaTion
LTC2924 zsms/mv Zfims/D w 16 L7LJCUEN2
LTC2924
16
2924fc
For more information www.linear.com/LTC2924
Typical applicaTions
Power-Up Sequence Power-Down Sequence
Series MOSFET Power Supply Sequencer
OUT1
OUT2
OUT3
OUT4
ON
DONE
FAULT
TMR
PGT
IN1
IN2
IN3
IN4
HYS/CFG
LTC2924
VCC
GND
150nF
2924 TA02a
SYSTEM
CONTROLLER
150nF
0.1µF
0.1µF
0.1µF
0.1µF
11.8k
52.3k
0.1µF
Q4
Q3
Q2
Q1
45.3k 6.04k 1.62k
7.68k 1.69k
Q1-Q4: IRL3714S
ALL RESISTORS 1%
3.09k
VON = 0.93V
VOFF
= 0.91V
VON = 2.79V
VOFF
= 2.73V
VON = 4.21V
VOFF
= 3.76V
VON = 3.32V
VOFF
= 2.80V
49.9k
10k
5V
EARLY
10k
5V
3.3V
1V
2V/DIV
5V
3.3V
1V
DONE
ON
TMR
10V/DIV
2V/DIV
2V/DIV
25ms/DIV
2924 TA02b
2V/DIV
5V
3.3V
1V
DONE
ON
TMR
10V/DIV
2V/DIV
2V/DIV
25ms/DIV
2924 TA02c
LTC2924 vNva L7HEJWEGR 1 7
LTC2924
17
2924fc
For more information www.linear.com/LTC2924
Typical applicaTions
Shutdown Pin Power Supply Sequencer
Power On Sequence Timer Delay Longer
than Power Off Sequence Timer Delay
OUT1
OUT2
OUT3
OUT4
ON
DONE
FAULT
TMR
PGT
IN1
IN2
IN3
IN4
HYS/CFG
VCC
GND
LTC2924
150nF
2924 TA03
SYSTEM
CONTROLLER
150nF
POWER SUPPLY 4
POWER SUPPLY 3
POWER SUPPLY 2
POWER SUPPLY 1
V
ON
≥ 3.01V
VOFF
≤ 2.68V
VON ≥ 4.49V
VOFF
≤ 3.99V
VON ≥ 1.43V
VOFF
≤ 1.27V
VON ≥ 2.25V
VOFF ≤ 2V
33.2k
9.31k
24.9k
0.1µF
15.8k 49.9k
11.81k 7.87k 8.45k
49.9k
2.5V
SHDN
1.6V
SHDN
5V
SHDN
3.3V
SHDN
10k
5V EARLY*
10k
*5V EARLY MUST BE ON BEFORE
SEQUENCING SUPPLIES
IN1
IN2
IN3
IN4
ON
TMR
OUT1
OUT2
OUT3
OUT4
PGT
FAULT
DONE
VCC
V
CC
GND
LTC2924
150nF
0.1µF
150nF 2924 TA04
2N7002 POWER ON TIMER DELAY = 30ms
POWER OFF TIMER DELAY = 15ms
VCC
10k
LTC2924 PARAsmC 18
LTC2924
18
2924fc
For more information www.linear.com/LTC2924
Typical applicaTions
Power-On Power-Off
2-Supply Sequencer with Delayed Sense Pin, One Channel Unused
OUT4
OUT3
OUT2
OUT1
ON
FAULT
DONE
TMR
VCC
IN4
IN3
IN2
IN1
PGT
HYS
GND
LTC2924
DC/DC
3.3V
Q2
10k 10k
150nF
0.1µF
1M
PARASITIC
RESISTANCE
D1
Q1
SYSTEM
CONTROLLER
SHDN
5V
SENSE+
MODULE
OUT+
VOUT
3.3V
VOUT
5V
VON ≥ 4.64V
VOFF ≤ 4V
VON ≥ 2.98V
VOFF
≤ 2.65V
49.9k
D1: 1N5711
Q1, Q2: IRL3714S
9.83k
64.9k 33.2k
8.55k
150nF
2924 TA05a
1V/DIV
2V/DIV
25ms/DIV
2924 TA05b
5V
3.3V
ON
TMR
DONE
1V/DIV
REMOTE SENSE ENABLE
1V/DIV
2V/DIV
25ms/DIV
2924 TA05c
5V
3.3V
ON
TMR
1V/DIV
REMOTE SENSE DISABLE
LTC2924 L7HEJWEGR 1 9
LTC2924
19
2924fc
For more information www.linear.com/LTC2924
Typical applicaTions
OUT1
OUT2
OUT3
OUT4
ON
DONE
FAULT
TMR
PGT
IN1
IN2
IN3
IN4
HYS/CFG
LTC2924
VCC
GND
150nF
2924 TA06a
SYSTEM
CONTROLLER
150nF
0.1µF
0.1µF
0.1µF
0.1µF
11.8k
52.3k
10k
0.1µF
Q4
Q3
Q2
Q1
45.3k 6.04k
7k
1.36k
7.68k 1.69k
Q1-Q4: IRL3714S
ALL RESISTORS 1%
VON – 4.5V
VOFF – 3.9V
VON = 2.79V
VOFF
= 2.73V
VON = 4.21V
VOFF
= 3.76V
VON = 3.32V
VOFF
= 2.80V
49.9k
100k
10k
5V
EARLY
10k
5V
3V
–5V
+
2N3906 SOT-23
LT1783
1M
Precision Negative Rail Sequencer
Power-Up Sequence Power-Down Sequence
2V/DIV
5V/DIV
10ms/DIV
2924 TA07b
5V
–5V
3.3V
ON
TMR
DONE
5V/DIV
2V/DIV
2V/DIV
5V/DIV
10ms/DIV
2924 TA07c
5V
–5V
3.3V
ON
TMR
DONE
5V/DIV
2V/DIV
[IC2924 V’DDDDDDDDT ‘DDDDDDJJEEL ms EEEEEE E1 QQQEQQQQ I 74 L4 L7 L7LJCUEN2
LTC2924
20
2924fc
For more information www.linear.com/LTC2924
package DescripTion
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641 Rev B)
Please refer to http://www.linear.com/product/LTC2924#packaging for the most recent package drawings.
GN16 REV B 0212
1 2 345678
.229 – .244
(5.817 – 6.198)
.150 – .157**
(3.810 – 3.988)
16 15 14 13
.189 – .196*
(4.801 – 4.978)
12 11 10 9
.016 – .050
(0.406 – 1.270)
.015 ±.004
(0.38 ±0.10) × 45°
0° – 8° TYP
.007 – .0098
(0.178 0.249)
.0532 – .0688
(1.35 – 1.75)
.008 – .012
(0.203 – 0.305)
TYP
.004 – .0098
(0.102 – 0.249)
.0250
(0.635)
BSC
.009
(0.229)
REF
.254 MIN
RECOMMENDED SOLDER PAD LAYOUT
.150 – .165
.0250 BSC.0165 ±.0015
.045 ±.005
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
INCHES
(MILLIMETERS)
NOTE:
1. CONTROLLING DIMENSION: INCHES
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641 Rev B)
LTC2924 L7 LJUW 2 1
LTC2924
21
2924fc
For more information www.linear.com/LTC2924
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
revision hisTory
REV DATE DESCRIPTION PAGE NUMBER
B 02/12 Updated PGT and TMR pin descriptions in Pin Functions.
Updated Selecting the Timing Capacitor and Selecting the Power Good Timer (PGT) Capacitor sections of
Applications Information.
Revision to Typical Application drawing TA06a.
6
12
19
C 02/16 Removed Lead Finish Part Numbers
Updated GN Package Drawing
2
20
(Revision history begins at Rev B)
LTC2924 22 L7ELUEN2
LTC2924
22
2924fc
For more information www.linear.com/LTC2924
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 2005
LT 0216 REV C • PRINTED IN USA
relaTeD parTs
Typical applicaTion
PART NUMBER DESCRIPTION COMMENTS
LTC2920-1/LTC2920-2 Single/Dual Power Supply Margining Controller Symmetric/Asymmetric High and Low Voltage Margining
LTC2921/LTC2922 Power Supply Tracker with Input Monitors 3 (LTC2921) or 5 (LTC2922) Remote Sense Switching
LTC2923 Power Supply Tracking Controller Up to 3 Supplies
LTC2925 Multiple Power Supply Tracking Controller Power Good Timer, Remote Sense Switch
LTC2926 MOSFET Controlled Power Supply Tracker Closed Loop (Feedback) Tracking for 3 Supplies
LTC2927 Single Power Supply Tracker For Point of Load or Distributed Applications
12V 3-Supply Sequencer with LTC2924 Power Supplied by a Zener Shunt Regulator
OUT4
IN4
OUT3
IN3
OUT2
IN2
OUT1
IN1
DONE
FAULT
LTC2924
ON
VCC
HYS/CFG
TMR PGT
GND
2.5VVIN
SHDN
3.3VVIN
SHDN
1.2VVIN
SHDN
SYSTEM
12V
SUPPLY
RESET_B
VCC1
VCC2
µC
VCC1
VCC2
FPGA
VCC1
VCC2
ASIC
VCC
VCC
2924 TA08
12V
1k
1.24k
ON ≥ 1.1V, OFF ≤ 1.09V
ON ≥ 3V, OFF ≤ 2.8V
ON ≥ 2.2V, OFF ≤ 2V
20k
5.11k
20k
7.68k
10k
10k
49.9k
2.94k1.5k
5.1V
ZENER
BZX84C5V1
0.1µF
49.9k
150nF
150nF

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