NX3DV3899 Datasheet by NXP USA Inc.

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1. General description
The NX3DV3899 is a dual double-pole double-throw analog data-switch suitable for use
as an analog or digital multiplexer/demultiplexer. It consists of four switches, each with two
independent input/outputs (nY0 and nY1) and a common input/output (nZ). The two digital
inputs (1S and 2S) are used to select the switch position. Schmitt trigger action at the
select input (nS) makes the circuit tolerant to slower input rise and fall times across the
entire VCC range from 1.4 V to 4.3 V.
A low input voltage threshold allows pin nS to be driven by lower level logic signals without
a significant increase in supply current ICC. This makes it possible for the NX3DV3899 to
switch 4.3 V signals with a 1.8 V digital controller, eliminating the need for logic level
translation. The NX3DV3899 allows signals with amplitude up to VCC to be transmitted
from nZ to nY0 or nY1; or from nY0 or nY1 to nZ.
2. Features and benefits
Wide supply voltage range from 1.4 V to 4.3 V
Very low ON resistance (peak):
7.2 (typical) at VCC =1.4V
5.4 (typical) at VCC =1.65V
2.9 (typical) at VCC =2.5V
2.4 (typical) at VCC =3.0V
2.3 (typical) at VCC =3.6V
2.2 (typical) at VCC =4.3V
Break-before-make switching
High noise immunity
ESD protection:
HBM JESD22-A114F Class 2A exceeds 2000 V (all pins)
HBM JESD22-A114F Class 3A exceeds 5000 V (I/O pins to GND)
MM JESD22-A115-A exceeds 200 V
CDM AEC-Q100-011 revision B exceeds 1000 V
CMOS low-power consumption
Latch-up performance exceeds 100 mA per JESD 78B Class II Level A
1.8 V control logic at VCC = 3.6 V
Control input accepts voltages above supply voltage
Very low supply current, even when input is below VCC
High current handling capability (350 mA continuous current under 3.3 V supply)
Specified from 40 C to +85 C and from 40 C to +125 C
NX3DV3899
Dual double-pole double-throw analog switch
Rev. 3 — 9 November 2011 Product data sheet
NX3DV3899 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 9 November 2011 2 of 22
NXP Semiconductors NX3DV3899
Dual double-pole double-throw analog switch
3. Applications
Data switch
Cell phone
PDA
Portable media player
4. Ordering information
5. Marking
6. Functional diagram
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
NX3DV3899HR 40 Cto+125C HXQFN16U plastic thermal enhanced extremely thin quad flat
package; no leads; 16 terminals; UTLP based;
body 3 30.5 mm
SOT1039-1
NX3DV3899GU 40 C to +125 C XQFN16 plastic, extremely thin quad flat package; no leads;
16 terminals; body 1.80 2.60 0.50 mm SOT1161-1
Table 2. Marking codes
Type number Marking code
NX3DV3899HR 99
NX3DV3899GU 9
Fig 1. Logic symbol
001aak174
1Z
1Y0
1Y1
2Z
2Y0
2Y1
3Z
3Y0
3Y1
4Z
4Y0
4Y1 2S
1S
DEED DEED DEED DEED
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Product data sheet Rev. 3 — 9 November 2011 3 of 22
NXP Semiconductors NX3DV3899
Dual double-pole double-throw analog switch
7. Pinning information
7.1 Pinning
Fig 2. Logic diagram
4Z
001aam785
3Z1Z
2Z
3Y11Y1
3Y0
4Y1
4Y0
2S
1Y0
2Y1
2Y0
1S
(1) This is not a supply pin, the substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad
however if it is soldered the solder land should remain
floating or be connected to GND.
Fig 3. Pin configuration SOT1039-1 (HXQFN16U) Fig 4. Pin configuration SOT1161-1 (XQFN16)
1
2
3
4
1Y0
1S
2Y1
NX3DV3899
2Z
12
11
10
9
4Z
4Y1
2S
3Y0
16
15
14
13
1Z
1Y1
V
CC
4Y0
5
6
7
8
2Y0
GND
GND(1)
3Y1
3Z
001aam786
Transparent top view
terminal 1
index area
NX3DV3899
terminal 1
index area
001aam787
Transparent top view
83Z
73Y1
6GND
52Y0
4Y013
VCC
14
1Y115
1Z16
4Z12
4Y111
2S10
3Y09
11Y0
21S
32Y1
42Z
la,
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Product data sheet Rev. 3 — 9 November 2011 4 of 22
NXP Semiconductors NX3DV3899
Dual double-pole double-throw analog switch
7.2 Pin description
8. Functional description
[1] H = HIGH voltage level; L = LOW voltage level.
9. Limiting values
[1] The minimum input voltage rating may be exceeded if the input current rating is observed.
[2] The minimum and maximum switch voltage ratings may be exceeded if the switch clamping current rating is observed but may not
exceed 4.6 V.
[3] For HXQFN16U package: above 135 C the value of Ptot derates linearly with 16.9 mW/K.
[4] For XQFN16 package: above 133 C the value of Ptot derates linearly with 14.5 mW/K.
Table 3. Pin description
Symbol Pin Description
1Y0, 2Y0, 3Y0, 4Y0 1, 5, 9, 13 independent input or output
1S, 2S 2, 10 select input
1Y1, 2Y1, 3Y1, 4Y1 15, 3, 7, 11 independent input or output
1Z, 2Z, 3Z, 4Z 16, 4, 8, 12 common output or input
GND 6 ground (0 V)
VCC 14 supply voltage
Table 4. Function table[1]
Input nS Channel on
LnY0
HnY1
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +4.6 V
VIinput voltage select input nS [1] 0.5 +4.6 V
VSW switch voltage [2] 0.5 VCC + 0.5 V
IIK input clamping current VI<0.5 V 50 - mA
ISK switch clamping current VI<0.5 V or VI>V
CC + 0.5 V - 50 mA
ISW switch current VSW >0.5 V or VSW < VCC + 0.5 V;
source or sink current -350 mA
VSW >0.5 V or VSW < VCC + 0.5 V;
pulsed at 1 ms duration, < 10 % duty cycle;
peak current
-500 mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb =40 Cto+125C
HXQFN16U [3] - 250 mW
XQFN16 [4] - 250 mW
Figuve 5 Figuve 6
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Product data sheet Rev. 3 — 9 November 2011 5 of 22
NXP Semiconductors NX3DV3899
Dual double-pole double-throw analog switch
10. Recommended operating conditions
[1] To avoid sinking GND current from terminal nZ when switch current flows in terminal nYn, the voltage drop across the bidirectional
switch must not exceed 0.4 V. If the switch current flows into terminal nZ, no GND current will flow from terminal nYn. In this case, there
is no limit for the voltage drop across the switch.
[2] Applies to control signal levels.
11. Static characteristics
Table 6. Recommended operating conditions
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 1.4 4.3 V
VIinput voltage select input nS 0 4.3 V
VSW switch voltage [1] 0V
CC V
Tamb ambient temperature 40 +125 C
t/V input transition rise and fall rate VCC = 1.4 V to 4.3 V [2] - 200 ns/V
Table 7. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground 0 V).
Symbol Parameter Conditions Tamb = 25 C Tamb = 40 C to +125 CUnit
Min Typ Max Min Max
(85 C) Max
(125 C)
VIH HIGH-level
input voltage VCC = 1.4 V to 1.6 V 0.9 - - 0.9 - - V
VCC = 1.65 V to 1.95 V 0.9 - - 0.9 - - V
VCC = 2.3 V to 2.7 V 1.1 - - 1.1 - - V
VCC = 2.7 V to 3.6 V 1.3 - - 1.3 - - V
VCC = 3.6 V to 4.3 V 1.4 - - 1.4 - - V
VIL LOW-level
input voltage VCC = 1.4 V to 1.6 V - - 0.3 - 0.3 0.3 V
VCC = 1.65 V to 1.95 V - - 0.4 - 0.4 0.3 V
VCC = 2.3 V to 2.7 V - - 0.4 - 0.4 0.4 V
VCC = 2.7 V to 3.6 V - - 0.5 - 0.5 0.5 V
VCC = 3.6 V to 4.3 V - - 0.6 - 0.6 0.6 V
IIinput leakage
current select input nS;
VI=GNDto4.3V;
VCC = 1.4 V to 4.3 V
--- -0.5 1A
IS(OFF) OFF-state
leakage
current
nY0 and nY1 port;
see Figure 5
VCC = 1.4 V to 4.3 V - - 5-50 500 nA
IS(ON) ON-state
leakage
current
nZ port; see Figure 6
VCC = 1.4 V to 4.3 V - - 5-50 500 nA
ICC supply current VI=V
CC or GND;
VSW =GNDorV
CC
VCC = 3.6 V - - 100 - 500 5000 nA
VCC = 4.3 V - - 150 - 800 6000 nA
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Product data sheet Rev. 3 — 9 November 2011 6 of 22
NXP Semiconductors NX3DV3899
Dual double-pole double-throw analog switch
11.1 Test circuits
ICC additional
supply current VSW =GNDorV
CC
VI= 2.6 V; VCC =4.3V - 2.0 4.0 - 7 7 A
VI= 2.6 V; VCC = 3.6 V - 0.35 0.7 - 1 1 A
VI= 1.8 V; VCC = 4.3 V - 7.0 10.0 - 15 15 A
VI= 1.8 V; VCC =3.6V - 2.5 4.0 - 5 5 A
VI= 1.8 V; VCC = 2.5 V - 50 200 - 300 500 nA
CIinput
capacitance -1.0----pF
CS(OFF) OFF-state
capacitance -8----pF
CS(ON) ON-state
capacitance -30----pF
Table 7. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground 0 V).
Symbol Parameter Conditions Tamb = 25 C Tamb = 40 C to +125 CUnit
Min Typ Max Min Max
(85 C) Max
(125 C)
VI=0.3VorV
CC 0.3 V; VO=V
CC 0.3 V or 0.3 V.
Fig 5. Test circuit for measuring OFF-state leakage current
I
S
012aaa000
nS
nZ
nY0
nY1
V
CC
GND
switch
switch
1
12
2
V
IL
V
IH
nS
V
IL
or V
IH
VIVO
VI=0.3VorV
CC 0.3 V; VO=V
CC 0.3 V or 0.3 V.
Fig 6. Test circuit for measuring ON-state leakage current
IS
012aaa001
nS
nZ
nY0
nY1
VCC
GND
switch
switch
1
12
2
VIL
VIH
nS
VO
VIL or VIH
VI
Figure 8 Figure 14 Figure 7
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Product data sheet Rev. 3 — 9 November 2011 7 of 22
NXP Semiconductors NX3DV3899
Dual double-pole double-throw analog switch
11.2 ON resistance
[1] Typical values are measured at Tamb = 25 C.
[2] Measured at identical VCC, temperature and input voltage.
[3] Flatness is defined as the difference between the maximum and minimum value of ON resistance measured at identical VCC and
temperature.
Table 8. ON resistance
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for graphs see Figure 8 to Figure 14.
Symbol Parameter Conditions Tamb = 40 C to +85 C Tamb = 40 C to +125 CUnit
Min Typ[1] Max Min Max
RON(peak) ON resistance
(peak) VI=GNDtoV
CC;
ISW = 100 mA; see Figure 7
VCC =1.4V - 7.2 9.3 - 10
VCC =1.65V - 5.4 7.3 - 8
VCC = 2.5 V - 2.9 3.9 - 4.5
VCC = 3.0 V - 2.4 3.4 - 4.5
VCC = 3.6 V - 2.3 3.3 - 4.2
VCC = 4.3 V - 2.2 3.3 - 4.2
RON ON resistance
mismatch
between
channels
VI=GNDtoV
CC;
ISW = 100 mA
[2]
VCC =3.0V - 0.8 - - -
VCC =4.3V - 0.7 - - -
RON(flat) ON resistance
(flatness) VI=GNDtoV
CC;
ISW = 100 mA
[3]
VCC =1.4V - 4.4 - - -
VCC =1.65V - 2.8 - - -
VCC =2.5V - 1.0 - - -
VCC =3.0V - 0.8 - - -
VCC =3.6V - 0.9 - - -
VCC =4.3V - 1.0 - - -
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Product data sheet Rev. 3 — 9 November 2011 8 of 22
NXP Semiconductors NX3DV3899
Dual double-pole double-throw analog switch
11.3 ON resistance test circuit and graphs
RON =V
SW / ISW.(1)V
CC =1.4V.
(2) VCC =1.65V.
(3) VCC =2.5V.
(4) VCC =3.0V.
(5) VCC =3.6V.
(6) VCC =4.3V.
Measured at Tamb =25C.
Fig 7. Test circuit for measuring ON resistance Fig 8. Typical ON resistance as a function of input
voltage
VI (V)
054231
001aam788
8
RON
(Ω)
6
4
2
1
3
5
7(1)
(2)
(3)
(4) (5) (6)
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Product data sheet Rev. 3 — 9 November 2011 9 of 22
NXP Semiconductors NX3DV3899
Dual double-pole double-throw analog switch
(1) Tamb = 125 C.
(2) Tamb =85C.
(3) Tamb =25C.
(4) Tamb =40 C.
(1) Tamb = 125 C.
(2) Tamb =85C.
(3) Tamb =25C.
(4) Tamb =40 C.
Fig 9. ON resistance as a function of input voltage;
VCC =1.4V Fig 10. ON resistance as a function of input voltage;
VCC =1.65V
VI (V)
0.0 0.4 0.8 1.2 1.41.00.60.2
001aam789
4
6
8
RON
(Ω)
2
(1)
(2)
(3)
(4)
VI (V)
0.0 2.01.60.8 1.20.4
001aam790
3.5
4.5
2.5
5.5
6.5
RON
(Ω)
1.5
(1)
(2)
(3)
(4)
(1) Tamb = 125 C.
(2) Tamb =85C.
(3) Tamb =25C.
(4) Tamb =40 C.
(1) Tamb = 125 C.
(2) Tamb =85C.
(3) Tamb =25C.
(4) Tamb =40 C.
Fig 11. ON resistance as a function of input voltage;
VCC =2.5V Fig 12. ON resistance as a function of input voltage;
VCC =3.0V
VI (V)
0.0 2.52.01.0 1.50.5
001aam791
2.25
2.75
1.75
3.25
3.75
RON
(Ω)
1.25
(1)
(2)
(3)
(4)
001aam792
VI (V)
0321
2.0
2.5
1.5
3.0
3.5
RON
(Ω)
1.0
(1)
(2)
(3)
(4)
/// Figure 17 Figure 15 Figure 15
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Product data sheet Rev. 3 — 9 November 2011 10 of 22
NXP Semiconductors NX3DV3899
Dual double-pole double-throw analog switch
12. Dynamic characteristics
(1) Tamb = 125 C.
(2) Tamb =85C.
(3) Tamb =25C.
(4) Tamb =40 C.
(1) Tamb = 125 C.
(2) Tamb =85C.
(3) Tamb =25C.
(4) Tamb =40 C.
Fig 13. ON resistance as a function of input voltage;
VCC =3.6V Fig 14. ON resistance as a function of input voltage;
VCC =4.3V
VI (V)
04312
001aam793
2.0
1.5
2.5
3.0
RON
(Ω)
1.0
(1)
(2)
(3)
(4)
VI (V)
054231
001aam794
1.5
2.0
1.0
2.5
3.0
RON
(Ω)
0.5
(1)
(2)
(3)
(4)
Table 9. Dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for test circuit see Figure 17.
Symbol Parameter Conditions Tamb = 25 C Tamb = 40 C to +125 CUnit
Min Typ[1] Max Min Max
(85 C) Max
(125 C)
ten enable time nS to nZ or nYn;
see Figure 15
VCC = 1.4 V to 1.6 V - 41 90 - 120 120 ns
VCC = 1.65 V to 1.95 V - 30 70 - 80 90 ns
VCC = 2.3 V to 2.7 V - 20 45 - 50 55 ns
VCC = 2.7 V to 3.6 V - 19 40 - 45 50 ns
VCC = 3.6 V to 4.3 V - 19 40 - 45 50 ns
tdis disable time nS to nZ or nYn;
see Figure 15
VCC = 1.4 V to 1.6 V - 24 70 - 80 90 ns
VCC = 1.65 V to 1.95 V - 15 55 - 60 65 ns
VCC = 2.3 V to 2.7 V - 9 25 - 30 35 ns
VCC = 2.7 V to 3.6 V - 8 20 - 25 30 ns
VCC = 3.6 V to 4.3 V - 8 20 - 25 30 ns
Figure 17 Figure 16 7
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Product data sheet Rev. 3 — 9 November 2011 11 of 22
NXP Semiconductors NX3DV3899
Dual double-pole double-throw analog switch
[1] Typical values are measured at Tamb = 25 C and VCC = 1.5 V, 1.8 V, 2.5 V, 3.3 V and 4.3 V respectively.
[2] Break-before-make guaranteed by design.
12.1 Waveform and test circuits
tb-m break-before-make
time see Figure 16 [2]
VCC = 1.4 V to 1.6 V - 20 - 9 - - ns
VCC = 1.65 V to 1.95 V - 17 - 7 - - ns
VCC = 2.3 V to 2.7 V - 13 - 4 - - ns
VCC = 2.7 V to 3.6 V - 11 - 3 - - ns
VCC = 3.6 V to 4.3 V - 11 - 2 - - ns
Table 9. Dynamic characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for test circuit see Figure 17.
Symbol Parameter Conditions Tamb = 25 C Tamb = 40 C to +125 CUnit
Min Typ[1] Max Min Max
(85 C) Max
(125 C)
Measurement points are given in Table 10.
Logic level: VOH is typical output voltage level that occurs with the output load.
Fig 15. Enable and disable times
012aaa003
VI
GND
nS input
nZ output
OFF to HIGH
HIGH to OFF
nZ output
HIGH to OFF
OFF to HIGH
nY1 connected to VEXT
nY0 connected to VEXT
VOH
GND
VOH
GND
VM
ten tdis
ten
tdis
VX
VX
VX
VX
Table 10. Measurement points
Supply voltage Input Output
VCC VMVX
1.4 V to 4.3 V 0.5VCC 0.9VOH
' ”‘3
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Product data sheet Rev. 3 — 9 November 2011 12 of 22
NXP Semiconductors NX3DV3899
Dual double-pole double-throw analog switch
a. Test circuit
b. Input and output measurement points
Fig 16. Test circuit for measuring break-before-make timing
012aaa004
GND
V
CC
V
EXT
= 1.5 V
nY0
nY1
nS
nZ
VI
V
VORLCL
G
001aag572
VI
tb-m
VO
0.9VO
0.9VO
0.5VI
Test data is given in Table 11.
Definitions test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
VEXT = External voltage for measuring switching times.
Fig 17. Test circuit for measuring switching times
012aaa005
nS
nZ
nY0
nY1
RLCL
V
CC
GND
V
EXT
= 1.5 V
switch
1
2
VI
V
VO
G
Table 11. Test data
Supply voltage Input Load
VCC VItr, tfCLRL
1.4 V to 4.3 V VCC 2.5ns 35pF 50
Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23
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Product data sheet Rev. 3 — 9 November 2011 13 of 22
NXP Semiconductors NX3DV3899
Dual double-pole double-throw analog switch
12.2 Additional dynamic characteristics
[1] fi is biased at 0.5VCC.
Table 12. Additional dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); VI = GND or VCC (unless otherwise
specified); tr = tf
2.5 ns; Tamb = 25
C.
Symbol Parameter Conditions Min Typ Max Unit
THD total harmonic
distortion fi=20Hzto20 kHz; R
L=600; see Figure 18 [1]
VCC =1.4V; V
I= 1 V (p-p) - 0.05 - %
VCC =1.65V; V
I= 1.2 V (p-p) - 0.02 - %
VCC =2.3V; V
I= 1.5 V (p-p) - 0.01 - %
VCC =2.7V; V
I= 2 V (p-p) - 0.01 - %
VCC =3.6V; V
I= 2 V (p-p) - 0.01 - %
VCC =4.3V; V
I= 2 V (p-p) - 0.01 - %
f(3dB) 3 dB frequency
response RL=50; see Figure 19 [1]
VCC = 1.4 V to 4.3 V - 200 - MHz
iso isolation (OFF-state) fi= 1 MHz; RL=50; see Figure 20 [1]
VCC = 1.4 V to 4.3 V - 70 - dB
Vct crosstalk voltage between digital inputs and switch;
fi= 1 MHz; CL= 50 pF; RL=50; see Figure 21
VCC = 1.4 V to 3.6 V - 210 - V
VCC = 3.6 V to 4.3 V - 300 - V
Xtalk crosstalk between switches;
fi= 1 MHz; RL=50;seeFigure 22
[1]
VCC = 1.4 V to 4.3 V - 90 - dB
Qinj charge injection fi= 1 MHz; CL= 0.1 nF; RL=1 M; Vgen =0V;
Rgen =0; see Figure 23
VCC =1.4V - 0.5 - pC
VCC =1.65V - 0.7 - pC
VCC =2.5V - 1.6 - pC
VCC =3.0V - 2.1 - pC
VCC =3.6V - 2.9 - pC
VCC =4.3V - 4.0 - pC
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Product data sheet Rev. 3 — 9 November 2011 14 of 22
NXP Semiconductors NX3DV3899
Dual double-pole double-throw analog switch
12.3 Test circuits
Fig 18. Test circuit for measuring total harmonic distortion
012aaa006
fi
RLswitch nS
1V
IL
2V
IH
switch
VCC
VIL or VIH
0.5VCC
nY0
nY1
1
2
nS
nZ
GND
D
Adjust fi voltage to obtain 0 dBm level at output. Increase fi frequency until dB meter reads 3dB.
Fig 19. Test circuit for measuring the frequency response when channel is in ON-state
012aaa007
fi
RLswitch nS
1V
IL
2V
IH
switch
VCC
VIL or VIH
0.5VCC
nY0
nY1
1
2
nS
nZ
GND
dB
Adjust fi voltage to obtain 0 dBm level at input.
Fig 20. Test circuit for measuring isolation (OFF-state)
012aaa008
fi
RLRLswitch nS
1V
IH
2V
IL
switch
VCC
VIL or VIH
0.5VCC 0.5VCC
nY0
nY1
1
2
nS
nZ
GND
dB
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Product data sheet Rev. 3 — 9 November 2011 15 of 22
NXP Semiconductors NX3DV3899
Dual double-pole double-throw analog switch
a. Test circuit
b. Input and output pulse definitions
Fig 21. Test circuit for measuring crosstalk voltage between digital inputs and switch
V
012aaa009
RL
switch
1
2V
IH
V
IL
nS
nS
nZ
nY0
nY1
V
CC
V
I
V
O
logic
input
0.5V
CC
RLCL
0.5V
CC
switch
1
2
G
V
ct
onoff
logic
input (nS) off
V
O
012aaa010
20 log10 (VO2 / VO1) or 20 log10 (VO1 / VO2).
Fig 22. Test circuit for measuring crosstalk between switches
V
001aak178
0.5V
CC
nZ or nY0
RL
VO1
CHANNEL
ON
CHANNEL
OFF V
0.5V
CC
nZ or nY0nY0 or nZ
nS
RL
VO2
Ri
50 Ω
nY0 or nZ
V
IL
50 Ωfi
NX3DV3899 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 9 November 2011 16 of 22
NXP Semiconductors NX3DV3899
Dual double-pole double-throw analog switch
a. Test circuit
b. Input and output pulse definitions
Definition: Qinj =VO CL.
VO = output voltage variation.
Rgen = generator resistance.
Vgen = generator voltage.
Fig 23. Test circuit for measuring charge injection
012aaa011
nS
nZ
nY0
nY1
RL
VICL
V
CC
GND
Rgen
Vgen
switch
1
2
V
O
G
012aaa012
ΔVO
offonoff
logic
input
VO
(nS)
97—1444 SQ “7‘4,ng
NX3DV3899 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 9 November 2011 17 of 22
NXP Semiconductors NX3DV3899
Dual double-pole double-throw analog switch
13. Package outline
Fig 24. Package outline SOT1039-1 (HXQFN16U)
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT1039-1 - - -- - -
SOT1039-1
07-11-14
07-12-01
UNIT A
max
mm 0.5 0.05
0.00 0.35
0.25 1.95
1.75 3.1
2.9 1.95
1.75 0.5 1.5 0.35
0.25 0.1
A1
DIMENSIONS (mm are the original dimensions)
HXQFN16U: plastic thermal enhanced extremely thin quad flat package; no leads;
16 terminals; UTLP based; body 3 x 3 x 0.5 mm
0 2.5 5 mm
scale
b D
3.1
2.9
DhE Ehe e1
1.5
e2L L1
0.1
0.0
v w
0.05
y
0.05
y1
0.1
C
y
C
y1
X
b
e2
e1
e
e
1/2 e
1/2 e
AC B
vM
Cw M
terminal 1
index area
Dh
Eh
L1
L
9
8
1316
12
4
1
5
BA
terminal 1
index area
D
E
detail X
A1
A
g@ M
NX3DV3899 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 9 November 2011 18 of 22
NXP Semiconductors NX3DV3899
Dual double-pole double-throw analog switch
Fig 25. Package outline SOT1161-1 (XQFN16)
References
Outline
version European
projection Issue date
IEC JEDEC JEITA
SOT1161-1 - - -
- - -
- - -
sot1161-1_po
09-12-28
09-12-29
Unit(1)
mm max
nom
min
0.5 0.05
0.00
0.25
0.20
0.15
1.9
1.8
1.7
2.7
2.6
2.5 0.4 1.2 0.45
0.40
0.35 0.1
A
Dimensions
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
XQFN16: plastic, extremely thin quad flat package; no leads;
16 terminals; body 1.80 x 2.60 x 0.50 mm SOT1161-1
A1A3
0.127
bDEee
1
1.2
e2LL
1
0.55
0.50
0.45
vw
0.05
y
0.05
y1
0.05
0 1 2 mm
scale
BA
terminal 1
index area
D
E
X
C
y
C
y1
detail X
AA1
A3
terminal 1
index area
b
e2
e1
AC B
v
Cw
L
L1
5 8
16 13
9
12
4
1
e
e
NX3DV3899 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 9 November 2011 19 of 22
NXP Semiconductors NX3DV3899
Dual double-pole double-throw analog switch
14. Abbreviations
15. Revision history
Table 13. Abbreviations
Acronym Description
CDM Charged Device Model
CMOS Complementary Metal-Oxide Semiconductor
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
PDA Personal Digital Assistant
Table 14. Revision history
Document ID Release date Data sheet status Change notice Supersedes
NX3DV3899 v.3 20111109 Product data sheet - NX3DV3899 v.2
Modifications: Legal pages updated.
NX3DV3899 v.2 20101123 Product data sheet - NX3DV3899 v.1
NX3DV3899 v.1 20101021 Product data sheet - -
NX3DV3899 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3. — 9 November 2011 20 of 22
NXP Semiconductors NX3DV3899
Dual double-pole double-throw analog switch
16. Legal information
16.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
: hitE:I/www.nxg.com salesaddresses®nx9£0m
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Product data sheet Rev. 3. — 9 November 2011 21 of 22
NXP Semiconductors NX3DV3899
Dual double-pole double-throw analog switch
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors NX3DV3899
Dual double-pole double-throw analog switch
© NXP B.V. 2011. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 9 November 2011
Document identifier: NX3DV3899
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
18. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
5 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
6 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
7 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
8 Functional description . . . . . . . . . . . . . . . . . . . 4
9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
10 Recommended operating conditions. . . . . . . . 5
11 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
11.1 Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
11.2 ON resistance. . . . . . . . . . . . . . . . . . . . . . . . . . 7
11.3 ON resistance test circuit and graphs. . . . . . . . 8
12 Dynamic characteristics . . . . . . . . . . . . . . . . . 10
12.1 Waveform and test circuits . . . . . . . . . . . . . . . 11
12.2 Additional dynamic characteristics . . . . . . . . . 13
12.3 Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17
14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 19
15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 19
16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 20
16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 20
16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
16.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 21
17 Contact information. . . . . . . . . . . . . . . . . . . . . 21
18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

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