L6384E Datasheet by STMicroelectronics

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This is information on a product in full production.
September 2015 DocID13862 Rev 3 1/18
L6384E
High voltage half-bridge driver
Datasheet - production data
Features
High voltage rail up to 600 V
dV/dt immunity ± 50 V/nsec in full temperature
range
Driver current capability
400 mA source
650 mA sink
Switching times 50/30 nsec rise/fall with 1 nF
load
CMOS/TTL Schmitt trigger inputs with
hysteresis and pull-down
Shutdown input
Deadtime setting
Undervoltage lockout
Integrated bootstrap diode
Clamping on VCC
Available in DIP-8/SO-8 packages
Applications
Home appliances
Induction heating
HVAC
Industrial applications and drives
Motor drivers
DC, AC, PMDC and PMAC motors
Lighting applications
Factory automation
Power supply systems
Description
The L6384E is a high voltage gate driver,
manufactured with the BCD™ “offline”
technology, and able to drive a half-bridge of
power MOSFET or IGBT devices. The high-side
(floating) section is able to work with voltage rail
up to 600 V. Both device outputs can sink and
source 650 mA and 400 mA respectively and
cannot be simultaneously driven high thanks to
single input configuration. Further prevention
from outputs cross conduction is guaranteed by
the deadtime function, tunable by the user
through an external resistor connected to the
DT/SD pin.
The L6384E device has one input pin, one enable
pin (DT/SD) and two output pins, and guarantees
matched delays between low-side and high-side
sections, thus simplifying device's high frequency
operation. The logic inputs are CMOS/TTL
compatible to ease the interfacing with controlling
devices. The bootstrap diode is integrated inside
the device, allowing a more compact and reliable
solution.
The L6384E features the UVLO protection and
a voltage clamp on the VCC supply voltage. The
voltage clamp is typically around 15.6 V and is
useful in order to ensure a correct device
functioning in cases where VCC supply voltage is
ramped up too slowly or is subject to voltage
drops.
The device is available in a DIP-8 tube and SO-8
tube and tape and reel packaging options.
DIP-8 SO-8
www.st.com
Contents L6384E
2/18 DocID13862 Rev 3
Contents
1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1 AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.2 DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.3 Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5 Bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
CBOOT selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6 Typical characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.1 DIP-8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.2 SO-8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
8 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
$%HE :: | 4 a
DocID13862 Rev 3 3/18
L6384E Block diagram
18
1 Block diagram
Figure 1. Block diagram
LOGIC
UV
DETECTION
LEVEL
SHIFTER
RS
V
CC
LVG
DRIVER
V
CC
IN
DT/SD
V
BOOT
HVG
DRIVER HVG
H.V.
LOAD
OUT
LVG
GND
D97IN518A
DEAD
TIME
V
CC
Idt
Vthi
BOOTSTRAP DRIVER
C
BOOT
4
3
5
6
7
8
1
2
Electrical data L6384E
4/18 DocID13862 Rev 3
2 Electrical data
2.1 Absolute maximum ratings
2.2 Thermal data
Table 1. Absolute maximum ratings
Symbol Parameter Value Unit
V
OUT
Output voltage -3 to VBOOT -18 V
V
CC
Supply voltage(1)
1. The device has an internal clamping Zener between GND and the VCC pin, it must not be supplied by a low
impedance voltage source.
- 0.3 to 14.6 V
I
s
Supply current(1) 25 mA
V
BOOT
Floating supply voltage -1 to 618 V
V
hvg
High-side gate output voltage -1 to VBOOT V
V
lvg
Low-side gate output voltage -0.3 to VCC +0.3 V
V
i
Logic input voltage -0.3 to VCC +0.3 V
V
SD
Shutdown/deadtime voltage -0.3 to VCC +0.3 V
dV
out
/dt Allowed output slew rate 50 V/ns
P
tot
Total power dissipation (T
j
= 85 °C) 750 mW
T
J
Junction temperature 150 °C
T
s
Storage temperature -50 to 150 °C
ESD Human body model 2 kV
Table 2. Thermal data
Symbol Parameter SO-8 DIP-8 Unit
R
th(JA)
Thermal resistance junction to ambient 150 100 °C/W
DocID13862 Rev 3 5/18
L6384E Electrical data
18
2.3 Recommended operating conditions
Table 3. Recommended operating conditions
Symbol Pin Parameter Test condition Min. Typ. Max. Unit
V
OUT
6 Output voltage (1)
1. If the condition VBOOT - VOUT < 18 V is guaranteed, VOUT can range from -3 to 580 V.
580 V
V
BS
(2)
2. VBS = VBOOT - VOUT
.
8 Floating supply voltage (1) 17 V
f
sw
Switching frequency HVG, LVG load C
L
= 1 nF 400 kHz
V
CC
2 Supply voltage V
clamp
V
T
j
Junction temperature -45 125 °C
_l_j_l__l_ _L_|__L_L
Pin connection L6384E
6/18 DocID13862 Rev 3
3 Pin connection
Figure 2. Pin connection (top view)
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Table 4. Pin description
No. Pin Type Function
1 IN I
Logic input: it is in phase with HVG and in opposition of phase with LVG. It is compatible
to VCC voltage. (V
il Max
= 1.5 V, V
ih Min
= 3.6 V).
2 V
CC
P Supply input voltage: there is an internal clamp [typ. 15.6 V].
3 DT/SD I
High impedance pin with two functionalities. When pulled lower than Vdt (typ. 0.5 V), the
device is shut down. A voltage higher than Vdt sets the deadtime between the high-side
gate driver and low-side gate driver. The deadtime value can be set forcing a certain
voltage level on the pin or connecting a resistor between the pin 3 and ground. Care
must be taken to avoid below threshold spikes on the pin 3 that can cause undesired
shutdown of the IC. For this reason the connection of the components between the pin 3
and ground has to be as short as possible. This pin can not be left floating for the same
reason. The pin has not be pulled through a low impedance to VCC, because of the drop
on the current source that feeds Rdt. The operative range is: Vdt … 270 K Idt, that
allows a dt range of 0.4 - 3.1 s.
4 GND P Ground
5 LVG O
Low-side driver output: the output stage can deliver 400 mA source and 650 mA sink
(typ. values). The circuit guarantees 0.3 V max. on the pin (at I
sink
= 10 mA) with
V
CC
> 3 V and lower than the turn-on threshold. This allows to omit the bleeder resistor
connected between the gate and the source of the external MOSFET normally used to
hold the pin low; the gate driver ensures low impedance also in SD conditions.
6 V
OUT
P
High-side driver floating reference: layout care has to be taken to avoid below ground
spikes on this pin.
7 HVG O
High-side driver output: the output stage can deliver 400 mA source and 650 mA sink
(typ. values). The circuit guarantees 0.3 V max. between this pin and V
OUT
(at I
sink
= 10 mA) with V
CC
> 3 V and lower than the turn-on threshold. This allows to omit
the bleeder resistor connected between the gate and the source of the external MOSFET
normally used to hold the pin low; the gate driver ensures low impedance also in SD
conditions.
8 VBOOT P
Bootstrap supply voltage: it is the high-side driver floating supply. The bootstrap capacitor
connected between this pin and the pin 6 can be fed by an internal structure named
“bootstrap driver” (a patented structure). This structure can replace the external
bootstrap diode.
CC
DocID13862 Rev 3 7/18
L6384E Electrical characteristics
18
4 Electrical characteristics
4.1 AC operation
4.2 DC operation
Table 5. AC operation electrical characteristics (V
CC
= 14.4 V; T
J
= 25 °C)
Symbol Pin Parameter Test condition Min. Typ. Max. Unit
t
on
1 vs. 5, 7 High/low-side driver turn-on
propagation delay V
OUT
= 0 V R
dt
= 47 k 200+
dt ns
t
onsd
3 vs. 5, 7 Shutdown input propagation
delay 220 280 ns
t
off
1 vs. 5, 7 High/low-side driver turn-off
propagation delay
V
OUT
= 0 V R
dt
= 47 k 250 300 ns
V
OUT
= 0 V R
dt
= 146 k 200 250 ns
V
OUT
= 0 V R
dt
= 270 k 170 200 ns
t
r
5, 7 Rise time C
L
= 1000 pF 50 ns
t
f
5, 7 Fall time C
L
= 1000 pF 30 ns
Table 6. DC operation electrical characteristics (V
CC
= 14.4 V; T
J
= 25 °C)
Symbol Pin Parameter Test condition Min. Typ. Max. Unit
Supply voltage section
V
clamp
2 Supply voltage clamping I
s
= 5 mA 14.6 15.6 16.6 V
V
CCth1
2 VCC UV turn-on threshold 11.5 12 12.5 V
V
CCth2
2
VCC UV turn-off threshold 9.5 10 10.5 V
V
CChys
VCC UV hysteresis 2 V
I
QCCU
Undervoltage quiescent supply
current V
CC
11 V 150 A
I
QCC
Quiescent current V
IN
= 0 380 500 A
Bootstrapped supply voltage section
V
BOOT
8
Bootstrap supply voltage 17 V
I
QBS
Quiescent current IN = HIGH 100 A
ILK High voltage leakage current V
hvg
= V
OUT
= V
BOOT
= 600 V 10 A
R
dson
Bootstrap driver on-resistance(1) V
CC
12.5 V; IN = LOW 125
High/low-side driver
I
so
5, 7
Source short-circuit current V
IN
= V
ih
(t
p
< 10 s) 300 400 mA
I
si
Sink short-circuit current V
IN
= V
il
(tp < 10 s) 500 650 mA
Electrical characteristics L6384E
8/18 DocID13862 Rev 3
4.3 Timing diagram
Figure 3. Input/output timing diagram
Symbol Pin Parameter Test condition Min. Typ. Max. Unit
Logic inputs
V
il
1, 3
Low level logic threshold voltage 1.5 V
V
ih
High level logic threshold
voltage 3.6 V
I
ih
High level logic input current V
IN
= 15 V 50 70 A
I
il
Low level logic input current V
IN
= 0 V 1 A
I
ref
3 Deadtime setting current 28 A
dt 3 vs. 5, 7 Deadtime setting range(2)
R
dt
= 47 k
R
dt
= 146 k
R
dt
= 270 k
0.4 0.5
1.5
2.7 3.1
s
s
s
V
dt
3 Shutdown threshold 0.5 V
1. RDS(on) is tested in the following way:
Where I
1
is the pin 8 current when V
BOOT
= V
BOOT1
, I
2
when V
BOOT
= V
BOOT2
.
2. The pin 3 is a high impedance pin. Therefore dt can be set also forcing a certain voltage V
3
on this pin. The deadtime is the
same obtained with an R
dt
if it is: R
dt
× I
ref
= V
3
.
Table 6. DC operation electrical characteristics (continued) (V
CC
= 14.4 V; T
J
= 25 °C)
RDSON
VCC VBOOT1
VCC VBOOT2

I1VCC,VBOOT1
I2VCC,VBOOT2

-----------------------------------------------------------------------------------------------=
IN
SD
HVG
LVG
D99IN1017
DocID13862 Rev 3 9/18
L6384E Bootstrap driver
18
5 Bootstrap driver
A bootstrap circuitry is needed to supply the high voltage section. This function is normally
accomplished by a high voltage fast recovery diode (Figure 4 a). In the L6384E device
a patented integrated structure replaces the external diode. It is realized by a high voltage
DMOS, driven synchronously with the low-side driver (LVG), with a diode in series, as
shown in Figure 4 b. An internal charge pump (Figure 4 b) provides the DMOS driving
voltage. The diode connected in series to the DMOS has been added to avoid undesirable
turn-on.
CBOOT selection and charging
To choose the proper C
BOOT
value the external MOSFET can be seen as an equivalent
capacitor. This capacitor C
EXT
is related to the MOSFET total gate charge:
Equation 1
The ratio between the capacitors C
EXT
and C
BOOT
is proportional to the cyclical voltage loss.
It has to be:
CBOOT>>>CEXT
E.g.: if Q
gate
is 30 nC and V
gate
is 10 V, C
EXT
is 3 nF. With C
BOOT
= 100 nF the drop would be
300 mV.
If HVG has to be supplied for a long time, the C
BOOT
selection has to take into account also
the leakage losses.
E.g.: HVG steady state consumption is lower than 100 A, so if HVG T
ON
is 5 ms, C
BOOT
has to supply 0.5 C to C
EXT
. This charge on a 1 F capacitor means a voltage drop of
0.5 V.
The internal bootstrap driver gives great advantages: the external fast recovery diode can
be avoided (it usually has a great leakage current).
This structure can work only if V
OUT
is close to GND (or lower) and in the meanwhile the
LVG is on. The charging time (T
charge
) of the C
BOOT
is the time in which both conditions are
fulfilled and it has to be long enough to charge the capacitor.
The bootstrap driver introduces a voltage drop due to the DMOS R
DSON
(typical value:
125 ). At low frequency this drop can be neglected. Anyway increasing the frequency it
must be taken in to account.
The following equation is useful to compute the drop on the bootstrap DMOS:
Equation 2
where Q
gate
is the gate charge of the external power MOSFET, R
dson
is the on-resistance of
the bootstrap DMOS, and T
charge
is the charging time of the bootstrap capacitor.
CEXT
Qgate
Vgate
---------------=
Vdrop Ich earg Rdson Vdrop
Qgate
Tch earg
------------------- Rdson
==
War-v J_[ gi i
Bootstrap driver L6384E
10/18 DocID13862 Rev 3
For example: using a power MOSFET with a total gate charge of 30 nC, the drop on the
bootstrap DMOS is about 1 V, if the T
charge
is 5 s. In fact:
Equation 3
V
drop
has to be taken into account when the voltage drop on C
BOOT
is calculated: if this drop
is too high, or the circuit topology doesn’t allow a sufficient charging time, an external diode
can be used.
Figure 4. Bootstrap driver
Vdrop
30nC
5s
---------------1250.8V=
TO LOAD
D99IN1067
H.V.
HVG
ab
LVG
HVG
LVG
C
BOOT
TO LOAD
H.V.
C
BOOT
D
BOOT
V
BOOT
V
S
V
S
V
OUT
V
BOOT
V
OUT
u n
DocID13862 Rev 3 11/18
L6384E Typical characteristic
18
6 Typical characteristic
Figure 5. Typical rise and fall times
vs. load capacitance
Figure 6. Quiescent current vs. supply
voltage
Figure 7. Deadtime vs. resistance Figure 8. Driver propagation delay
vs. temperature
Figure 9. Deadtime vs. temperature Figure 10. Shutdown threshold
vs. temperature
02468101214V
S
(V)
10
10
2
10
3
10
4
Iq
(μA)
D99IN1016
50 100 150 200 250 300
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
dt (s)
Rdt (k)
Typ.
@ Vcc = 14.4V
-45 -25 0 25 50 75 100 125
0
100
200
300
400
Ton,Toff (ns)
@ Rdt = 47kOhm
@ Rdt = 146kOhm
@ Rdt = 270kOhm
Tj (°C)
Typ.
Typ.
Typ.
@ Vcc = 14.4V
-45 -25 0 25 50 75 100 125
Tj (°C)
0
0.5
1
1.5
2
2.5
3
dt (s)
R=47K
R=146K
R=270K
Typ.
Typ.
Typ.
@ Vcc = 14.4V
-45 -25 025 50 75 100 125
0
0.2
0.4
0.6
0.8
1
Vdt (V)
Tj (°C)
Typ.
@ Vcc = 14.4V
Typical characteristic L6384E
12/18 DocID13862 Rev 3
Figure 11. VCC UV turn-on vs. temperature Figure 12. Output source current
vs. temperature
Figure 13. VCC UV turn-off
vs. temperature
Figure 14. Output sink current
vs. temperature
-45 -25 0 25 50 75 100 125
10
11
12
13
14
15
Vccth1 (V)
Tj (°C)
Typ.
-45 -25 0 25 50 75 100 125
10
11
12
13
14
15
Vccth1 (V)
Tj (°C)
Typ.
-45 -25 0 25 50 75 100 125
0
200
400
600
800
1000
Current (mA)
Tj (°C)
Typ.
@ Vcc = 14.4V
-45 -25 0 25 50 75 100 125
0
200
400
600
800
1000
Current (mA)
Tj (°C)
Typ.
@ Vcc = 14.4V
-45 -25 0 25 50 75 100 125
8
9
10
11
12
13
Vccth2 (V)
Tj (°C)
Typ.
-45 -25 0 25 50 75 100 125
8
9
10
11
12
13
Vccth2 (V)
Tj (°C)
Typ.
-45 -25 0 25 50 75 100 125
0
200
400
600
800
1000
Current (mA)
Tj (°C)
Typ.
@ Vcc = 14.4V
-45 -25 0 25 50 75 100 125
0
200
400
600
800
1000
Current (mA)
Tj (°C)
Typ.
@ Vcc = 14.4V
L 93 I’ll—IWW |_l|_l|_l|_l
DocID13862 Rev 3 13/18
L6384E Package information
18
7 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
7.1 DIP-8 package information
Figure 15. DIP-8 package outline
$0Y
Package information L6384E
14/18 DocID13862 Rev 3
Table 7. DIP-8 package mechanical data
Symbol
Dimensions (mm) Dimensions (inch)
Min. Typ. Max. Min. Typ. Max.
A 3.32 0.131
a1 0.51 0.020
B 1.15 1.65 0.045 0.065
b 0.356 0.55 0.014 0.022
b1 0.204 0.304 0.008 0.012
D 10.92 0.430
E 7.95 9.75 0.313 0.384
e 2.54 0.100
e3 7.62 0.300
e4 7.62 0.300
F 6.6 0.260
I 5.08 0.200
L 3.18 3.81 0.125 0.150
Z 1.52 0.060
ZV W > EL r) SEAT‘NG PLANE 025 mm GAGE PLANE gfi \ L 7 L1
DocID13862 Rev 3 15/18
L6384E Package information
18
7.2 SO-8 package information
Figure 16. SO-8 package outline
$0Y
Package information L6384E
16/18 DocID13862 Rev 3
Table 8. SO-8 package mechanical data
Symbol
Dimensions (mm) Dimensions (inch)
Min. Typ. Max. Min. Typ. Max.
A 1.750 0.0689
A1 0.100 0.250 0.0039 0.0098
A2 1.250 0.0492
b 0.280 0.480 0.0110 0.0189
c 0.170 0.230 0.0067 0.0091
D(1)
1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs
shall not exceed 0.15 mm in total (both sides).
4.800 4.900 5.000 0.1890 0.1929 0.1969
E 5.800 6.000 6.200 0.2283 0.2362 0.2441
E1(2)
2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not
exceed 0.25 mm per side.
3.800 3.900 4.000 0.1496 0.1535 0.1575
e 1.270 0.0500
h 0.250 0.500 0.0098 0.0197
L 0.400 1.270 0.0157 0.0500
L1 1.040 0.0409
k0°8°0°8°
ccc 0.100 0.0039
DocID13862 Rev 3 17/18
L6384E Order codes
18
8 Order codes
9 Revision history
Table 9. Order code
Order code Package Packaging
L6384E DIP-8 Tube
L6384ED SO-8 Tube
L6384ED013TR SO-8 Tape and reel
Table 10. Document revision history
Date Revision Changes
12-Oct-2007 1 First release
20-Jun-2014 2
Added Section : Applications on page 1.
Updated Section : Description on page 1 (replaced by new description).
Updated Table 1: Device summary on page 1 (moved from page 15 to page 1,
updated title).
Updated Figure 1: Block diagram on page 3 (moved from page 1 to page 3,
numbered and added title to Section 1: Block diagram on page 3).
Updated Section 2.1: Absolute maximum ratings on page 4 (removed note below
Table 2: Absolute maximum ratings).
Updated Table 5: Pin description on page 5 (updated “Type” of several pins).
Updated Table 7 on page 6 (updated “Max.” value of IQBS symbol).
Updated Section : CBOOT selection and charging on page 8 (updated values of
“E.g.: HVG”).
Numbered Equation 1 on page 8, Equation 2 on page 8 and Equation 3 on page 9.
Updated Section 7: Package information on page 12 [updated/added titles, updated
ECOPACK text, reversed order of Figure 15 and Table 8, Figure 16 and Table 9
(numbered tables), removed 3D package figures, minor modifications].
Minor modifications throughout document.
16-Sep-2015 3
Updated Table 1 on page 4 (added ESD parameter and value, minor modifications).
Updated note 1. below Table 6 on page 7 (replaced VCBOOTx by VBOOTx).
Moved Table 9 on page 17 (moved from page 1 to page 17, updated titles).
Updated cross-references throughout document.
Minor modifications throughout document.
L6384E
18/18 DocID13862 Rev 3
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