USBLC6-2 Datasheet by STMicroelectronics

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USBLC6-2 Very low capacitance ESD protection I Very low capaCitance between lines to GND for optimized data integrity and speed I Low PCB space consumption: 2.9 mm2 max for SOT7666 and 9 mm2 max for SOT2376L I Enhanced ESD protection: lEC 610007472 level 4 compliance guaranteed at device level, hence greater immunity at system level I ESD protection of Veus I High reliability offered by monolithic integration I Low leakage current for longer operation of battery powered devices I Fast response time I Consistent D+ / Dr signal balance: 7 Very low capacitance matching tolerance I/O 10 GND = 0.015 pF 7 Compliant With USB 2.0 requirements Complies with the [allowing standards: I IEC 610007472 level 4: r 15 kV (air discharge) 7 8 kV (contact discharge) October 2011 / ' SOT-666 USBLCS-ZPS SOT23-6L USBLCG-ZSCS Figure 1. Functional diagram (top view) C I E j rm E :l Appficafions I USB 2.0 ports up to 480 Mb/s (high speed) I Compatible with USB1.1 low and full speed I Ethernet port: 10/100 Mb/s I SIM card protection I Video line protection I Portable electronics Descfipfion The USBLCSVZSCG and USBLCGVZF’S are monolithic application specific devices dedicated to ESD protection of high speed inter1aces, such as USB 2.0, Ethernet links and video lines. The very low line capacitance secures a high level of signal integrity Without compromising in protecting sensitive chips against the most stringently characterized ESD strikes. Doc ID 11265 Flev5 1/14
October 2011 Doc ID 11265 Rev 5 1/14
14
USBLC6-2
Very low capacitance ESD protection
Features
2 data-line protection
Protects VBUS
Very low capacitance: 3.5 pF max.
Very low leakage current: 150 nA max.
SOT-666 and SOT23-6L packages
RoHS compliant
Benefits
Very low capacitance between lines to GND for
optimized data integrity and speed
Low PCB space consumption: 2.9 mm2 max for
SOT-666 and 9 mm² max for SOT23-6L
Enhanced ESD protection: IEC 61000-4-2
level 4 compliance guaranteed at device level,
hence greater immunity at system level
ESD protection of VBUS
High reliability offered by monolithic integration
Low leakage current for longer operation of
battery powered devices
Fast response time
Consistent D+ / D- signal balance:
Very low capacitance matching tolerance
I/O to GND = 0.015 pF
Compliant with USB 2.0 requirements
Complies with the following standards:
IEC 61000-4-2 level 4:
15 kV (air discharge)
8 kV (contact discharge)
Figure 1. Functional diagram (top view)
Applications
USB 2.0 ports up to 480 Mb/s (high speed)
Compatible with USB 1.1 low and full speed
Ethernet port: 10/100 Mb/s
SIM card protection
Video line protection
Portable electronics
Description
The USBLC6-2SC6 and USBLC6-2P6 are
monolithic application specific devices dedicated
to ESD protection of high speed interfaces, such
as USB 2.0, Ethernet links and video lines.
The very low line capacitance secures a high level
of signal integrity without compromising in
protecting sensitive chips against the most
stringently characterized ESD strikes.
SOT23-6L
USBLC6-2SC6
SOT-666
USBLC6-2P6
116
25
34
I/O1 I/O1
GND VBUS
I/O2 I/O2
www.st.com
Tamb
Characteristics USBLC6-2
2/14 Doc ID 11265 Rev 5
1 Characteristics
Table 1. Absolute ratings
Symbol Parameter Value Unit
VPP Peak pulse voltage
IEC 61000-4-2 air discharge
IEC 61000-4-2 contact discharge
MIL STD883G-Method 3015-7
15
15
25
kV
Tstg Storage temperature range -55 to +150 °C
TjOperating junction temperature range -40 to +125 °C
TLLead solder temperature (10 seconds duration) 260 °C
Table 2. Electrical characteristics (Tamb = 25 °C)
Symbol Parameter Test conditions
Value
Unit
Min. Typ. Max.
IRM Leakage current VRM = 5.25 V 10 150 nA
VBR
Breakdown voltage between
VBUS and GND IR = 1 mA 6 V
VFForward voltage IF = 10 mA 1.1 V
VCL Clamping voltage
IPP = 1 A, 8/20 µs
Any I/O pin to GND 12 V
IPP = 5 A, 8/20 µs
Any I/O pin to GND 17 V
Ci/o-GND
Capacitance between I/O
and GND VR = 1.65 V 2.5 3.5 pF
ΔCi/o-GND 0.015
Ci/o-i/o Capacitance between I/O VR = 1.65 V 1.2 1.7 pF
ΔCi/o-i/o 0.04
USBLC6-2 Characteristics
Doc ID 11265 Rev 5 3/14
Figure 2. Capacitance versus voltage
(typical values)
Figure 3. Line capacitance versus frequency
(typical values)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
C(pF)
F=1MHz
V =30mV
T =25°C
OSC RMS
j
C =I/O-I/O
j
C =I/O-GND
O
Data line voltage (V)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
1 10 100 1000
C(pF)
V =30mV
T =25°C
OSC RMS
j
V =0V to 3.3V
LINE
F(MHz)
Figure 4. Relative variation of leakage
current versus junction
temperature (typical values)
Figure 5. Frequency response
1
10
100
25 50 75 100 125
T (°C)
j
V =5V
BUS
I[T
RM j] / I [T
RM j=25°C]
100.0k 1.0M 10.0M 100.0M 1.0G
-20.00
-15.00
-10.00
-5.00
0.00
S21(dB)
F(Hz)
Technical information USBLC6-2
4/14 Doc ID 11265 Rev 5
2 Technical information
2.1 Surge protection
The USBLC6-2 is particularly optimized to perform surge protection based on the rail to rail
topology.
The clamping voltage VCL can be calculated as follow:
VCL+ = VTRANSIL + VF for positive surges
VCL- = - VF for negative surges
with: VF = VT + Rd.Ip
(VF forward drop voltage) / (VT forward drop threshold voltage)
and VTRANSIL = VBR + Rd_TRANSIL.IP
Calculation example
We assume that the value of the dynamic resistance of the clamping diode is typically:
Rd = 0.5 Ω and VT = 1.1 V
We assume that the value of the dynamic resistance of the transil diode is typically:
Rd_TRANSIL = 0.5 Ω and VBR = 6.1 V
For an IEC 61000-4-2 surge Level 4 (Contact Discharge: Vg = 8 kV, Rg = 330 Ω),
VBUS = +5 V, and if in first approximation, we assume that:
Ip = Vg / Rg = 24 A.
So, we find:
VCL+ = +31.2 V
VCL- = -13 V
Note: The calculations do not take into account phenomena due to parasitic inductances.
2.2 Surge protection application example
If we consider that the connections from the pin VBUS to VCC, from I/O to data line and from
GND to PCB GND plane are done by tracks of 10 mm long and 0.5 mm large, we assume
that the parasitic inductances LVBUS, LI/O and LGND of these tracks are about 6 nH. So when
an IEC 61000-4-2 surge occurs on data line, due to the rise time of this spike (tr=1ns), the
voltage VCL has an extra value equal to LI/O.dl/dt + LGND.dI/dt.
The dI/dt is calculated as:
dI/dt = Ip/tr = 24 A/ns
The overvoltage due to the parasitic inductances is:
LI/O.dl/dt = LGND.dI/dt = 6 nH x 24 A/ns = 144 V
By taking into account the effect of these parasitic inductances due to unsuitable layout, the
clamping voltage will be:
VCL+ = +31.2 + 144 + 144 = 319.2 V
VCL- = -13.1 - 144 - 144 = -301.1 V
2.3 n significantly reduce this phenomena With simple layout opiimi on that some recommendations have to be lollowed (see 2.3: How (ion). e 6. ESD behavior: parasitic phenomena due to unsuitahl zsn m. on m n". . m. was pm u... ell m m luvs m, R. my a mum 5mg. vufivmmstt .VF. Ll/O fl . LeNn'fl suige)“ “‘ l“ N aliv- H, a {inimui ggg ,, , _7 _- m .1 m - VCL-- v; we m Lem)m surge)“ VYRANSlL: VBRVRd-IP How to ensure good ESD protection While the USBLCBVZ prowdes high immunity to ESD surge, elficieni protection depends on the layout of the board. In the same way, with the rail to rail topology, the track from data lines to l/O pins, from VCC to VBUS pin and lrom GND plane to GND pin must be as short as possible to avoid overvoltages due to parasitic phenomena (see Figure 6. and Figure 7. for layout consideration) behavior: layout optimization Figure 8. ESD behavior: m conditions 1 s I: [pl—LN» ] ESD SURGE r E ’1 El TESTBOA E ’ I ’ 3 IN E' 1 Unsuitable layout I: : E j \ E I El E k] 2 E II Optimized layout ‘7] Doc ID 11265 Rev 5 5/14
USBLC6-2 Technical information
Doc ID 11265 Rev 5 5/14
We can significantly reduce this phenomena with simple layout optimization. It is for this
reason that some recommendations have to be followed (see 2.3: How to ensure good ESD
protection).
Figure 6. ESD behavior: parasitic phenomena due to unsuitable layout
2.3 How to ensure good ESD protection
While the USBLC6-2 provides high immunity to ESD surge, efficient protection depends on
the layout of the board. In the same way, with the rail to rail topology, the track from data
lines to I/O pins, from VCC to VBUS pin and from GND plane to GND pin must be as short as
possible to avoid overvoltages due to parasitic phenomena (see Figure 6. and Figure 7. for
layout consideration)
VBUS
LI/O LVBUS
LGND
LI/O
LGND
V pin
CC
VCL
VF
I/O pin
VTRANSIL V+V
TRANSIL F
-V
F
VCL-
t = 1 ns
r
t
t
t = 1 ns
r
VCL+
GND pin
Data line
Positive
Surge
Negative
Surge
ESD surge on data line
di
dt LI/O + LGND
di
dt
di
dt
-LI/O - LGND
di
dt
di
dt
V+=V +V + L + L surge > 0
CL TRANSIL F I/O GND
V = -V - L - L surge > 0
CL- F I/O GND
di
dt
di
dt
di
dt
di
dt
di
dt
Rd.IpVV BR
TRANSIL +=
Figure 7. ESD behavior: layout optimization Figure 8. ESD behavior: measurement
conditions
Unsuitable layout
Optimized layout
1
16
25
34
1
16
25
34
+5 V
IN OUT
TEST BOARD
ESD SURGE
USBLC6-2SC6
Technical information USBLC6-2
6/14 Doc ID 11265 Rev 5
Important:
A good precaution to take is to put the protection device as close as possible to the
disturbance source (generally the connector).
2.4 Crosstalk behavior
2.4.1 Crosstalk phenomenon
Figure 11. Crosstalk phenomenon
The crosstalk phenomenon is due to the coupling between 2 lines. The coupling factor (β12
or β21) increases when the gap across lines decreases, particularly in silicon dice. In the
above example the expected signal on load RL2 is α2VG2, in fact the real voltage at this point
has got an extra value β21VG1. This part of the VG1 signal represents the effect of the
crosstalk phenomenon of the line 1 on the line 2. This phenomenon has to be taken into
account when the drivers impose fast digital data or high frequency analog signals in the
disturbing line. The perturbed line will be more affected if it works with low voltage signal or
high load impedance (few kΩ).
Figure 9. ESD response to IEC 61000-4-2
(+15 kV air discharge)
Figure 10. ESD response to IEC 61000-4-2
(-15 kV air discharge)
Vin
Vout
Vin
Vout
Line 1
Line 2
VG1
VG2
RG1
RG2
DRIVERS
R
L1
RL2
RECEIVERS
αβ
+
112
VG1 VG2
αβ
+
221
VG2 VG1
. . E“ NETWORK ANALYSER NETWORK ANALYSER E 'l: PORT 2 PORT 1 ths Figure 12. shows me measuremem cxrcuil forlhe analog applicanon. In usual frequency range 01 analog signals (up lo 240 MHz) lhe elfecl on dislurbed line is less man 755 dB (see Figure 13.). Figure 13. Analog crosstalk resulis l llllll! As lhe USBLCGVZ is designed lo prolecl high speed da1a lines, i1 musk ensure a good lransmisslon of operahng signals. The frequency response (Figure 5.) glves allenualion informalion and shows 1hal lhe USBLCGVZ is well sullable for dala llne lransmission up 10 480 Mbil/s while i1 works as a filler for undesirable signals like GSM (900 MHz) lrequencies, for inslance. ‘7] Doc ID 11265 Rev 5 7/14
USBLC6-2 Technical information
Doc ID 11265 Rev 5 7/14
Figure 12. Analog crosstalk measurements
Figure 12. shows the measurement circuit for the analog application. In usual frequency
range of analog signals (up to 240 MHz) the effect on disturbed line is less than -55 dB (see
Figure 13.).
Figure 13. Analog crosstalk results
As the USBLC6-2 is designed to protect high speed data lines, it must ensure a good
transmission of operating signals. The frequency response (Figure 5.) gives attenuation
information and shows that the USBLC6-2 is well suitable for data line transmission up to
480 Mbit/s while it works as a filter for undesirable signals like GSM (900 MHz) frequencies,
for instance.
NETWORK ANALYSER
PORT 2
NETWORK ANALYSER
PORT 1
TEST BOARD
Vbus
USBL
C6-2SC6
100.0k 1.0M 10.0M 100.0M 1.0G
- 120.00
- 90.00
- 60.00
- 30.00
0.00
dB
F (Hz)
USBLCG-2 BLC6-2 W 'H'u - DOWNSTREAM TRANSCEIVER Vans Rx lers + Rxns+ NS} F gs Swmc x lers . a fix as. rx N5. 3 GND Tst/Fs+ 41+ .2. W rx we. W Q my 6 Hum m. Gm) rx lS/FS + b—W rx we. Mod: sw. swz Low Speed LS Open Ckzsed FuH Speed Fs mused Open ngh Speed H5 mused men oven Open Figure 15. T1IE1IEthernet protection .ch LE Tx +§H§ml—E Ir: . sum“ fl .m L; Rx\ +§HEWLE 71—5 a sum“ if? 3/14 Doc ID 11265 Rev 5 £7]
Technical information USBLC6-2
8/14 Doc ID 11265 Rev 5
2.5 Application examples
Figure 14. USB 2.0 port application diagram using USBLC6-2
Figure 15. T1/E1/Ethernet protection
HUB-
DOWNSTREAM
TRANSCEIVER
+ 5V
RS
RS
RS
RS
RPD
RPD
RPD
RPD
Protecting
Bus Switch
DEVICE-
UPSTREAM
TRANSCEIVER
+ 3.3V
SW1
RPU
VBUS
D+
D-
GND
VBUS VBUS
VBUS
RX LS/FS +RX LS/FS +
RX LS/FS +
RX LS/FS +
RX HS +RX HS +
RX HS +
RX HS +
TX HS +TX HS +
TX HS +
TX HS +
TX LS/FS +TX LS/FS +
TX LS/FS +
TX LS/FS +
RS
RS
USB
connector
TX LS/FS - TX LS/FS -
TX LS/FS -
TX LS/FS -
RX LS/FS - RX LS/FS -
RX LS/FS -
RX LS/FS -
RX HS - RX HS -
RX HS -
RX HS -
TX HS - TX HS -
TX HS -
TX HS -
GND GND
GND
GND
SW2
DEVICE-
UPSTREAM
TRANSCEIVER
USBLC6-4SC6
USBLC6-2P6
USBLC6-2SC6
+ 3.3V
SW1
RPU
VBUS
D+
D-
GND
RS
RS
USB
connector
SW2
OpenClosed then openHigh Speed HS
OpenClosedFull Speed FS
ClosedOpenLow Speed LS
SW
2
SW
1
Mode
DATA
TRANSCEIVER
SMP75-8
SMP75-8
Tx
Rx
+VCC
+VCC
100nF
100nF
USBLC6-2SC6USBLC6-2SC6
USBLCS-Z 2.6 PSpice model Figure 16. shows the PSpice model of one USBLCSVZ cell. In 1h defined by the PSptce parameters given in Figure 17. Figure 16. PSpice model LIIO nuo R mm c w E E W MODEL = Dlow MODEL = Dhigh : u LGND “6““ MODEL = Dxenel R em) 0 w E u E w- MODEL = Dlow MODEL = Dhigh E E LIIO nuo R D-in C W E E ’W‘ Note: This simulation model is available only for an ambient temperat W O HO / m min :1 CJO 0 9p 2 Op 40,; LGND 550p \EV 1m Im 1m RGND 60m GND D :l M D 3333 0 3333 0 3333 E RS 0 2 o 52 a M N" 3 VJ 0 6 O 6 D 6 Tr om on an ”SEEM Doc ID 11265 Flev5
USBLC6-2 Technical information
Doc ID 11265 Rev 5 9/14
2.6 PSpice model
Figure 16. shows the PSpice model of one USBLC6-2 cell. In this model, the diodes are
defined by the PSpice parameters given in Figure 17.
Figure 16. PSpice model
Note: This simulation model is available only for an ambient temperature of 27 °C.
MODEL = Dlow MODEL = Dhigh
VBUS
LI/O
LGND
GND
D+in
MODEL = Dzener
RI/O
LI/O
D-in
RI/O
LI/O
LI/O
RGND RI/O
D-out
RI/O
MODEL = Dlow MODEL = Dhigh
LI/O
D+out
RI/O
Figure 17. PSpice parameters Figure 18. USBLC6-2 PCB layout
considerations
Dlow Dhigh Dzener
BV 50 50 7.3
CJ0 0.9p 2.0p 40p
IBV 1m 1m 1m
M 0.3333 0.3333 0.3333
RS 0.2 0.52 0.84
VJ 0.6 0.6 0.6
TT 0.1u 0.1u 0.1u
LI/O 750p
RI/O 110m
LGND 550p
RGND 60m
D+in D+out
D-out
GND
USBLC6-2
D-in
V
BUS
1
C = 100nF
BUS
Ordering information scheme USBLC6-2
10/14 Doc ID 11265 Rev 5
3 Ordering information scheme
Figure 19. Ordering information scheme
USB LC 6 - 2 xxx
Product Designation
Low capacitance
Breakdown Voltage
Packages
6 = 6 Volts
2 = 2 lines
SC6 = SOT23-6L
P6 = SOT-666
Number of lines protected
‘T’j g2; u #14 k 7 n R R WT ' 7 7 U Ll” Lf
USBLC6-2 Package information
Doc ID 11265 Rev 5 11/14
4 Package information
Epoxy meets UL94, V0
Lead-free packages
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Table 3. SOT-666 dimensions
Ref.
Dimensions
Millimeters Inches
Min. Typ. Max. Min. Typ. Max.
A 0.45 0.60 0.018 0.024
A3 0.08 0.18 0.003 0.007
b 0.17 0.34 0.007 0.013
b1 0.19 0.27 0.34 0.007 0.011 0.013
D 1.50 1.70 0.059 0.067
E 1.50 1.70 0.059 0.067
E1 1.10 1.30 0.043 0.051
e0.50 0.020
L1 0.19 0.007
L2 0.10 0.30 0.004 0.012
L3 0.10 0.004
D
b
L3
L1
e
b1
E1
L2
E
A
A3
Figure 20. SOT-666 footprint
dimensions in mm
Figure 21. SOT-666 marking
0.50
2.60
0.62
0.30
0.99
F
Package information Table 4. SOT23-6L dimensions Dim Ref. Millimeters Min. Typ. Ma A O 90 1. A1 0 0. A2 0 90 1. b O 35 0 c O 09 O. D 2 80 3 E 1 50 1. e O 95 H 2 60 3. L O 10 O. 6 O” 10 Figure 22. SOT23-6L loolprim Figure 23. SOT23-6L mark dimensions in mm 0.60 7 1.20 0.95 ‘ 3.50 2.30 ‘ 1 1o . 12/14 Doc ID 11265 Flev5
Package information USBLC6-2
12/14 Doc ID 11265 Rev 5
Table 4. SOT23-6L dimensions
Ref.
Dimensions
Millimeters Inches
Min. Typ. Max. Min. Typ. Max.
A 0.90 1.45 0.035 0.057
A1 0 0.10 0 0.004
A2 0.90 1.30 0.035 0.051
b 0.35 0.50 0.014 0.020
c 0.09 0.20 0.004 0.008
D 2.80 3.05 0.11 0.118
E 1.50 1.75 0.059 0.069
e 0.95 0.037
H 2.60 3.00 0.102 0.118
L 0.10 0.60 0.004 0.024
θ0° 10° 0° 10°
A2
A
L
H
c
b
E
D
e
e
A1
q
Figure 22. SOT23-6L footprint
dimensions in mm
Figure 23. SOT23-6L marking
0.95
0.60
1.20
1.10
3.50 2.30
UL26
USBLC6-2 Ordering information
Doc ID 11265 Rev 5 13/14
5 Ordering information
6 Revision history
Table 5. Ordering information
Order code Marking Package Weight Base qty Delivery mode
USBLC6-2SC6 UL26 SOT23-6L 16.7 mg 3000 Tape and reel
USBLC6-2P6 F SOT-666 2.9 mg 3000 Tape and reel
Table 6. Document revision history
Date Revision Changes
14-Mar-2005 1 First issue.
07-Jun-2005 2 Format change to figure 3; no content changed.
20-Mar-2008 3
Added marking illustrations - Figures 21 and 23. Added
ECOPACK statement. Updated operating junction temperature
range in absolute ratings, page 2. Technical information section
updated. Reformatted to current standards.
27-Jun-2011 4 Updated leakage current for VRM = 5.25 V as specified in USB
standard. Updated marking illustrations Figure 21 and Figure 23.
24-Oct-2011 5 Updated legal statement.
USBLC6-2
14/14 Doc ID 11265 Rev 5
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