STD5N20L Datasheet by STMicroelectronics

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S2 D(TAE) 5(1) sis) SCD7550
1/10September 2004
NEW DATASHEET ACCORDING TO PCN DSG-TRA/04/532
STD5N20L
N-CHANNEL 200V - 0.65 - 5A DPAK
STripFET™ MOSFET
Table 1: General Features
TYPICAL RDS(on) = 0.65 @ 5V
CONDUCTION LOSSES REDUCED
LOW INPUT CAPACIATNCE
LOW THRESHOLD DEVICE
DESCRIPTION
The STD5N20L utilizes the latest advanced de-
sign rules of ST’s proprietary STripFET™ technol-
ogy. This is suitable for the most demanding DC
Motor Control and lighting application.
APPLICATIONS
UPS AND MOTOR CONTROL
LIGHTING
Table 2: Order Codes
Figure 1: Package
Figure 2: Internal Schematic Diagram
TYPE VDSS RDS(on) IDPw
STD5N20L 200 V < 0.7 5 A 33 W
1
3
DPAK
SALES TYPE MARKING PACKAGE PACKAGING
STD5N20LT4 D5N20L DPAK TAPE & REEL
Rev. 3
STD5N20L
2/10
Table 3: Absolute Maximum ratings
( ) Pulse width limited by safe operating area
Table 4: Thermal Data
ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED)
Table 5: On/Off
Symbol Parameter Value Unit
VDS Drain-source Voltage (VGS = 0) 200 V
VDGR Drain-gate Voltage (RGS = 20 k)200 V
VGS Gate- source Voltage ±20 V
IDDrain Current (continuous) at TC = 25°C5A
IDDrain Current (continuous) at TC = 100°C3.6 A
IDM ( ) Drain Current (pulsed) 20 A
PTOT Total Dissipation at TC = 25°C33 W
Derating Factor 0.27 W/°C
Tstg Storage Temperature 55 to 150 °C
TjOperating Junction Temperature
Rthj-case Thermal Resistance Junction-case Max 3.75 °C/W
Rthj-amb Thermal Resistance Junction-ambient Max 100 °C/W
TlMaximum Lead Temperature For Soldering Purpose 275 °C
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V(BR)DSS Drain-source
Breakdown Voltage ID = 250 µA, VGS = 0 200 V
IDSS Zero Gate Voltage
Drain Current (VGS = 0) VDS = Max Rating A
VDS= Max Rating, TC= 125°C10 µA
IGSS Gate-body Leakage
Current (VDS = 0) VGS = ±20V ±100 nA
VGS(th) Gate Threshold Voltage VDS = VGS, ID = 50µA 12.5V
RDS(on) Static Drain-source On
Resistance VGS = 5 V, ID = 2.5 A 0.65 0.7
3/10
STD5N20L
Table 6: Dynamic
Table 7: Source Drain Diode
(1) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
(2) Starting Tj =25 °C, Id = 5 A, VDD = 50 V
(*) Pulse width limited by safe operating area
Symbol Parameter Test Conditions Min. Typ. Max. Unit
gfs (2) Forward Transconductance VDS = 15 V, ID = 5 A 6.5 S
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
VDS = 25V, f = 1 MHz, VGS = 0 242
44
6
pF
pF
pF
td(on)
tr
td(off)
tf
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
VDD = 100 V, ID = 2.5 A
RG = 4.7Ω, VGS = 5V
(Resistive Load see Figure 14)
11.5
21.5
14
15.5
ns
ns
ns
ns
Qg
Qgs
Qgd
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
VDD = 160 V, ID = 5 A,
VGS = 5V
5
1.5
3
6nC
nC
nC
Symbol Parameter Test Conditions Min. Typ. Max. Unit
ISD Source-drain Current 5 A
ISDM (*) Source-drain Current (pulsed) 20 A
VSD (1) Forward On Voltage ISD = 5 A, VGS = 0 1.5 V
trr
Qrr
IRRM
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
ISD = 5 A, di/dt = 100 A/µs,
VDD = 100 V, Tj = 25°C
(see test circuit, see Figure 15)
93
237
5.1
ns
nC
A
trr
Qrr
IRRM
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
ISD = 5 A, di/dt = 100 A/µs,
VDD = 100 V, Tj = 150°C
(see test circuit, see Figure 15)
97
286
5.9
ns
nC
A
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STD5N20L
4/10
Figure 3: Safe Operating Area
Figure 4: Output Characteristics
Figure 5: Transconductance
Figure 6: Thermal Impedance
Figure 7: Transfer Characteristics
Figure 8: Static Drain-source On Resistance
Vns (V) ‘2 Vnttm (mm M 0.9 0.8 0.7 0.5 Vsn< v)="" 1.00="" 0.90="" 0.50="" 0.70="" 0.60="" 0.50="" 750="" 50="" 5="" i00="" 4="" am="" 350="" t="" 6="" “(06)="" m="" 570="" i50="" mt)="" w21="" m="" 5="" isn(a)="" wmsu="" cw)="" 500="" 400="" 200="" c="" o="" ‘="" 0="" 20="" so="" 40="" v.50!)="" my="" 330="" rm(dn)="" (warm)="" 2.5="" 2.0="" 1.5="" to="" 0.5="" —50="" 0="" 50="" i00="" 150m?="">
5/10
STD5N20L
Figure 9: Gate Charge vs Gate-source Voltage
Figure 10: Normalized Gate Thereshold Volt-
age vs Temperature
Figure 11: Source-Drain Diode Forward Char-
acteristics
Figure 12: Capacitance Variations
Figure 13: Normalized On Resistance vs Tem-
perature
.1 l _ _ 250 A A A J FAST :3 L: now am. DW 2 *a a a ' n 5 RG 5 swmn
STD5N20L
6/10
Figure 14: Switching Times Test Circuit For
Resistive Load
Figure 15: Test Circuit For Inductive Load
Switching and Diode Recovery Times
Figure 16: Gate Charge Test Circuit
CZ A1 0.50 MIN. FLAT ZDNE A2 11/2
7/10
STD5N20L
DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 2.20 2.40 0.087 0.094
A1 0.90 1.10 0.035 0.043
A2 0.03 0.23 0.001 0.009
B 0.64 0.90 0.025 0.035
B2 5.20 5.40 0.204 0.213
C 0.45 0.60 0.018 0.024
C2 0.48 0.60 0.019 0.024
D 6.00 6.20 0.236 0.244
E 6.40 6.60 0.252 0.260
G 4.40 4.60 0.173 0.181
H 9.35 10.10 0.368 0.398
L2 0.8 0.031
L4 0.60 1.00 0.024 0.039
V2 0o8o0o0o
P032P_B
TO-252 (DPAK) MECHANICAL DATA
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STD5N20L
8/10
TAPE AND REEL SHIPMENT (suffix ”T4”)*
TUBE SHIPMENT (no suffix)*
DPAK FOOTPRINT
* on sales type
DIM. mm inch
MIN. MAX. MIN. MAX.
A 330 12.992
B1.5 0.059
C 12.8 13.2 0.504 0.520
D20.2 0.795
G 16.4 18.4 0.645 0.724
N50 1.968
T 22.4 0.881
BASE QTY BULK QTY
2500 2500
REEL MECHANICAL DATA
DIM. mm inch
MIN. MAX. MIN. MAX.
A0 6.8 7 0.267 0.275
B0 10.4 10.6 0.409 0.417
B1 12.1 0.476
D1.5 1.6 0.059 0.063
D1 1.5 0.059
E1.65 1.85 0.065 0.073
F 7.4 7.6 0.291 0.299
K0 2.55 2.75 0.100 0.108
P0 3.9 4.1 0.153 0.161
P1 7.9 8.1 0.311 0.319
P2 1.9 2.1 0.075 0.082
R40 1.574
W 15.7 16.3 0.618 0.641
TAPE MECHANICAL DATA
All dimensions
are in millimeters
All dimensions are in millimeters
9/10
STD5N20L
Table 8: Revision History
Date Revision Description of Changes
08-June-2004 2 New Stylesheet. Datasheet according to PCN DSG-TRA/04/532
20-Sep-2004 3 Changes on Table 3, and on Figure 3.
STD5N20L
10/10
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