ADC1115S125 Datasheet by NXP USA Inc.

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1. General description
The ADC1115S125 is a single channel 11-bit Analog-to-Digital Converter (ADC) optimized
for high dynamic performance and low power consumption at sample rates up to
125 Msps. Pipelined architecture and output error correction ensure the ADC1115S125 is
accurate enough to guarantee zero missing codes over the entire operating range.
Supplied from a single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in
CMOS mode, because of a separate digital output supply.
The ADC1115S125 supports the Low Voltage Differential Signalling (LVDS) Double Data
Rate (DDR) output standard. An integrated Serial Peripheral Interface (SPI) allows the
user to easily configure the ADC.
The device also includes a SPI programmable full-scale to allow flexible input voltage
range from 1 V to 2 V (peak-to-peak). With excellent dynamic performance from the
baseband to input frequencies of 170 MHz or more, the ADC1115S125 is ideal for use in
communications, imaging and medical applications - especially in high Intermediate
Frequency (IF) applications because of the integrated input buffer. The input buffer
ensures that the input impedance remains constant and low and the performance
consistent over a wide frequency range.
2. Features and benefits
ADC1115S125
Single 11-bit ADC; 125 Msps with input buffer; CMOS or LVDS
DDR digital outputs
Rev. 2 — 17 December 2010 Product data sheet
SNR, 66.5 dBFS; SFDR, 86 dBc Input bandwidth, 600 MHz
Sample rate up to 125 Msps Power dissipation, 840 mW including
analog input buffer
11-bit pipelined ADC core Serial Peripheral Interface (SPI)
Clock input divided by 2 for less jitter
contribution
Duty cycle stabilizer
Integrated input buffer Fast OuT-of-Range (OTR) detection
Flexible input voltage range: 1 V (p-p) to
2 V (p-p)
Offset binary, two’s complement, gray
code
CMOS or LVDS DDR digital outputs Power-down mode and Sleep mode
Pin compatible with the ADC1415S
series, the ADC1215S series and the
ADC1015S series
HVQFN40 package
ADC1115S125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 2 — 17 December 2010 2 of 38
NXP Semiconductors ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
3. Applications
4. Ordering information
5. Block diagram
Wireless and wired broadband
communications
Spectral analysis
Portable instrumentation Ultrasound equipment
Imaging systems Software defined radio
Digital predistortion loop, power
amplifier linearization
Table 1. Ordering information
Type number fs (Msps) Package
Name Description Version
ADC1115S125HN/C1 125 HVQFN40 plastic thermal enhanced very thin quad flat package;
no leads; 40 terminals; body 6 ×6×0.85 mm SOT618-6
Fig 1. Block diagram
ADC1115S
SPI
OUTPUT
DRIVERS
OUTPUT
DRIVERS
SYSTEM
REFERENCE AND
POWER
MANAGEMENT
ERROR
CORRECTION AND
DIGITAL
PROCESSING
ADC CORE
11-BIT
PIPELINED
S/H
INPUT
STAGE
INP
OTR
SDIO/ODS
SCLK/DFS
PWD
REFT
CMOS:
D10 to D0
or
LVDS DDR:
D9_D10_P
to D0_D1_P
D9_D10_M
to D0_D1_M
INM
CLOCK INPUT
STAGE AND DUTY
CYCLE CONTROL
REFB
CLKM
CLKP
SENSE
VREF
VCM
005aaa14
6
CS
OE
INPUT
BUFFER
CMOS:
DAV
or
LVDS DDR:
DAVP
DAVM
:EEQQEEQEEQ UUUUUUUUUU flflflflflfiflflfifl 3333333333 :EEEEEEEEEE UUUUUUUUUU flflflflflflflflflfl 3333333333 Type,
ADC1115S125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 2 — 17 December 2010 3 of 38
NXP Semiconductors ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
6. Pinning information
6.1 Pinning
6.2 Pin description
Fig 2. Pin configuration with CMOS digital outputs
selected Fig 3. Pin configuration with LVDS/DDR digital
outputs selected
ADC1115S
HVQFN40
D6
D5
D4
D3
D2
D1
D0
n.c.
n.c.
n.c.
VDDA3V
INP
INM
AGND
VDDA5V
VCM
AGND
REFT
REFB
VDDA3V
CLKP
CLKM
DEC
PWD
D10
D9
D8
D7
VREF
SENSE
SDIO/ODS
SCLK/DFS
OTR
OGND
VDDO
n.c.
DAV
10 21
9 22
8 23
7 24
6 25
5 26
4 27
3 28
2 29
1 30
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
AGND
terminal 1
index area
Transparent top view
005aaa14
7
OE
CS
ADC1115S
HVQFN40
D5_D6_M
D5_D6_P
D3_D4_M
D3_D4_P
D1_D2_M
D1_D2_P
LOW_D0_M
LOW_D0_P
n.c.
n.c.
VDDA3V
INP
INM
AGND
VDDA5V
VCM
AGND
REFT
REFB
VDDA3V
CLKP
CLKM
DEC
PWD
D9_D10_M
D9_D10_P
D7_D8_M
D7_D8_P
VREF
SENSE
SDIO/ODS
SCLK/DFS
OTR
OGND
VDDO
n.c.
DAV
10 21
9 22
8 23
7 24
6 25
5 26
4 27
3 28
2 29
1 30
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
AGND
terminal 1
index area
Transparent top view
005aaa148
OE
CS
Table 2. Pin description (CMOS digital outputs)
Symbol Pin Type [1] Description
REFB 1 O bottom reference
REFT 2 O top reference
AGND 3 G analog ground
VCM 4 O common-mode output voltage
VDDA5V 5 P analog power supply 5 V
AGND 6 G analog ground
INM 7 I complementary analog input
INP 8 I analog input
AGND 9 G analog ground
VDDA3V 10 P analog power supply 3 V
VDDA3V 11 P analog power supply 3 V
CLKP 12 I clock input
CLKM 13 I complementary clock input
DEC 14 O regulator decoupling node
OE 15 I output enable, active LOW
PWD 16 I power down, active HIGH
Type,
ADC1115S125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 2 — 17 December 2010 4 of 38
NXP Semiconductors ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
[1] P: power supply; G: ground; I: input; O: output; I/O: input/output.
D10 17 O data output bit 10 (Most Significant Bit (MSB))
D9 18 O data output bit 9
D8 19 O data output bit 8
D7 20 O data output bit 7
D6 21 O data output bit 6
D5 22 O data output bit 5
D4 23 O data output bit 4
D3 24 O data output bit 3
D2 25 O data output bit 2
D1 26 O data output bit 1
D0 27 O data output bit 0 (Least Significant Bit (LSB))
n.c. 28 - not connected
n.c. 29 - not connected
n.c. 30 - not connected
DAV 31 O data valid output clock
n.c. 32 - not connected
VDDO 33 P output power supply
OGND 34 G output ground
OTR 35 O out of range
SCLK/DFS 36 I SPI clock / data format select
SDIO/ODS 37 I/O SPI data IO / output data standard
CS 38 I SPI chip select
SENSE 39 I reference programming pin
VREF 40 I/O voltage reference input/output
Table 3. Pin description (LVDS/DDR) digital outputs)
Symbol Pin[1] Type [2] Description
D9_D10_M 17 O differential output data D9 and D10 multiplexed, complement
D9_D10_P 18 O differential output data D9 and D10 multiplexed, true
D7_D8_M 19 O differential output data D7 and D8 multiplexed, complement
D7_D8_P 20 O differential output data D7 and D8 multiplexed, true
D5_D6_M 21 O differential output data D5 and D6 multiplexed, complement
D5_D6_P 22 O differential output data D5 and D6 multiplexed, true
D3_D4_M 23 O differential output data D3 and D4 multiplexed, complement
D3_D4_P 24 O differential output data D3 and D4 multiplexed, true
D1_D2_M 25 O differential output data D1 and D2 multiplexed, complement
D1_D2_P 26 O differential output data D1 and D2 multiplexed, true
LOW_D0_M 27 O differential output data D0 multiplexed, complement
LOW_D0_P 28 O differential output data D0 multiplexed, true
n.c. 29 - not connected
Table 2. Pin description (CMOS digital outputs) …continued
Symbol Pin Type [1] Description
cteriskics,
ADC1115S125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 2 — 17 December 2010 5 of 38
NXP Semiconductors ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
[1] Pins 1 to 16 and pins 33 to 40 are the same for both CMOS and LVDS DDR outputs (see Table 2)
[2] P: power supply; G: ground; I: input; O: output; I/O: input/output.
7. Limiting values
8. Thermal characteristics
[1] Value for six layers board in still air with a minimum of 25 thermal vias.
9. Static characteristics
n.c. 30 - not connected
DAVM 31 O data valid output clock, complement
DAVP 32 O data valid output clock, true
Table 3. Pin description …continued (LVDS/DDR) digital outputs)
Symbol Pin[1] Type [2] Description
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VOoutput voltage pins D10 to D0 or
pins D9_D10_P to D0_D1_P and
pins D9_D10_M to D0_D1_M
0.4 +3.9 V
VDDA(3V) analog supply voltage
3V on pin VDDA3V 0.5 +4.6 V
VDDA(5V) analog supply voltage
5V on pin VDDA5V 0.5 +6.0 V
VDDO output supply voltage 0.5 +4.6 V
Tstg storage temperature 55 +125 °C
Tamb ambient temperature 40 +85 °C
Tjjunction temperature - 125 °C
Table 5. Thermal characteristics
Symbol Parameter Conditions Typ Unit
Rth(j-a) thermal resistance from junction to ambient [1] 30.5 K/W
Rth(j-c) thermal resistance from junction to case [1] 13.3 K/W
Table 6. Static characteristics[1]
Symbol Parameter Conditions Min Typ Max Unit
Supplies
VDDA(5V) analog supply voltage 5 V 4.75 5.0 5.25 V
VDDA(3V) analog supply voltage 3 V 2.85 3.0 3.4 V
VDDO output supply voltage CMOS mode 1.65 1.8 3.6 V
LVDS DDR mode 2.85 3.0 3.6 V
IDDA(5V) analog supply current 5 V fclk =125Msps;
fi=70MHz -46-mA
ADC1115S125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 2 — 17 December 2010 6 of 38
NXP Semiconductors ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
IDDA(3V) analog supply current 3 V fclk =125Msps;
fi=70MHz -205-mA
IDDO output supply current CMOS mode;
fclk =125Msps;
fi=70MHz
-11-mA
LVDS DDR mode:
fclk =125Msps;
fi=70MHz
-39-mA
P power dissipation analog supply only - 840 - mW
Power-down mode - 2 - mW
Standby mode - 40 - mW
Clock inputs: pins CLKP and CLKM
LVPECL
Vi(clk)dif differential clock input voltage peak-to-peak - 1.6 - V
SINE wave
Vi(clk)dif differential clock input voltage peak - ±3.0 - V
LVCMOS
VIL LOW-level input voltage - - 0.3VDDA(3V) V
VIH HIGH-level input voltage 0.7VDDA(3V) --V
Logic inputs: pins PWD and OE
VIL LOW-level input voltage 0 - 0.8 V
VIH HIGH-level input voltage 2 - VDDA(3V) V
IIL LOW-level input current - 55 - μA
IIH HIGH-level input current - 65 - μA
Serial peripheral interface: pins CS, SDIO/ODS, SCLK/DFS
VIL LOW-level input voltage 0 - 0.3VDDA(3V) V
VIH HIGH-level input voltage 0.7VDDA(3V) -V
DDA(3V) V
IIL LOW-level input current 10 - +10 μA
IIH HIGH-level input current 50 - +50 μA
CIinput capacitance - 4 - pF
Digital outputs, CMOS mode: pins D10 to D0, OTR, DAV
Output levels, VDDO =3V
VOL LOW-level output voltage OGND - 0.2VDDO V
VOH HIGH-level output voltage 0.8VDDO -V
DDO V
COoutput capacitance high impedance;
OE =HIGH -3-pF
Output levels, VDDO =1.8V
VOL LOW-level output voltage OGND - 0.2VDDO V
VOH HIGH-level output voltage 0.8VDDO -V
DDO V
Digital outputs, LVDS mode: pins D9_D10_P to D0_D1_P, D9_D10_M to D0_D1_M, DAVP and DAVM
Output levels, VDDO = 3 V only, Rload =100Ω
VO(offset) output offset voltage output buffer current
set to 3.5 mA -1.2-V
Table 6. Static characteristics[1] …continued
Symbol Parameter Conditions Min Typ Max Unit
merislics,
ADC1115S125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 2 — 17 December 2010 7 of 38
NXP Semiconductors ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
[1] Typical values measured at VDDA(3V) =3V, V
DDO = 1.8 V, VDDA(5V) =5V; T
amb =25°C and CL= 5 pF; minimum and maximum values
are across the full temperature range Tamb =40 °C to +85 °C at VDDA(3V) =3V, V
DDO = 1.8 V, VDDA(5V) =5V, V
INP VINM =1 dBFS;
internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified.
VO(dif) differential output voltage output buffer current
set to 3.5 mA -350-mV
COoutput capacitance - 3 - pF
Analog inputs: pins INP and INM
IIinput current 5- +5μA
RIinput resistance - 550 - Ω
CIinput capacitance - 1.3 - pF
VI(cm) common-mode input voltage VINP =V
INM 0.9 1.5 2 V
Biinput bandwidth - 600 - MHz
VI(dif) differential input voltage peak-to-peak 1 2 V
Common mode output voltage: pin VCM
VO(cm) common-mode output voltage - 0.5VDDA(3V) -V
IO(cm) common-mode output current - 4 - mA
I/O reference voltage: pin VREF
VVREF voltage on pin VREF output - 0.5 to 1 - V
input 0.5 - 1 V
Accuracy
INL integral non-linearity - ±0.2 - LSB
DNL differential non-linearity guaranteed no
missing codes -±0.1 - LSB
Eoffset offset error - ±2- mV
EGgain error - ±0.5 - %FS
Supply
PSRR power supply rejection ratio 200 mV (p-p) on
VDDA(3V)
-54 - dBc
Table 6. Static characteristics[1] …continued
Symbol Parameter Conditions Min Typ Max Unit
ADC1115S125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 2 — 17 December 2010 8 of 38
NXP Semiconductors ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
10. Dynamic characteristics
10.1 Dynamic characteristics
[1] Typical values measured at VDDA(3V) =3V, V
DDO = 1.8 V, VDDA(5V) =5V; T
amb =25°C and CL= 5 pF; minimum and maximum values
are across the full temperature range Tamb =40 °C to +85 °C at VDDA(3V) =3V, V
DDO = 1.8 V, VDDA(5V) =5V, V
INP VINM =1 dBFS;
internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified.
Table 7. Dynamic characteristics[1]
Symbol Parameter Conditions ADC1115S125 Unit
Min Typ Max
Analog signal processing
α2H second harmonic level fi=3MHz - 88 - dBc
fi=30MHz - 87 - dBc
fi=70MHz - 85 - dBc
fi=170MHz - 83 - dBc
α3H third harmonic level fi=3MHz - 87 - dBc
fi=30MHz - 86 - dBc
fi=70MHz - 84 - dBc
fi=170MHz - 82 - dBc
THD total harmonic distortion fi=3MHz - 84 - dBc
fi=30MHz - 83 - dBc
fi=70MHz - 81 - dBc
fi=170MHz - 79 - dBc
ENOB effective number of bits fi=3MHz - 10.7 - bits
fi= 30 MHz - 10.7 - bits
fi= 70 MHz - 10.7 - bits
fi=170MHz - 10.6 - bits
SNR signal-to-noise ratio fi=3MHz - 66.2 - dBFS
fi= 30 MHz - 66.2 - dBFS
fi= 70 MHz - 66.0 - dBFS
fi=170MHz - 65.8 - dBFS
SFDR spurious-free dynamic
range fi=3MHz - 87 - dBc
fi=30MHz - 86 - dBc
fi=70MHz - 84 - dBc
fi=170MHz - 82 - dBc
IMD Intermodulation distortion fi=3MHz - 89 - dBc
fi=30MHz - 88 - dBc
fi=70MHz - 86 - dBc
fi=170MHz - 84 - dBc
lerislicL
ADC1115S125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 2 — 17 December 2010 9 of 38
NXP Semiconductors ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
10.2 Clock and digital output timing
[1] Typical values measured at VDDA(3V) =3V, V
DDO = 1.8 V, VDDA(5V) =5V; T
amb =25°C and CL= 5 pF; minimum and maximum values
are across the full temperature range Tamb =40 °C to +85 °C at VDDA(3V) =3V, V
DDO = 1.8 V, VDDA(5V) =5V, V
INP VINM =1 dBFS;
internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified.
[2] Measured between 20 % to 80 % of VDDO.
[3] Rise time measured from 50 mV to +50 mV; fall time measured from +50 mV to 50 mV.
Table 8. Clock and digital output timing characteristics[1]
Symbol Parameter Conditions Min Typ Max Unit
Clock timing input: pins CLKP and CLKM
fclk clock frequency 100 - 125 MHz
tlat(data) data latency time - 13.5 - clock cycles
δclk clock duty cycle DCS_EN = 1 30 50 70 %
DCS_EN = 0 45 50 55 %
td(s) sampling delay time - 0.8 - ns
twake wake-up time - 76 - μs
CMOS Mode timing output: pins D10 to D0 and DAV
tPD propagation delay DATA 8.2 9.7 11.3 ns
DAV - 3.4 - ns
tsu set-up time - 5.6 - ns
thhold time - 2.8 - ns
trrise time DATA [2] 0.39 - 2.4 ns
DAV 0.26 - 2.4 ns
tffall time DATA [2] 0.19 - 2.4 ns
LVDS DDR mode timing output: pins D9_D10_P to D0_D1_P, D9_D10_M to D0_D1_M, DAVP and DAVM
tPD propagation delay DATA 2.2 4.0 6.6 ns
DAV - 2.2 - ns
tsu set-up time - 1.9 - ns
thhold time - 1.7 - ns
trrise time DATA [3] 0.5 - 5 ns
DAV 0.18 - 2.4 ns
tffall time DATA [3] 0.15 - 1.6 ns
ADC1115S125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 2 — 17 December 2010 10 of 38
NXP Semiconductors ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
Fig 4. CMOS mode timing
Fig 5. LDVS DDR mode timing
(N 12)
t
d(s)
t
clk
NN + 1
N + 2
t
clk
t
su
t
PD
t
h
t
PD
CLKP
CLKM
DATA
DAV
005aaa06
0
(N 11)(N 13)(N 14)
005aaa061
(N 14)
td(s)
tclk
NN + 1
N + 2
CLKP
CLKM
DAVP
DAVM
tsu thth
tsu
tPD
tPD
Dx_Dx + 1_P
Dx_Dx + 1_M
DxDx + 1 Dx + 1 Dx + 1 Dx + 1 Dx + 1
DxDxDx
Dx
(N 11)(N 12)(N 13)
tclk
’1? T AME; F7— )I’lllljiilllK
ADC1115S125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 2 — 17 December 2010 11 of 38
NXP Semiconductors ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
10.3 SPI timings
[1] Typical values measured at VDDA(3V) =3V, V
DDO = 1.8 V, VDDA(5V) =5V, T
amb =25°C and CL=5pF;
minimum and maximum values are across the full temperature range Tamb =40 °C to +85 °C at
VDDA =3V, V
DDO =1.8V.
Table 9. SPI timings characteristics[1]
Symbol Parameter Conditions Min Typ Max Unit
tw(SCLK) SCLK pulse width - 40 - ns
tw(SCLKH) SCLK HIGH pulse width - 16 - ns
tw(SCLKL) SCLK LOW pulse width - 16 - ns
tsu set-up time data to SCLK HIGH - 5 - ns
CS to SCLK HIGH - 5 - ns
thhold time data to SCLK HIGH - 2 - ns
CS to SCLK HIGH - 2 - ns
fclk(max) maximum clock frequency - 25 - MHz
Fig 6. SPI timing
tsu
SDIO
SCLK
R/W W1 W0 A12 A11 D2 D1 D0
tsu th
thtw(SCLK)
005aaa06
5
CS
tw(SCLKL)
tw(SCLKH)
ADC1115S125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 2 — 17 December 2010 12 of 38
NXP Semiconductors ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
10.4 Typical characteristics
T=25°C; VDD =3V; f
i= 170 MHz; fs= 125 Msps
(1) DCS on
(2) DCS off
T=25°C; VDD =3V; f
i= 170 MHz; fs= 125 Msps
(1) DCS on
(2) DCS off
Fig 7. Spurious-free dynamic range as a function of
duty cycle (δ)Fig 8. Signal-to-noise ratio as a function of duty
cycle (δ)
δ (%)
10 907030 50
001aam616
40
60
20
80
100
SFDR
(dBc)
0
(1)
(2)
δ (%)
10 907030 50
001aam615
40
20
60
80
SNR
(dBFS)
0
(1)
(2)
(1) Tamb =40 °C, typical supply voltages
(2) Tamb =+25°C, typical supply voltages
(3) Tamb =+90°C, typical supply voltages
(1) Tamb =40 °C, typical supply voltages
(2) Tamb =+25°C, /typical supply voltages
(3) Tamb =+90°C, typical supply voltages
Fig 9. Spurious-free dynamic range as a function of
duty cycle (δ)Fig 10. Signal-to-noise ratio as a function of duty
cycle (δ)
δ (%)
10 907030 50
001aam617
84
88
92
SFDR
(dBc)
80
(1)
(2)
(3)
δ (%)
10 907030 50
001aam618
40
60
80
SNR
(dBFS)
20
(1)
(2)
(3)
Figure 13
ADC1115S125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 2 — 17 December 2010 13 of 38
NXP Semiconductors ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
11. Application information
11.1 Device control
The ADC1115S125 can be controlled via the Serial Peripheral Interface (SPI control
mode) or directly via the I/O pins (Pin control mode).
11.1.1 SPI and Pin control modes
The device enters Pin control mode at power-up, and remains in this mode as long as pin
CS is held HIGH. In Pin control mode, the SPI pins SDIO, CS and SCLK are used as
static control pins.
SPI control mode is enabled by forcing pin CS LOW. Once SPI control mode has been
enabled, the device remains in this mode. The transition from Pin control mode to SPI
control mode is illustrated in Figure 13.
When the device enters SPI control mode, the output data standard and data format are
determined by the level on pin SDIO as soon as a transition is triggered by a falling edge
on CS.
Fig 11. Spurious-free dynamic range as a function of
common-mode input voltage (Vi(cm))Fig 12. Signal-to-noise ratio as a function of
common-mode input voltage (Vi(cm))
VI(cm) (V)
3.52.50.5 3.02.01.00 1.5
001aam659
78
74
86
82
90
SFDR
(dBc)
70
VI(cm) (V)
3.52.50.5 3.02.01.00 1.5
001aam660
69
67
73
71
75
SNR
(dBFS)
65
Fig 13. Control mode selection
R/W
SPI control mode
Pin control mode
Data format
offset binary
Data format
two's complement
LVDS DDR
SDIO/ODS
SCLK/DFS
W1 W0 A12
005aaa03
9
CMOS
CS
Table 19 n Table 10 Table 23 e Table 23 Section 11.3 Table 21 Figure 14
ADC1115S125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 2 — 17 December 2010 14 of 38
NXP Semiconductors ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
11.1.2 Operating mode selection
The active ADC1115S125 operating mode (Power-up, Power-down or Sleep) can be
selected via the SPI interface (see Table 19) or using pins PWD and OE in Pin control
mode, as described in Table 10.
11.1.3 Selecting the output data standard
The output data standard (CMOS or LVDS DDR) can be selected via the SPI interface
(see Table 23) or using pin ODS in Pin control mode. LVDS DDR is selected when ODS is
HIGH, otherwise CMOS is selected.
11.1.4 Selecting the output data format
The output data format can be selected via the SPI interface (offset binary, two’s
complement or gray code; see Table 23) or using pin DFS in Pin control mode (offset
binary or two’s complement). Offset binary is selected when DFS is LOW. When DFS is
HIGH, two’s complement is selected.
11.2 Analog inputs
11.2.1 Input stage
The analog input of the ADC1115S125 supports a differential or a single-ended input
drive. Optimal performance is achieved using differential inputs. The ADC inputs are
internally biased and need to be decoupled.
The full-scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p)
via a programmable internal reference (see Section 11.3 and Table 21).
The equivalent circuit of the input buffer followed by the Sample and Hold (S/H) input
stage, including ElectroStatic Discharge (ESD) protection and circuit and package
parasitics, is shown in Figure 14.
Table 10. Operating mode selection via pin PWD and OE
Pin PWD Pin OE Operating mode Output high-Z
0 0 Power-up no
0 1 Power-up yes
1 0 Sleep yes
1 1 Power-down yes
1.1, ll, 1:, ll,
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Product data sheet Rev. 2 — 17 December 2010 15 of 38
NXP Semiconductors ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
The integrated input buffer offers the following advantages:
The kickback effect is avoided - the charge injection and glitches generated by the
S/H input stage are isolated from the input circuitry. So there’s no need for additional
filtering.
The input capacitance is very low and constant over a wide frequency range, which
makes the ADC1115S125 easy to drive.
The sample phase occurs when the internal clock (derived from the clock signal on pin
CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the
clock signal goes LOW, the stage enters the hold phase and the voltage information is
transmitted to the ADC core.
Fig 14. Input sampling circuit and input buffer
INP
package ESD parasitics
switch
Ron = 15 Ω
4 pF
4 pF
sampling
capacitor
sampling
capacitor
switch
Ron = 15 Ω
INM
8
7
internal
clock
internal
clock
INPUT
BUFFER
Figure 15 Figure 16 if I
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Product data sheet Rev. 2 — 17 December 2010 16 of 38
NXP Semiconductors ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
11.2.2 Transformer
The configuration of the transformer circuit is determined by the input frequency. The
configuration shown in Figure 15 would be suitable for a baseband application.
The configuration shown in Figure 16 is recommended for high frequency applications. In
both cases, the choice of transformer is a compromise between cost and performance.
Fig 15. Single transformer configuration suitable for baseband applications
Fig 16. Dual transformer configuration suitable for high intermediate frequency
application
005aaa10
8
100 nF
100 nF
100 nF
100 nF INP
INM
VCM
Analog
input
ADT1-1WT
100 nF
100 nF
50 Ω
005aaa10
9
100 nF
100 nF
100 nF
INP
INM
100 Ω
50 Ω
50 Ω
ADT1-1WTADT1-1WT
Analog
input
100 nF
100 nF
VCM
100 nF
Semiconductors 11-bit, 125 M System reference and Internal/external refere The ADC1115$125 has a s the ADC lullrscale. This ref and SENSE (programmabl |NTREF[2:O] when hit INTR Table 21 Figure 18 0 Figure 21 The equivalent reference c n Figure 17 by providing a voltage on p Figure 20 I (( REFERENC> .L ' AMP i T I 4(( VREF EXL BUFFER EX SENSE SELECTION LOGIC ((7 Fig 17. Reference equivalent schematic If bit INTREF_EN is set to logic 0, the ref externally as detailed in Table 11. Table 11. Reference selection Selection SFI bit SENSE INTHEF_EN internal 0 AGND (Figure 18) internal 0 (Figure 19) external 0 (Figure 20) v, internal via SPI 1 (Figure 21) [1] The volmge an pin VREF is doubled Aucmssrzs All ("mm we.” mum Producl data sheel Rev. 2 — 17 D
ADC1115S125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 2 — 17 December 2010 17 of 38
NXP Semiconductors ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
11.3 System reference and power management
11.3.1 Internal/external references
The ADC1115S125 has a stable and accurate built-in internal reference voltage to adjust
the ADC full-scale. This reference voltage can be set internally via SPI or with pins VREF
and SENSE (programmable in 1 dB steps between 0 dB and 6 dB via control bits
INTREF[2:0] when bit INTREF_EN = logic 1; see Table 21). See Figure 18 to Figure 21.
The equivalent reference circuit is shown in Figure 17. External reference is also possible
by providing a voltage on pin VREF as described in Figure 20.
If bit INTREF_EN is set to logic 0, the reference voltage is determined either internally or
externally as detailed in Table 11.
[1] The voltage on pin VREF is doubled internally to generate the internal reference voltage.
Fig 17. Reference equivalent schematic
Table 11. Reference selection
Selection SPI bit
INTREF_EN SENSE pin VREF pin Full-scale (p-p)
internal
(Figure 18)0 AGND 330 pF capacitor to AGND 2 V
internal
(Figure 19)0 pin VREF connected to pin SENSE and
via a 330 pF capacitor to AGND 1 V
external
(Figure 20)0V
DDA(3V) external voltage between
0.5 V and 1 V[1] 1 V to 2 V
internal via SPI
(Figure 21)1 pin VREF connected to pin SENSE and
via 330 pF capacitor to AGND 1 V to 2 V
EXT_ref
EXT_ref
005aaa164
REFAT/
REFBT
REFAB/
REFBB
SENSE
VREF
SELECTION
LOGIC
BANDGAP
REFERENCE
ADC CORE
BUFFER
REFERENCE
AMP
Figure 18 Figure 21 If i T <§1 i="" ddaj:="" fig="" 20.="" exlernal="" reference,="" 1="" v="" (p-p)="" lo="" 2="" v="" full-scale="" v="" unsnuna="" 11.3.2="" programmable="" fu="" the="" lulliscale="" is="" pro="" (see="" table="" 12).="" 11.3.3="" common-mode="" o="" a="" 0.1="" “f="" filter="" capac="" 11.3.4="" biasing="" the="" commonimode="" buffer="" bias="" current="" 0="" (see="" table="" 22).="" ancmssus="" am.“="" producl="" data="" sheel="">
ADC1115S125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 2 — 17 December 2010 18 of 38
NXP Semiconductors ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
Figure 18 to Figure 21 illustrate how to connect the SENSE and VREF pins to select the
required reference voltage source.
11.3.2 Programmable full-scale
The full-scale is programmable between 1 V (peak-to-peak) to 2 V (peak-to-peak)
(see Table 12).
11.3.3 Common-mode output voltage (VO(cm))
A 0.1 μF filter capacitor should be connected between pin VCM and ground.
11.3.4 Biasing
The common-mode input voltage (VI(cm)) on pins INP and INM is set internally. The input
buffer bias current can be set to one of three levels (high, medium or low) via the SPI
(see Table 22).
Fig 18. Internal reference, 2 V (p-p) full scale Fig 19. Internal reference, 1 V (p-p) full scale
Fig 20. External reference, 1 V (p-p) to 2 V (p-p)
full-scale Fig 21. Internal reference via SPI, 1 V (p-p) to 2 V (p-p)
full-scale
330 pF
VREF
SENSE
005aaa11
6
REFERENCE
EQUIVALENT
SCHEMATIC
330
pF
005aaa11
7
VREF
SENSE
REFERENCE
EQUIVALENT
SCHEMATIC
0.1 μF
VDDA
V
005aaa11
9
VREF
SENSE
REFERENCE
EQUIVALENT
SCHEMATIC
REFERENCE
EQUIVALENT
SCHEMATIC
330 pF
005aaa11
8
VREF
SENSE
Table 12. Reference SPI gain control
INTREF Gain Full-scale (p-p)
000 0 dB 2 V
001 1dB 1.78V
010 2dB 1.59V
011 3dB 1.42V
100 4dB 1.26V
101 5dB 1.12V
110 6dB 1V
111 reserved x
4H7 W—lli Iii 4H7 4H7 '7 4H7 4H7
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Product data sheet Rev. 2 — 17 December 2010 19 of 38
NXP Semiconductors ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
11.4 Clock input
11.4.1 Drive modes
The ADC1115S can be driven differentially (LVPECL). It can also be driven by a
single-ended Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS) signal
connected to pin CLKP (pin CLKM should be connected to ground via a capacitor) or
CLKM (pin CLKP should be connected to ground via a capacitor).
a. Rising edge LVCMOS b. Falling edge LVCMOS
Fig 22. LVCMOS single-ended clock input
a. Sine clock input b. Sine clock input (with transformer)
c. LVPECL clock input1
Fig 23. Differential clock input
LVCMOS
clock input
CLKP
CLKM
005aaa17
4
005aaa05
3
LVCMOS
clock input
CLKP
CLKM
Sine
clock input
CLKP
CLKM
005aaa17
3
Sine
clock input
CLKP
CLKM
005aaa05
4
LVPECL
clock input
005aaa17
2
CLKP
CLKM
11.4.3 11.4.4 Aucllissizs Product data sheet Figure 24 iii—He wH>H>H 1H>H>H iii—He iii—IF 505335555 vcmmk, = commcnrmode vollage oi the diiterenliai inpul slage. Fig 24. Equivalent input circuit Singlerended or differential clock inputs can be selected via the SPI interface (se Tabie 20). ll singlerended is enabied, the input pin (CLKM or CLKP) is seiected v bit SE_SEL. If singlerended is impiemented without setting bit SE_SEL to the appropriate vai unused pin should be connected to ground via a capacitor. Duty cycle stabilizer The duty cycle stabilizer can improve the overall pedormances of the ADC by compensating the duty cycle oi the input ciock signai. When the duty cycle stabi active (bit DCS_EN : iogic 1; see Table 20), the circuit can handle signals with d cycies of between 30 % and 7D % (typical). When the duty cycle stabilizer is dis (DCS_EN = logic 0), the input ciock signal should have a duty cycle of between 55%. Clock input divider The ADC1115$125 contains an input ciock divider that divides the incoming cloc lactor of 2 (when bit CLKDIV : iogic 1; see Table 20). This feature allows the us deiiver a higher ciock frequency with better jitter performance, leading to a bette result once acquisition has been perlormed. Aii mtnrmiimn Diwifluflm 1m; flncumenl is guhltclluilgii mime“ meP a V min Rev. 2 — l7 December 20")
ADC1115S125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 2 — 17 December 2010 20 of 38
NXP Semiconductors ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
11.4.2 Equivalent input circuit
The equivalent circuit of the input clock buffer is shown in Figure 24. The common-mode
voltage of the differential input stage is set via internal 5 kΩ resistors.
Single-ended or differential clock inputs can be selected via the SPI interface (see
Table 20). If single-ended is enabled, the input pin (CLKM or CLKP) is selected via control
bit SE_SEL.
If single-ended is implemented without setting bit SE_SEL to the appropriate value, the
unused pin should be connected to ground via a capacitor.
11.4.3 Duty cycle stabilizer
The duty cycle stabilizer can improve the overall performances of the ADC by
compensating the duty cycle of the input clock signal. When the duty cycle stabilizer is
active (bit DCS_EN = logic 1; see Table 20), the circuit can handle signals with duty
cycles of between 30 % and 70 % (typical). When the duty cycle stabilizer is disabled
(DCS_EN = logic 0), the input clock signal should have a duty cycle of between 45% and
55%.
11.4.4 Clock input divider
The ADC1115S125 contains an input clock divider that divides the incoming clock by a
factor of 2 (when bit CLKDIV = logic 1; see Table 20). This feature allows the user to
deliver a higher clock frequency with better jitter performance, leading to a better SNR
result once acquisition has been performed.
Vcm(clk) = common-mode voltage of the differential input stage.
Fig 24. Equivalent input circuit
CLKP
CLKM
005aaa05
6
Package ESD Parasitics
5 kΩ5 kΩ
Vcm(clk)
SE_SEL SE_SEL
Table 23 Figure25 VDD Parasmcs ESD Package E $ E i f i ”X t I T I OGN Fig 25. CMOS digital output buffer 0055:3057 The output resistance is 50 S) and is the combination oi the an internal resisto equivalent output resistance cl the butler. There is no need lor an external da resistor. The drive strength of both data and DAV buffers can be programmed n urder to adjust the rise and fall times ol the output digital signals (see Table 30
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Product data sheet Rev. 2 — 17 December 2010 21 of 38
NXP Semiconductors ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
11.5 Digital outputs
11.5.1 Digital output buffers: CMOS mode
The digital output buffers can be configured as CMOS by setting bit LVDS_CMOS to
logic 0 (see Table 23).
Each digital output has a dedicated output buffer. The equivalent circuit of the CMOS
digital output buffer is shown in Figure 25. The buffer is powered by a separate
OGND/VDDO to ensure 1.8 V to 3.3 V compatibility and is isolated from the ADC core.
Each buffer can be loaded by a maximum of 10 pF.
The output resistance is 50 Ω and is the combination of the an internal resistor and the
equivalent output resistance of the buffer. There is no need for an external damping
resistor. The drive strength of both data and DAV buffers can be programmed via the SPI
in order to adjust the rise and fall times of the output digital signals (see Table 30):
Fig 25. CMOS digital output buffer
VDDO
ESD PackageParasitics
OGND
Dx
005aaa057
50 Ω
LOGIC
DRIVER
Table 23 (Figure 26 Tab‘e 32 Figure 27 Table 31
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Product data sheet Rev. 2 — 17 December 2010 22 of 38
NXP Semiconductors ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
11.5.2 Digital output buffers: LVDS DDR mode
The digital output buffers can be configured as LVDS DDR by setting bit LVDS_CMOS to
logic 1 (see Table 23).
Each output should be terminated externally with a 100 Ω resistor (typical) at the receiver
side (Figure 26) or internally via SPI control bits LVDS_INT_TER[2:0] (see Figure 27 and
Table 32).
The default LVDS DDR output buffer current is set to 3.5 mA. It can be programmed via
the SPI (bits DAVI[1:0] and DATAI[1:0]; see Table 31) in order to adjust the output logic
voltage levels.
Fig 26. LVDS DDR digital output buffer - externally terminated
Fig 27. LVDS DDR digital output buffer - internally terminated
Table 13. LVDS DDR output register 2
LVDS_INT_TER[2:0] Resistor value (Ω)
000 no internal termination
001 300
010 180
011 110
100 150
VCCO
3.5 mA
typ
D
n
P/D
n + 1
P
D
n
M/D
n + 1
M
OGND
100 Ω
005aaa05
8
+
+
RECEIVER
VCCO
OGND
005aaa05
9
D
x
P/D
x
+ 1
P
D
x
M/D
x + 1
M
100 Ω
3.5 mA
typ
+
+
RECEIVER
Figure 4 Figure 5 Table 29 Table 25 Table 26 e Table 27 Table 28
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Product data sheet Rev. 2 — 17 December 2010 23 of 38
NXP Semiconductors ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
11.5.3 DAta Valid (DAV) output clock
A data valid output clock signal (DAV) is provided that can be used to capture the data
delivered by the ADC1115S125. Detailed timing diagrams for CMOS and LVDS DDR
modes are provided in Figure 4 and Figure 5 respectively.
11.5.4 Out-of-Range (OTR)
An out-of-range signal is provided on pin OTR. The latency of OTR is fourteen clock
cycles. The OTR response can be speeded up by enabling Fast OTR (bit
FASTOTR = logic 1; see Table 29). In this mode, the latency of OTR is reduced to only
four clock cycles. The Fast OTR detection threshold (below full-scale) can be
programmed via bits FASTOTR_DET[2:0].
11.5.5 Digital offset
By default, the ADC1115S125 delivers output code that corresponds to the analog input.
However it is possible to add a digital offset to the output code via the SPI (bits
DIG_OFFSET[5:0]; see Table 25).
11.5.6 Test patterns
For test purposes, the ADC1115S125 can be configured to transmit one of a number of
predefined test patterns (via bits TESTPAT_SEL[2:0]; see Table 26). A custom test pattern
can be defined by the user (TESTPAT_USER; see Table 27 and Table 28) and is selected
when TESTPAT_SEL[2:0] = 101. The selected test pattern is transmitted regardless of the
analog input.
101 100
110 81
111 60
Table 13. LVDS DDR output register 2 …continued
LVDS_INT_TER[2:0] Resistor value (Ω)
Table 14. Fast OTR register
FASTOTR_DET[2:0] Detection level (dB)
000 20.56
001 16.12
010 11.02
011 7.82
100 5.49
101 3.66
110 2.14
111 0.86
Table 17 1, W0,
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Product data sheet Rev. 2 — 17 December 2010 24 of 38
NXP Semiconductors ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
11.5.7 Output codes versus input voltage
11.6 Serial Peripheral Interface (SPI)
11.6.1 Register description
The ADC1115S125 serial interface is a synchronous serial communications port that
allows easy interfacing with many commonly-used microprocessors. It provides access to
the registers that control the operation of the chip.
This interface is configured as a 3-wire type (SDIO as bidirectional pin)
Pin SCLK is the serial clock input and CS is the chip select pin.
Each read/write operation is initiated by a LOW level on CS. A minimum of three bytes is
transmitted (two instruction bytes and at least one data byte). The number of data bytes is
determined by the value of bits W1 and W2 (see Table 17).
[1] Bit R/W indicates whether it is a read (logic 1) or a write (logic 0) operation.
[2] Bits W1 and W0 indicate the number of bytes to be transferred after the instruction byte (see Table 17).
Table 15. Output codes
VINP VINM Offset binary Two’s complement OTR pin
< 1 000 0000 0000 100 0000 0000 1
1.0000000 000 0000 0000 100 0000 0000 0
0.9990234 000 0000 0001 100 0000 0001 0
0.9980469 000 0000 0010 100 0000 0010 0
0.9970703 000 0000 0011 100 0000 0011 0
0.996093 000 0000 0100 100 0000 0100 0
.... .... .... 0
0.0019531 011 1111 1110 111 1111 1110 0
0.0009766 011 1111 1111 111 1111 1111 0
0.0000000 100 0000 0000 000 0000 0000 0
+0.0009766 100 0000 0001 000 0000 0001 0
+0.0019531 100 0000 0010 000 0000 0010 0
.... .... .... 0
+0.9960938 111 1111 1011 011 1111 1011 0
+0.9970703 111 1111 1100 011 1111 1100 0
+0.9980469 111 1111 1101 011 1111 1101 0
+0.9990234 111 1111 1110 011 1111 1110 0
+1.0000000 111 1111 1111 011 1111 1111 0
> +1 111 1111 1111 011 1111 1111 1
Table 16. Instruction bytes for the SPI
MSB LSB
Bit 76543210
Description R/W[1] W1[2] W0[2] A12 A11 A10 A9 A8
A7 A6 A5 A4 A3 A2 A1 A0
Figure 29 Table 23 Table 23
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Product data sheet Rev. 2 — 17 December 2010 25 of 38
NXP Semiconductors ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
Bits A12 to A0 indicate the address of the register being accessed. In the case of a
multiple byte transfer, this address is the first register to be accessed. An address counter
is increased to access subsequent addresses.
The steps involved in a data transfer are as follows:
1. A falling edge on CS in combination with a rising edge on SCLK determine the start of
communications.
2. The first phase is the transfer of the 2-byte instruction.
3. The second phase is the transfer of the data which can vary in length but is always a
multiple of 8 bits. The MSB is always sent first (for instruction and data bytes).
4. A rising edge on CS indicates the end of data transmission.
11.6.2 Default modes at start-up
During circuit initialization, it does not matter which output data standard has been
selected. At power-up, the device enters Pin control mode.
A falling edge on CS triggers a transition to SPI control mode. When the ADC1115S125
enters SPI control mode, the output data standard (CMOS/LVDS DDR) is determined by
the level on pin SDIO (see Figure 29). Once in SPI control mode, the output data standard
can be changed via bit LVDS/CMOS in Table 23.
When the ADC1115S125 enters SPI control mode, the output data format (two’s
complement or offset binary) is determined by the level on pin SCLK (gray code can only
be selected via the SPI). Once in SPI control mode, the output data format can be
changed via bit DATA_FORMAT[1:0] in Table 23.
Table 17. Number of data bytes to be transferred after the instruction bytes
W1 W0 Number of bytes transmitted
001 byte
012 bytes
103 bytes
1 1 4 bytes or more
Fig 28. SPI mode timing
SCLK
SDIO R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D3 D2 D1 D0D0 D7 D6 D5 D4
Instruction bytes Register N (data) Register N + 1 (data)
005aaa06
2
CS
\ I
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Product data sheet Rev. 2 — 17 December 2010 26 of 38
NXP Semiconductors ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
Fig 29. Default mode at start-up: SCLK LOW = offset binary; SDIO HIGH = LVDS DDR
Fig 30. Default mode at start-up: SCLK HIGH = two’s complement; SDIO LOW = CMOS
CS
SDIO
(CMOS LVDS DDR)
SCLK
(Data format)
Offset binary, LVDS DDR
default mode at start-up
005aaa06
3
SDIO
(CMOS LVDS DDR)
SCLK
(Data format)
two's complement, CMOS
default mode at start-up 005aaa06
4
CS
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
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Product data sheet Rev. 2 — 17 December 2010 27 of 38
NXP Semiconductors ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
11.6.3 Register allocation map
Table 18. Register allocation map
Addr.
Hex Register name R/W Bit definition Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bin
0005 Reset and
operating mode R/W SW_RST RESERVED[2:0] - - OP_MODE[1:0] 0000
0000
0006 Clock R/W - - - SE_SEL DIFF_SE - CLKDIV DCS_EN 0000
0001
0008 Internal reference R/W - - - - INTREF_EN INTREF[2:0] 0000
0000
0010 Input buffer R/W - - - - - - IB_IBIAS[1:0
]- 0000
0011
0011 Output data
standard. R/W - - - LVDS_
CMOS OUTBUF OUTBUS_SWAP DATA_FORMAT[1:0] 0000
0000
0012 Output clock R/W - - - - DAVINV DAVPHASE[2:0] 0000
1110
0013 Offset R/W - - DIG_OFFSET[5:0] 0000
0000
0014 Test pattern 1 R/W - - - - - TESTPAT_SEL[2:0] 0000
0000
0015 Test pattern 2 R/W TESTPAT_USER[10:3] 0000
0000
0016 Test pattern 3 R/W TESTPAT_USER[2:0] - - - - - 0000
0000
0017 Fast OTR R/W - - - - FASTOTR FASTOTR_DET[2:0] 0000
0000
0020 CMOS output R/W - - - - DAV_DRV[1:0] DATA_DRV[1:0] 0000
1110
0021 LVDS DDR O/P 1 R/W - - DAVI_x2_EN DAVI[1:0] DATAI_x2_EN DATAI[1:0] 0000
0000
0022 LVDS DDR O/P 2 R/W - - - - BIT_BYTE_WISE LVDS_INT_TER[2:0] 0000
0000
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Product data sheet Rev. 2 — 17 December 2010 28 of 38
NXP Semiconductors ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
Table 19. Reset and operating mode control register (address 0005h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 SW_RST R/W reset digital section
0no reset
1 performs a reset on SPI registers
6 to 4 RESERVED[2:0] 000 reserved
3 to 2 - 00 not used
1 to 0 OP_MODE[1:0] R/W operating mode
00 normal (Power-up)
01 Power-down
10 Sleep
11 normal (Power-up)
Table 20. Clock control register (address 0006h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 5 - 000 not used
4 SE_SEL R/W single-ended clock input pin select
0CLKM
1CLKP
3 DIFF_SE R/W differential/single ended clock input select
0 fully differential
1 single-ended
2 - 0 not used
1 CLKDIV R/W clock input divide by 2
0disabled
1 enabled
0 DCS_EN R/W duty cycle stabilizer
0 disabled
1 enabled
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Product data sheet Rev. 2 — 17 December 2010 29 of 38
NXP Semiconductors ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
Table 21. Internal reference control register (address 0008h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 4 - 0000 not used
3 INTREF_EN R/W programmable internal reference enable
0disable
1 active
2 to 0 INTREF[2:0] R/W programmable internal reference
000 0 dB (FS = 2 V)
001 1dB (FS=1.78V)
010 2dB (FS=1.59V)
011 3dB (FS=1.42V)
100 4dB (FS=1.26V)
101 5dB (FS=1.12V)
110 6dB (FS=1V)
111 reserved
Table 22. Input buffer control register (address 0010h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 2 - 000000 not used
1 to 0 IB_IBIAS[1:0] R/W input buffer bias current
00 not used
01 medium
10 low
11 high
Table 23. Output data standard control register (address 0011h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 5 - 000 not used
4 LVDS_CMOS R/W output data standard: LVDS DDR or CMOS
0CMOS
1 LVDS DDR
3 OUTBUF R/W output buffers enable
0 output enabled
1 output disabled (high Z)
2 OUTBUS_SWAP R/W output bus swapping
0 no swapping
1 output bus is swapped (MSB becomes LSB and vice versa)
ADC1115S125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 2 — 17 December 2010 30 of 38
NXP Semiconductors ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
1 to 0 DATA_FORMAT[1:0] R/W output data format
00 offset binary
01 two’s complement
10 gray code
11 offset binary
Table 23. Output data standard control register (address 0011h) bit description …continued
Default values are highlighted.
Bit Symbol Access Value Description
Table 24. Output clock register (address 0012h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 4 - 0000 not used
3 DAVINV R/W output clock data valid (DAV) polarity
0normal
1inverted
2 to 0 DAVPHASE[2:0] R/W DAV phase select
000 output clock shifted (ahead) by 3 ns
001 output clock shifted (ahead) by 2.5 ns
010 output clock shifted (ahead) by 2 ns
011 output clock shifted (ahead) by 1.5 ns
100 output clock shifted (ahead) by 1 ns
101 output clock shifted (ahead) by 0.5 ns
110 default value as defined in timing section
111 output clock shifted (delayed) by 0.5 ns
Table 25. Offset register (address 0013h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 6 - 00 not used
5 to 0 DIG_OFFSET[5:0] R/W digital offset adjustment
011111 +31 LSB
... ...
000000 0
... ...
100000 32 LSB
Table 26. Test pattern register 1 (address 0014h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 3 - 00000 not used
ADC1115S125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 2 — 17 December 2010 31 of 38
NXP Semiconductors ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
2 to 0 TESTPAT_SEL[2:0] R/W digital test pattern select
000 off
001 mid scale
010 FS
011 +FS
100 toggle ‘1111..1111’/’0000..0000’
101 custom test pattern
110 ‘1010..1010.’
111 ‘010..1010’
Table 26. Test pattern register 1 (address 0014h) bit description …continued
Default values are highlighted.
Bit Symbol Access Value Description
Table 27. Test pattern register 2 (address 0015h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 0 TESTPAT_USER[10:3] R/W 00000000 custom digital test pattern (bits 10 to 3)
Table 28. Test pattern register 3 (address 0016h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 5 TESTPAT_USER[2:0] R/W 000 custom digital test pattern (bits 2 to 0)
4 to 0 - 00000 not used
Table 29. Fast OTR register (address 0017h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 4 - 0000 not used
3 FASTOTR R/W fast Out-of-Range (OTR) detection
0 disabled
1 enabled
2 to 0 FASTOTR_DET[2:0] R/W set fast OTR detect level
000 20.56 dB
001 16.12 dB
010 11.02 dB
011 7.82 dB
100 5.49 dB
101 3.66 dB
110 2.14 dB
111 0.86 dB
ADC1115S125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 2 — 17 December 2010 32 of 38
NXP Semiconductors ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
Table 30. CMOS output register (address 0020h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 4 - 0000 not used
3 to 2 DAV_DRV[1:0] R/W drive strength for DAV CMOS output buffer
00 low
01 medium
10 high
11 very high
1 to 0 DATA_DRV[1:0] R/W drive strength for DATA CMOS output buffer
00 low
01 medium
10 high
11 very high
Table 31. LVDS DDR output register 1 (address 0021h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 6 - 00 not used
5 DAVI_x2_EN R/W double LVDS current for DAV LVDS buffer
0 disabled
1 enabled
4 to 3 DAVI[1:0] R/W LVDS current for DAV LVDS buffer
00 3.5 mA
01 4.5 mA
10 1.25 mA
11 2.5 mA
2 DATAI_x2_EN R/W double LVDS current for DATA LVDS buffer
0 disabled
1 enabled
1 to 0 DATAI[1:0] R/W LVDS current for DATA LVDS buffer
00 3.5 mA
01 4.5 mA
10 1.25 mA
11 2.5 mA
ADC1115S125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 2 — 17 December 2010 33 of 38
NXP Semiconductors ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
Table 32. LVDS DDR output register 2 (address 0022h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 4 - 0000 not used
3 BIT/BYTE_WISE R/W DDR mode for LVDS output
0 bit wise (even data bits output on DAV rising edge / odd data
bits output on DAV falling edge)
1 byte wise (MSB data bits output on DAV rising edge / LSB data
bits output on DAV falling edge)
2 to 0 LVDS_INTTER[2:0] R/W internal termination for LVDS buffer (DAV and DATA)
000 no internal termination
001 300 Ω
010 180 Ω
011 110 Ω
100 150 Ω
101 100 Ω
110 81 Ω
111 60 Ω
‘ I \ _ mi» 3 D 3 3 E, i i,i i,i ,7, :> 3 :> ‘ r, 3 ‘ \ \ I ‘ 30 ‘ ‘ n n n n H n H H 0 ' |ermmaH 40 31 \\ / mdexarea 0,, ’ ’ \ 0 2 5 5 mm x_‘_‘_‘_‘_1_‘_‘_‘_‘_1 Dwmensuons 55"? um Am M b 0 DH) Dh Em E” e 2‘ e; L v y h max 100 005 030 61 455 01 455 05 mm mm 005 002 021 02 50 440 so no 05 4.5 45 04 0.1 005 005 0.1 mm 000 000 010 59 425 59 425 03 Note 1 masuc or mam prmmsmns am 075 mm maximum perswde are not mc‘uded salSYErfiipa Here ences Omlme V Emopean ‘ssue dam versm \EC ‘ JEDEC ‘ JEITA Pmecmn SOT618-6 M0-220 a @ W Aucmss‘zs Producl data sheel Fig 31. Package ouuine SOT618-6 (HVOFN40) AH mmmm Wm.” lmsflnzumem 5 mm mm d‘xdmmev: Rev. 2 — 17 December 2010 meV a v 20m Au 0ng: mm 34 of 33
ADC1115S125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 2 — 17 December 2010 34 of 38
NXP Semiconductors ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
12. Package outline
Fig 31. Package outline SOT618-6 (HVQFN40)
References
Outline
version
European
projection Issue date
IEC JEDEC JEITA
SOT618-6 - - -
MO-220
sot618-6_po
Unit
mm
max
nom
min
1.00
0.85
0.80
0.05
0.02
0.00
0.30
0.21
0.18
0.2
6.1
6.0
5.9
6.1
6.0
5.9
0.5 0.1 0.05
A(1)
Dimensions
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
H
VQFN40: plastic thermal enhanced very thin quad flat package; no leads;
4
0 terminals; body 6 x 6 x 0.85 mm SOT618-
6
A1bcD
(1)
0.1
y1
Dh
4.55
4.40
4.25
E(1) Eh
4.55
4.40
4.25
ee
1
4.5
e2
4.5
L
0.5
0.4
0.3
vw
0.05
y
0 2.5 5 mm
scale
terminal 1
index area
terminal 1
index area
B
DA
E
b
e1
eAC B
v
Cw
11 20
e2
e
21
30
Dh
3140
Eh
L
1
10
C
y
C
y1
X
c
detail X
A1
A
1/2 e
1/2 e
09-02-23
09-03-04
Secuon 10.4 “Tygwca‘ charameri ics"
ADC1115S125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 2 — 17 December 2010 35 of 38
NXP Semiconductors ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
13. Revision history
Table 33. Revision history
Document ID Release date Data sheet status Change
notice Supersedes
ADC1115S125 v.2 20101217 Product data sheet - ADC1115S125 v.1
Modifications: Data sheet status changed from Preliminary to Product.
Text and drawings updated throughout entire data sheet.
Section 10.4 “Typical characteristics added to the data sheet.
ADC1115S125 v.1 20100412 Preliminary data sheet - -
ADC1115S125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 2 — 17 December 2010 36 of 38
NXP Semiconductors ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
14. Legal information
14.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
14.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
14.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
hug :l/www. nxgcom salesaddresses®nx9£0m
ADC1115S125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 2 — 17 December 2010 37 of 38
NXP Semiconductors ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
14.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
15. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
© NXP B.V. 2010. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 17 December 2010
Document identifier: ADC1115S125
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
16. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
8 Thermal characteristics . . . . . . . . . . . . . . . . . . 5
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
10.1 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
10.2 Clock and digital output timing . . . . . . . . . . . . . 9
10.3 SPI timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
10.4 Typical characteristics . . . . . . . . . . . . . . . . . . 12
11 Application information. . . . . . . . . . . . . . . . . . 13
11.1 Device control. . . . . . . . . . . . . . . . . . . . . . . . . 13
11.1.1 SPI and Pin control modes . . . . . . . . . . . . . . . 13
11.1.2 Operating mode selection. . . . . . . . . . . . . . . . 14
11.1.3 Selecting the output data standard. . . . . . . . . 14
11.1.4 Selecting the output data format. . . . . . . . . . . 14
11.2 Analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . 14
11.2.1 Input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
11.2.2 Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . 16
11.3 System reference and power management . . 17
11.3.1 Internal/external references . . . . . . . . . . . . . . 17
11.3.2 Programmable full-scale. . . . . . . . . . . . . . . . . 18
11.3.3 Common-mode output voltage (VO(cm)) . . . . . 18
11.3.4 Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
11.4 Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
11.4.1 Drive modes . . . . . . . . . . . . . . . . . . . . . . . . . 19
11.4.2 Equivalent input circuit . . . . . . . . . . . . . . . . . . 20
11.4.3 Duty cycle stabilizer . . . . . . . . . . . . . . . . . . . . 20
11.4.4 Clock input divider . . . . . . . . . . . . . . . . . . . . . 20
11.5 Digital outputs. . . . . . . . . . . . . . . . . . . . . . . . . 21
11.5.1 Digital output buffers: CMOS mode . . . . . . . . 21
11.5.2 Digital output buffers: LVDS DDR mode. . . . . 22
11.5.3 DAta Valid (DAV) output clock . . . . . . . . . . . . 23
11.5.4 Out-of-Range (OTR). . . . . . . . . . . . . . . . . . . . 23
11.5.5 Digital offset . . . . . . . . . . . . . . . . . . . . . . . . . . 23
11.5.6 Test patterns. . . . . . . . . . . . . . . . . . . . . . . . . . 23
11.5.7 Output codes versus input voltage . . . . . . . . . 24
11.6 Serial Peripheral Interface (SPI). . . . . . . . . . . 24
11.6.1 Register description . . . . . . . . . . . . . . . . . . . . 24
11.6.2 Default modes at start-up . . . . . . . . . . . . . . . . 25
11.6.3 Register allocation map . . . . . . . . . . . . . . . . . 27
12 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 34
13 Revision history . . . . . . . . . . . . . . . . . . . . . . . 35
14 Legal information . . . . . . . . . . . . . . . . . . . . . . 36
14.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 36
14.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
14.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 36
14.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 37
15 Contact information . . . . . . . . . . . . . . . . . . . . 37
16 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

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