CS8421 Datasheet by Cirrus Logic Inc.

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32-Bit, 192-kHz Asynchronous Sample Rate Converter
Features
175-dB Dynamic Range
–140-dB THD+N
No Programming Required
No External Master Clock Required
Supports Sample Rates up to 211 kHz
Input/Output Sample Rate Ratios of 7.5:1 to 1:8
Master Clock Support for 128 x Fs, 256 x Fs,
384 x Fs, and 512 x Fs (Master Mode)
16-, 20-, 24-, or 32-bit Data I/O
32-bit Internal Signal Processing
Dither Automatically Applied and Scaled to
Output Resolution
Flexible 3-wire Serial Digital Audio Input and
Output Ports
Master and Slave Modes for Both Input and
Output
Bypass Mode
Time Division Multiplexing (TDM) Mode
Attenuates Clock Jitter
Multiple Device Outputs are Phase Matched
Linear Phase FIR Filter
Automatic Soft Mute/Unmute
+2.5-V Digital Supply (VD)
+3.3-V or 5.0-V Digital Interface (VL)
Space-saving 20-pin TSSOP and QFN
Packages
The CS8421 supports sample rates up to 211 kHz and
is available in 20-pin TSSOP and QFN packages in both
Commercial (-10° to +70°C) and Automotive (-40° to
+85°C and -40° to +105°C) grades. The CDB8421 Cus-
tomer Demonstration board is also available for device
evaluation and implementation suggestions. See “Or-
dering Information” on page 35 for complete details.
Serial
Audio
Input
Time
Varying
Digital
Filters
BYPASS
Digital
PLL
Clock
Generator
ILRCK
ISCLK
SDIN
Sync Info
Data Serial
Audio
Output
OLRCK
OSCLK
SDOUT
XTI XTO
SRC_UNLOCK
2.5 V (VD) GND
RST
Sync Info
Data Data
Level Translators
TDM_IN
MS_SEL
SAIF
SAOF
Serial
Port
Mode
Decoder
Level Translators
Level Translators
MCLK_OUT
3.3 V or 5.0 V (VL)
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CS8421
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CS8421
General Description
The CS8421 is a 32-bit, high-performance, monolithic CMOS stereo asynchronous sample-rate converter.
Digital audio inputs and outputs can be 32, 24, 20, or 16 bits. Input and output data can be completely asynchronous,
synchronous to an external data clock, or the part can operate without any external clock by using an integrated
oscillator.
Audio data is input and output through configurable 3-wire input/output ports. The CS8421 does not require any soft-
ware control via a control port.
Target applications include digital recording systems (DVD-R/RW, CD-R/RW, PVR, DAT, MD, and VTR), digital mix-
ing consoles, high-quality D/A, effects processors, computer audio systems, and automotive audio systems.
The CS8421 is also suitable for use as an asynchronous decimation or interpolation filter. See Cirrus Logic Appli-
cation Note AN270, “Audio A/D Conversion with an Asynchronous Decimation Filter”, available at www.cirrus.com
for more details.
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CS8421
TABLE OF CONTENTS
1. PIN DESCRIPTIONS ............................................................................................................................ 5
1.1 TSSOP Pin Descriptions ................................................................................................................ 5
1.2 QFN Pin Descriptions ..................................................................................................................... 7
2. CHARACTERISTICS AND SPECIFICATIONS ..................................................................................... 9
SPECIFIED OPERATING CONDITIONS .............................................................................................. 9
ABSOLUTE MAXIMUM RATINGS ........................................................................................................9
PERFORMANCE SPECIFICATIONS.................................................................................................. 10
DIGITAL FILTER CHARACTERISTICS .............................................................................................. 11
DC ELECTRICAL CHARACTERISTICS ............................................................................................. 11
DIGITAL INPUT CHARACTERISTICS ................................................................................................ 12
DIGITAL INTERFACE SPECIFICATIONS .......................................................................................... 12
SWITCHING SPECIFICATIONS ......................................................................................................... 12
3. TYPICAL CONNECTION DIAGRAMS ................................................................................................14
4. APPLICATIONS .................................................................................................................................. 16
4.1 Three-wire Serial Input/Output Audio Port .................................................................................... 16
4.2 Mode Selection ............................................................................................................................. 17
4.3 Sample Rate Converter (SRC) ..................................................................................................... 19
4.3.1 Data Resolution and Dither .............................................................................................. 19
4.3.2 SRC Locking and Varispeed ............................................................................................ 19
4.3.3 Bypass Mode ................................................................................................................... 19
4.3.4 Muting .............................................................................................................................. 20
4.3.5 Group Delay and Phase Matching Between Multiple CS8421 Parts ............................... 20
4.3.6 Master Clock .................................................................................................................... 20
4.3.7 Clocking ........................................................................................................................... 21
4.4 Time Division Multiplexing (TDM) Mode ....................................................................................... 21
4.5 Reset, Power-Down, and Start-Up ............................................................................................... 22
4.6 Power Supply, Grounding, and PCB Layout ................................................................................ 23
5. PERFORMANCE PLOTS ................................................................................................................ 24
6. PACKAGE DIMENSIONS ................................................................................................................... 33
TSSOP THERMAL CHARACTERISTICS ........................................................................................... 33
QFN THERMAL CHARACTERISTICS ................................................................................................ 34
7. ORDERING INFORMATION ............................................................................................................... 35
8. REVISION HISTORY .......................................................................................................................... 35
LIST OF FIGURES
Figure 1. Non-TDM Slave Mode Timing..................................................................................................... 13
Figure 2. TDM Slave Mode Timing ............................................................................................................ 13
Figure 3. Non-TDM Master Mode Timing................................................................................................... 13
Figure 4. TDM Master Mode Timing .......................................................................................................... 13
Figure 5. Typical Connection Diagram, No External Master Clock ............................................................ 14
Figure 6. Typical Connection Diagram, Master and Slave Modes ............................................................. 15
Figure 7. Serial Audio Interface Format - I²S ............................................................................................. 17
Figure 8. Serial Audio Interface Format - Left-Justified.............................................................................. 17
Figure 9. Serial Audio Interface Format - Right-Justified ........................................................................... 17
Figure 10. Typical Connection Diagram for Crystal Circuit ........................................................................ 21
Figure 11. TDM Slave Mode Timing Diagram............................................................................................ 21
Figure 12. TDM Master Mode Timing Diagram.......................................................................................... 22
Figure 13. TDM Mode Configuration (All CS8421 Outputs are Slave)....................................................... 22
Figure 14. TDM Mode Configuration (First CS8421 Output is Master, All Others are Slave) .................... 22
Figure 15. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 48 kHz:48 kHz ..................................... 24
Figure 16. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 44.1 kHz:192 kHz ................................ 24
Figure 17. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 44.1 kHz:48 kHz .................................. 24
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Figure 18. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 48 kHz:44.1 kHz .................................. 24
Figure 19. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 48 kHz:96 kHz ..................................... 24
Figure 20. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 96 kHz:48 kHz ..................................... 24
Figure 21. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 192 kHz:48 kHz ................................... 25
Figure 22. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 48 kHz:96 kHz.................................. 25
Figure 23. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 48 kHz:48 kHz.................................. 25
Figure 24. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 44.1 kHz:192 kHz............................. 25
Figure 25. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 44.1 kHz:48 kHz............................... 25
Figure 26. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 48 kHz:44.1 kHz............................... 25
Figure 27. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 96 kHz:48 kHz.................................. 26
Figure 28. IMD, 10 kHz and 11 kHz -7 dBFS, 96 kHz:48 kHz ................................................................... 26
Figure 29. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 192 kHz:48 kHz................................ 26
Figure 30. IMD, 10 kHz and 11 kHz -7 dBFS, 48 kHz:44.1 kHz ................................................................ 26
Figure 31. IMD, 10 kHz and 11 kHz -7 dBFS, 44.1 kHz:48 kHz ................................................................ 26
Figure 32. Wideband FFT Plot (16k Points) 0 dBFS 20 kHz Tone, 44.1 kHz:48 kHz ................................ 26
Figure 33. Wideband FFT Plot (16k Points) 0 dBFS 80 kHz Tone, 192 kHz:192 kHz ............................... 27
Figure 34. Wideband FFT Plot (16k Points) 0 dBFS 20 kHz Tone, 48 kHz:96 kHz ................................... 27
Figure 35. Wideband FFT Plot (16k Points) 0 dBFS 20 kHz Tone, 48 kHz:48 kHz ................................... 27
Figure 36. Wideband FFT Plot (16k Points) 0 dBFS 20 kHz Tone, 96 kHz:48 kHz ................................... 27
Figure 37. Wideband FFT Plot (16k Points) 0 dBFS 20 kHz Tone, 48 kHz:44.1 kHz ................................ 27
Figure 38. THD+N vs. Output Sample Rate, 0 dBFS 1 kHz Tone, Fsi = 192 kHz ..................................... 27
Figure 39. THD+N vs. Output Sample Rate, 0 dBFS 1 kHz Tone, Fsi = 48 kHz ....................................... 28
Figure 40. THD+N vs. Output Sample Rate, 0 dBFS 1 kHz Tone, Fsi = 96 kHz ....................................... 28
Figure 41. THD+N vs. Output Sample Rate, 0 dBFS 1 kHz Tone, Fsi = 44.1 kHz .................................... 28
Figure 42. Dynamic Range vs. Output Sample Rate, -60 dBFS 1 kHz Tone, Fsi = 192 kHz .................... 28
Figure 43. THD+N vs. Output Sample Rate, 0 dBFS 1 kHz Tone, Fsi = 32 kHz ....................................... 28
Figure 44. Dynamic Range vs. Output Sample Rate, -60 dBFS 1 kHz Tone, Fsi = 32 kHz ...................... 28
Figure 45. Dynamic Range vs. Output Sample Rate, -60 dBFS 1 kHz Tone, Fsi = 96 kHz ...................... 29
Figure 46. Dynamic Range vs. Output Sample Rate, -60 dBFS 1 kHz Tone, Fsi = 44.1 kHz ................... 29
Figure 47. Frequency Response with 0 dBFS Input ..................................................................................29
Figure 48. Passband Ripple, 192 kHz:48 kHz ........................................................................................... 29
Figure 49. Dynamic Range vs. Output Sample Rate, -60 dBFS 1 kHz Tone, Fsi = 48 kHz ...................... 29
Figure 50. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone, 48 kHz:48 kHz ........................................ 29
Figure 51. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone, 48 kHz:44.1 kHz ..................................... 30
Figure 52. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone, 48 kHz:96 kHz ........................................ 30
Figure 53. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone, 96 kHz:48 kHz ........................................ 30
Figure 54. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone, 44.1 kHz:192 kHz ................................... 30
Figure 55. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone, 44.1 kHz:48 kHz ..................................... 30
Figure 56. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone, 192 kHz:44.1 kHz ................................... 30
Figure 57. THD+N vs. Input Amplitude, 1 kHz Tone, 48 kHz:44.1 kHz ..................................................... 31
Figure 58. THD+N vs. Input Amplitude, 1 kHz Tone, 48 kHz:96 kHz ........................................................ 31
Figure 59. THD+N vs. Input Amplitude, 1 kHz Tone, 96 kHz:48 kHz ........................................................ 31
Figure 60. THD+N vs. Input Amplitude, 1 kHz Tone, 44.1 kHz:192 kHz ................................................... 31
Figure 61. THD+N vs. Input Amplitude, 1 kHz Tone, 44.1 kHz:48 kHz ..................................................... 31
Figure 62. THD+N vs. Input Amplitude, 1 kHz Tone, 192 kHz:48 kHz ...................................................... 31
Figure 63. THD+N vs. Frequency Input, 0 dBFS, 48 kHz:44.1 kHz........................................................... 32
Figure 64. THD+N vs. Frequency Input, 0 dBFS, 48 kHz:96 kHz .............................................................. 32
Figure 65. THD+N vs. Frequency Input, 0 dBFS, 44.1 kHz:48 kHz ........................................................... 32
Figure 66. THD+N vs. Frequency Input, 0 dBFS, 96 kHz:48 kHz .............................................................. 32
LIST OF TABLES
Table 1. Serial Audio Port Master/Slave and Clock Ratio Select Start-Up Options (MS_SEL) ................. 18
Table 2. Serial Audio Input Port Start-Up Options (SAIF) .......................................................................... 18
Table 3. Serial Audio Output Port Start-Up Options (SAOF) ..................................................................... 18
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1. PIN DESCRIPTIONS
1.1 TSSOP PIN DESCRIPTIONS
1
2
3
4
516
6
7
8
15
14
13
12
11
9
10
17
18
19
20
SRC_UNLOCK
XTO
SAIF
XTI
SAOF
VD
VL
GND
GND
RST
MS_SEL
BYPASS
OLRCK
ILRCK
OSCLK
ISCLK
SDOUT
SDIN
TDM_IN
MCLK_OUT
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Pin Name # Pin Description
XTO 1 Crystal Out (Output) - Crystal output for Master clock. See “Master Clock” on page 20.
XTI 2 Crystal/Oscillator In (Input) - Crystal or digital clock input for Master clock. See “Master Clock”
on page 20.
VD 3 Digital Power (Input) - Digital core power supply. Typically +2.5 V.
GND 4 Ground (Input) - Ground for I/O and core logic.
RST 5
Reset (Input) - When RST is low, the CS8421 enters a low-power mode and all internal states are
reset. On initial power-up, RST must be held low until the power supply is stable and all input
clocks are stable in frequency and phase.
BYPASS 6
Sample Rate Converter Bypass (Input) - When BYPASS is high, the sample rate converter will
be bypassed, and any data input through the serial audio input port will be directly output on the
serial audio output port. When BYPASS is low, the sample rate converter will operate normally.
ILRCK 7 Serial Audio Input Left/Right Clock (Input/Output) - Word-rate clock for the audio data on the
SDIN pin.
ISCLK 8 Serial Audio Bit Clock (Input/Output) - Serial-bit clock for audio data on the SDIN pin.
SDIN 9 Serial Audio Input Data Port (Input) - Audio data serial input pin.
MCLK_OUT 10
Master Clock Output (Output) - Buffered and level-shifted output for Master clock. If MCLK_OUT
is not required, this pin should be pulled high through a 47 k resistor to turn the output off. See
“Master Clock” on page 20.
TDM_IN 11 Serial Audio TDM Input (Input) - Time Division Multiplexing serial audio data input. Grounded
when not used. See “Time Division Multiplexing (TDM) Mode” on page 21.
SDOUT 12 Serial Audio Output Data Port (Output) - Audio data serial output pin. Optionally, this pin may be
pulled low through a 47-k resistor, but must not be pulled high.
OSCLK 13 Serial Audio Bit Clock (Input/Output) - Serial-bit clock for audio data on the SDOUT pin.
OLRCK 14 Serial Audio Input Left/Right Clock (Input/Output) - Word-rate clock for the audio data on the
SDOUT pin.
MS_SEL 15 Master/Slave Select (Input) - Used to select Master or Slave for the input and output serial audio
ports at startup and reset. See Table 1 on page 18 for settings.
GND 16 Ground (Input) - Ground for I/O and core logic.
VL 17 Logic Power (Input) - Input/Output power supply. Typically +3.3 V or +5.0 V.
SAOF 18 Serial Audio Output Format Select (Input) - Used to select the serial audio output format at
startup and reset. See Table 3 on page 18 for format settings.
SAIF 19 Serial Audio Input Format Select (Input) - Used to select the serial audio input format at startup
and reset. See Table 2 on page 18 for format settings.
SRC_UNLOCK 20 SRC Unlock Indicator (Output) - Indicates when the SRC is unlocked. See “SRC Locking and
Varispeed” on page 19.
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1.2 QFN PIN DESCRIPTIONS
76
5
4
3
2
1
8910
11
12
13
14
15
16
17
181920
Top-Down View
20-pin QFN Package
Thermal Pad
XTI
XTO
SRC_UNLOC
SAIF
SAOF
ISCLK
SDIN
MCLK_OUT
TDM_IN
SDOUT
VD
GND
RST
BYPASS
ILRCK
VL
GND
MS_SEL
OLRCK
OSCLK
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Pin Name # Pin Description
VD 1 Digital Power (Input) - Digital core power supply. Typically +2.5 V.
GND 2 Ground (Input) - Ground for I/O and core logic.
RST 3
Reset (Input) - When RST is low, the CS8421 enters a low-power mode and all internal states are
reset. On initial power-up, RST must be held low until the power supply is stable and all input clocks
are stable in frequency and phase.
BYPASS 4
Sample Rate Converter Bypass (Input) - When BYPASS is high, the sample-rate converter will be
bypassed, and any data input through the serial audio input port will be directly output on the serial
audio output port. When BYPASS is low, the sample rate converter will operate normally.
ILRCK 5 Serial Audio Input Left/Right Clock (Input/Output) - Word-rate clock for the audio data on the
SDIN pin.
ISCLK 6 Serial Audio Bit Clock (Input/Output) - Serial-bit clock for audio data on the SDIN pin.
SDIN 7 Serial Audio Input Data Port (Input) - Audio data serial input pin.
MCLK_OUT 8
Master Clock Output (Output) - Buffered and level-shifted output for Master clock. If MCLK_OUT
is not required, this pin should be pulled high through a 47 k resistor to turn the output off. See
“Master Clock” on page 20.
TDM_IN 9 Serial Audio TDM Input (Input) - Time Division Multiplexing serial audio data input. Grounded
when not used. See “Time Division Multiplexing (TDM) Mode” on page 21.
SDOUT 10 Serial Audio Output Data Port (Output) - Audio data serial output pin. Optionally, this pin may be
pulled low through a 47-k resistor, but must not be pulled high.
OSCLK 11 Serial Audio Bit Clock (Input/Output) - Serial bit clock for audio data on the SDOUT pin.
OLRCK 12 Serial Audio Input Left/Right Clock (Input/Output) - Word rate clock for the audio data on the
SDOUT pin.
MS_SEL 13 Master/Slave Select (Input) - Used to select Master or Slave for the input and output serial audio
ports at startup and reset. See Table 1 on page 18 for settings.
GND 14 Ground (Input) - Ground for I/O and core logic.
VL 15 Logic Power (Input) - Input/Output power supply. Typically +3.3 V or +5.0 V.
SAOF 16 Serial Audio Output Format Select (Input) - Used to select the serial audio output format at
startup and reset. See Table 3 on page 18 for format settings.
SAIF 17 Serial Audio Input Format Select (Input) - Used to select the serial audio input format at startup
and reset. See Table 2 on page 18 for format settings.
SRC_UNLOCK 18 SRC Unlock Indicator (Output) - Indicates when the SRC is unlocked. See “SRC Locking and
Varispeed” on page 19.
XTO 19 Crystal Out (Output) - Crystal output for Master clock. See “Master Clock” on page 20.
XTI 20 Crystal/Oscillator In (Input) - Crystal or digital clock input for Master clock. See “Master Clock” on
page 20.
Thermal Pad -
Thermal Pad - Thermal relief pad for optimized heat dissipation. This pad must be electrically
connected to GND. See “Power Supply, Grounding, and PCB Layout” on page 23 for more
information.
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2. CHARACTERISTICS AND SPECIFICATIONS
(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical per-
formance characteristics and specifications are derived from measurements taken at nominal supply voltages and
TA = 25°C.)
SPECIFIED OPERATING CONDITIONS
(GND = 0 V, all voltages with respect to 0 V)
ABSOLUTE MAXIMUM RATINGS
(GND = 0 V; all voltages with respect to 0 V. Operation beyond these limits may result in permanent damage to the device. Nor-
mal operation is not guaranteed at these extremes.)
Notes:
1. Transient currents of up to 100 mA will not cause SCR latch-up.
2. Numbers separated by a colon indicate input and output sample rates. For example, 48 kHz:96 kHz indicates that
Fsi = 48 khz and Fso = 96 kHz.
Parameter Symbol Min Nominal Max Units
Power Supply Voltage VD
VL
2.38
3.14
2.5
3.3 or 5.0
2.62
5.25
V
V
Ambient Operating Temperature: ‘-CZ’
‘-CNZ’
‘-DZ’
‘-EZ’
‘-ENZ’
TA-10
-10
-40
-40
-40
-
-
-
-
-
+70
+70
+85
+105
+105
°C
°C
°C
°C
°C
Parameter Symbol Min Max Units
Power Supply Voltage VD
VL
-0.3
-0.3
3.5
6.0
V
V
Input Current, Any Pin Except Supplies (Note 1) Iin 10mA
Input Voltage Vin -0.3 VL+0.4 V
Ambient Operating Temperature (power applied) TA-55 +125 °C
Storage Temperature Tstg -65 +150 °C
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PERFORMANCE SPECIFICATIONS
(XTI/XTO = 27 MHz; Input signal = 1.000 kHz, 0 dBFS, Measurement Bandwidth = 20 to Fso/2 Hz, and Word Width = 32-Bits,
unless otherwise stated.)
Parameter Min Typ Max Units
Resolution 16 - 32 bits
Sample Rate with XTI = 27.000 MHz Slave
Master
7.2
53
-
-
207
211
kHz
kHz
Sample Rate with other XTI clocks Slave
Master
XTI/3750
XTI/512
-
-
XTI/130
XTI/128
kHz
kHz
Sample Rate with ring oscillator (XTI to GND or VL, XTO floating) 12 - 96 kHz
Sample Rate Ratio - Upsampling - - 1:8
Sample Rate Ratio - Downsampling - - 7.5:1
Gain Error -0.2 - -0.02 dB
Interchannel Gain Mismatch - 0.0 - dB
Interchannel Phase Deviation - 0.0 - Degrees
Peak Idle Channel Noise Component (32-bit operation) - - -192 dBFS
Dynamic Range (20 Hz to Fso/2, 1 kHz, -60 dBFS Input)
44.1 kHz:48 kHz A-Weighted
Unweighted
-
-
180
177
-
-
dB
dB
44.1 kHz:192 kHz A-Weighted
Unweighted
-
-
175
172
-
-
dB
dB
48 kHz:44.1 kHz A-Weighted
Unweighted
-
-
180
177
-
-
dB
dB
48 kHz:96 kHz A-Weighted
Unweighted
-
-
179
176
-
-
dB
dB
96 kHz:48 kHz A-Weighted
Unweighted
-
-
176
173
-
-
dB
dB
192 kHz:32 kHz A-Weighted
Unweighted
-
-
175
172
-
-
dB
dB
Total Harmonic Distortion + Noise (20 Hz to Fso/2, 1 kHz, 0 dBFS Input)
32 kHz:48 kHz - -161 - dB
44.1 kHz:48 kHz - -171 - dB
44.1 kHz:192 kHz - -130 - dB
48 kHz:44.1 kHz - -160 - dB
48 kHz:96 kHz - -148 - dB
96 kHz:48 kHz - -168 - dB
192 kHz:32 kHz - -173 - dB
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DIGITAL FILTER CHARACTERISTICS
3. The equation for the group delay through the sample-rate converter is (56.581 / Fsi) + (55.658 / Fso). For example,
if the input sample rate is 192 kHz and the output sample rate is 96 kHz, the group delay through the sample-rate
converter is (56.581/192,000) + (55.658/96,000) =.875 milliseconds.
DC ELECTRICAL CHARACTERISTICS
(GND = 0 V; all voltages with respect to 0 V.)
4. Power Down Mode is defined as RST = LOW with all clocks and data lines held static, except when a crystal is
attached across XTI-XTO, in which case the crystal will begin oscillating.
5. Normal operation is defined as RST = HI.
Parameter Min Typ Max Units
Passband (Upsampling or Downsampling) - - 0.4535*Fso Hz
Passband Ripple - - ±0.007 dB
Stopband 0.5465*Fso - - Hz
Stopband Attenuation 125 - - dB
Group Delay SRC Mode
Bypass Mode
-
-
(Note 3)
-
-
3/Fsi
s
s
Parameter Symbol Min Typ Max Units
Power-Down Mode (Note 4)
Supply Current in power-down VD
(Oscillator attached to XTI-XTO) VL = 3.3 V
VL = 5.0 V
50
100
200
A
A
A
Supply Current in power-down VD
(Crystal attached to XTI-XTO) VL = 3.3 V
VL = 5.0 V
100
1.5
4
A
mA
mA
Normal Operation (Note 5)
Supply Current at 48 kHz Fsi and Fso VD
(Oscillator attached to XTI-XTO) VL = 3.3 V
VL = 5.0 V
24
2.5
4
mA
mA
mA
Supply Current at 192 kHz Fsi and Fso VD
(Oscillator attached to XTI-XTO) VL = 3.3 V
VL = 5.0 V
80
8
13
mA
mA
mA
Supply Current at 48 kHz Fsi and Fso VD
(Crystal attached to XTI-XTO) VL = 3.3 V
VL = 5.0 V
24
3
7
mA
mA
mA
Supply Current at 192 kHz Fsi and Fso VD
(Crystal attached to XTI-XTO) VL = 3.3 V
VL = 5.0 V
80
4
6.5
mA
mA
mA
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DIGITAL INPUT CHARACTERISTICS
DIGITAL INTERFACE SPECIFICATIONS
(GND = 0 V; all voltages with respect to 0 V.)
SWITCHING SPECIFICATIONS
(Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF)
Parameters Symbol Min Typ Max Units
Input Leakage Current Iin --±10A
Input Capacitance Iin -8- pF
Input Hysteresis -250- mV
Parameters Symbol Min Max Units
High-Level Output Voltage, except MCLK_OUT and SDOUT (IOH=-4 mA) VOH 0.77xVL - V
Low-Level Output Voltage, except MCLK_OUT and SDOUT (IOL=4 mA) VOL -.6V
High-Level Output Voltage, MCLK_OUT (IOH=-6 mA) VOH 0.77xVL - V
Low-Level Output Voltage, MCLK_OUT (IOL=6 mA) VOL -.6V
High-Level Output Voltage, SDOUT (IOH=-8 mA) VOH 0.77xVL - V
Low-Level Output Voltage, SDOUT (IOL=8 mA) VOL -.65V
High-Level Input Voltage VIH 0.6xVL VL+0.3 V
Low-Level Input Voltage VIL -0.3 0.8 V
Parameters Symbol Min Max Units
RST pin Low Pulse Width (Note 6) 1-ms
XTI Frequency (Note 7) Crystal
Digital Clock Source
16.384
1.024
27.000
27.000
MHz
MHz
XTI Pulse Width High/Low 14.8 - ns
MCLK_OUT Duty Cycle 45 55 %
Slave Mode
I/OSCLK Frequency - 24.576 MHz
OLRCK High Time (Note 8) tlrckh 326 - ns
I/OSCLK High Time tsckh 9-ns
I/OSCLK Low Time tsckl 9-ns
I/OLRCK Edge to I/OSCLK Rising tlcks 6-ns
OLRCK Rising Edge to OSCLK Rising Edge (TDM) tfss 5-ns
I/OSCLK Rising Edge to I/OLRCK Edge tlckd 5-ns
OSCLK Rising Edge to OLRCK Falling Edge (TDM) tfsh 5-ns
OSCLK Falling Edge/OLRCK Edge to SDOUT Output Valid tdpd -18ns
SDIN/TDM_IN Setup Time Before I/OSCLK Rising Edge tds 3.5 - ns
SDIN/TDM_IN Hold Time After I/OSCLK Rising Edge tdh 5-ns
__- __— __— _— _— CIRRUS LOGIC“
DS641F7 13
CS8421
6. After powering up the CS8421, RST should be held low until the power supplies and clocks are settled.
7. The maximum possible sample rate is XTI/128.
8. OLRCK must remain high for at least 8 OSCLK periods in TDM Mode.
9. Only the input or the output serial port can be set as master at a given time.
Master Mode (Note 9)
I/OSCLK Frequency (non-TDM) 64*Fsi/o MHz
OSCLK Frequency (TDM) 256*Fso MHz
I/OLRCK Duty Cycle 45 55 %
I/OSCLK Duty Cycle 45 55 %
I/OSCLK Falling Edge to I/OLRCK Edge tlcks -5ns
OSCLK Falling Edge to OLRCK Edge (TDM) tfss -5ns
OSCLK Falling Edge to SDOUT Output Valid tdpd -7ns
SDIN/TDM_IN Setup Time Before I/OSCLK Rising Edge tds 3-ns
SDIN/TDM_IN Hold Time After I/OSCLK Rising Edge tdh 5-ns
Parameters Symbol Min Max Units
tds
OLRCK
(input)
tdh
tsckh tsckl
tfsh
tfss
OSCLK
(input)
TDM_IN
(input)
SDOUT
(output)
MSB
tdpd
MSB-1
MSB MSB-1
tlrckh
Figure 1. Non-TDM Slave Mode Timing Figure 2. TDM Slave Mode Timing
tds
OLRCK
(output)
tdh
tdpd
tfss
OSCLK
(output)
TDM_IN
(input)
SDOUT
(output)
MSB MSB-1
MSB MSB-1
tds
MSB
tdh
tdpd
MSB-1
tlcks
I/OLRCK
(output)
I/OSCLK
(output)
SDIN
(input)
SDOUT
(output) MSB MSB-1
Figure 3. Non-TDM Master Mode Timing Figure 4. TDM Master Mode Timing
__- __— __— _— __— CIRRUS LOGIC”
14 DS641F7
CS8421
3. TYPICAL CONNECTION DIAGRAMS
CS8421
VD VL
Serial
Audio
Source
ILRCK
ISCLK
SDIN
BYPASS
+2.5 V +3.3 V or +5.0 V
0.1 F0.1 F
Serial
Audio
Input
Device
OLRCK
OSCLK
SDOUT
XTI
RST
SRC_UNLOCK
SAOF
TDM_IN
Hardware Control
Settings
GND
SAIF
MS_SEL
GND
**
1 k*
***
Figure 5. Typical Connection Diagram, No External Master Clock
* When no external master clock is supplied to the part, both input and output must be set to Slave Mode for the
part to operate properly. This is done by connecting the MS_SEL pin to ground through a resistance of 0 to 1 k
+ 1% as stated in Table 1, “Serial Audio Port Master/Slave and Clock Ratio Select Start-Up Options (MS_SEL),”
on page 18.
** The connection (VL or GND) and value of these two resistors determines the mode of operation for the input and
output serial ports as described in Table 2 on page 18 and Table 3 on page 18.
*** This pin must not be pulled high. See Section 1, “Pin Descriptions.”
__- __— __— _— __— CIRRUS LOGIC”
DS641F7 15
CS8421
CS8421
VD VL
Serial
Audio
Source
ILRCK
ISCLK
SDIN
BYPASS
+2.5 V +3.3 V or +5.0 V
0.1 F0.1 F
Serial
Audio
Input
Device
OLRCK
OSCLK
SDOUT
XTI
XTO
RST
SRC_UNLOCK
SAOF
TDM_IN
Hardware Control
Settings
Crystal /Clock
Source
GND
SAIF
MS_SEL
GND
MCLK_OUT To external
hardware
47 k
***
***
Figure 6. Typical Connection Diagram, Master and Slave Modes
* The connection (VL or GND) and value of these three resistors determines the mode of operation for the input
and output serial ports as described in Table 1 Serial Audio Port Master/Slave and Clock Ratio Select Start-Up Op-
tions (MS_SEL), and Table 2, “Serial Audio Input Port Start-Up Options (SAIF),” on page 18 and Table 3, “Serial
Audio Output Port Start-Up Options (SAOF),” on page 18.
** MCLK_OUT pin should be pulled high through a 47 k resistor if an MCLK output is not needed.
*** This pin must not be pulled high. See Section 1, “Pin Descriptions.”
__- __— __— _— __— CIRRUS LOGIC”
16 DS641F7
CS8421
4. APPLICATIONS
The CS8421 is a 32-bit, high-performance, monolithic CMOS stereo asynchronous sample-rate converter.
The digital audio data is input and output through configurable 3-wire serial ports. The digital audio input/output ports
offer Left-Justified, Right-Justified, and I²S serial audio formats. The CS8421 also supports a TDM Mode which al-
lows multiple channels of digital audio data on one serial line. A Bypass Mode allows the data to be passed directly
to the output port without sample rate conversion.
The CS8421 does not require a control port interface, helping to speed design time by not requiring the user to de-
velop software to configure the part. Pins that are sensed after reset allow the part to be configured. See “Reset,
Power-Down, and Start-Up” on page 22.
Target applications include digital recording systems (DVD-R/RW, CD-R/RW, PVR, DAT, MD, and VTR), digital mix-
ing consoles, high quality D/A, effects processors and computer audio systems.
Figure 5 and 6 show the supply and external connections to the CS8421.
4.1 Three-wire Serial Input/Output Audio Port
A 3-wire serial audio input/output port is provided. The interface format should be chosen to suit the attached device
through the MS_SEL, SAIF, and SAOF pins. Tables 1, 2, and 3 show the pin functions and their corresponding set-
tings. The following parameters are adjustable:
Master or Slave
Master clock (MCLK) frequencies of 128*Fsi/o, 256*Fsi/o, 384*Fsi/o, and 512*Fsi/o (Master Mode)
Audio data resolution of 16-, 20-, 24-, or 32-bits
Left- or Right-Justification of the data relative to left/right clock (LRCK) as well as I²S
Figures 7, 8, and 9 show the input/output formats available.
In Master Mode, the left/right clock and the serial bit clock are outputs, derived from the XTI input pin master clock.
In Slave Mode, the left/right clock and the serial bit clock are inputs and may be asynchronous to the XTI master
clock. The left/right clock should be continuous, but the duty cycle can be less than 50% if enough serial clocks are
present in each phase to clock all of the data bits.
ISCLK is always set to 64*Fsi when the input is set to master. In normal operation, OSCLK is set to 64*Fso. In TDM
Slave Mode, OSCLK must operate at N*64*Fso, where N is the number of CS8421’s connected together. In TDM
Master Mode, OSCLK is set to 256*Fso
For more information about serial audio formats, refer to the Cirrus Logic applications note AN282, “The 2-Channel
Serial Audio Interface: A Tutorial”, available at www.cirrus.com.
__- __— __— _— __— CIRRUS LOGIC”
DS641F7 17
CS8421
4.2 Mode Selection
The CS8421 uses the resistors attached to the MS_SEL, SAIF, and SAOF pins to determine the modes of operation.
After reset, the resistor value and condition (VL or GND) are sensed. This operation will take approximately 4 s to
complete. The SRC_UNLOCK pin will remain high and the SDOUT pin will be muted until the mode detection se-
quence has completed. After this, if all clocks are stable, SRC_UNLOCK will be brought low when audio output is
valid and normal operation will occur. Tables 1, 2, and 3 show the pin functions and their corresponding settings. If
the 1.0 k option is selected for MS_SEL, SAIF, or SAOF, the resistor connected to that pin may be replaced by a
direct connection to VL or GND as appropriate.
The resistor attached to each mode-selection pin should be placed physically close to the CS8421. The end of the
resistor not connected to the mode selection pins should be connected as close as possible to VL and GND to min-
imize noise. Tables 1, 2, and 3 show the pin functions and their corresponding settings.
I/OLRCK
I/OSCLK
MSB LSB MSB LSB
Channel A
SDIN
SDOUT MSB
Channel B
Figure 7. Serial Audio Interface Format - I²S
MSB LSB MSB LSB MSB
I/OLRCK
I/OSCLK
SDIN
SDOUT
Channel A Channel B
Figure 8. Serial Audio Interface Format - Left-Justified
I/OLRCK
I/OSCLK
Channel A
SDIN
Channel B
MSB
SDOUT
MSB MSB
MSB LSB
LSB
LSB
LSB
MSB Extended MSB Extended
Figure 9. Serial Audio Interface Format - Right-Justified
__- __— __— _— _— CIRRUS LOGIC“
18 DS641F7
CS8421
MS_SEL pin Input M/S Output M/S
1.0 k± 1% to GND Slave Slave
1.96 k± 1% to GND Slave Master (128 x Fso)
4.02 k± 1% to GND Slave Master (256 x Fso)
8.06 k± 1% to GND Slave Master (384 x Fso)
16.2 k± 1% to GND Slave Master (512 x Fso)
1.0 k± 1% to VL Master (128 x Fsi)Slave
1.96 k± 1% to VL Master (256 x Fsi)Slave
4.02 k± 1% to VL Master (384 x Fsi)Slave
8.06 k± 1% to VL Master (512 x Fsi) Slave
Table 1. Serial Audio Port Master/Slave and Clock Ratio Select Start-Up Options (MS_SEL)
SAIF pin Input Port Configuration
1.0 k± 1% to GND I²S up to 32-bit data
1.96 k± 1% to GND Left-Justified up to 32-bit data
4.02 k± 1% to GND Right-Justified 16-bit data
1.0 k± 1% to VL Right-Justified 20-bit data
1.96 k± 1% to VL Right-Justified 24-bit data
4.02 k± 1% to VL Right-Justified 32-bit data
Table 2. Serial Audio Input Port Start-Up Options (SAIF)
SAOF pin Output Port Configuration
1.0 k± 1% to GND I²S 16-bit data
1.96 k± 1% to GND I²S 20-bit data
4.02 k± 1% to GND I²S 24-bit data
8.06 k± 1% to GND I²S 32-bit data
16.2 k± 1% to GND Left-Justified 16-bit data
32.4 k± 1% to GND Left-Justified 20-bit data
63.4 k± 1% to GND Left-Justified 24-bit data
127.0 k± 1% to GND Left-Justified 32-bit data
1.0 k± 1% to VL Right-Justified 16-bit data
1.96 k± 1% to VL Right-Justified 20-bit data
4.02 k± 1% to VL Right-Justified 24-bit data
8.06 k± 1% to VL Right-Justified 32-bit data
16.2 k± 1% to VL TDM Mode 16-bit data
32.4 k± 1% to VL TDM Mode 20-bit data
63.4 k± 1% to VL TDM Mode 24-bit data
127.0 k± 1% to VL TDM Mode 32-bit data
Table 3. Serial Audio Output Port Start-Up Options (SAOF)
__- __— __— _— __— CIRRUS LOGIC”
DS641F7 19
CS8421
4.3 Sample Rate Converter (SRC)
Multirate digital signal processing techniques are used to conceptually upsample the incoming data to a very
high rate and then downsample to the outgoing rate. The internal data path is 32-bits wide even if a lower
bit depth is selected at the output. The filtering is designed so that a full input audio bandwidth of 20 kHz is
preserved if the input sample and output sample rates are greater than or equal to 44.1 kHz. When the out-
put sample rate becomes less than the input sample rate, the input is automatically band-limited to avoid
aliasing products in the output. Careful design ensures minimum ripple and distortion products are added
to the incoming signal. The SRC also determines the ratio between the incoming and outgoing sample rates
and sets the filter corner frequencies appropriately. Any jitter in the incoming signal has little impact on the
dynamic performance of the rate converter and has no influence on the output clock.
4.3.1 Data Resolution and Dither
When using the serial audio input port in Left-Justified and I²S Modes, all input data is treated as 32-bits
wide. Any truncation that has been done prior to the CS8421 to less than 32-bits should have been done
using an appropriate dithering process. If the serial audio input port is in Right-Justified Mode, the input
data will be truncated to the bit depth set by SAIF pin setting. If the SAIF bit depth is set to 16-, 20-, or 24-
bits, and the input data is 32-bits wide, truncation distortion will occur. Similarly, in any serial audio input
port mode, if an inadequate number of bit clocks are entered (i.e. 16 clocks instead of 20 clocks), the input
words will be truncated, causing truncation distortion at low levels. In summary, there is no dithering
mechanism on the input side of the CS8421, and care must be taken to ensure that no truncation occurs.
Dithering is used internally where appropriate inside the SRC block.
The output side of the SRC can be set to 16-, 20-, 24-, or 32-bits. Dithering is applied and is automatically
scaled to the selected output word length. This dither is not correlated between left and right channels.
4.3.2 SRC Locking and Varispeed
The SRC calculates the ratio between the input sample rate and the output sample rate and uses this in-
formation to set up various parameters inside the SRC block. The SRC takes some time to make this cal-
culation, approximately 4200/Fso (87.5 ms at Fso of 48 kHz).
If Fsi is changing, as in a varispeed application, the SRC will track the incoming sample rate. During this
tracking mode, the SRC will still rate convert the audio data, but at increased distortion levels. Once the
incoming sample rate is stable, the SRC will return to normal levels of audio quality. The data buffer in the
SRC can overflow if the input sample rate changes at greater than 10%/sec. There is no provision for vari-
speed applications where Fso is changing.
The SRC_UNLOCK pin is used to indicate when the SRC is not locked. When RST is asserted, or if there
is a change in Fsi or Fso, SRC_UNLOCK will be set high. The SRC_UNLOCK pin will continue to be high
until the SRC has reacquired lock and settled, at which point it will transition low. When the SRC_UN-
LOCK pin is set low, SDOUT is outputting valid audio data. This can be used to signal a DAC to unmute
its output.
4.3.3 Bypass Mode
When the BYPASS pin is set high, the input data bypasses the sample rate converter and is sent directly
to the serial audio output port. No dithering is performed on the output data. This mode is ideal for passing
non-audio data through without a sample-rate conversion. ILRCK and OLRCK should be the same sam-
ple rate and synchronous in this mode. The group delay in this mode is greatly reduced from normal SRC
mode as noted in the “Digital Filter Characteristics” on page 11.
__- __— __— _— __— CIRRUS LOGIC”
20 DS641F7
CS8421
4.3.4 Muting
The SDOUT pin is set to all zero output (full mute) immediately after the RST pin is set high. When the
output from the SRC becomes valid, though the SRC may not have reached full performance, SDOUT is
unmuted over a period of approximately 4096 OLRCK cycles (soft unmuted). When the output becomes
invalid, depending on the condition, SDOUT is either immediately set to all zero output (hard muted) or
SDOUT is muted over a period of approximately 4096 OLRCK cycles until it reaches full mute (soft mut-
ed). The SRC will soft mute SDOUT if there is an illegal ratio between ILRCK and the XTI master clock.
Conditions that will cause the SRC to hard mute SDOUT include removing OLRCK, the RST pin being
set low, or illegal ratios between OLRCK and the XTI master clock. After all invalid states have been
cleared, the SRC will soft unmute SDOUT.
4.3.5 Group Delay and Phase Matching Between Multiple CS8421 Parts
The equation for the group delay through the sample rate converter is shown in “Digital Filter Character-
istics” on page 11. This phase delay is equal across multiple parts. Therefore, when multiple parts operate
at the same Fsi and Fso and use a common XTI/XTO clock, their output data is phase matched.
4.3.6 Master Clock
The CS8421 uses the clock signal supplied through XTI as its master clock (MCLK). MCLK can be sup-
plied from a digital clock source, a crystal oscillator, or a fundamental mode crystal. Figure 10 shows the
typical connection diagram for using a fundamental mode crystal. Please refer to the crystal manufactur-
er’s specifications for the external capacitor recommendations. If XTO is not used, such as with a digital
clock source or crystal oscillator, XTO should be left unconnected or pulled low through a 47 k resistor
to GND.
If either serial audio port is set as master, MCLK will be used to supply the sub-clocks to the master SCLK
and LRCK. In this case, MCLK will be synchronous to the master serial audio port. If both serial audio
ports are set as slave, MCLK can be asynchronous to either or both ports. If the user needs to change the
clock source to XTI while the CS8421 is still powered on and running, a RESET must be issued once the
XTI clock source is present and valid to ensure proper operation.
When both serial ports are configured as slave and operating at sample rates less than 96 kHz, the
CS8421 has the ability to operate without a master clock input through XTI. This benefits the design by
not requiring extra external clock components (lowering production cost) and not requiring a master clock
to be routed to the CS8421, resulting in lowered noise contribution in the system. In this mode, an internal
oscillator provides the clock to run all of the internal logic. To enable the internal oscillator, simply tie XTI
to GND or VL. In this mode, XTO should be left unconnected.
The CS8421 can also provide a buffered MCLK output through the MCLK_OUT pin. This pin can be used
to supply MCLK to other system components that operate synchronously to MCLK. If MCLK_OUT is not
needed, the output of the pin can be disabled by pulling the pin high through a 47 k resistor to VL. MC-
LK_OUT is also disabled when using the internal oscillator mode. The MCLK_OUT pin will be set low
when disabled by using the internal oscillator mode.
__- __— __— _— __— CIRRUS LOGIC” V—V m,,,m::m::u7fli::M:M:M:M:fl \ C] \ C] \ [I \ C] | C] \ C] | [I \ [I \ \ \ \ \ \ \ | \ \
DS641F7 21
CS8421
4.3.7 Clocking
In order to ensure proper operation of the CS8421, the clock or crystal attached to XTI must simultane-
ously satisfy the requirements of LRCK for both the input and output as follows:
If the input is set to master, Fsi XTI/128 and Fso XTI/130.
If the output is set to master, Fso XTI/128 and Fsi XTI/130.
If both input and output are set to slave, XTI 130*[maximum(Fsi,Fso)], XTI/Fsi < 3750, and XTI/Fso <
3750.
4.4 Time Division Multiplexing (TDM) Mode
TDM Mode allows several CS8421 to be serially connected together allowing their corresponding SDOUT
data to be multiplexed onto one line for input into a DSP or other TDM-capable multichannel device.
The CS8421 can operate in two TDM modes. The first mode consists of all of the CS8421’s output ports set
to slave, as shown in Figure 13. The second mode consists of one CS8421 output port set to master and
the remaining CS8421’s output ports set to slave, as shown in Figure 14.
The TDM_IN pin is used to input the data, while the SDOUT pin is used to output the data. The first CS8421
in the chain should have its TDM_IN set to GND. Data is transmitted from SDOUT most significant bit first
on the first OSCLK falling edge after an OLRCK transition and is valid on the rising edge of OSCLK.
In TDM Slave Mode, the number of channels that can be multiplexed to one serial data line depends on the
output sampling rate. For Slave Mode, OSCLK must operate at N*64*Fso, where N is the number of
CS8421’s connected together. The maximum allowable OSCLK frequency is 24.576 MHz, so for Fso =
48 kHz, N = 8 (16 channels of serial audio data).
In TDM Master Mode, OSCLK operates at 256*Fso, which is equivalent to N = 4, so a maximum of 8 chan-
nels of digital audio can be multiplexed together. Note that for TDM Master Mode, MCLK must be at least
256*Fso, where Fso 96 kHz. OLRCK identifies the start of a new frame. Each time-slot is 32-bits wide,
with the valid data sample left-justified within the time-slot. Valid data lengths are 16-, 20-, 24- or 32-bits.
Figures 11 and 12 show the interface format for Master and Slave TDM Modes with a 32-bit word-length.
XTI XTO
CC
R
Figure 10. Typical Connection Diagram for Crystal Circuit
OLRCK
OSCLK
LSBMSB LSBMSB LSBMSB LSBMSB LSBMSB LSBMSB
SDOUT/
TDM_IN
SDOUT 3, ch A
32 clks 32 clks 32 clks 32 clks 32 clks 32 clks
LSBMSB LSBMSB
32 clks 32 clks
SDOUT 3, ch B SDOUT 2, ch A SDOUT 2, ch B SDOUT 1, ch A SDOUT 1, ch B
SDOUT 4, ch A SDOUT 4, ch B
Figure 11. TDM Slave Mode Timing Diagram
__- __— __— _— _— CIRRUS LOGIC“ J—l—I—V W m """ W 7777 M 77777 M 7777 W mm """ fl \ [I \ {I} \ [I \ C] | [I \ C] \ C] \ C} \ :1 “a
22 DS641F7
CS8421
4.5 Reset, Power-Down, and Start-Up
When RST is low, the CS8421 enters a low-power mode, all internal states are reset, and the outputs are
disabled. After RST transitions from low to high, the part senses the resistor value on the configuration pins
(MS_SEL, SAIF, and SAOF) and sets the appropriate mode of operation. After the mode has been set (ap-
proximately 4 s), the part is set to normal operation and all outputs are functional.
OLRCK
OSCLK
LSBMSB LSBMSB LSBMSB LSBMSB LSBMSB LSBMSB
SDOUT/
TDM_IN
SDOUT 3, ch A
32 clks 32 clks 32 clks 32 clks 32 clks 32 clks
LSBMSB LSBMSB
32 clks 32 clks
SDOUT 3, ch B SDOUT 2, ch A SDOUT 2, ch B SDOUT 1, ch A SDOUT 1, ch B
SDOUT 4, ch A SDOUT 4, ch B
256 OSCLKs
Figure 12. TDM Master Mode Timing Diagram
ILRCK
ISCLK
SDIN
OLRCK
OSCLK
SDOUTTDM_IN
OLRCK
OSCLK
SDOUTTDM_IN
ILRCK
ISCLK
SDIN
Output
Clock
Source
LRCK
SCLK
OLRCK OSCLK SDOUT
PCM Source 2
OLRCK OSCLK SDOUT
PCM Source 1
CS84211
Slave
CS84212
Slave
LRCK
SCLK
SDIN
DSP
Slave
OLRCK
OSCLK
SDOUTTDM_IN
ILRCK
ISCLK
SDIN
CS84213
Slave
OLRCK
OSCLK
SDOUTTDM_IN
ILRCK
ISCLK
SDIN
CS84214
Slave
OLRCK OSCLK SDOUT
PCM Source 3
OLRCK OSCLK SDOUT
PCM Source 4
Figure 13. TDM Mode Configuration (All CS8421 Outputs are Slave)
ILRCK
ISCLK
SDIN
OLRCK
OSCLK
SDOUTTDM_IN
CS84211
OLRCK OSCLK SDOUT
PCM Source 2
OLRCK OSCLK SDOUT
PCM Source 1
Master
LRCK
SCLK
SDIN
DSP
Slave
OLRCK
OSCLK
SDOUTTDM_IN
ILRCK
ISCLK
SDIN
CS84214
Slave
OLRCK
OSCLK
SDOUTTDM_IN
ILRCK
ISCLK
SDIN
CS84212
Slave
OLRCK
OSCLK
SDOUTTDM_IN
ILRCK
ISCLK
SDIN
CS84213
Slave
OLRCK OSCLK SDOUT
PCM Source 3
OLRCK OSCLK SDOUT
PCM Source 4
Figure 14. TDM Mode Configuration (First CS8421 Output is Master, All Others are Slave)
__- __— __— _— __— CIRRUS LOGIC”
DS641F7 23
CS8421
4.6 Power Supply, Grounding, and PCB Layout
The CS8421 operates from a VD = +2.5 V and VL = +3.3 V or +5.0 V supply. The supplies should be applied
and removed together or the VL supply should be applied first and removed last. Follow normal supply de-
coupling practices; see Figure 6.
Extensive use of power and ground planes, ground-plane fill in unused areas, and surface-mount decou-
pling capacitors are recommended. Decoupling capacitors should be mounted on the same side of the
board as the CS8421 to minimize inductance effects, and all decoupling capacitors should be as close to
the CS8421 as possible. The pin of the configuration resistors not connected to MS_SEL, SAIF, and SAOF
should be connected as close as possible to VL or GND.
The CS8421 is available in the compact QFN package. The underside of the QFN package reveals a metal
pad that serves as a thermal relief to provide for optimal heat dissipation. This pad must mate with an equally
dimensioned copper pad on the PCB and must be electrically connected to ground. A series of vias should
be used to connect this copper pad to one or more larger ground planes on other PCB layers.
__- __— __— _— _— CIRRUS LOGIC“
24 DS641F7
CS8421
5. PERFORMANCE PLOTS
-200
+0
-180
-160
-140
-120
-100
-80
-60
-40
-20
d
B
F
S
5k 20k10k 15k
Hz
-200
+0
-180
-160
-140
-120
-100
-80
-60
-40
-20
d
B
F
S
20k 80k40k 60k
Hz
Figure 15. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz
Tone, 48 kHz:48 kHz
Figure 16. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz
Tone, 44.1 kHz:192 kHz
-200
+0
-180
-160
-140
-120
-100
-80
-60
-40
-20
d
B
F
S
5k 20k10k 15k
Hz
-200
+0
-180
-160
-140
-120
-100
-80
-60
-40
-20
d
B
F
S
2.5k 20k5k 7.5k 10k 12.5k 15k 17.5k
Hz
Figure 17. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz
Tone, 44.1 kHz:48 kHz
Figure 18. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz
Tone, 48 kHz:44.1 kHz
-200
+0
-180
-160
-140
-120
-100
-80
-60
-40
-20
d
B
F
S
10k 40k20k 30k
Hz
-200
+0
-180
-160
-140
-120
-100
-80
-60
-40
-20
d
B
F
S
5k 20k10k 15k
Hz
Figure 19. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz
Tone, 48 kHz:96 kHz
Figure 20. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz
Tone, 96 kHz:48 kHz
__- __— __— _— _— CIRRUS LOGIC“
DS641F7 25
CS8421
-200
+0
-180
-160
-140
-120
-100
-80
-60
-40
-20
d
B
F
S
5k 20k10k 15k
Hz
-200
-60
-180
-160
-140
-120
-100
-80
d
B
F
S
10k 40k20k 30k
Hz
Figure 21. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz
Tone, 192 kHz:48 kHz
Figure 22. Wideband FFT Plot (16k Points) -60 dBFS
1 kHz Tone, 48 kHz:96 kHz
-200
-60
-180
-160
-140
-120
-100
-80
d
B
F
S
5k 20k10k 15k
Hz
-200
-60
-180
-160
-140
-120
-100
-80
d
B
F
S
20k 80k40k 60k
Hz
Figure 23. Wideband FFT Plot (16k Points) -60 dBFS
1 kHz Tone, 48 kHz:48 kHz
Figure 24. Wideband FFT Plot (16k Points) -60 dBFS
1 kHz Tone, 44.1 kHz:192 kHz
-200
-60
-180
-160
-140
-120
-100
-80
d
B
F
S
5k 20k10k 15k
Hz
-200
-60
-180
-160
-140
-120
-100
-80
d
B
F
S
2.5k 20k5k 7.5k 10k 12.5k 15k 17.5k
Hz
Figure 25. Wideband FFT Plot (16k Points) -60 dBFS
1 kHz Tone, 44.1 kHz:48 kHz
Figure 26. Wideband FFT Plot (16k Points) -60 dBFS
1 kHz Tone, 48 kHz:44.1 kHz
__- __— __— _— _— CIRRUS LOGIC“
26 DS641F7
CS8421
-200
-60
-180
-160
-140
-120
-100
-80
d
B
F
S
5k 20k10k 15k
Hz
-200
+0
-180
-160
-140
-120
-100
-80
-60
-40
-20
d
B
F
S
5k 20k10k 15k
Hz
Figure 27. Wideband FFT Plot (16k Points) -60 dBFS
1 kHz Tone, 96 kHz:48 kHz
Figure 28. IMD, 10 kHz and 11 kHz -7 dBFS,
96 kHz:48 kHz
-200
-60
-180
-160
-140
-120
-100
-80
d
B
F
S
5k 20k10k 15k
Hz
-200
+0
-180
-160
-140
-120
-100
-80
-60
-40
-20
d
B
F
S
2.5k 20k5k 7.5k 10k 12.5k 15k 17.5k
Hz
Figure 29. Wideband FFT Plot (16k Points) -60 dBFS
1 kHz Tone, 192 kHz:48 kHz
Figure 30. IMD, 10 kHz and 11 kHz -7 dBFS,
48 kHz:44.1 kHz
-200
+0
-180
-160
-140
-120
-100
-80
-60
-40
-20
d
B
F
S
5k 20k10k 15k
Hz
-200
+0
-180
-160
-140
-120
-100
-80
-60
-40
-20
d
B
F
S
5k 20k10k 15k
Hz
Figure 31. IMD, 10 kHz and 11 kHz -7 dBFS,
44.1 kHz:48 kHz
Figure 32. Wideband FFT Plot (16k Points) 0 dBFS 20 kHz
Tone, 44.1 kHz:48 kHz
__- __— __— _— _— CIRRUS LOGIC“
DS641F7 27
CS8421
-200
+0
-180
-160
-140
-120
-100
-80
-60
-40
-20
d
B
F
S
20k 80k40k 60k
Hz
-200
+0
-180
-160
-140
-120
-100
-80
-60
-40
-20
d
B
F
S
10k 40k20k 30k
Hz
Figure 33. Wideband FFT Plot (16k Points) 0 dBFS 80 kHz
Tone, 192 kHz:192 kHz
Figure 34. Wideband FFT Plot (16k Points) 0 dBFS 20 kHz
Tone, 48 kHz:96 kHz
-200
+0
-180
-160
-140
-120
-100
-80
-60
-40
-20
d
B
F
S
5k 20k10k 15k
Hz
-200
+0
-180
-160
-140
-120
-100
-80
-60
-40
-20
d
B
F
S
5k 20k10k 15k
Hz
Figure 35. Wideband FFT Plot (16k Points) 0 dBFS 20 kHz
Tone, 48 kHz:48 kHz
Figure 36. Wideband FFT Plot (16k Points) 0 dBFS 20 kHz
Tone, 96 kHz:48 kHz
-200
+0
-180
-160
-140
-120
-100
-80
-60
-40
-20
d
B
F
S
2.5k 20k5k 7.5k 10k 12.5k 15k 17.5k
Hz
-150
-120
-147.5
-145
-142.5
-140
-137.5
-135
-132.5
-130
-127.5
-125
-122.5
d
B
F
S
50k 175k75k 100k 125k 150k
Hz
Figure 37. Wideband FFT Plot (16k Points) 0 dBFS 20 kHz
Tone, 48 kHz:44.1 kHz
Figure 38. THD+N vs. Output Sample Rate, 0 dBFS 1 kHz
Tone, Fsi = 192 kHz
__- __— __— _— _— CIRRUS LOGIC“
28 DS641F7
CS8421
-150
-120
-147.5
-145
-142.5
-140
-137.5
-135
-132.5
-130
-127.5
-125
-122.5
d
B
F
S
50k 175k75k 100k 125k 150k
Hz
-150
-120
-147.5
-145
-142.5
-140
-137.5
-135
-132.5
-130
-127.5
-125
-122.5
d
B
F
S
50k 175k75k 100k 125k 150k
Hz
Figure 39. THD+N vs. Output Sample Rate, 0 dBFS 1 kHz
Tone, Fsi = 48 kHz
Figure 40. THD+N vs. Output Sample Rate, 0 dBFS 1 kHz
Tone, Fsi = 96 kHz
-150
-120
-147.5
-145
-142.5
-140
-137.5
-135
-132.5
-130
-127.5
-125
-122.5
d
B
F
S
50k 175k75k 100k 125k 150k
Hz
-145
-135
-144
-143
-142
-141
-140
-139
-138
-137
-136
d
B
F
S
50k 175k75k 100k 125k 150k
Hz
Figure 41. THD+N vs. Output Sample Rate, 0 dBFS 1 kHz
Tone, Fsi = 44.1 kHz
Figure 42. Dynamic Range vs. Output Sample Rate, -
60 dBFS 1 kHz Tone, Fsi = 192 kHz
-150
-120
-147.5
-145
-142.5
-140
-137.5
-135
-132.5
-130
-127.5
-125
-122.5
d
B
F
S
50k 175k75k 100k 125k 150k
Hz
-150
-120
-147.5
-145
-142.5
-140
-137.5
-135
-132.5
-130
-127.5
-125
-122.5
d
B
F
S
50k 175k75k 100k 125k 150k
Hz
Figure 43. THD+N vs. Output Sample Rate, 0 dBFS 1 kHz
Tone, Fsi = 32 kHz
Figure 44. Dynamic Range vs. Output Sample Rate, -
60 dBFS 1 kHz Tone, Fsi = 32 kHz
__- __— __— _— _— CIRRUS LOGIC“
DS641F7 29
CS8421
-150
-120
-147.5
-145
-142.5
-140
-137.5
-135
-132.5
-130
-127.5
-125
-122.5
d
B
F
S
50k 175k75k 100k 125k 150k
Hz
-150
-120
-147.5
-145
-142.5
-140
-137.5
-135
-132.5
-130
-127.5
-125
-122.5
d
B
F
S
50k 175k75k 100k 125k 150k
Hz
Figure 45. Dynamic Range vs. Output Sample Rate, -
60 dBFS 1 kHz Tone, Fsi = 96 kHz
Figure 46. Dynamic Range vs. Output Sample Rate, -
60 dBFS 1 kHz Tone, Fsi = 44.1 kHz
-140
+0
-120
-100
-80
-60
-40
-20
d
B
F
S
0 60k10k 20k 30k 40k 50k
Hz
192 kHz:32 kHz
192 kHz:48 kHz
192 kHz:96 kHz
-0.2
+0
-0.18
-0.16
-0.14
-0.12
-0.1
-0.08
-0.06
-0.04
-0.02
d
B
F
S
0 25k5k 10k 15k 20k
Hz
Figure 47. Frequency Response with 0 dBFS Input Figure 48. Passband Ripple, 192 kHz:48 kHz
-150
-120
-147.5
-145
-142.5
-140
-137.5
-135
-132.5
-130
-127.5
-125
-122.5
d
B
F
S
50k 175k75k 100k 125k 150k
Hz
-140
+0
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
F
S
-140 +0-120 -100 -80 -60 -40 -20
dBFS
Figure 49. Dynamic Range vs. Output Sample Rate, -
60 dBFS 1 kHz Tone, Fsi = 48 kHz
Figure 50. Linearity Error, 0 to -140 dBFS Input, 200 Hz
Tone, 48 kHz:48 kHz
__- __— __— _— _— CIRRUS LOGIC“
30 DS641F7
CS8421
-140
+0
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
F
S
-140 +0-120 -100 -80 -60 -40 -20
dBFS
-140
+0
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
F
S
-140 +0-120 -100 -80 -60 -40 -20
dBFS
Figure 51. Linearity Error, 0 to -140 dBFS Input, 200 Hz
Tone, 48 kHz:44.1 kHz
Figure 52. Linearity Error, 0 to -140 dBFS Input, 200 Hz
Tone, 48 kHz:96 kHz
-140
+0
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
F
S
-140 +0-120 -100 -80 -60 -40 -20
dBFS
-140
+0
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
F
S
-140 +0-120 -100 -80 -60 -40 -20
dBFS
Figure 53. Linearity Error, 0 to -140 dBFS Input, 200 Hz
Tone, 96 kHz:48 kHz
Figure 54. Linearity Error, 0 to -140 dBFS Input, 200 Hz
Tone, 44.1 kHz:192 kHz
-140
+0
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
F
S
-140 +0-120 -100 -80 -60 -40 -20
dBFS
-140
+0
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
F
S
-140 +0-120 -100 -80 -60 -40 -20
dBFS
Figure 55. Linearity Error, 0 to -140 dBFS Input, 200 Hz
Tone, 44.1 kHz:48 kHz
Figure 56. Linearity Error, 0 to -140 dBFS Input, 200 Hz
Tone, 192 kHz:44.1 kHz
__- __— __— _— _— CIRRUS LOGIC“
DS641F7 31
CS8421
-180
-110
-175
-170
-165
-160
-155
-150
-145
-140
-135
-130
-125
-120
-115
d
B
F
S
-140 +0-120 -100 -80 -60 -40 -20
dBFS
-180
-110
-175
-170
-165
-160
-155
-150
-145
-140
-135
-130
-125
-120
-115
d
B
F
S
-140 +0-120 -100 -80 -60 -40 -20
dBFS
Figure 57. THD+N vs. Input Amplitude, 1 kHz Tone,
48 kHz:44.1 kHz
Figure 58. THD+N vs. Input Amplitude, 1 kHz Tone,
48 kHz:96 kHz
-180
-110
-175
-170
-165
-160
-155
-150
-145
-140
-135
-130
-125
-120
-115
d
B
F
S
-140 +0-120 -100 -80 -60 -40 -20
dBFS
-180
-110
-175
-170
-165
-160
-155
-150
-145
-140
-135
-130
-125
-120
-115
d
B
F
S
-140 +0-120 -100 -80 -60 -40 -20
dBFS
Figure 59. THD+N vs. Input Amplitude, 1 kHz Tone,
96 kHz:48 kHz
Figure 60. THD+N vs. Input Amplitude, 1 kHz Tone,
44.1 kHz:192 kHz
-180
-110
-175
-170
-165
-160
-155
-150
-145
-140
-135
-130
-125
-120
-115
d
B
F
S
-140 +0-120 -100 -80 -60 -40 -20
dBFS
-180
-110
-175
-170
-165
-160
-155
-150
-145
-140
-135
-130
-125
-120
-115
d
B
F
S
-140 +0-120 -100 -80 -60 -40 -20
dBFS
Figure 61. THD+N vs. Input Amplitude, 1 kHz Tone,
44.1 kHz:48 kHz
Figure 62. THD+N vs. Input Amplitude, 1 kHz Tone,
192kHz:48kHz
__- __— __— _— _— CIRRUS LOGIC“
32 DS641F7
CS8421
All performance plots represent typical performance. Measurements for all performance plots were taken under the
following conditions, unless otherwise stated:
VD = 2.5 V, VL = 3.3 V
Serial Audio Input port set to slave
Serial Audio Output port set to slave
Input and output clocks and data are asynchronous
XTI/XTO = 27 MHz
Input signal = 1.000 kHz, 0 dBFS
Measurement Bandwidth = 20 to (Fso/2) Hz
Word Width = 24 Bits
-180
-110
-175
-170
-165
-160
-155
-150
-145
-140
-135
-130
-125
-120
-115
d
B
F
S
0 20k2.5k 5k 7.5k 10k 12.5k 15k 17.5k
Hz
-180
-110
-175
-170
-165
-160
-155
-150
-145
-140
-135
-130
-125
-120
-115
d
B
F
S
-140 +0-120 -100 -80 -60 -40 -20
dBFS
Figure 63. THD+N vs. Frequency Input, 0 dBFS,
48 kHz:44.1 kHz
Figure 64. THD+N vs. Frequency Input, 0 dBFS,
48 kHz:96 kHz
-180
-110
-175
-170
-165
-160
-155
-150
-145
-140
-135
-130
-125
-120
-115
d
B
F
S
0 20k2.5k 5k 7.5k 10k 12.5k 15k 17.5k
Hz
-180
-110
-175
-170
-165
-160
-155
-150
-145
-140
-135
-130
-125
-120
-115
d
B
F
S
0 20k2.5k 5k 7.5k 10k 12.5k 15k 17.5k
Hz
Figure 65. THD+N vs. Frequency Input, 0 dBFS,
44.1 kHz:48 kHz
Figure 66. THD+N vs. Frequency Input, 0 dBFS,
96 kHz:48 kHz
__- __— __— _— _— CIRRUS LOGIC“ 1 ¢ 4 O DIM MIN NOM MAX MIN NOM MAX A » -» 0,043 -- -- 1.10 A1 0.002 0.004 0,006 0,05 -- 0.15 A2 0.03346 0.0354 0,037 0,85 0,90 0.95 b 0.00748 0.0096 0,012 0.19 0.245 0.30 2,3 D 0.252 0.256 0,259 6,40 6,50 6.60 1 E 0.248 0.2519 0,256 6,30 6,40 6.50 E1 0.169 0.1732 0,177 4,30 4,40 4.50 1 e » -» 0,026 -- -- 0.65 L 0.020 0.024 0,028 0,50 0,60 0.70 0" 4" 8° 0° 4° 8°
DS641F7 33
CS8421
6. PACKAGE DIMENSIONS
Notes:
1. “D” and “E1” are reference datums and do not include mold flash or protrusions, but do include mold mismatch and
are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side.
2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in
excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more
than 0.07 mm at least material condition.
3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
TSSOP THERMAL CHARACTERISTICS
INCHES MILLIMETERS NOTE
DIM MIN NOM MAX MIN NOM MAX
A -- -- 0.043 -- -- 1.10
A1 0.002 0.004 0.006 0.05 -- 0.15
A2 0.03346 0.0354 0.037 0.85 0.90 0.95
b 0.00748 0.0096 0.012 0.19 0.245 0.30 2,3
D 0.252 0.256 0.259 6.40 6.50 6.60 1
E 0.248 0.2519 0.256 6.30 6.40 6.50
E1 0.169 0.1732 0.177 4.30 4.40 4.50 1
e -- -- 0.026 -- -- 0.65
L 0.020 0.024 0.028 0.50 0.60 0.70
µ0° 8°
JEDEC #: MO-153
Controlling Dimension is Millimeters.
Parameter Symbol Min Typ Max Units
Junction to Ambient Thermal Impedance 2 Layer Board
4 Layer Board JA
-
-
48
38
-
-
°C/Watt
°C/Watt
20L TSSOP (4.4 MM BODY) PACKAGE DRAWING
E
N
123
eb2A1
A2 A
D
SEATING
PLANE
E11
L
SIDE VIEW
END VIEW
TOP VIEW
__- __— __— _— _— CIRRUS LOGIC“ 20-PIN QFN (5 x 5 MM BODY) PACKAGE DRAWING \ INCHES MILLIMETERS
34 DS641F7
CS8421
1. Dimensioning and tolerance per ASME Y 14.5M-1995.
2. Dimensioning lead width applies to the plated terminal and is measured between 0.23mm and 0.33mm from the
terminal tip.
QFN THERMAL CHARACTERISTICS
INCHES MILLIMETERS NOTE
DIM MIN NOM MAX MIN NOM MAX
A -- -- 0.0394 -- -- 1.00 1
A1 0.0000 -- 0.0020 0.00 -- 0.05 1
b 0.0091 0.0110 0.0130 0.23 0.28 0.33 1, 2
D 0.1969 BSC 5.00 BSC 1
D2 0.1201 0.1220 0.1240 3.05 3.10 3.15 1
E 0.1969 BSC 5.00 BSC 1
E2 0.1202 0.1221 0.1241 3.05 3.10 3.15 1
e 0.0256 BSC 0.65 BSC 1
L 0.0197 0.0236 0.0276 0.50 0.60 0.70 1
JEDEC #: MO-220
Controlling Dimension is Millimeters.
Parameter Symbol Min Typ Max Units
Junction to Ambient Thermal Impedance 2 Layer Board
4 Layer Board JA
-
-
128
35
-
-
°C/Watt
°C/Watt
Side View
A
A1 D2
L
bePin #1 Corner
Bottom View
Top View
Pin #1 Corner
D
EE2
20-PIN QFN (5 5 MM BODY) PACKAGE DRAWING
__- __— __— _— __— CIRRUS LOGIC” 058421 Rail 058421 -0ZZ Tape and Reel CSBAZ1-CZZR Rail CS84Z1-0NZ Tape and Reel CSBAZ1»CNZR Rail 058421 -DZZ Tape and Reel CSBAZ1-DZZR Rail 088421»EZZ Tape and Reel CSB421-EZZR Rail CSBAZl-ENZ Tape and Reel C584Z1-ENZR CD38421 Evalualion Board for 088421 - - » 0DB8421 Added ~40“ lo +105°C Aulomolive grade lo feaiure liSl on page 23. F6 Added nore regarding lhe SDOUT pin in Figure 5 and Figure 6. F7 Updaled power supply sequencing in Section 4.6 Power Supply, Grounding, and PCB Layoul.
DS641F7 35
CS8421
7. ORDERING INFORMATION
8. REVISION HISTORY
Release Changes
F5
JUL ‘10
Added -40° to +105°C Automotive grade to feature list on page 23.
Added Ambient Operating Temperature entry for ‘-EZ’ and ‘-ENZ’ in “Specified Operating Conditions” on page 9.
Added entries for CS8421-EZZ/ENZ and CS8421-EZZR/ENZR in “Ordering Information” on page 35.
F6
JUL ‘12
Added note regarding the SDOUT pin in Figure 5 and Figure 6.
F7
AUG ‘15
Updated power supply sequencing in Section 4.6 Power Supply, Grounding, and PCB Layout.
Updated legal text.
Product Description Package Pb-Free Temp Range Container Order#
CS8421
32-bit Asynchronous Sample Rate
Converter
20-TSSOP
YES
-10° to +70°C
Rail CS8421-CZZ
Tape and Reel CS8421-CZZR
20-QFN Rail CS8421-CNZ
Tape and Reel CS8421-CNZR
20-TSSOP -40° to +85°C Rail CS8421-DZZ
Tape and Reel CS8421-DZZR
20-TSSOP
-40° to +105°C
Rail CS8421-EZZ
Tape and Reel CS8421-EZZR
20-QFN Rail CS8421-ENZ
Tape and Reel CS8421-ENZR
CDB8421 Evaluation Board for CS8421 - - - CDB8421
__- __— __— _— __— CIRRUS LOGIC” www.cirrus.com
36 DS641F7
CS8421
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative.
To find the one nearest to you, go to www.cirrus.com.
IMPORTANT NOTICE
The products and services of Cirrus Logic International (UK) Limited; Cirrus Logic, Inc.; and other companies in the Cirrus Logic group (collectively either
“Cirrus Logic” or “Cirrus”) are sold subject to Cirrus Logic’s terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, indemnification, and limitation of liability. Software is provided pursuant to applicable license terms. Cirrus Logic reserves the right
to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest
version of relevant information from Cirrus Logic to verify that the information is current and complete. Testing and other quality control techniques are
utilized to the extent Cirrus Logic deems necessary. Specific testing of all parameters of each device is not necessarily performed. In order to minimize
risks associated with customer applications, the customer must use adequate design and operating safeguards to minimize inherent or procedural
hazards. Cirrus Logic is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of
Cirrus Logic products.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE
PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS LOGIC PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR
WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, NUCLEAR SYSTEMS,
LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS LOGIC PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD
TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS LOGIC DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED,
INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS LOGIC
PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS LOGIC
PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS LOGIC, ITS OFFICERS, DIRECTORS,
EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT
FROM OR ARISE IN CONNECTION WITH THESE USES.
This document is the property of Cirrus Logic and by furnishing this information, Cirrus Logic grants no license, express or implied, under any patents,
mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Any provision or publication of any third party’s products or
services does not constitute Cirrus Logic’s approval, license, warranty or endorsement thereof. Cirrus Logic gives consent for copies to be made of the
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only if the reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices and conditions (including this
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