ADUC7023 Datasheet by Analog Devices Inc.

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ANALOG Precision Analog Microcontroller, 12-Bit Analog DEVICES I/o, ARM7TDM| MCU with Enhanced IRu Handler ADu87023
Precision Analog Microcontroller, 12-Bit Analog
I/O, ARM7TDMI MCU with Enhanced IRQ Handler
Data Sheet
ADuC7023
FEATURES
Analog I/O
Multichannel, 12-bit, 1 MSPS ADC
Up to 12 ADC channels
Fully differential and single-ended modes
0 V to VREF analog input range
12-bit voltage output DACs
4 DAC outputs available
On-chip voltage reference
On-chip temperature sensor
Voltage comparator
Microcontroller
ARM7TDMI core, 16-bit/32-bit RISC architecture
JTAG port supports code download and debug
Clocking options
Trimmed on-chip oscillator (±3%)
External watch crystal
External clock source up to 44 MHz
41.78 MHz PLL with programmable divider
Memory
62 kB Flash/EE memory, 8 kB SRAM
In-circuit download, JTAG-based debug
Software-triggered in-circuit reprogrammability
Vectored interrupt controller for FIQ and IRQ
8 priority levels for each interrupt type
Interrupt on edge or level external pin inputs
On-chip peripherals
fully I2C-compatible channels
SPI (20 Mbps in master mode, 10 Mbps in slave mode)
With 4-byte FIFO on input and output stages
Up to 20 GPIO pinsDigital only GPIOs are 5 V tolerant
3× general-purpose timers
Watchdog timer (WDT)
Programmable logic array (PLA)
16 PLA elements
16-bit, 5-channel PWM
Power
Specified for 3 V operation
Active mode: 11 mA at 5 MHz, 28 mA at 41.78 MHz
Packages and temperature range
32-lead 5 mm × 5 mm LFCSP
40-lead LFCSP
36-Lead WLCSP
Fully specified for 40°C to +125°C operation
Tools
Low cost QuickStart development system
Full third-party support
APPLICATIONS
Optical networking
Industrial control and automation systems
Smart sensors, precision instrumentation
Base station systems
GENERAL DESCRIPTION
The ADuC7023 is a fully integrated, 1 MSPS, 12-bit data acquisition
system, incorporating high performance multichannel ADCs,
16-bit/32-bit MCUs, and Flash/EE memory on a single chip.
The ADC consists of up to 12 single-ended inputs. An additional four
inputs are available but are multiplexed with the four DAC output
pins. The ADC can operate in single-ended or differential input modes.
The ADC input voltage is 0 V to VREF. A low drift band gap reference,
temperature sensor, and voltage comparator complete the ADC
peripheral set.
The DAC output range is programmable to one of two voltage ranges.
The DAC outputs have an enhanced feature of being able to retain
their output voltage during a watchdog or software reset sequence.
The devices operate from an on-chip oscillator and a PLL, generating
an internal high frequency clock of 41.78 MHz. This clock is routed
through a programmable clock divider from which the MCU core
clock operating frequency is generated. The microcontroller core is an
ARM7TDMI®, 16-bit/32-bit RISC machine that offers up to 41 MIPS
peak performance. Eight kilobytes of SRAM and 62 kilobytes of
nonvolatile Flash/EE memory are provided on chip. The ARM7TDMI
core views all memory and registers as a single linear array.
The ADuC7023 contains an advanced interrupt controller. The
vectored interrupt controller (VIC) allows every interrupt to be
assigned a priority level. It also supports nested interrupts to a
maximum level of eight per IRQ and FIQ. When IRQ and FIQ
interrupt sources are combined, a total of 16 nested interrupt
levels are supported.
On-chip factory firmware supports in-circuit download via the I2C
serial interface port, and nonintrusive emulation is supported via
the JTAG interface. These features are incorporated into a low cost
QuickStart™ development system supporting this MicroConverter®
family. The part contains a 16-bit PWM with five output signals.
For communication purposes, the part contains 2 × I2C channels that
can be individually configured for master or slave mode. An SPI
interface supporting both master and slave modes is also provided.
The parts operate from 2.7 V to 3.6 V and are specified over an
industrial temperature range of −40°C to +125°C. The ADuC7023 is
available in either a 32-lead or 40-lead LFCSP package. A 36-ball
wafer level CSP package (WLCSP) is also available.
Rev. G Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
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Tel: 781.329.4700 ©20102015 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
ADuC7023 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 3
Functional Block Diagram .............................................................. 5
Specifications ..................................................................................... 6
Timing Specifications .................................................................. 9
Absolute Maximum Ratings .......................................................... 14
ESD Caution ................................................................................ 14
Pin Configurations and Function Descriptions ......................... 15
Typical Performance Characteristics ........................................... 19
Terminology .................................................................................... 20
ADC Specifications .................................................................... 20
DAC Specifications..................................................................... 20
Overview of the ARM7TDMI Core ............................................. 21
Thumb Mode (T) ........................................................................ 21
Long Multiply (M) ...................................................................... 21
EmbeddedICE (I) ....................................................................... 21
Exceptions ................................................................................... 21
ARM Registers ............................................................................ 21
Interrupt Latency ........................................................................ 22
Memory Organization ................................................................... 23
Memory Access ........................................................................... 23
Flash/EE Memory ....................................................................... 23
SRAM ........................................................................................... 23
Memory Mapped Registers ....................................................... 23
ADC Circuit Overview .................................................................. 30
Transfer Function ....................................................................... 30
Typical Operation ....................................................................... 31
MMR Interface ............................................................................ 31
Converter Operation .................................................................. 34
Driving the Analog Inputs ........................................................ 35
Calibration ................................................................................... 35
Temperature Sensor ................................................................... 35
Band Gap Reference ................................................................... 37
Nonvolatile Flash/EE Memory ..................................................... 38
Programming .............................................................................. 38
Security ........................................................................................ 39
Flash/EE Control Interface ....................................................... 39
Execution Time from SRAM and Flash/EE ............................ 42
Reset and Remap ........................................................................ 42
Other Analog Peripherals .............................................................. 45
DAC .............................................................................................. 45
Power Supply Monitor ............................................................... 47
Comparator ................................................................................. 47
Oscillator and PLLPower Control ........................................ 49
Digital Peripherals .......................................................................... 52
General-Purpose Input/Output................................................ 52
Serial Peripheral Interface ......................................................... 55
I2C ..................................................................................................... 60
Configuring External Pins for I2C Functionality ................... 60
Serial Clock Generation ............................................................ 60
I2C Bus Addresses ....................................................................... 60
I2C Registers ................................................................................ 61
Programmable Logic Array (PLA)........................................... 68
Pulse-Width Modulator ................................................................. 72
Pulse-Width Modulator General Overview ........................... 72
Processor Reference Peripherals ................................................... 77
Interrupt System ......................................................................... 77
IRQ ............................................................................................... 77
Fast Interrupt Request (FIQ) .................................................... 78
Vectored Interrupt Controller (VIC) ....................................... 79
Timers .......................................................................................... 84
Hardware Design Considerations ................................................... 89
Power Supplies ............................................................................. 89
Grounding and Board Layout Recommendations ................. 90
Clock Oscillator .......................................................................... 90
Power-On Reset Operation ....................................................... 91
Typical System Configuration .................................................. 92
Development Tools......................................................................... 93
PC-Based Tools ........................................................................... 93
In-Circuit I2C Downloader ....................................................... 93
Outline Dimensions ....................................................................... 94
Ordering Guide .......................................................................... 96
Rev. G | Page 2 of 97
Rev. E to Rev ()N V
Data Sheet ADuC7023
REVISION HISTORY
1/15Rev. F to Rev. G
Changes to Table 53 ........................................................................ 51
Changes to I2C Section ................................................................... 60
Changes to Table 65 ........................................................................ 61
Changes to Table 72 ........................................................................ 64
Changes to I2CREPS Bit Description, Table 73 .......................... 66
5/14Rev. E to Rev. F
Change CONVSTART Pin to CONVSTART Pin ................ Throughout
Change to Layout, Power Requirements Parameter, Table 1 ....... 7
Change to Table 8 ............................................................................ 13
Changes to Figure 7 and Table 9 ................................................... 14
Change to Table 21 .......................................................................... 28
Change to Figure 23 ........................................................................ 30
Change to JTAG Access Section .................................................... 37
Changes to Table 36 ........................................................................ 42
Changes to Table 55 ........................................................................ 51
Changes to I2C Bus Addresses Section ......................................... 59
Change to Table 84 .......................................................................... 71
Added PWM2LEN Register Section............................................. 75
7/13Rev. D to Rev. E
Changes to Ordering Guide ........................................................... 95
7/13—Rev. C to Rev. D
Added WLCSP (Throughout) ......................................................... 1
Changes to Features Section ............................................................ 1
Added Shared Analog/Digital Inputs to AGND Rating of −0.3 V
to AV DD + 0.3 V, Endnote 1, and Endnote 2; Table 8 .................. 13
Added Figure 9; Renumbered Sequentially; Added WLCSP Pin
Numbers to Table 9 ......................................................................... 14
Changes to Pin P1.7/PWM3/SDA1/PLAI[6] and Pin
P1.6/PWM2/SCL1/PLAI[5] Descriptions; Table 9 ..................... 16
Changes to ADC Circuit Overview Section, Transfer Function
Section, and Figure 20 Caption ..................................................... 29
Changes to Typical Operation Section, ADCCON Register
Section, and ADCON[13] Description in Table 24 .................... 30
Changes to Bits[4:3] Value 10 Description; Table 24.................. 31
Changes to Converter Operation Section and Deleted Pseudo
Differential Mode Section .............................................................. 33
Changes to Figure 27 and Figure 28 Caption .............................. 34
Changes to Table 30 and Following Text ...................................... 36
Changes to JTAG Access Section .................................................. 37
Changes to References to ADC and the DACs Section ............. 45
Changes to General-Purpose Input/Output Section .................. 51
Changes to SPIDIV Register Section ............................................ 56
Changes to Bits[1:0] Value 01 Description; Table 66.................. 61
Changes to T0CLRI Register Section ........................................... 84
Changes to Figure 53 ...................................................................... 90
Updated Outline Dimensions ........................................................ 93
Changes to Ordering Guide ........................................................... 95
5/12Rev. B to Rev. C
Changed SDATA to SDA and SCLK to SCL, Table 2; SDATA to
SDA and SCLK to SCL, Table 3; and SDATA to SDA and SCLK
to SCL, Figure 2 ................................................................................. 8
Changes to Figure 7, Figure 8, and Table 9 .................................. 14
Changed SCLK to SCL, Table 17 ................................................... 25
Changed SCLK to SCL, Table 18 ................................................... 26
Changes to Bit 6, Table 24 and 4 to 0, Description Column,
Table 25 ............................................................................................. 30
Changed Reference in REFCON Register Section from Table 22
to Table 30 ........................................................................................ 35
Added Note 1 to Table 53 ............................................................... 49
Changes to Note 1, Table 55........................................................... 50
Changed SPICLK (Serial Clock I/O) Pin Section to SCLK
(Serial Clock I/O) Pin Section ....................................................... 53
Changed SPICLK to SCLK in Serial Peripheral Interface Section
and in SCLK (Serial Clock I/O) Pin Section ............................... 53
Changes to Table 79 ........................................................................ 68
Changes to Timers Section ............................................................ 82
Added Hours, Minutes, Seconds, and 1/128 Format Section and
Table 101 ........................................................................................... 82
Changes to T0LD Register Section and T1LD Register Section ..... 83
Changes to T2LD Register Section......................................................... 85
Updated Outline Dimensions........................................................ 92
Changes to Ordering Guide ........................................................... 93
7/10Rev. A to Rev. B
Changes to Temperature Sensor Parameter in Table 1 ................ 6
Change to Table 10 and changes to Table 11 ............................... 23
Changes to Table 12 and Table 13 ................................................. 24
Changes to Table 16 and Table 17 ................................................. 25
Changes to Table 18 ........................................................................ 26
Change to Table 21 and changes to Table 22 ............................... 27
Changes to Table 24 ........................................................................ 29
Changes to ADCGN Register and ADCOF Register Sections . 32
Changes to Temperature Sensor Section ..................................... 34
Changes to Table 29 ........................................................................ 35
Change to REMAP Register and RSTCLR Register Sections ... 41
Change to RSTKEY1 Register and RSTKEY2 Register
Sections ............................................................................................. 42
Changes to Oscillator and PLLPower Control Section .......... 48
Changes to General-Purpose Input/Output Section .................. 51
Changes to Serial Peripheral Interface Section ........................... 53
Changes to Table 75 ........................................................................ 67
Changes to Table 83 and Pulse-Width Modulator General
Overview Section ............................................................................ 70
Changes to Table 84 ........................................................................ 71
Change to Table 85 .......................................................................... 72
Change to FIQSTAN Register Section ......................................... 81
Change to T2CLRI Register Section ............................................. 85
Rev. G | Page 3 of 97
ADuC7023 Data Sheet
6/10Rev. 0 to Rev. A
Changes to Temperature Sensor Parameter in Table 1 ................ 6
Changes to Table 24 ........................................................................ 29
Changes to Temperature Sensor Section ..................................... 34
Changes to DACBKEY0 Register Section and to Table 43 ....... 47
Changes to Ordering Guide .......................................................... 93
1/10Revision 0: Initial Version
Rev. G | Page 4 of 97
Data Sheet ADuC7023
FUNCTIONAL BLOCK DIAGRAM
08675-001
ADuC7023
40-LEAD LFCSP
DAC0
DAC1
DAC2
DAC3
ADC0
XCLKI
XCLKO
RST
V
REF
ADC12
ADC2/CMP0
ADC3/CMP1
CMP
OUT
12-BIT
DAC
12-BIT
DAC
12-BIT
DAC
12-BIT
DAC
VECTORED
INTERRUPT
CONTROLLER
1MSPS
12-BIT ADC
TEMP
SENSOR
BAND GAP
REF
MUX
OSC
AND PLL
PSM
POR
ARM7TDMI-BASED MCU WITH
ADDITIONAL PERIPHERALS
PLA
3 GENERAL-
PURPOSE TIMERS
2k × 32 SRAM
31k × 16 FLASH/EEPROM
SPI, 2 × I
2
C
GPIO
PWM
JTAG
Figure 1.
Rev. G | Page 5 of 97
ADuC7023 Data Sheet
SPECIFICATIONS
AVDD = IOVDD = 2.7 V to 3.6 V, VREF = 2.5 V internal reference, fCORE = 41.78 MHz, TA = −40°C to +125°C, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
ADC CHANNEL SPECIFICATIONS Eight acquisition clocks and fADC/2
ADC Power-Up Time 5 μs
DC Accuracy1, 2
Resolution 12 Bits
Integral Nonlinearity ±0.6 ±1.5 LSB 2.5 V internal reference
±1.0 LSB 1.0 V external reference
Differential Nonlinearity3, 4 ±0.5 +1/−0.9 LSB 2.5 V internal reference
+0.7/−0.6 LSB 1.0 V external reference
DC Code Distribution 1 LSB ADC input is a dc voltage
ENDPOINT ERRORS5
Offset Error ±1 ±2 LSB
Offset Error Match ±1 LSB
Gain Error ±2 LSB
Gain Error Match ±1 LSB
DYNAMIC PERFORMANCE fIN = 10 kHz sine wave, fSAMPLE = 1 MSPS
Signal-to-Noise Ratio (SNR) 69 dB Includes distortion and noise components
Total Harmonic Distortion (THD) −78 dB
Peak Harmonic or Spurious Noise −75 dB
Channel-to-Channel Crosstalk −80 dB Measured on adjacent channels
ANALOG INPUT
Input Voltage Ranges
Differential Mode VCM ± VREF/26 V
Single-Ended Mode 0 to VREF V
Leakage Current ±1 ±6 µA
Input Capacitance 20 pF During ADC acquisition
ON-CHIP VOLTAGE REFERENCE
REF
Output Voltage 2.5 V
Accuracy ±4 mV TA = 25°C
Reference Temperature Coefficient ±15 ppm/°C
Power Supply Rejection Ratio 75 dB
Output Impedance 51 TA = 25°C
Internal VREF Power-On Time 1 ms
EXTERNAL REFERENCE INPUT
Input Voltage Range 0.625 AVDD V
DAC CHANNEL SPECIFICATIONS
DC Accuracy7 RL = 5 kΩ, CL = 100 pF
Resolution 12 Bits
Relative Accuracy ±2 LSB
Differential Nonlinearity ±1 LSB Guaranteed monotonic
Offset Error ±15 mV 2.5 V internal reference
Gain Error8 ±1 %
Gain Error Mismatch 0.1 % % of full scale on DAC0
DC Accuracy9 RL = 1 kΩ, CL = 100 pF
Resolution 12 Bits
Relative Accuracy ±2.5 LSB
Differential Nonlinearity ±1 LSB Guaranteed monotonic
Offset Error
±15
mV
Gain Error
10
±1
%
Gain Error Mismatch
0.1
%
ANALOG OUTPUTS
Output Voltage Range 1 0 to 2.5 V VREF range: AGND to AVDD
Output Voltage Range 2 0 to AVDD V
Output Impedance 2
Rev. G | Page 6 of 97
Data Sheet ADuC7023
Parameter Min Typ Max Unit Test Conditions/Comments
DAC IN OP AMP MODE
DAC Output Buffer in Op Amp Mode
Input Offset Voltage ±0.25 mV
Input Offset Voltage Drift 8 µV/°C
Input Offset Current 0.3 nA
Input Bias Current 0.4 nA
Gain 80 dB 5 kΩ load
Unity-Gain Frequency 5 MHz RL = 5 kΩ, CL = 100 pF
CMRR 80 dB
Settling Time 10 µs RL = 5 kΩ, CL = 100 pF
Output Slew Rate 1.5 V/µs RL = 5 kΩ, CL = 100 pF
PSRR 75 dB
DAC AC CHARACTERISTICS
Voltage Output Settling Time 10 µs
Digital-to-Analog Glitch Energy ±20 nV-sec 1 LSB change at major carry (where maximum number of
bits simultaneously change in the DACxDAT register)
COMPARATOR
Input Offset Voltage ±10 mV
Input Bias Current
1
µA
Input Voltage Range AGND AVDD 1.2 V
Input Capacitance
7
pF
Hysteresis4, 6 2 15 mV
in the CMPCON register
Response Time 3 µs 100 mV overdrive and configured with CMPRES = 11
TEMPERATURE SENSOR Indicates die temperature
Voltage Output at 25°C 1.369 V
Voltage TC 4.42 mV/°C
Accuracy with No Calibration ±3 °C
Accuracy with One Point Calibration
Using Contents of TEMPREF Register
±1.5 °C
θJA Thermal Impedance
40-Lead LFCSP 26 °C/W
32-Lead LFCSP 32.5 °C/W
POWER SUPPLY MONITOR (PSM)
IOVDD Trip Point Selection 2.79 V One trip point
Power Supply Trip Point Accuracy ±2 % Of the selected nominal trip point voltage
POWER-ON RESET 2.41 V
WATCHDOG TIMER (WDT)
Timeout Period 0 512 sec
FLASH/EE MEMORY
Endurance11 10,000 Cycles
Data Retention12 20 Years TJ = 85°C
DIGITAL INPUTS All digital inputs excluding XCLKI and XCLKO
Logic 1 Input Current ±0.2 ±1 µA VIH = VDD or VIH = 5 V
Logic 0 Input Current −40 −60 µA VIL = 0 V; except TDI
−80 −120 µA VIL = 0 V; TDI
Input Capacitance 10 pF
LOGIC INPUTS4 All logic inputs excluding XCLKI
VINL, Input Low Voltage 0.8 V
V
INH
, Input High Voltage
2.0
V
LOGIC OUTPUTS All digital outputs excluding XCLKO
VOH, Output High Voltage 2.4 V ISOURCE = 1.6 mA
VOL, Output Low Voltage13 0.4 V ISINK = 1.6 mA
CRYSTAL INPUTS XCLKI AND XCLKO
Logic Inputs, XCLKI Only
VINL, Input Low Voltage 1.1 V
VINH, Input High Voltage 1.7 V
XCLKI Input Capacitance 20 pF
XCLKO Output Capacitance 20 pF
Rev. G | Page 7 of 97
ADuC7023 Data Sheet
Parameter Min Typ Max Unit Test Conditions/Comments
INTERNAL OSCILLATOR 32.768 kHz
±3 %
MCU CLOCK RATE
From 32 kHz Internal Oscillator 326 kHz CD = 7
From 32 kHz External Crystal 41.78 MHz CD = 0
Using an External Clock 0.05 44 MHz TA = 85°C
0.05 41.78 MHz TA = 125°C
START-UP TIME Core clock = 41.78 MHz
At Power-On 66 ms
From Pause/Nap Mode 24 ns CD = 0
3.07 µs CD = 7
From Sleep Mode 1.58 ms
From Stop Mode 1.7 ms
PROGRAMMABLE LOGIC ARRAY (PLA)
Pin Propagation Delay 12 ns From input pin to output pin
Element Propagation Delay 2.5 ns
POWER REQUIREMENTS14, 15
Power Supply Voltage Range
AVDD to AGND and IOVDD to DGND 2.7 3.6 V
Analog Power Supply Currents
AV
DD
Current
200
µA
Digital Power Supply Current
IOVDD Current in Normal Mode Code executing from Flash/EE
8.5 10 mA CD = 7
11 15 mA CD = 3
28 35 mA CD = 0 (41.78 MHz clock)
IOVDD Current in Pause Mode 14 20 mA CD = 0 (41.78 MHz clock)
IOVDD Current in Sleep Mode 230 650 µA TA = 125°C
Additional Power Supply Currents
ADC 1.4 mA At 1 MSPS
0.7 mA At 62.5 kSPS
DAC 400 µA Per DAC
ESD TESTS 2.5 V reference, TA = 25°C
HBM Passed 3 kV
FICDM Passed 1.0 kV
1 All ADC channel specifications are guaranteed during normal microcontroller core operation.
2 Apply to all ADC input channels.
3 Measured using the factory-set default values in the ADC offset register (ADCOF) and gain coefficient register (ADCGN).
4 Not production tested but supported by design and/or characterization data on production release.
5 Measured using the factory-set default values in ADCOF and ADCGN with an external AD845 op amp as an input buffer stage as shown in Figure 28. Based on external ADC
system components, the user may need to execute a system calibration to remove external endpoint errors and achieve these specifications (see the Calibration section).
6 The input signal can be centered on any dc common-mode voltage (VCM) as long as this value is within the ADC voltage input range specified.
7 DAC linearity is calculated using a reduced code range of 100 to 3995.
8 DAC gain error is calculated using a reduced code range of 100 to internal 2.5 V VREF.
9 DAC linearity is calculated using a reduced code range of 100 to 3995.
10 DAC gain error is calculated using a reduced code range of 100 to internal 2.5 V VREF.
11 Endurance is qualified as per JEDEC Standard 22 Method A117 and measured at −40°C, +25°C, +85°C, and +125°C.
12 Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Standard 22 Method A117. Retention lifetime derates with junction temperature.
13 Test carried out with a maximum of eight I/Os set to a low output level.
14 Power supply current consumption is measured in normal, pause, and sleep modes under the following conditions: normal mode with 3.6 V supply, pause mode with
3.6 V supply, and sleep mode with 3.6 V supply.
15 IOVDD power supply current decreases typically by 2 mA during a Flash/EE erase cycle.
Rev. G | Page 8 of 97
"XX /J‘ / +._ AMER + l * |
Data Sheet ADuC7023
TIMING SPECIFICATIONS
Table 2. I2C Timing in Fast Mode (400 kHz)
Slave Master
Parameter
Description
Min
Max
Typ
Unit
tL SCL low pulse width 200 1360 ns
t
H
SCL high pulse width
100
1140
ns
tSHD Start condition hold time 300 ns
tDSU Data setup time 100 740 ns
tDHD Data hold time 0 400 ns
tRSU Setup time for repeated start 100 ns
tPSU Stop condition setup time 100 800 ns
tBUF Bus-free time between a stop condition and a start condition 1.3 µs
tR Rise time for both SCL and SDA 300 200 ns
tF Fall time for both SCL and SDA 300 ns
Table 3. I2C Timing in Standard Mode (100 kHz)
Slave
Parameter
Description
Min
Max
Unit
tL SCL low pulse width 4.7 µs
tH SCL high pulse width 4.0 ns
tSHD Start condition hold time 4.0 µs
tDSU Data setup time 250 ns
tDHD Data hold time 0 3.45 µs
tRSU Setup time for repeated start 4.7 µs
tPSU Stop condition setup time 4.0 µs
tBUF Bus-free time between a stop condition and a start condition 4.7 µs
tR Rise time for both SCL and SDA 1 µs
tF Fall time for both SCL and SDA 300 ns
08675-002
SDA (I/O)MSB LSB ACK MSB
1982–71
P S S(R)
t
R
t
F
t
RSU
t
DSU
t
DSU
t
PSU
t
BUF
t
H
t
F
t
R
t
DHD
t
DHD
t
SHD
t
SUP
t
L
t
SUP
REPEATED
START
START
CONDITION
STOP
CONDITION
SCL (I)
Figure 2. I2C-Compatible Interface Timing
Rev. G | Page 9 of 97
Table 4‘ SP1 Masm Mod: Timing (Phase Mud: : 1) A; « n E
ADuC7023 Data Sheet
Table 4. SPI Master Mode Timing (Phase Mode = 1)
Parameter Description Min Typ Max Unit
tSL SCLK low pulse width1 (SPIDIV + 1) × tUCLK ns
tSH SCLK high pulse width1 (SPIDIV + 1) × tUCLK ns
tDAV Data output valid after SCLK edge 25 ns
tDSU Data input setup time before SCLK edge1 1 × tUCLK ns
tDHD Data input hold time after SCLK edge1 2 × tUCLK ns
tDF Data output fall time 5 12.5 ns
tDR Data output rise time 5 12.5 ns
tSR SCLK rise time 5 12.5 ns
tSF SCLK fall time 5 12.5 ns
1 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.
08675-003
MOSI MSB BIT 6 TO BIT 1 LSB
MISO MSB IN BIT 6 TO BIT 1 LSB IN
SCLK
(POLARITY = 0)
SCLK
(POLARITY = 1)
t
SF
t
SR
t
SL
t
SH
t
DAV
t
DSU
t
DHD
t
DF
t
DR
Figure 3. SPI Master Mode Timing (Phase Mode = 1)
Rev. G | Page 10 of 97
Table 5‘ SP1 Masm Mode Timing (Phase Mud: : o)
Data Sheet ADuC7023
Table 5. SPI Master Mode Timing (Phase Mode = 0)
Parameter Description Min Typ Max Unit
tSL SCLK low pulse width1 (SPIDIV + 1) × tUCLK ns
tSH SCLK high pulse width1 (SPIDIV + 1) × tUCLK ns
tDAV Data output valid after SCLK edge 25 ns
tDOSU Data output setup before SCLK edge 75 ns
tDSU Data input setup time before SCLK edge1 1 × tUCLK ns
tDHD Data input hold time after SCLK edge1 2 × tUCLK ns
tDF Data output fall time 5 12.5 ns
tDR Data output rise time 5 12.5 ns
tSR SCLK rise time 5 12.5 ns
t
SF
SCLK fall time
5
12.5
ns
1 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.
08675-004
MSB BIT 6 TO BIT 1 LSB
MSB IN BIT 6 TO BIT 1 LSB IN
MOSI
MISO
SCLK
(POLARITY = 0)
SCLK
(POLARITY = 1)
t
SF
t
SR
t
SL
t
DAV
t
SH
t
DF
t
DR
t
DOSU
t
DSU
t
DHD
Figure 4. SPI Master Mode Timing (Phase Mode = 0)
Rev. G | Page 11 of 97
ADuC7023 Data Sheet
Table 6. SPI Slave Mode Timing (Phase Mode = 1)
Parameter Description Min Typ Max Unit
tSS SS to SCLK edge 200 ns
tSL SCLK low pulse width1 (SPIDIV + 1) × tUCLK ns
tSH SCLK high pulse width1 (SPIDIV + 1) × tUCLK ns
tDAV Data output valid after SCLK edge 25 ns
tDSU Data input setup time before SCLK edge1 1 × tUCLK ns
tDHD Data input hold time after SCLK edge1 2 × tUCLK ns
t
DF
Data output fall time
5
12.5
ns
tDR Data output rise time 5 12.5 ns
tSR SCLK rise time 5 12.5 ns
tSF SCLK fall time 5 12.5 ns
tSFS SS high after SCLK edge 0 ns
1 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.
08675-005
MOSI
MISO
SCLK
(POLARITY = 0)
SCLK
(POLARITY = 1)
t
SF
t
SFS
t
SR
t
SL
t
DAV
t
SH
t
DF
t
DR
t
DSU
t
DHD
SS
MSB BIT 6 TOBIT 1 LSB
MSB IN BIT 6 TO BIT 1 LSB IN
t
SS
Figure 5. SPI Slave Mode Timing (Phase Mode = 1)
Rev. G | Page 12 of 97
El
Data Sheet ADuC7023
Table 7. SPI Slave Mode Timing (Phase Mode = 0)
Parameter Description Min Typ Max Unit
tSS SS to SCLK edge 200 ns
tSL SCLK low pulse width1 (SPIDIV + 1) × tUCLK ns
tSH SCLK high pulse width1 (SPIDIV + 1) × tUCLK ns
tDAV Data output valid after SCLK edge 25 ns
tDSU Data input setup time before SCLK edge1 1 × tUCLK ns
tDHD Data input hold time after SCLK edge1 2 × tUCLK ns
t
DF
Data output fall time
5
12.5
ns
tDR Data output rise time 5 12.5 ns
tSR SCLK rise time 5 12.5 ns
tSF SCLK fall time 5 12.5 ns
tDOCS Data output valid after SS edge 25 ns
tSFS SS high after SCLK edge 0 ns
1 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.
08675-006
MSB IN BIT 6 TO BIT 1 LSB IN
MSB BIT6 TO BIT 1 LSB
MOSI
MISO
SCLK
(POLARITY = 0)
SCLK
(POLARITY = 1)
t
SF
t
SFS
t
SR
t
SL
t
DAV
t
SH
t
DF
t
DR
t
DSU
t
DOCS
t
DHD
SS
t
SS
Figure 6. SPI Slave Mode Timing (Phase Mode = 0)
Rev. G | Page 13 of 97
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ADuC7023 Data Sheet
ABSOLUTE MAXIMUM RATINGS
AGND = GNDREF, TA = 25°C, unless otherwise noted.
Table 8.
1 These limits apply to the P0.0, P0.1, P0.2, P0.3, P0.4, P0.5, P0.6, P0.7, P1.0,
P1.1, P1.6, and P1.7 pins.
2 These limits apply to the P1.2, P1.3, P1.4, P1.5, P2.0, P2.2, P2.3, and P2.4 pins.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Only one absolute maximum rating can be applied at any one time.
ESD CAUTION
Parameter Rating
AVDD to IOVDD 0.3 V to +0.3 V
AGND to DGND −0.3 V to +0.3 V
IOVDD to DGND, AVDD to AGND 0.3 V to +6 V
Digital Input Voltage to DGND1 −0.3 V to +5.3 V
Digital Output Voltage to DGND1 −0.3 V to IOVDD + 0.3 V
Shared Analog/Digital Inputs to AGND2 −0.3 V to AVDD + 0.3 V
V
REF
to AGND
−0.3 V to AV
DD
+ 0.3 V
Analog Inputs to AGND
−0.3 V to AVDD + 0.3 V
Analog Outputs to AGND 0.3 V to AVDD + 0.3 V
Operating Temperature Range, Industrial 40°C to +125°C
Storage Temperature Range 65°C to +150°C
Junction Temperature
150°C
θJA Thermal Impedance
40-Lead LFCSP 26°C/W
32-Lead LFCSP 32.5°C/W
36-Lead WLCSP 50°C/W
Peak Solder Reflow Temperature
SnPb Assemblies (10 sec to 30 sec) 240°C
RoHS Compliant Assemblies
(20 sec to 40 sec)
260°C
Rev. G | Page 14 of 97
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Data Sheet ADuC7023
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
NOTES
1. EXPOSED PAD. THE PADDLE NEEDS TO BE SOLDERED AND
EITHER CONNECTED TO AGND OR LEFT FLOATING.
08675-048
1
AV
DD
2
GND
REF
3DAC0 4DAC1 5DAC2 6DAC3 7P1.4/ADC10/PLAO[3] 8
P2.0/ADC12/PWM4/PLAI[7] 9
10
P0.5/SDA0/PLAI[1]/COMP
OUT
23 RTCK
24 TMS
25 P0.0/nTRST/ADC
BUSY
PLAI[8]/BM
26 P0.1/PLAI[9]/TDO
27 P0.2/PLAO[8]/TDI
28 P0.3/PLAO[9]/TCK
29 P1.5/ADC6/PWM
TRIPINPUT
/PLAO[4]
30 P2.2/ADC7/SYNC/PLAO[6]
22 XCLKO
21 XCLKI
11
P0.6/MISO/PLAI[2]
12
P0.7/MOSI/PLAO[0]
13
P1.0/SPICLK/PWM0/PLAO[1]
15
P1.6/PWM2/SCL1/PLAI[5]
17
DGND 16
P1.7/PWM3/SDA1/PLAI[6]
18
IOV
DD
19
LV
DD
20
33 P1.2/ADC4/IRQ2/PLAI[3]/ECLK
34 P1.3/ADC5/IRQ3/PLAI[4]
35 V
REF
36 ADC0
37 ADC1
38 ADC2/CMP0
39 ADC3/CMP1
40 AGND
32 P2.4/ADC9/PLAI[10]
31 P2.3/ADC8/PLAO[7]
ADuC7023
TOP VIEW
(Not to Scale)
RST
14
P1.1/SS/IRQ1/PWM1/PLAO[2]/TI
P0.4/IRQ0/SCL0/PLAI[0]/CONV
START
Figure 7. 40-Lead LFCSP Pin Configuration
08675-007
AV
DD
GND
REF
DAC0
DAC1
DAC2
DAC3
P0.5/SDA0/PLAI[1]/COMP
OUT
P0.3/PLAO[9]/TCK
P0.2/PLAO[8]/TDI
P0.1/PLAI[9]/TDO
P0.0/nTRST/ADC
BUSY
/PLAI[8]/BM
TMS
RTCK
XCLKO
XCLKI
P0.6/MISO/SCL1/PLAI[2]
P0.7/MOSI/SDA1/PLAO[0]
P1.0/SPICLK/PWM0/PLAO[1]
DGND
IOV
DD
LV
DD
AGND
ADC3/CMP1
ADC2/CMP0
ADC1
ADC0
V
REF
P1.3/ADC5/IRQ3/PLAI[4]
P1.2/ADC4/IRQ2/PLAI[3]/ECLK
RST
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
ADuC7023
TOP VIEW
(Not to Scale)
NOTES
1. EXPOSED PAD. THE PADDLE NEEDS TO BE SOLDERED AND
EITHER CONNECTED TO AGND OR LEFT FLOATING.
P1.1/SS/IRQ1/PWM1/PLAO[2]/T1
P0.4/IRQ0/SCL0/PLAI[0]/CONV
START
Figure 8. 32-Lead LFCSP Pin Configuration
ADuC7023
TOP VIEW
(BALL SIDE DOWN)
Not to Scale
08675-109
1
A
B
C
D
E
F
A1
B1
C1
D1
E1
F1
A2
B2
C2
D2
E2
F2
A3
B3
C3
D3
E3
F3
A4
B4
C4
D4
E4
F4
A5
B5
C5
D5
E5
F5
A6
B6
C6
D6
E6
F6
2 3 4
BALLA1
CORNER
5 6
Figure 9. 36-Lead WLCSP Pin Configuration
Table 9. Pin Function Descriptions
Pin No.
40-
LFCSP
32-
LFCSP
36-
WLCSP Mnemonic Description
0 0 N/A Exposed Paddle Exposed Pad. The paddle needs to be soldered and either connected to
AGND or left floating.
36 28 A4 ADC0 Single-Ended or Differential Analog Input 0.
37 29 B4 ADC1 Single-Ended or Differential Analog Input 1.
38 30 A5 ADC2/CMP0 Single-Ended or Differential Analog Input 2/Comparator Positive Input.
39 31 B5 ADC3/CMP1 Single-Ended or Differential Analog Input 3/Comparator Negative Input.
32 N/A B2 P2.4/ADC9/PLAI[10] General-Purpose Input and Output Port 2.4/ADC Single-Ended or Dif-
ferential Analog Input/Programmable Logic Array Input Element 10.
By default, this pin is configured as a digital input with a weak pull-up
resistor enabled.
Rev. G | Page 15 of 97
ADuC7023 Data Sheet
Pin No.
40-
LFCSP
32-
LFCSP
36-
WLCSP Mnemonic Description
31 N/A A1 P2.3/ADC8/PLAO[7] General-Purpose Input and Output Port 2.3/ADC Single-Ended or
Differential Analog Input 8/Programmable Logic Array Output Element 7.
By default, this pin is configured as a digital input with a weak pull-up
resistor enabled. When used as ADC input, pull-up resistor should be
disabled manually.
30 N/A B1 P2.2/ADC7/SYNC/PLAO[6] General-Purpose Input and Output Port 2.2/ADC Single-Ended or
Differential Analog Input 7/PWM Sync/Programmable Logic Array Output
Element 6. By default, this pin is configured as a digital input with a weak
pull-up resistor enabled. When used as ADC input, pull-up resistor should
be disabled manually.
8 N/A E6 P2.0/ADC12/PWM4/PLAI[7] General-Purpose Input and Output Port 2.0/ADC Single-Ended or
Differential Analog Input 12/PWM Output 4/Programmable Logic Array Input
Element 7. By default, this pin is configured as a digital input with a weak pull-
up resistor enabled. When used as an ADC input, it is not possible to
disable the internal pull-up resister. This means that this pin has a higher
leakage current value than other analog input pins.
2 2 C4 GNDREF Ground Voltage Reference for the ADC. For optimal performance, the
analog power supply should be separated from DGND.
3 3 C5 DAC0 DAC0 Voltage Output or ADC Input.
4 4 C6 DAC1 DAC1 Voltage Output or ADC Input.
5 5 D5 DAC2 DAC2 Voltage Output
6 6 D6 DAC3 DAC3 Voltage Output
24 20 D2 TMS Test Mode Select, JTAG Test Port Input. Debug and download access.
This pin has an internal pull-up resistor to IOVDD. In some cases an external
pull-up resistor is also required to ensure the part does not enter an
erroneous state.
25
21
D1
P0.0/nTRST/ADC
BUSY
/PLAI[8]/BM
This is a multifunction pin as follows:
General-Purpose Input and Output Port 0.0. By default, this pin is
configured as GPIO.
JTAG Reset Input. Debug and download access. If this pin is held low, JTAG
access is not possible because the JTAG interface is held in reset and
P0.1/P0.2/P0.3 are configured as GPIO pins.
ADC Busy Signal.
Programmable Logic Array Input Element 8.
Boot Mode Entry Pin. The ADuC7023 enters I2C download mode if BM is
low at reset with a flash address 0x80014 = 0xFFFFFFFFF. The ADuC7023
executes code if BM is pulled high at reset or if BM is low at reset with a
flash address 0x80014 not equal to 0xFFFFFFFFF.
26 22 C1 P0.1/PLAI[9]/TDO The default value of this pin depends on the level of P0.0/BM. If P0.0/
BM = 0, this pin defaults to a general purpose input. If P0.0/BM = 1, this
pin defaults to a JTAG test data output pin and does not work as a GPIO.
This is a multifunction pin as follows:
General-Purpose Input and Output Port 0.1.
Programmable Logic Array Input Element 9.
Test Data Out, JTAG Test Port Output. Debug and download access. When
debugging the part via JTAG, this pin must not be toggled by user code,
and the GP0CON/GP0DAT register bits affecting this pin must not be
changed as doing so disables JTAG access.
27
23
C2
P0.2/PLAO[8]/TDI
The default value of this pin depends on the level of P0.0/BM. If P0.0/
BM = 0, this pin defaults to a general purpose input. If P0.0/BM = 1, this pin
defaults to a JTAG test data input pin and does not work as a GPIO. This is a
multifunction pin as follows:
General-Purpose Input and Output Port 0.2.
Programmable Logic Array Output Element 8.
Test Data In, JTAG Test Port Input. Debug and download access. When
debugging the part via JTAG, this pin must not be toggled by user code,
and the GP0CON/GP0DAT register bits affecting this pin must not be
changed as doing so disables JTAG access.
Rev. G | Page 16 of 97
W
Data Sheet ADuC7023
Pin No.
40-
LFCSP
32-
LFCSP
36-
WLCSP Mnemonic Description
28 24 C3 P0.3/PLAO[9]/TCK The default value of this pin depends on the level of P0.0/BM. If P0.0/BM =
0, this pin defaults to a general purpose input. If P0.0/BM = 1, this pin
defaults to a JTAG test data clock pin. This is a multifunction pin as follows:
General-Purpose Input and Output Port 0.3.
Programmable Logic Array Output Element 9.
Test Clock, JTAG Test Port Clock Input. Debug and download access. When
debugging the part via JTAG, this pin must not be toggled by user code
and the GP0CON/GP0DAT register bits affecting this pin must not be
changed as doing so disables JTAG access.
17
13
E3
DGND
Digital Ground.
18 14 F3 IOVDD 3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator.
19 15 D3 LVDD 2.6 V Output of the On-Chip Voltage Regulator. This output must be
connected to a 0.47 µF capacitor to DGND only.
20 16 F2 RST Reset Input, Active Low.
23 19 E1 RTCK Return JTAG Clock Signal. This is not the standard JTAG clock signal. It is
an output signal from the JTAG controller. If using a 20-lead JTAG header,
connect to Pin 11.
9 7 F6 P0.4/IRQ0/SCL0/PLAI[0]/CONV General-Purpose Input and Output Port 0.4/External Interrupt Request 0/ I2C0
Clock Signal/Programmable Logic Array Input Element 0/ADC External
Convert Start. By default, this pin is configured as a digital input with a
weak pull-up resistor enabled.
10 8 E5 P0.5/SDA0/PLAI[1]/COMPOUT General-Purpose Input and Output Port 0.5/I2C0 Data Signal/ Programmable
Logic Array Input Element 1/Voltage Comparator Output. By default, this
pin is configured as a digital input with a weak pull-up resistor enabled.
9 F5 P0.6/MISO/SCL1/PLAI[2] General-Purpose Input and Output Port 0.6/SPI MISO Signal/I2C1 Clock On
32-Lead and 36-Ball Packages/Programmable Logic Array Input Element 2.
By default, this pin is configured as a digital input with a weak pull-up
resistor enabled.
10 D4 P0.7/MOSI/SDA1/PLAO[0] General-Purpose Input and Output Port 0.7/SPI MOSI Signal/I2C1 Data
Signal On 32-Lead and 36-Ball Packages/Programmable Logic Array Output
Element 0.
By default, this pin is configured as a digital input with a weak pull-up
resistor enabled.
11 P0.6/MISO/PLAI[2] General-Purpose Input and Output Port 0.6/SPI MISO Signal/Programmable
Logic Array Input Element 2. By default, this pin is configured as a digital
input with a weak pull-up resistor enabled.
12 P0.7/MOSI/PLAO[0] General-Purpose Input and Output Port 0.7/SPI MOSI Signal/Programmable
Logic Array Output Element 0. By default this pin is configured as a digital
input with a weak pull-up reisistor enabled.
21 17 F1 XCLKI Input to the Crystal Oscillator Inverter and Input to the Internal Clock
Generator Circuits. Connect to DGND if unused.
22 18 E2 XCLKO Output from the Crystal Oscillator Inverter. Leave unconnected if unused.
16 N/A N/A P1.7/PWM3/SDA1/PLAI[6] General-Purpose Input and Output Port 1.7/PWM Output 3/I2C1 Data
Signal/Programmable Logic Array Input Element 6. By default, this pin is
configured as a digital input with a weak pull-up resistor enabled.
15 N/A N/A P1.6/PWM2/SCL1/PLAI[5] General-Purpose Input and Output Port 1.6/PWM Output 2/I2C1 Clock
Signal/Programmable Logic Array Input Element 5. By default, this pin is
configured as a digital input with a weak pull-up resistor enabled.
29 N/A N/A P1.5/ADC6/PWMTRIPINPUT/PLAO[4] General-Purpose Input and Output Port 1.5/ADC Single-Ended or
Differential Analog Input 6/PWMTRIPINPUT/Programmable Logic Array Output
Element 4. By default, this pin is configured as a digital input with a weak
pull-up resistor enabled. When used as ADC input, the pull-up resistor
should be disabled manually.
7 N/A N/A P1.4/ADC10/PLAO[3] General-Purpose Input and Output Port 1.4/ADC Single-Ended or Dif-
ferential Analog Input 10/Programmable Logic Array Output Element 3.
By default, this pin is configured as a digital input with a weak pull-up
resistor enabled. When used as ADC input, the pull-up resistor should be
disabled manually.
Rev. G | Page 17 of 97
Pm/E
ADuC7023 Data Sheet
Pin No.
40-
LFCSP
32-
LFCSP
36-
WLCSP Mnemonic Description
34 26 A3 P1.3/ADC5/IRQ3/PLAI[4] General-Purpose Input and Output Port 1.3/ADC Single-Ended or
Differential Analog Input 5/External Interrupt Request 3/ Programmable
Logic Array Input Element 4.
By default, this pin is configured as a digital input with a weak pull-up
resistor enabled. When used as ADC input, the pull-up resistor should be
disabled manually.
33 25 A2 P1.2/ADC4/IRQ2/PLAI[3]/ECLK/ General-Purpose Input and Output Port 1.2/ADC Single-Ended or
Differential Analog Input 4/External Interrupt Request 2/ Programmable
Logic Array Input Element 3/Input-Output for External Clock.
By default, this pin is configured as a digital input with a weak pull-up
resistor enabled. When used as ADC input, the pull-up resistor should be
disabled manually.
14 12 F4 P1.1/SS/IRQ1/PWM1/PLAO[2]/T1 General-Purpose Input and Output Port 1.1/SPI Interface Slave Select
(Active Low)/External Interrupt Request 1/PWM Output 1/ Programmable
Logic Array Output Element 2/Timer 1 Input Clock. By default, this pin is
configured as a digital input with a weak pull-up resistor enabled.
13 11 E4 P1.0/SCLK/PWM0/PLAO[1] General-Purpose Input and Output Port 1.0/SPI Interface Clock Signal/
PWM Output 0/Programmable Logic Array Output Element 1. By default,
this pin is configured as a digital input with a weak pull-up resistor enabled.
35 27 B3 VREF 2.5 V Internal Voltage Reference. Must be connected to a 0.47 µF capacitor
when using the internal reference.
40 32 A6 AGND Analog Ground. Ground reference point for the analog circuitry.
1 1 B6 AVDD 3.3 V Analog Power.
Rev. G | Page 18 of 97
“IN-WWI"In-mww'mml'mmmwmnwnmvmlm WWWMIIWWWWW
Data Sheet ADuC7023
Rev. G | Page 19 of 97
TYPICAL PERFORMANCE CHARACTERISTICS
0.5
0.6
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
0 500 1000 1500 2000 2500 3000 3500 4095
ADC CODES
DNL (LSB)
08675-049
SAMPLING RATE = 950kSPS
WORST CASE POSITIVE = 0.63, CODE = 2364
WORST CASE NEGATIVE = –0.46, CODE = 2363
Figure 10. Typical DNL, fADC = 950 kSPS, Internal Reference Used
0.6
0.4
0.2
0
–0.2
–0.6
–0.4
–0.8
–1.0
0 500 1000 1500 2000 2500 3000 3500 4095
ADC CODES
INL (LSB)
08675-050
SAMPLING RATE = 950kSPS
WORST CASE POSITIVE = 0.57, CODE = 4063
WORST CASE NEGATIVE = –0.90, CODE = 3356
Figure 11. Typical INL, fADC = 950 kSPS, Internal Reference Used
0.6
0.5
0.4
0.3
0.2
0.1
–0.1
0
–0.2
–0.3
–0.4
–0.5
–0.6
0 500 1000 1500 2000 2500 3000 3500 4095
ADC CODES
DNL (LSB)
08675-051
SAMPLING RATE = 950kSPS
WORST CASE POSITIVE = 0.64, CODE = 3583
WORST CASE NEGATIVE = –0.61, CODE = 1830
Figure 12. Typical DNL, fADC = 950 kSPS, External 1.0 V Reference Used
1.2
1.0
0.8
0.6
0.4
0.2
–0.2
0
–0.4
–0.6
–0.8
–1.0
0 500 1000 1500 2000 2500 3000 3500 4095
ADC CODES
INL (LSB)
08675-052
SAMPLING RATE = 950kSPS
WORST CASE POSITIVE = 1.09, CODE = 4032
WORST CASE NEGATIVE = –0.98, CODE = 3422
Figure 13. Typical INL, fADC = 950 kSPS, External 1.0 V Reference Used
20
0
–20
–40
–60
–80
–100
–200
–400
0 20,000 40,000 60,000 80,000 104,400
FREQUENCY (Hz)
SINAD, THD AND PHSN OF ADC (dB)
08675-053
Figure 14. SINAD, THD, and PHSN of ADC , Internal 2.5 V Reference Used
ADuC7023 Data Sheet
TERMINOLOGY
ADC SPECIFICATIONS
Integral Nonlinearity (INL)
The maximum deviation of any code from a straight line
passing through the endpoints of the ADC transfer function.
The endpoints of the transfer function are zero scale, a point
½ LSB below the first code transition, and full scale, a point
½ LSB above the last code transition.
Differential Nonlinearity (DNL)
The difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset Error
The deviation of the first code transition (0000 . . . 000) to
(0000 . . . 001) from the ideal, that is, +½ LSB.
Gain Error
The deviation of the last code transition from the ideal AIN
voltage (full scale − 1.5 LSB) after the offset error has been
adjusted out.
Signal to (Noise + Distortion) Ratio
The measured ratio of signal to (noise + distortion) at the
output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (fS/2), excluding dc.
The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the
quantization noise.
The theoretical signal to (noise + distortion) ratio for an ideal
N-bit converter with a sine wave input is given by
Signal to (Noise + Distortion) = (6.02 N + 1.76) dB
Thus, for a 12-bit converter, this is 74 dB.
Total Harmonic Distortion
The ratio of the rms sum of the harmonics to the fundamental.
DAC SPECIFICATIONS
Relative Accuracy
Otherwise known as endpoint linearity, relative accuracy is a
measure of the maximum deviation from a straight line passing
through the endpoints of the DAC transfer function. It is
measured after adjusting for zero error and full-scale error.
Voltage Output Settling Time
The amount of time it takes the output to settle to within a
1 LSB level for a full-scale input change.
Rev. G | Page 20 of 97
Data Sheet ADuC7023
OVERVIEW OF THE ARM7TDMI CORE
The ARM7® core is a 32-bit reduced instruction set computer
(RISC). It uses a single 32-bit bus for instruction and data. The
length of the data can be 8 bits, 16 bits, or 32 bits. The length of
the instruction word is 32 bits.
The ARM7TDMI is an ARM7 core with four additional features: T
support for the thumb (16-bit) instruction set, D support for
debug, M support for long multiplications, and I includes the
EmbeddedICE module to support embedded system debugging.
THUMB MODE (T)
An ARM instruction is 32 bits long. The ARM7TDMI
processor supports a second instruction set that has been
compressed into 16 bits, called the Thumb® instruction set.
Faster execution from 16-bit memory and greater code density
can usually be achieved by using the Thumb instruction set
instead of the ARM instruction set, which makes the
ARM7TDMI core particularly suitable for embedded
applications.
However, the Thumb mode has two limitations. Thumb code
typically requires more instructions for the same job. As a result,
ARM code is usually best for maximizing the performance of time
critical code. Also, the Thumb instruction set does not include
some of the instructions needed for exception handling, which
automatically switches the core to ARM code for exception
handling.
See the ARM7TDMI user guide for details on the core
architecture, the programming model, and both the ARM
and ARM Thumb instruction sets.
LONG MULTIPLY (M)
The ARM7TDMI instruction set includes four extra instruc-
tions that perform 32-bit by 32-bit multiplication with a 64-bit
result, and 32-bit by 32-bit multiplication-accumulation (MAC)
with a 64-bit result. These results are achieved in fewer cycles
than required on a standard ARM7 core.
EmbeddedICE (I)
EmbeddedICE provides integrated on-chip support for the core.
The EmbeddedICE module contains the breakpoint and watch-
point registers that allow code to be halted for debugging purposes.
These registers are controlled through the JTAG test port.
When a breakpoint or watchpoint is encountered, the processor
halts and enters debug state. Once in a debug state, the
processor registers can be inspected as well as the Flash/EE,
SRAM, and memory mapped registers.
EXCEPTIONS
ARM supports five types of exceptions and a privileged
processing mode for each type. The five types of exceptions are:
Normal interrupt or IRQ. This is provided to service
general-purpose interrupt handling of internal and
external events.
Fast interrupt or FIQ. This is provided to service data
transfers or communication channels with low latency. FIQ
has priority over IRQ.
Memory abort.
Attempted execution of an undefined instruction.
Software interrupt instruction (SWI). This can be used to
make a call to an operating system.
Typically, the programmer defines interrupt as IRQ, but for
higher priority interrupt, that is, faster response time, the
programmer can define interrupt as FIQ.
ARM REGISTERS
ARM7TDMI has a total of 37 registers: 31 general-purpose
registers and six status registers. Each operating mode has
dedicated banked registers.
When writing user-level programs, 15 general-purpose 32-bit
registers (R0 to R14), the program counter (R15), and the current
program status register (CPSR) are usable. The remaining
registers are only used for system-level programming and
exception handling.
When an exception occurs, some of the standard registers are
replaced with registers specific to the exception mode. All excep-
tion modes have replacement banked registers for the stack
pointer (R13) and the link register (R14) as represented in
Figure 15. The fast interrupt mode has more registers (R8 to R12)
for fast interrupt processing. This means the interrupt processing
can begin without the need to save or restore these registers,
and thus save critical time in the interrupt handling process.
08675-008
USABLE IN USER MODE
SYSTEM MODES ONLY
SPSR_UND
SPSR_IRQ
SPSR_ABT
SPSR_SVC
R8_FIQ
R9_FIQ
R10_FIQ
R11_FIQ
R12_FIQ
R13_FIQ
R14_FIQ
R13_UND
R14_UND
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15 (PC)
R13_IRQ
R14_IRQ
R13_ABT
R14_ABT
R13_SVC
R14_SVC
SPSR_FIQ
CPSR
USER MODE FIQ
MODE SVC
MODE ABORT
MODE IRQ
MODE UNDEFINED
MODE
Figure 15. Register Organization
Rev. G | Page 21 of 97
ADuC7023 Data Sheet
More information relative to the model of the programmer and
the ARM7TDMI core architecture can be found in ARM7TDMI
technical and ARM architecture manuals available directly from
ARM Ltd.
INTERRUPT LATENCY
The worst-case latency for a fast interrupt request (FIQ)
consists of the following: the longest time the request can take
to pass through the synchronizer, the time for the longest
instruction to complete (the longest instruction is an LDM) that
loads all the registers including the PC, and the time for the
data abort and FIQ entry.
At the end of this time, the ARM7TDMI executes the instruc-
tion at 0x1C (FIQ interrupt vector address). The maximum
total time is 50 processor cycles, which is just under 1.2 µs in a
system using a continuous 41.78 MHz processor clock.
The maximum interrupt request (IRQ) latency calculation is
similar but must allow for the fact that FIQ has higher priority
and could delay entry into the IRQ handling routine for an
arbitrary length of time. This time can be reduced to 42 cycles if
the LDM command is not used. Some compilers have an option
to compile without using this command. Another option is to run
the part in thumb mode where the time is reduced to 22 cycles.
The minimum latency for FIQ or IRQ interrupts is a total of
five cycles, which consist of the shortest time the request can
take through the synchronizer, plus the time to enter the
exception mode.
The ARM7TDMI always runs in ARM (32-bit) mode when in
privileged modes, for example, when executing interrupt
service routines.
Rev. G | Page 22 of 97
Data Sheet ADuC7023
Rev. G | Page 23 of 97
MEMORY ORGANIZATION
The ADuC7023 incorporates two separate blocks of memory:
8 kB of SRAM and 64 kB of on-chip Flash/EE memory; 62 kB of
on-chip Flash/EE memory is available to the user, and the
remaining 2 kB are reserved for the factory configured boot
page. These two blocks are mapped as shown in Figure 16.
RESERVED
MMRs
0xFFFFFFFF
0x0008FFFF
0x00011FFF
0x0000FFFF
0x00000000
0x00010000
0x00080000
0xFFFF0000
RESERVED
FLASH/EE
(FLASH/EE OR SRAM)
REMAPPABLE MEMORY SPACE
SRAM
08675-009
Figure 16. Physical Memory Map
By default, after a reset, the Flash/EE memory is mirrored at
Address 0x00000000. It is possible to remap the SRAM at
Address 0x00000000 by clearing Bit 0 of the Remap MMR.
This remap function is described in more detail in the Flash/EE
Memory section.
MEMORY ACCESS
The ARM7 core sees memory as a linear array of the 232 byte
location where the different blocks of memory are mapped as
outlined in Figure 16.
The ADuC7023 memory organizations are configured in little
endian format, which means that the least significant byte is
located in the lowest byte address, and the most significant byte
is in the highest byte address.
0
8675-010
BIT 31
BYTE 2
A
6
2
.
.
.
BYTE 3
B
7
3
.
.
.
BYTE 1
9
5
1
.
.
.
BYTE 0
8
4
0
.
.
.
BIT 0
32 BITS
0xFFFFFFFF
0x00000004
0x00000000
Figure 17. Little Endian Format
FLASH/EE MEMORY
The total 64 kB of Flash/EE memory is organized as 32k × 16 bits;
31k × 16 bits is user space and 1 k × 16 bits is reserved for the
on-chip kernel. The page size of this Flash/EE memory is 512 bytes.
62 kilobytes of Flash/EE memory are available to the user as
code and nonvolatile data memory. There is no distinction
between data and program because ARM code shares the same
space. The real width of the Flash/EE memory is 16 bits, which
means that in ARM mode (32-bit instruction), two accesses to
the Flash/EE are necessary for each instruction fetch. It is,
therefore, recommended to use Thumb mode when executing
from Flash/EE memory for optimum access speed. The
maximum access speed for the Flash/EE memory is 41.78 MHz
in Thumb mode and 20.89 MHz in full ARM mode. More
details about Flash/EE access time are outlined later in the
Execution Time from SRAM and Flash/EE section.
SRAM
Eight kilobytes of SRAM are available to the user, organized as
2k × 32 bits, that is, two words. ARM code can run directly from
SRAM at 41.78 MHz, given that the SRAM array is configured
as a 32-bit wide memory array. More details about SRAM access
time are outlined later in the Execution Time from SRAM and
Flash/EE section.
MEMORY MAPPED REGISTERS
The memory mapped register (MMR) space is mapped into the
upper two pages of the memory array and accessed by indirect
addressing through the ARM7 banked registers.
The MMR space provides an interface between the CPU and
all on-chip peripherals. All registers, except the core registers,
reside in the MMR area. All shaded locations shown in Figure 18
are unoccupied or reserved locations and should not be
accessed by user software. Table 10 to Table 23 show the full
MMR memory map.
The access time for reading from or writing to an MMR depends
on the advanced microcontroller bus architecture (AMBA) bus
used to access the peripheral. The processor has two AMBA
buses: advanced high performance bus (AHB) used for system
modules and advanced peripheral bus (APB) used for lower
performance peripheral. Access to the AHB is one cycle, and
access to the APB is two cycles. All peripherals on the ADuC7023
are on the APB except the Flash/EE memory and the GPIOs.
ADuC7023 Data Sheet
FLASH CONTROL
INTERFACE
GPIO
PLA
SPI
I2C1
I2C0
DAC
ADC
BAND GAP
REFERENCE
POWER SUPPLY
MONITOR
PLL AND
OSCILLATOR CONTROL
WATCHDOG
TIMER
GENERAL-PURPOSE
TIMER
TIMER0
REMAP AND
SYSTEM CONTROL
INTERRUPT
CONTROLLER
0xFFFFFFFF
0xFFFFF820
0xFFFFF800
0xFFFFF46C
0xFFFFF400
0xFFFF0FBF
0xFFFF0F80
0xFFFF0B54
0xFFFF0B00
0xFFFF0A14
0xFFFF0A00
0xFFFF0948
0xFFFF0900
0xFFFF0848
0xFFFF0800
0xFFFF0620
0xFFFF0600
0xFFFF0538
0xFFFF0500
0xFFFF0490
0xFFFF048C
0xFFFF0448
0xFFFF0440
0xFFFF0420
0xFFFF0404
0xFFFF0370
0xFFFF0360
0xFFFF0334
0xFFFF0320
0xFFFF0310
0xFFFF0300
0xFFFF0238
0xFFFF0220
0xFFFF0140
0xFFFF0000
08675-011
PWM
Figure 18. Memory Mapped Registers
Rev. G | Page 24 of 97
Table 10. IRQ Address Base : OxFFFFOOOO
Data Sheet ADuC7023
Table 10. IRQ Address Base = 0xFFFF0000
Address Name Byte Access Type Default Value Description
0x0000 IRQSTA 4 R 0x00000000 Active IRQ source.
0x0004 IRQSIG 4 R Current state of all IRQ sources (enabled and disabled).
0x0008 IRQEN 4 R/W 0x00000000 Enabled IRQ sources.
0x000C IRQCLR 4 W MMR to disable IRQ sources.
0x0010 SWICFG 4 W Software interrupt configuration MMR.
0x0014 IRQBASE 4 R/W 0x00000000 Base address of all vectors. Points to start of a 64-byte memory block
which can contain up to 32 pointers to separate subroutine handlers.
0x001C IRQVEC 4 R 0x00000000
This register contains the subroutine address for the currently active IRQ
source.
0x0020 IRQP0 4 R/W 0x00000000 This register contains the interrupt priority setting for Interrupt Source 1
to Interrupt Source 7. An interrupt can have a priority setting of 0 to 7.
0x0024 IRQP1 4 R/W 0x00000000 This register contains the interrupt priority setting for Interrupt Source 8
to Interrupt Source 15.
0x0028 IRQP2 4 R/W 0x00000000 This register contains the interrupt priority setting for Interrupt Source 16 to
Interrupt Source 21.
0x002C
RESERVED
4
R/W
0x00000000
Reserved.
0x0030 IRQCONN 4 R/W 0x00000000 Used to enable IRQ and FIQ interrupt nesting.
0x0034 IRQCONE 4 R/W 0x00000000 This register configures the external interrupt sources as rising edge,
falling edge, or level triggered.
0x0038 IRQCLRE 4 R/W 0x00000000 Used to clear an edge level triggered interrupt source.
0x003C IRQSTAN 4 R/W 0x00000000 This register indicates the priority level of an interrupt that has just
caused an interrupt exception.
0x0100 FIQSTA 4 R 0x00000000 Active FIQ source.
0x0104 FIQSIG 4 R Current state of all FIQ sources (enabled and disabled).
0x0108 FIQEN 4 R/W 0x00000000 Enabled FIQ sources.
0x010C FIQCLR 4 W MMR to disable FIQ sources.
0x011C
FIQVEC
4
R
0x00000000
FIQ interrupt vector.
0x013C FIQSTAN 4 RW 0x00000000 This register indicates the priority level of an FIQ that has just caused an
FIQ exception.
Table 11. System Control Address Base = 0xFFFF0200
Address Name Byte Access Type Default Value1 Description
0x0220 Remap2 1 R/W 0x00 Remap control register.
0x0230 RSTSTA 1 R/W 0x01 RSTSTA status MMR.
0x0234 RSTCLR 1 W 0x00 RSTCLR MMR for clearing RSTSTA register.
0x0248 RSTKEY1 1 W 0xXX 0x76 should be written to this register before writing to RSTCFG.
0x024C RSTCFG 1 R/W 0x00 This register allows the DAC and GPIO outputs to retain state after a
watchdog or software reset.
0x0250 RSTKEY2 1 W 0xXX 0xB1 should be written to this register after writing to RSTCFG.
1 N/A means not applicable.
2 Updated by kernel.
Rev. G | Page 25 of 97
Table 13. PLL/PSM Base Address : OXFFFF0400 Table [5. ADC Address Base : OxFFFFOSOO
ADuC7023 Data Sheet
Table 12. Timer Address Base = 0xFFFF0300
Address Name Byte Access Type Default Value1 Description
0x0300 T0LD 2 R/W 0x0000 Timer0 load register.
0x0304 T0VAL 2 R 0xFFFF Timer0 value register.
0x0308 T0CON 2 R/W 0x0000 Timer0 control MMR.
0x030C T0CLRI 1 W 0xXX Timer0 interrupt clear register.
0x0320 T1LD 4 R/W 0x00000000 Timer1 load register.
0x0324 T1VAL 4 R 0xFFFFFFFF Timer1 value register
0x0328 T1CON 4 R/W 0x00000000 Timer1 control MMR.
0x032C T1CLRI 1 W 0xXX Timer1 interrupt clear register.
0x0330 T1CAP 4 R 0x00000000 Timer1 capture register.
0x0360
T2LD
2
R/W
0x0000
Timer2 load register.
0x0364 T2VAL 2 R 0xFFFF Timer2 value register.
0x0368 T2CON 2 R/W 0x0000 Timer2 control MMR.
0x036C T2CLRI 1 W 0xXX Timer2 interrupt clear register.
1 N/A means not applicable.
Table 13. PLL/PSM Base Address = 0xFFFF0400
Address Name Byte Access Type Default Value1 Description
0x0404 POWKEY1 2 W 0xXXXX POWCON0 prewrite key.
0x0408 POWCON0 1 R/W 0x00 Power control and core speed control register.
0x040C
POWKEY2
2
W
0xXXXX
POWCON0 postwrite key.
0x0410 PLLKEY1 2 W 0xXXXX PLLCON prewrite key.
0x0414 PLLCON 1 R/W 0x21 PLL clock source selection MMR.
0x0418 PLLKEY2 2 W 0xXXXX PLLCON postwrite key.
0x0434 POWKEY3 2 W 0xXXXX POWCON1 prewrite key.
0x0438 POWCON1 2 R/W 0x0004 Power control and core speed control register.
0x043C POWKEY4 2 W 0xXXXX POWCON1 postwrite key.
0x0440 PSMCON 2 R/W 0x0008 Power supply monitor control register.
0x0444 CMPCON 2 R/W 0x0000 Comparator control register.
1 N/A means not applicable.
Table 14. Reference Base Address = 0xFFFF0480
Address: 0x048C
Name: REFCON
Byte: 1
Access type: Read/write
Default value: 0x00
Description: Reference control register.
Table 15. ADC Address Base = 0xFFFF0500
Address Name Byte Access Type Default Value Description
0x0500 ADCCON 2 R/W 0x0600 ADC control MMR.
0x0504 ADCCP 1 R/W 0x00 ADC positive channel selection register.
0x0508 ADCCN 1 R/W 0x01 ADC negative channel selection register.
0x050C ADCSTA 1 R 0x00 ADC status MMR.
0x0510 ADCDAT 4 R 0x00000000 ADC data output MMR.
0x0514 ADCRST 1 R/W 0x00 ADC reset MMR.
Rev. G | Page 26 of 97
Table 18. 1 C1 Base Add! css : 0XFFFF0900
Data Sheet ADuC7023
Address Name Byte Access Type Default Value Description
0x0530 ADCGN 2 R/W Factory configured ADC gain calibration MMR.
0x0534 ADCOF 2 R/W Factory configured ADC offset calibration MMR.
0x0544 TSCON 1 R/W 0x00 Temperature sensor chopping enable register.
0x0548 TEMPREF 2 R/W Factory configured Temperature sensor reference value.
Table 16. DAC Address Base = 0xFFFF0600
Address Name Byte Access Type Default Value Description
0x0600 DAC0CON 1 R/W 0x00 DAC0 control MMR.
0x0604 DAC0DAT 4 R/W 0x00000000 DAC0 data MMR.
0x0608 DAC1CON 1 R/W 0x00 DAC1 control MMR.
0x060C DAC1DAT 4 R/W 0x00000000 DAC1 data MMR.
0x0610 DAC2CON 1 R/W 0x00 DAC2 control MMR.
0x0614 DAC2DAT 4 R/W 0x00000000 DAC2 data MMR.
0x0618
DAC3CON
1
R/W
0x00
DAC3 control MMR.
0x061C DAC3DAT 4 R/W 0x00000000 DAC3 data MMR.
0x0654 DACBCFG 1 R/W 0x00 DAC Configuration MMR
0x0650 DACBKEY0 2 W 0x0000 DAC Key0 MMR
0x0658 DACBKEY1 2 W 0x0000 DAC Key1 MMR
Table 17. I2C0 Base Address = 0XFFFF0800
Address Name Byte Access Type Default Value Description
0x0800 I2C0MCON 2 R/W 0x0000 I2C0 master control register.
0x0804
I2C0MSTA
2
R
0x0000
I
2
C0 master status register.
0x0808 I2C0MRX 1 R 0x00 I2C0 master receive register.
0x080C I2C0MTX 1 W 0x00 I2C0 master transmit register.
0x0810 I2C0MCNT0 2 R/W 0x0000 I2C0 master read count register. Write the number of required
bytes into this register prior to reading from a slave device.
0x0814 I2C0MCNT1 1 R 0x00 I2C0 master current read count register. This register contains the
number of bytes already received during a read from slave sequence.
0x0818 I2C0ADR0 1 R/W 0x00 I2C0 address byte register. Write the required slave address in here
prior to communications.
0x081C I2C0ADR1 1 R/W 0x00 I2C0 address byte register. Write the required slave address in here
prior to communications. Used in 10-bit mode only.
0x0824
I2C0DIV
2
R/W
0x1F1F
I
2
C0 clock control register. Used to configure the SCL frequency.
0x0828 I2C0SCON 2 R/W 0x0000 I2C0 slave control register.
0x082C I2C0SSTA 2 R/W 0x0000 I2C0 slave status register.
0x0830 I2C0SRX 1 R 0x00 I2C0 slave receive register.
0x0834 I2C0STX 1 W 0x00 I2C0 slave transmit register.
0x0838 I2C0ALT 1 R/W 0x00 I2C0 hardware general call recognition register.
0x083C I2C0ID0 1 R/W 0x00 I2C0 slave ID0 register. Slave bus ID register.
0x0840 I2C0ID1 1 R/W 0x00 I2C0 slave ID1 register. Slave bus ID register.
0x0844 I2C0ID2 1 R/W 0x00 I2C0 slave ID2 register. Slave bus ID register.
0x0848 I2C0ID3 1 R/W 0x00 I2C0 slave ID3 register. Slave bus ID register.
0x084C I2C0FSTA 2 R/W 0x0000 I2C0 FIFO status register. Used in both master and slave modes.
Table 18. I2C1 Base Address = 0XFFFF0900
Address Name Byte Access Type Default Value Description
0x0900 I2C1MCON 2 R/W 0x0000 I2C1 master control register.
0x0904 I2C1MSTA 2 R 0x0000 I2C1 master status register.
0x0908 I2C1MRX 1 R 0x00 I2C1 master receive register.
0x090C I2C1MTX 1 W 0x00 I2C1 master transmit register.
0x0910 I2C1MCNT0 2 R/W 0x0000 I2C1 master read count register. Write the number of required bytes
into this register prior to reading from a slave device.
Rev. G | Page 27 of 97
Table 20. PLA Base Add: cs5 : OXFFFFOBOO
ADuC7023 Data Sheet
Address Name Byte Access Type Default Value Description
0x0914 I2C1MCNT1 1 R 0x00 I2C1 master current read count register. This register contains the
number of bytes already received during a read from slave sequence.
0x0918 I2C1ADR0 1 R/W 0x00 I2C1 address byte register. Write the required slave address in here
prior to communications.
0x091C
I2C1ADR1
1
R/W
0x00
I
2
C1 address byte register. Write the required slave address in here
prior to communications. Used in 10-bit mode only.
0x0924 I2C1DIV 2 R/W 0x1F1F I2C1 clock control register. Used to configure the SCL frequency.
0x0928 I2C1SCON 2 R/W 0x0000 I2C1 slave control register.
0x092C I2C1SSTA 2 R/W 0x0000 I2C1 slave status register.
0x0930 I2C1SRX 1 R 0x00 I2C1 slave receive register.
0x0934 I2C1STX 1 W 0x00 I2C1 slave transmit register.
0x0938 I2C1ALT 1 R/W 0x00 I2C1 hardware general call recognition register.
0x093C I2C1ID0 1 R/W 0x00 I2C1 slave ID0 register. Slave bus ID register.
0x0940 I2C1ID1 1 R/W 0x00 I2C1 slave ID1 register. Slave bus ID register.
0x0944 I2C1ID2 1 R/W 0x00 I2C1 slave ID2 register. Slave bus ID register.
0x0948 I2C1ID3 1 R/W 0x00 I2C1 slave ID3 register. Slave bus ID register.
0x094C I2C1FSTA 2 R/W 0x0000 I2C1 FIFO status register. Used in both master and slave modes.
Table 19. SPI Base Address = 0xFFFF0A00
Address Name Byte Access Type Default Value Description
0x0A00 SPISTA 2 R 0x0000 SPI status MMR.
0x0A04 SPIRX 1 R 0x00 SPI receive MMR.
0x0A08 SPITX 1 W 0xXX SPI transmit MMR.
0x0A0C SPIDIV 1 R/W 0x00 SPI baud rate select MMR.
0x0A10
SPICON
2
R/W
0x0000
SPI control MMR.
Table 20. PLA Base Address = 0XFFFF0B00
Address Name Byte Access Type Default Value Description
0x0B00 PLAELM0 2 R/W 0x0000 PLA Element 0 control register.
0x0B04 PLAELM1 2 R/W 0x0000 PLA Element 1 control register.
0x0B08 PLAELM2 2 R/W 0x0000 PLA Element 2 control register.
0x0B0C PLAELM3 2 R/W 0x0000 PLA Element 3 control register.
0x0B10 PLAELM4 2 R/W 0x0000 PLA Element 4 control register.
0x0B14
PLAELM5
2
R/W
0x0000
PLA Element 5 control register.
0x0B18 PLAELM6 2 R/W 0x0000 PLA Element 6 control register.
0x0B1C PLAELM7 2 R/W 0x0000 PLA Element 7 control register.
0x0B20 PLAELM8 2 R/W 0x0000 PLA Element 8 control register.
0x0B24 PLAELM9 2 R/W 0x0000 PLA Element 9 control register.
0x0B28 PLAELM10 2 R/W 0x0000 PLA Element 10 control register.
0x0B2C PLAELM11 2 R/W 0x0000 PLA Element 11 control register.
0x0B30 PLAELM12 2 R/W 0x0000 PLA Element 12 control register.
0x0B34 PLAELM13 2 R/W 0x0000 PLA Element 13 control register.
0x0B38 PLAELM14 2 R/W 0x0000 PLA Element 14 control register.
0x0B3C PLAELM15 2 R/W 0x0000 PLA Element 15 control register.
0x0B40 PLACLK 1 R/W 0x00 PLA clock select register.
0x0B44 PLAIRQ 4 R/W 0x00000000 PLA interrupt control register.
0x0B48 PLAADC 4 R/W 0x00000000 PLA ADC trigger control register.
0x0B4C PLADIN 4 R/W 0x00000000 PLA data in register.
0x0B50 PLADOUT 4 R 0x00000000 PLA data out register.
0x0B54 PLALCK 1 W 0x00 PLA lock register.
Rev. G | Page 28 of 97
Table 21. PWM Base Address : OXFFFFOFSO Table 22. GPlO Base Address : OXFFFFF400 Table 23. Flash/Eli Base Address : OXFFFFFSOO
Data Sheet ADuC7023
Table 21. PWM Base Address = 0xFFFF0F80
Address Name Byte Access Type Default Value Description
0x0F80 PWMCON1 2 R/W 0x0012 PWM Control Register 1. See the Pulse-Width Modulator section
for full details.
0x0F84 PWM0COM0 2 R/W 0x0000 Compare Register 0 for PWM Output 0 and PWM Output 1.
0x0F88 PWM0COM1 2 R/W 0x0000 Compare Register 1 for PWM Output 0 and PWM Output 1.
0x0F8C PWM0COM2 2 R/W 0x0000 Compare Register 2 for PWM Output 0 and PWM Output 1.
0x0F90 PWM0LEN 2 R/W 0x0000 Frequency control for PWM Output 0 and PWM Output 1.
0x0F94 PWM1COM0 2 R/W 0x0000 Compare Register 0 for PWM Output 2 and PWM Output 3.
0x0F98 PWM1COM1 2 R/W 0x0000 Compare Register 1 for PWM Output 2 and PWM Output 3.
0x0F9C PWM1COM2 2 R/W 0x0000 Compare Register 2 for PWM Output 2 and PWM Output 3.
0x0FA0
PWM1LEN
2
R/W
0x0000
Frequency control for PWM Output 2 and PWM Output 3.
0x0FA4 PWM2COM0 2 R/W 0x0000 Compare Register 0 for PWM Output 4.
0x0FA8 PWM2COM1 2 R/W 0x0000 Compare Register 1 for PWM Output 4.
0x0FB0 PWM2LEN 2 R/W 0x0000 Frequency control for PWM Output 4.
0x0FB8 PWMCLRI 2 W 0x0000 PWM interrupt clear register. Writing any value to this register
clears a PWM interrupt source.
Table 22. GPIO Base Address = 0xFFFFF400
Address Name Byte Access Type Default Value Description
0xF400
GP0CON
4
R/W
0x00001111
GPIO Port0 control MMR.
0xF404 GP1CON 4 R/W 0x00000000 GPIO Port1 control MMR.
0xF408 GP2CON 4 R/W 0x00000000 GPIO Port2 control MMR.
0xF420 GP0DAT 4 R/W 0x000000XX GPIO Port0 data control MMR.
0xF424 GP0SET 4 W 0x000000XX GPIO Port0 data set MMR.
0xF428 GP0CLR 4 W 0x000000XX GPIO Port0 data clear MMR.
0xF42C GP0PAR 4 R/W 0x22220000 GPIO Port0 pull-up disable MMR.
0xF430 GP1DAT 4 R/W 0x000000XX GPIO Port1 data control MMR.
0xF434 GP1SET 4 W 0x000000XX GPIO Port1 data set MMR.
0xF438 GP1CLR 4 W 0x000000XX GPIO Port1 data clear MMR.
0xF43C GP1PAR 4 R/W 0x22000022 GPIO Port1 pull-up disable MMR.
0xF440
GP2DAT
4
R/W
0x000000XX
GPIO Port2 data control MMR.
0xF444 GP2SET 4 W 0x000000XX GPIO Port2 data set MMR.
0xF448 GP2CLR 4 W 0x000000XX GPIO Port2 data clear MMR.
0xF44C GP2PAR 4 R/W 0x00000000 GPIO Port2 pull-up disable MMR.
Table 23. Flash/EE Base Address = 0xFFFFF800
Address Name Byte Access Type Default Value Description
0xF800 FEESTA 1 R 0x20 Flash/EE status MMR.
0xF804 FEEMOD 2 R/W 0x0000 Flash/EE control MMR.
0xF808
FEECON
1
R/W
0x07
Flash/EE control MMR.
0xF80C FEEDAT 2 R/W 0xXXXX Flash/EE data MMR.
0xF810 FEEADR 2 R/W 0x0000 Flash/EE address MMR.
0xF818 FEESIGN 3 R 0xFFFFFF Flash/EE LFSR MMR.
0xF81C FEEPRO 4 R/W 0x00000000 Flash/EE protection MMR.
0xF820 FEEHIDE 4 R/W 0xFFFFFFFF Flash/EE protection MMR.
Rev. G | Page 29 of 97
ADuC7023 Data Sheet
Rev. G | Page 30 of 97
ADC CIRCUIT OVERVIEW
The analog-to-digital converter (ADC) incorporates a fast,
multichannel, 12-bit ADC. It can operate from 2.7 V to 3.6 V
supplies and is capable of providing a throughput of up to
1 MSPS when the clock source is 41.78 MHz. This block
provides the user with a multichannel multiplexer, a differential
track-and-hold, an on-chip reference, and an ADC.
The ADC consists of a 12-bit successive approximation
converter based around two capacitor DACs. Depending on the
input signal configuration, the ADC can operate in one of two
different modes: fully differential mode (for small and balanced
signals) or single-ended mode (for any single-ended signals).
The converter accepts an analog input range of 0 V to VREF when
operating in single-ended mode. In fully differential mode, the
input signal must be balanced around a common-mode voltage
(VCM) in the 0 V to AVDD range with a maximum amplitude of
2 VREF (see Figure 19).
08675-012
AV
DD
V
CM
V
CM
V
CM
0
2V
REF
2V
REF
2V
REF
Figure 19. Examples of Balanced Signals in Fully Differential Mode
A high precision, low drift, factory calibrated, 2.5 V reference is
provided on chip. An external reference can also be connected as
described later in the Band Gap Reference section.
Single or continuous conversion modes can be initiated in the
software. An external CONVSTART pin, an output generated from
the on-chip PLA, or a Timer0 or Timer1 overflow can also be
used to generate a repetitive trigger for ADC conversions.
A voltage output from an on-chip band gap reference propor-
tional to absolute temperature can also be routed through the
front-end ADC multiplexer. This temperature channel can be
selected as an ADC input. This facilitates an internal temperature
sensor channel that measures die temperature.
TRANSFER FUNCTION
Single-Ended Mode
In single-ended mode, the input range is 0 V to VREF. The
output coding is straight binary in single-ended mode with
1 LSB = FS/4096, or
2.5 V/4096 = 0.61 mV, or
610 μV when VREF = 2.5 V
The ideal code transitions occur midway between successive
integer LSB values (that is, 1/2 LSB, 3/2 LSB, 5/2 LSB, … ,
FS − 3/2 LSB). The ideal input/output transfer characteristic
is shown in Figure 20.
08675-013
OUTPUT CODE
VOLTAGE INPUT
1111 1111 1111
1111 1111 1110
1111 1111 1101
1111 1111 1100
0000 0000 0011
1LSB0V +FS – 1LSB
0000 0000 0010
0000 0000 0001
0000 0000 0000
1LSB = FS
4096
Figure 20. ADC Transfer Function in Single-Ended Mode
Fully Differential Mode
The amplitude of the differential signal is the difference between
the signals applied to the VIN+ and VIN– pins (that is, VIN+
VIN−). The maximum amplitude of the differential signal is,
therefore, −VREF to +VREF p-p (that is, 2 × VREF). This is regardless of
the common mode (CM). The common mode is the average of
the two signals, for example, (VIN+ + VIN–)/2, and is, therefore,
the voltage on which the two inputs are centered. This results in
the span of each input being CM ±VREF/2. This voltage has to be
set up externally, and its range varies with VREF (see the Driving
the Analog Inputs section).
The output coding is twos complement in fully differential mode
with 1 LSB = 2 VREF/4096 or 2 × 2.5 V/4096 = 1.22 mV when
VREF = 2.5 V. The output result is ±11 bits, but this is shifted by
one to the right. This allows the result in the ADCDAT MMR to
be declared as a signed integer when writing C code. The
designed code transitions occur midway between successive
integer LSB values (that is, 1/2 LSB, 3/2 LSB, 5/2 LSB, … , FS −
3/2 LSB). The ideal input/output transfer characteristic is shown
in Figure 21.
08675-014
OUTPUT CODE
VOLTAGE INPUT (V
IN
+ – V
IN
–)
0 1111 1111 1110
0 1111 1111 1100
0 1111 1111 1010
0 0000 0000 0010
0 0000 0000 0000
1 1111 1111 1110
1 0000 0000 0100
1 0000 0000 0010
1 0000 0000 0000
–V
REF
+ 1LSB +V
REF
– 1LSB0LSB
1LSB = 2 × V
REF
4096
SIGN
BIT
Figure 21. ADC Transfer Function in Differential Mode
Wfiflj
Data Sheet ADuC7023
Rev. G | Page 31 of 97
TYPICAL OPERATION
When configured via the ADC control and channel selection
registers, the ADC converts the analog input and provides a
12-bit result in the ADC data register.
The top four bits are the sign bits. The 12-bit result is placed
from Bit 16 to Bit 27 as shown in Figure 22. Note that in fully
differential mode, the result is represented in twos complement
format. In single-ended mode, the result is represented in
straight binary format.
08675-015
SIGN BITS 12-BIT ADC RESULT
31 27 16 15 0
Figure 22. ADC Result Format
The same format is used in DACxDAT, simplifying the software.
Current Consumption
The ADC in standby mode, that is, powered up but not
converting, typically consumes 640 μA. The internal reference
adds 140 μA. During conversion, the extra current is 0.3 μA
multiplied by the sampling frequency (in kHz).
Timing
Figure 23 gives details of the ADC timing. Users control the
ADC clock speed and the number of acquisition clocks in the
ADCCON MMR. By default, the acquisition time is eight
clocks, and the clock divider is two. The number of extra clocks
(such as bit trial or write) is set to 19, which gives a sampling
rate of 774 kSPS. For conversion on the temperature sensor, set
ADCCON = 0x37A3. When using multiple channels including
the temperature sensor, the timing settings revert to the user-
defined settings after reading the temperature sensor channel.
08675-016
ADC CLOCK
A
CQ BIT TRIAL
DATA
ADCSTA = 0 ADCSTA = 1
ADC INTERRUPT
WRITE
CONV
START
ADC
BUSY
ADCDAT
Figure 23. ADC Timing
MMR INTERFACE
The ADC is controlled and configured via the eight MMRs
described in this section.
ADCCON Register
Name: ADCCON
Address: 0xFFFF0500
Default value: 0x0600
Access: Read/write
Function: ADCCON is an ADC control register
that allows the programmer to enable the
ADC peripheral, select the mode of
operation of the ADC (either in single-
ended mode or fully differential mode),
and select the conversion type. This MMR
is described in Table 24.
Table 24. ADCCON MMR Bit Designations
Bit Value Description
15 to 14 Reserved.
13
Temperature sensor conversion enable. Set to 1 for temperature sensor conversions and single
software conversions. Set to 0 for normal ADC conversions.
12 to 10 ADC clock speed.
000 fADC/1. This divider is provided to obtain 1 MSPS ADC with an external clock <41.78 MHz.
001 fADC/2 (default value).
010 fADC/4.
011 fADC/8.
100 fADC/16.
101 fADC/32.
9 to 8 ADC acquisition time.
00 2 clocks.
01 4 clocks.
10 8 clocks (default value).
11 16 clocks.
ADuC7023 Data Sheet
Bit Value Description
7 Enable start conversion.
This bit is set by the user to start any type of conversion command.
This bit is cleared by the user to disable a start conversion (clearing this bit does not stop the ADC
when continuously converting).
6 Reserved
5 ADC power control.
This bit is set by the user to place the ADC in normal mode (the ADC must be powered up for at least
5 μs before it converts correctly).
This bit is cleared by the user to place the ADC in power-down mode.
4 to 3 Conversion mode.
00 Single-ended mode.
01 Differential mode.
10 Reserved.
11 Reserved.
2 to 0 Conversion type.
000 Enable CONVSTART pin as a conversion input.
001 Enable Timer1 as a conversion input.
010 Enable Timer0 as a conversion input.
011 Single software conversion. This bit is set to 000 after conversion (note that Bit 13 of the ADCCON
MMR should be set before starting a single software conversion to avoid further conversions
triggered by the CONVSTART pin).
100
Continuous software conversion.
101 PLA conversion.
Other Reserved.
ADCCP Register
Name: ADCCP
Address: 0xFFFF0504
Default value: 0x00
Access: Read/write
Function: ADCCP is an ADC positive channel
selection register. This MMR is described in
Table 25.
Table 25. ADCCP MMR Bit Designation
Bit Value Description
7 to 5
Reserved.
4 to 0 Positive channel selection bits.
00000 ADC0.
00001 ADC1.
00010 ADC2.
00011 ADC3.
00100 ADC41.
00101 ADC51.
00110 ADC61.
00111
ADC7
1
.
01000 ADC81.
01001 ADC91.
01010
ADC101.
01011 Reserved.
01100 ADC121.
01101 Reserved
01110 DAC0
01111 DAC1
10000 Temperature sensor.
10001 AGND (self-diagnostic feature).
10010 Internal reference (self-diagnostic feature).
10011 AVDD/2.
Others
Reserved.
1 When a selected ADC channel is shared with one GPIO, by default, this pin is
configured with a weak pull-up resistor enabled. The pull-up resistor should
be disabled manually in the appropriate GPxPAR register. Note the internal
pull-up resistor on P2.0/AIN12 for 40-lead package cannot be disabled.
Rev. G | Page 32 of 97
Data Sheet ADuC7023
ADCCN Register
Name: ADCCN
Address: 0xFFFF0508
Default value: 0x01
Access: Read/write
Function: ADCCN is an ADC negative channel
selection register. This MMR is described in
Table 26.
Table 26. ADCCN MMR Bit Designation
Bit Value Description
7 to 5 Reserved.
4 to 0 Negative channel selection bits.
00000 ADC0.
00001 ADC1.
00010 ADC2.
00011 ADC3.
00100 ADC4.
00101 ADC5.
00110 ADC6.
00111 ADC7.
01000
ADC8.
01001 ADC9.
01010 ADC10.
01011 Reserved
01100 ADC12.
01101 Reserved
01110 Reserved
01111 DAC1.
10000 Temperature sensor.
10001 AGND (self-diagnostic feature).
10010 Internal reference (self-diagnostic feature).
10011 Reserved
Others Reserved.
ADCSTA Register
Name: ADCSTA
Address: 0xFFFF050C
Default Value: 0x00
Access: Read
Function: ADCSTA is an ADC status register that
indicates when an ADC conversion result is
ready. The ADCSTA register contains only
one bit, ADCReady (Bit 0), representing
the status of the ADC. This bit is set at the
end of an ADC conversion, generating an
ADC interrupt. It is cleared automatically
by reading the ADCDAT MMR. When the
ADC is performing a conversion, the status
of the ADC can be read externally via the
ADCBUSY pin. This pin is high during a
conversion. When the conversion is
finished, ADCBUSY goes back low. This
information can be available on P0.0 (see
the General-Purpose Input/Output section)
if enabled in the ADCCON register.
ADCDAT Register
Name: ADCDAT
Address: 0xFFFF0510
Default value: 0x00000000
Access: Read
Function: ADCDAT is an ADC data result register.
Hold the 12-bit ADC result as shown in
Figure 22.
ADCRST Register
Name: ADCRST
Address: 0xFFFF0514
Default Value: 0x00
Access: Read/write
Function: ADCRST resets the digital interface of the
ADC. Writing any value to this register
resets all the ADC registers to their
default value.
Rev. G | Page 33 of 97
M M ) H} h
ADuC7023 Data Sheet
Rev. G | Page 34 of 97
ADCGN Register
Name: ADCGN
Address: 0xFFFF0530
Default value: Factory configured
Access: Read/write
Function: ADCGN is a 10-bit gain calibration
register.
ADCOF Register
Name: ADCOF
Address: 0xFFFF0534
Default value: Factory configured
Access: Read/write
Function: ADCOF is a 10-bit offset calibration
register.
CONVERTER OPERATION
The ADC incorporates a successive approximation (SAR)
architecture involving a charge-sampled input stage. This
architecture can operate in two different modes: differential
and single-ended.
Differential Mode
The ADuC7023 contains a successive approximation ADC
based on two capacitive DACs. Figure 24 and Figure 25 show
simplified schematics of the ADC in acquisition and conversion
phase, respectively. The ADC is comprised of control logic, a
SAR, and two capacitive DACs. In Figure 24 (the acquisition
phase), SW3 is closed and SW1 and SW2 are in Position A. The
comparator is held in a balanced condition, and the sampling
capacitor arrays acquire the differential signal on the input.
08675-017
CAPACITIVE
DAC
CAPACITIVE
DAC
CONTROL
LOGIC
COMPARATOR
SW3
SW1
A
A
B
B
SW2
C
S
C
S
V
REF
ADC0
A
DC11
MUX
CHANNEL+
CHANNEL
Figure 24. ADC Acquisition Phase
08675-018
CAPACITIVE
DAC
CAPACITIVE
DAC
CONTROL
LOGIC
COMPARATOR
SW3
SW1
A
A
B
B
SW2
C
S
C
S
V
REF
ADC0
A
DC11
MUX
CHANNEL+
CHANNEL
Figure 25. ADC Conversion Phase
When the ADC starts a conversion, as shown in Figure 25,
SW3 opens, and then SW1 and SW2 move to Position B. This
causes the comparator to become unbalanced. Both inputs are
disconnected once the conversion begins. The control logic
and the charge redistribution DACs are used to add and
subtract fixed amounts of charge from the sampling capacitor
arrays to bring the comparator back into a balanced condition.
When the comparator is rebalanced, the conversion is complete.
The control logic generates the ADC output code. The output
impedances of the sources driving the VIN+ and VIN– pins must
be matched; otherwise, the two inputs have different settling
times, resulting in errors.
Single-Ended Mode
In single-ended mode, SW2 is always connected internally to
ground. The VIN− pin can be floating. The input signal range on
VIN+ is 0 V to VREF.
08675-020
CAPACITIVE
DAC
CAPACITIVE
DAC
CONTROL
LOGIC
COMPARATOR
SW3
SW1
A
BC
S
C
S
ADC0
A
DC11
MUX
CHANNEL+
CHANNEL
Figure 26. ADC in Single-Ended Mode
Analog Input Structure
Figure 27 shows the equivalent circuit of the analog input structure
of the ADC. The four diodes provide ESD protection for the analog
inputs. Care must be taken to ensure that the analog input signals
never exceed the supply rails by more than 300 mV; this causes
these diodes to become forward-biased and start conducting
into the substrate. These diodes can conduct up to 10 mA
without causing irreversible damage to the part.
Data Sheet ADuC7023
The C1 capacitors in Figure 27 are typically 4 pF and can be
primarily attributed to pin capacitance. The resistors are
lumped components made up of the on resistance of the
switches. The value of these resistors is typically about 100 Ω.
The C2 capacitors are the ADC sampling capacitors and
typically have a capacitance of 16 pF.
AV
DD
C1
D
D
R1 C2
AV
DD
C1
D
D
R1 C2
08675-021
Figure 27. Equivalent Analog Input Circuit Conversion Phase: Switches Open,
Track Phase: Switches Closed
For ac applications, removing high frequency components from
the analog input signal is recommended by using an RC low-
pass filter on the relevant analog input pins. In applications
where harmonic distortion and signal-to-noise ratio are critical,
the analog input should be driven from a low impedance
source. Large source impedances significantly affect the ac
performance of the ADC. This can necessitate the use of an
input buffer amplifier. The choice of the op amp is a function of
the particular application. Figure 28 and Figure 29 give an
example of an ADC front end.
08675-022
ADuC7023
ADC0
10Ω
0.01µF
Figure 28. Buffering Single-Ended Differential Input
08675-023
ADuC7023
ADC0
V
REF
ADC1
Figure 29. Buffering Differential Inputs
When no amplifier is used to drive the analog input, limit the
source impedance to values lower than 1 kΩ. The maximum
source impedance depends on the amount of total harmonic
distortion (THD) that can be tolerated. The THD increases as
the source impedance increases and the performance degrades.
DRIVING THE ANALOG INPUTS
Internal or external references can be used for the ADC. When
operating in differential mode, there are restrictions on the
common-mode input signal (VCM), which is dependent upon
the reference value and supply voltage used to ensure that the
signal remains within the supply rails. Table 27 gives some
calculated VCM minimum and VCM maximum values.
Table 27. VCM Ranges
AVDD VREF VCM Min VCM Max Signal Peak-to-Peak
3.3 V 2.5 V 1.25 V 2.05 V 2.5 V
2.048 V 1.024 V 2.276 V 2.048 V
1.25 V
0.75 V
2.55 V
1.25 V
3.0 V 2.5 V 1.25 V 1.75 V 2.5 V
2.048 V
1.024 V
1.976 V
2.048 V
1.25 V
0.75 V
2.25 V
1.25 V
CALIBRATION
By default, the factory-set values written to the ADC offset
(ADCOF) and gain coefficient registers (ADCGN) yield
optimum performance in terms of endpoint errors and linearity
for standalone operation of the part (see the Specifications
section). If system calibration is required, it is possible to
modify the default offset and gain coefficients to improve
endpoint errors, but note that any modification to the factory-
set ADCOF and ADCGN values can degrade ADC linearity
performance.
For system offset error correction, the ADC channel input stage
must be tied to AGND. A continuous software ADC conversion
loop must be implemented by modifying the value in ADCOF until
the ADC result (ADCDAT) reads Code 0 to Code 1. If the
ADCDAT value is greater than 1, ADCOF should be decremented
until ADCDAT reads Code 0 to Code 1. Offset error correction
is done digitally and has a resolution of 0.25 LSB and a range of
±3.125% of VREF.
For system gain error correction, the ADC channel input
stage must be tied to VREF. A continuous software ADC
conversion loop must be implemented to modify the value
in ADCGN until the ADCDAT reads Code 4094 to Code 4095.
If the ADCDAT value is less than 4094, ADCGN should be
incremented until ADCDAT reads Code 4094 to Code 4095.
Similar to the offset calibration, the gain calibration resolution
is 0.25 LSB with a range of ±3% of VREF.
TEMPERATURE SENSOR
The ADuC7023 provides a voltage output from an on-chip
band gap reference that is proportional to absolute temperature.
This voltage output can also be routed through the front-end
ADC multiplexer (effectively an additional ADC channel
input), facilitating an internal temperature sensor channel,
measuring die temperature.
An ADC temperature sensor conversion differs from a standard
ADC voltage. The ADC performance specifications do not
apply to the temperature sensor.
Chopping of the internal amplifier should be enabled using the
TSCON register. To enable this mode, the user must set Bit 0 of
TSCON. The user must also take two consecutive ADC readings
and average them in this mode.
Rev. G | Page 35 of 97
Table 29. TEMPREF MMR BR Designations
ADuC7023 Data Sheet
The ADCCON register must be configured to 0x37A3.
To calculate die temperature use the following formula:
TTREF = (VADCVTREF) × K
where:
T is the temperature result.
TREF is 25°C.
VADC is the average ADC result from two consecutive
conversions.
VTREF is 1369 mV, which corresponds to TREF = 25°C as
described in Table 1.
K is the gain of the ADC in temperature sensor mode as
determined by characterization data, K = 0.2262°C/mV. This
corresponds to 1/V TC specification as shown in Table 1.
Using the default values from Table 1 and without any calibra-
tion, this equation becomes
T – 25°C = (VADC − 1369) × 0.2262
where:
VADC is in millivolts.
For increased accuracy, perform a single point calibration at a
controlled temperature value.
For the calculation shown without calibration, (TREF, VTREF) =
(25°C, 1369 mV). The idea of a single point calibration is to use
other known (TREF, VTREF) values to replace the common (25°C,
1369 mV) for every part.
For some users, it is not possible to get such a known pair. For
these cases, an ADuC7023 comes with a single point calibration
value loaded in the TEMPREF register. For more details on this
register, see the TEMPREF Register section.
During production testing of the ADuC7023, the TEMPREF
register is loaded with an offset adjustment factor. Each part
will have a different value in the TEMPREF register. Using this
single point calibration, use the same formula as shown:
TTREF = (VADCVTREF) × K
where:
TREF is 27°C when using the TEMPREF register method, but is
not guaranteed.
TTREF can be calculated using the TEMPREF register.
TSCON Register
Name: TSCON
Address: 0xFFFF0544
Default value: 0x00
Access: Read/write
Table 28. TSCON MMR Bit Designations
Bit Description
7 to 1 Reserved.
0 Temperature sensor chop enable bit.
This bit is set to 1 to enable chopping of the internal
amplifier to the ADC.
This bit is cleared to disable chopping.
This bit is cleared by default.
TEMPREF Register
Name: TEMPREF
Address: 0xFFFF0548
Default value: Factory configured
Access: Read/write
Table 29. TEMPREF MMR Bit Designations
Bit Description
15 to 9 Reserved.
8 Temperature reference voltage sign.
7 to 0 Temperature sensor offset calibration voltage.
To calculate the VTREF from the TEMPREF register,
perform the following calculation:
If TEMPREF sign negative, subtract TEMPREF from 2292
CTREF = 2292 TEMPREF[7:0]
where TEMREF[8] = 1.
or
If TEMREF sign positive, add TEMPREF to 2292
CTREF = TEMPREF[7:0] + 2292
where:
TEMPREF[8] = 0.
Then,
VTREF = (CTREF × VREF)/4096 × 1000
where:
CTREF is calculated as above.
VREF is 2.5 V, internal reference voltage.
Insert VTREF into
TTREF = (VADCVTREF) × K
where:
TREF is 27°C, when using TEMREF register.
VADC is the average ADC result from two
consecutive conversions.
VTREF is calculated as above.
Note that ADC code value 2292 is a default value when
using the TEMREF register. It is not an exact value and
must only be used with the TEMPREF register.
Rev. G | Page 36 of 97
Table 30. REFCON MMR BR Designations
Data Sheet ADuC7023
BAND GAP REFERENCE
The ADuC7023 provides an on-chip band gap reference of
2.5 V, which can be used for the ADC and DAC. This internal
reference also appears on the VREF pin. When using the internal
reference, a 0.47 µF capacitor must be connected from the external
VREF pin to AGND to ensure stability and fast response during
ADC conversions. This reference can also be connected to an
external pin (VREF) and used as a reference for other circuits in
the system.
An external buffer is required because of the low drive capability
of the VREF output. A programmable option also allows an
external reference input on the VREF pin.
REFCON Register
Name: REFCON
Address: 0xFFFF048C
Default value: 0x00
Access: Read/write
Function: The band gap reference interface consists
of an 8-bit MMR REFCON described in
Table 30.
Table 30. REFCON MMR Bit Designations
Bit Description
7 to 1 Reserved.
0 Internal reference output enable.
This bit is set by the user to connect the internal 2.5 V
reference to the VREF pin. The reference can be used
for an external component but needs to be buffered.
This bit is cleared by the user to disconnect the
reference from the VREF pin.
To connect an external reference source to the ADuC7023,
configure REFCON = 0x01. ADC and the DACs can be
configured to use the same or different reference resource.
See Table 42.
Rev. G | Page 37 of 97
ADuC7023 Data Sheet
NONVOLATILE FLASH/EE MEMORY
The ADuC7023 incorporates Flash/EE memory technology on
chip to provide the user with nonvolatile, in-circuit reprogram-
mable memory space.
Like EEPROM, flash memory can be programmed in-system at
a byte level, although it must first be erased. The erase is performed
in page blocks. As a result, flash memory is often and more
correctly referred to as Flash/EE memory.
The Flash/EE memory represents a step closer to the ideal memory
device that includes nonvolatility, in-circuit programmability,
high density, and low cost. Incorporated in the ADuC7023,
Flash/EE memory technology allows the user to update program
code space in-circuit, without needing to replace one-time
programmable (OTP) devices at remote operating nodes.
Each part contains a 64 kB array of Flash/EE memory. The lower
62 kB are available to the user, and the upper 2 kB contain
permanently embedded firmware, allowing in-circuit serial
download. These 2 kB of embedded firmware also contain a
power-on configuration routine that downloads factory-
calibrated coefficients to the various calibrated peripherals
(such as ADC, temperature sensor, and band gap references).
This 2 kB embedded firmware is hidden from user code.
Flash/EE Memory Reliability
The Flash/EE memory arrays on the parts are fully qualified for
two key Flash/EE memory characteristics: Flash/EE memory
cycling endurance and Flash/EE memory data retention.
Endurance quantifies the ability of the Flash/EE memory to be
cycled through many program, read, and erase cycles. A single
endurance cycle is composed of four independent, sequential
events, defined as:
1. Initial page erase sequence.
2. Read/verify sequence (single Flash/EE).
3. Byte program sequence memory.
4. Second read/verify sequence (endurance cycle).
In reliability qualification, every half word (16-bit wide) location of
the three pages (top, middle, and bottom) in the Flash/EE memory
is cycled 10,000 times from 0x0000 to 0xFFFF. As indicated in
Table 1, the Flash/EE memory endurance qualification is carried
out in accordance with JEDEC Retention Lifetime Specification
A117 over the industrial temperature range of −40° to +125°C.
The results allow the specification of a minimum endurance
figure over a supply temperature of 10,000 cycles.
Retention quantifies the ability of the Flash/EE memory to retain
its programmed data over time. Again, the parts are qualified in
accordance with the formal JEDEC Retention Lifetime Specifi-
cation (A117) at a specific junction temperature (TJ = 85°C). As
part of this qualification procedure, the Flash/EE memory is
cycled to its specified endurance limit before data retention is
characterized. This means that the Flash/EE memory is
guaranteed to retain its data for its fully specified retention
lifetime every time the Flash/EE memory is reprogrammed. In
addition, note that retention lifetime, based on activation
energy of 0.6 eV, derates with TJ as shown in Figure 30.
150
300
450
600
30 40 55 70 85 100 125 135 150
RETENTION (Years)
0
08675-024
JUNCTION TEMPERATURE (°C)
Figure 30. Flash/EE Memory Data Retention
PROGRAMMING
The 62 kB of Flash/EE memory can be programmed in circuit,
using the serial download mode or the provided JTAG mode.
Downloading (In-Circuit Programming) via I2C
The ADuC7023 facilitates code download via the the I2C port.
The parts enter download mode after a reset or power cycle if
the BM pin is pulled low through an external 1 kΩ resistor and
Flash Addess 0x80014 = 0xFFFFFFFF. Once in download mode,
the user can download code to the full 62 kB of Flash/EE
memory while the device is in-circuit in its target application
hardware. An executable PC I2C download is provided as part
of the development system for serial downloading via the I2C. A
USB to I2C download dongle can be purchased from Analog
Devices, Inc. This board connects to the USB port of a PC and
to the I2C port of the ADuC7023. The part number is USB-
I2C/LIN-CONV-Z.
The AN-806 Application Note describes the protocol for serial
downloading via the I2C in more detail.
JTAG Access
The JTAG protocol uses the on-chip JTAG interface to facilitate
code download and debug.
The JTAG interface is active as long as the part is not in download
mode; that is, the P0.0/BM pin = 0 and Address 0x80014 =
0xFFFFFFF at reset.
When debugging, user code must not write to the bits in
GP0CON/GP0DAT corresponding to P0.0/P0.1/P0.2 and P0.3
pins. If user code changes the state of any of these pins, JTAG
debug pods are not able to connect to the ADuC7023. In case
this happens, the user should have a function in code that can
be called externally to mass erase the part. Alternatively, the
user should ensure that Flash Address 0x80014 is erased to
allow erasing of the part through the I2C interface.
Rev. G | Page 38 of 97
Data Sheet ADuC7023
SECURITY
The 62 kB of Flash/EE memory available to the user can be read
and write protected.
Bit 31 of the FEEPRO/FEEHIDE MMR (see Table 34) protects
the 62 kB from being read through JTAG programming mode.
The other 31 bits of this register protect writing to the flash
memory. Each bit protects four pages, that is, 2 kB. Write
protection is activated for all types of access.
Three Levels of Protection
Protection can be set and removed by writing directly into
FEEHIDE MMR. This protection does not remain after reset.
Protection can be set by writing into FEEPRO MMR. It only
takes effect after a save protection command (0x0C) and a reset.
The FEEPRO MMR is protected by a key to avoid direct access.
The key is saved once and must be entered again to modify
FEEPRO. A mass erase sets the key back to 0xFFFF but also
erases all the user code.
Flash can be permanently protected by using the FEEPRO
MMR and a particular value of key: 0xDEADDEAD. Entering
the key again to modify the FEEPRO register is not allowed.
Sequence to Write the Key
1. Write the bit in FEEPRO corresponding to the page to be
protected.
2. Enable key protection by setting Bit 6 of FEEMOD (Bit 5
must equal 0).
3. Write a 32-bit key in FEEADR, FEEDAT.
4. Run the write key command 0x0C in FEECON; wait for
the read to be successful by monitoring FEESTA.
5. Reset the part.
To remove or modify the protection, the same sequence is used
with a modified value of FEEPRO. If the key chosen is the value
0xDEAD, the memory protection cannot be removed. Only a mass
erase unprotects the part, but it also erases all user code.
The sequence to write the key is illustrated in the following
example (this protects writing Page 4 to Page 7 of the Flash):
FEEPRO=0xFFFFFFFD; //Protect Page 4 to
Page 7
FEEMOD=0x48; //Write key enable
FEEADR=0x1234; //16 bit key value
FEEDAT=0x5678; //16 bit key value
FEECON= 0x0C; //Write key command
Follow the same sequence to protect the part permanently with
FEEADR = 0xDEAD and FEEDAT = 0xDEAD.
FLASH/EE CONTROL INTERFACE
Serial and JTAG programming use the Flash/EE control interface,
which includes the eight MMRs outlined in this section.
FEESTA Register
Name: FEESTA
Address: 0xFFFFF800
Default value: 0x20
Access: Read
Function: FEESTA is a read-only register that reflects the
status of the flash control interface as
described in Table 31.
Table 31. FEESTA MMR Bit Designations
Bit Description
7 to 6 Reserved.
5 Reserved.
4 Reserved.
3 Flash interrupt status bit.
This bit is set automatically when an interrupt occurs, that is, when a command is complete and the Flash/EE interrupt enable bit
in the FEEMOD register is set.
This bit is cleared when reading FEESTA register.
2 Flash/EE controller busy.
This bit is set automatically when the controller is busy.
This bit is cleared automatically when the controller is not busy.
1 Command fail.
This bit is set automatically when a command is not completed.
This bit is cleared automatically when reading FEESTA register.
0 Command pass.
This bit is set by the MicroConverter when a command is completed.
This bit is cleared automatically when reading the FEESTA register.
Rev. G | Page 39 of 97
Table 32. FEEMOD MMR BR Designations Table 33. Command Codes in FEECON
ADuC7023 Data Sheet
FEEMOD Register
Name: FEEMOD
Address: 0xFFFFF804
Default value: 0x0000
Access: Read/write
Function: FEEMOD sets the operating mode of the flash control interface. Table 32 shows FEEMOD MMR bit designations.
Table 32. FEEMOD MMR Bit Designations
Bit Description
15 to 9 Reserved.
8 Reserved. Always set this bit to 0.
7 to 5 Reserved. Always set this bit to 0 except when writing keys. See the Sequence to Write the Key section.
4 Flash/EE interrupt enable.
This bit is set by the user to enable the Flash/EE interrupt. The interrupt occurs when a command is complete.
This bit is cleared by the user to disable the Flash/EE interrupt.
3 Erase/write command protection.
This bit is set by the user to enable the erase and write commands.
This bit is cleared to protect the Flash/EE against erase/write command.
2 to 0 Reserved. Always set this bit to 0.
FEECON Register
Name: FEECON
Address: 0xFFFFF808
Default value: 0x07
Access: Read/write
Function: FEECON is an 8-bit command register. The commands are described in Table 33.
Table 33. Command Codes in FEECON
Code Command Description
0x001 Null Idle state.
0x011 Single read Load FEEDAT with the 16-bit data. Indexed by FEEADR.
0x02
1
Single write
Write FEEDAT at the address pointed by FEEADR. This operation takes 50 µs.
0x031 Erase/write Erase the page indexed by FEEADR, and write FEEDAT at the location pointed by FEEADR. This operation takes
approximately 24 ms.
0x041 Single verify Compare the contents of the location pointed by FEEADR to the data in FEEDAT. The result of the comparison is
returned in FEESTA Bit 1.
0x05
1
Single erase
Erase the page indexed by FEEADR.
0x061 Mass erase Erase 62 kB of user space. The 2 kB of kernel are protected. This operation takes 2.48 sec. To prevent accidental
execution, a command sequence is required to execute this instruction. See the Command Sequence for
Executing a Mass Erase section.
0x07 Reserved Reserved.
0x08 Reserved Reserved.
0x09
Reserved
Reserved.
0x0A Reserved Reserved.
0x0B Signature Give a signature of the 64 kB of Flash/EE in the 24-bit FEESIGN MMR. This operation takes 32,778 clock cycles.
0x0C Protect This command can run one time only. The value of FEEPRO is saved and removed only with a mass erase (0x06) or
the key (FEEADR/FEEDAT).
Rev. G | Page 40 of 97
Table 34. FEEPRO and FEEHIDE MMR Bil Designafiuns
Data Sheet ADuC7023
Code Command Description
0x0D Reserved Reserved.
0x0E Reserved Reserved.
0x0F Ping No operation; interrupt generated.
1 The FEECON register always reads 0x07 immediately after execution of any of these commands.
FEEDAT Register
Name: FEEDAT
Address: 0xFFFFF80C
Default value: 0xXXXX
Access: Read/write
Function: FEEDAT is a 16-bit data register.
FEEADR Register
Name: FEEADR
Address: 0xFFFFF810
Default value: 0x0000
Access: Read/write
Function: FEEADR is another 16-bit address register.
FEESIGN Register
Name: FEESIGN
Address: 0xFFFFF818
Default value: 0xFFFFFF
Access: Read
Function: FEESIGN is a 24-bit code signature.
FEEPRO Register
Name: FEEPRO
Address: 0xFFFFF81C
Default value: 0x00000000
Access: Read/write
Function: FEEPRO MMR provides protection following a
subsequent reset of the MMR. It requires a
software key (see Table 34).
FEEHIDE Register
Name: FEEHIDE
Address: 0xFFFFF820
Default value: 0xFFFFFFFF
Access: Read/write
Function: FEEHIDE MMR provides immediate
protection. It does not require any software
key. The protection settings in FEEHIDE are
cleared by a reset (see Table 34).
Table 34. FEEPRO and FEEHIDE MMR Bit Designations
Bit
Description
31 Read protection.
This bit is cleared by the user to protect the code
This bit is set by the user to allow reading the code.
30 to 0 Write protection for Page 123 to Page 120, Page 119 to
Page 116, and Page 0 to Page 3.
This bit is cleared by the user to protect the pages in
writing.
This bit is set by the user to allow writing the pages.
Command Sequence for Executing a Mass Erase
FEEDAT = 0x3CFF;
FEEADR = 0xFFC3;
FEEMOD = FEEMOD|0x8; //Erase key enable
FEECON = 0x06; //Mass erase
command
Rev. G | Page 41 of 97
<»>
ADuC7023 Data Sheet
EXECUTION TIME FROM SRAM AND FLASH/EE
Execution from SRAM
Fetching instructions from SRAM takes one clock cycle because
the access time of the SRAM is 2 ns, and a clock cycle is 22 ns
minimum. However, if the instruction involves reading or
writing data to memory, one extra cycle must be added if the
data is in SRAM (or three cycles if the data is in Flash/EE); one
cycle to execute the instruction and two cycles to obtain the
32-bit data from Flash/EE. A control flow instruction (a branch
instruction, for example) takes one cycle to fetch but also takes
two cycles to fill the pipeline with the new instructions.
Execution from Flash/EE
Because the Flash/EE width is 16 bits and the access time for
16-bit words is 22 ns, execution from Flash/EE cannot be
completed in one cycle (as can be done from SRAM when the
CD bit = 0). Also, some dead times are needed before accessing
data for any value of CD bits.
In ARM mode, where instructions are 32 bits, two cycles are
needed to fetch any instruction when CD = 0. In thumb mode,
where instructions are 16 bits, one cycle is needed to fetch any
instruction.
Timing is identical in both modes when executing instructions
that involve using the Flash/EE for data memory. If the instruction
to be executed is a control flow instruction, an extra cycle is
needed to decode the new address of the program counter, and
then four cycles are needed to fill the pipeline. A data processing
instruction involving only the core register does not require any
extra clock cycles. However, if it involves data in Flash/EE, an
extra clock cycle is needed to decode the address of the data,
and two cycles are needed to get the 32-bit data from Flash/EE.
An extra cycle must also be added before fetching another
instruction. Data transfer instructions are more complex and
are summarized in Table 35.
Table 35. Execution Cycles in ARM/Thumb Mode
Instructions
Fetch
Cycles
Dead
Time Data Access
Dead
Time
LD
1
2/1
1
2
1
LDH 2/1 1 1 1
LDM/PUSH 2/1 N2 2 × N2 N1
STR1 2/1 1 2 × 20 ns 1
STRH 2/1 1 20 ns 1
STRM/POP 2/1 N1 2 × N × 20 ns1 N1
1 The SWAP instruction combines an LD and STR instruction with only one
fetch, giving a total of eight cycles + 40 ns.
2 N is the number of data to load or store in the multiple load/store instruction
(1 < N ≤ 16).
RESET AND REMAP
The ARM exception vectors are all situated at the bottom of the
memory array, from Address 0x00000000 to Address 0x00000020
as shown in Figure 31.
08675-025
KERNEL
INTERRUPT
SERVICE ROUTINES
INTERRUPT
SERVICE ROUTINES
ARM EXCEPTION
VECTOR ADDRESSES 0x00000020
0x00011FFF
0x0008FFFF
0xFFFFFFFF
FLASH/EE
SRAM
MIRROR SPACE
0x00000000 0x00000000
0x00010000
0x00080000
Figure 31. Remap for Exception Execution
By default, and after any reset, the Flash/EE is mirrored at the
bottom of the memory array. The remap function allows the
programmer to mirror the SRAM at the bottom of the memory
array, which facilitates execution of exception routines from
SRAM instead of from Flash/EE. This means exceptions are
executed twice as fast, being executed in 32-bit ARM mode with
32-bit wide SRAM instead of 16-bit wide Flash/EE memory.
Remap Operation
When a reset occurs on the ADuC7023, execution automatically
starts in factory programmed, internal configuration code. This
kernel is hidden and cannot be accessed by user code. If the part is
in normal mode (BM pin is high), it executes the power-on
configuration routine of the kernel and then jumps to the reset
vector address, 0x00000000, to execute the reset exception
routine of the user.
Because the Flash/EE is mirrored at the bottom of the memory
array at reset, the reset interrupt routine must always be written
in Flash/EE.
The remap is done from Flash/EE by setting Bit 0 of the Remap
register. Caution must be taken to execute this command from
Flash/EE above Address 0x00080020, and not from the bottom
of the array because this is replaced by the SRAM.
This operation is reversible. The Flash/EE can be remapped at
Address 0x00000000 by clearing Bit 0 of the Remap MMR.
Caution must again be taken to execute the remap function
from outside the mirrored area. Any type of reset remaps the
Flash/EE memory at the bottom of the array.
Rev. G | Page 42 of 97
Table 36. REMAP MMR Bil Dcsignafiuns
Data Sheet ADuC7023
REMAP Register
Name: REMAP
Address: 0xFFFF0220
Default value: 0x00
Access: Read/write
Table 36. REMAP MMR Bit Designations
Bit Name Description
7 to 5 Reserved.
4
Read-only bit. Indicates the size of the
Flash/EE memory available. If this bit is set,
only 32 kB of Flash/EE memory is available.
3
Read-only bit. Indicates the size of the
SRAM memory available. If this bit is set,
only 4 kB of SRAM is available.
2 to 1
JTAFO
Read only bits. See the P0.0/BM description
for further details. The kernel sets these
bits to [11] if BM = 0 and 0x80014 ≠
0xFFFFFFFF at reset.
If these bits are set to [00], then P0.1/P0.2/
P0.3 are configured as JTAG pins. P0.1/P0.2
cannot be used as GPIO. P0.3 can be used
as GPIO, but this disables JTAG access.
If these bits are set to [1x], then P0.1/P0.2/
P0.3 are configured as GPIO pins. P0.1/P0.2/
P0.3 can also be used as JTAG, but JTAG
access is disabled if they are used as GPIO.
These bits are configured by the kernel
after any reset sequence and depend on
the state of P0.0 and the value at Address
0x80014 during the last reset sequence.
0 Remap Remap bit.
This bit is set by the user to remap the
SRAM to Address 0x00000000.
This bit is cleared automatically after reset
to remap the Flash/EE memory to Address
0x00000000.
Reset Operation
There are four kinds of reset: external, power-on, watchdog
expiration, and software force. The RSTSTA register indicates
the source of the last reset, and RSTCLR allows clearing of the
RSTSTA register. These registers can be used during a reset
exception service routine to identify the source of the reset. If
RSTSTA is null, the reset is external.
The RSTCFG register allows different peripherals to retain their
state after a watchdog or software reset.
RSTSTA Register
Name: RSTSTA
Address: 0xFFFF0230
Default value: 0x01
Access: Read/write
Table 37. RSTSTA MMR Bit Designations
Bit Description
7 to 3 Reserved.
2 Software reset.
This bit is set by the user to force a software reset.
This bit is cleared by setting the corresponding bit
in RSTCLR.
1 Watchdog timeout.
This bit is set automatically when a watchdog
timeout occurs.
This bit is cleared by setting the corresponding bit
in RSTCLR.
0 Power-on reset.
This bit is set automatically when a power-on reset
occurs.
This bit is cleared by setting the corresponding bit
in RSTCLR.
RSTCLR Register
Name: RSTCLR
Address: 0xFFFF0234
Default value: 0x00
Access: Write
Function: Note that to clear the RSTSTA register, users
must write the Value 0x07 to the RSTCLR
register.
RSTCFG Register
Name: RSTCFG
Address: 0xFFFF024C
Default value: 0x00
Access: Read/write
Rev. G | Page 43 of 97
ADuC7023 Data Sheet
Table 38. RSTCFG MMR Bit Designations
Bit Description
7 to 3 Reserved. Always set to 0.
2 This bit is set to 1 to configure the DAC outputs to retain
their state after a watchdog or software reset.
This bit is cleared for the DAC pins and registers to
return to their default state.
1 Reserved. Always set to 0.
0 This bit is set to 1 to configure the GPIO pins to retain
their state after a watchdog or software reset.
This bit is cleared for the GPIO pins and registers to
return to their default state.
RSTKEY1 Register
Name: RSTKEY1
Address: 0xFFFF0248
Default value: 0xXX
Access Write
RSTKEY2Register
Name: RSTKEY2
Address: 0xFFFF0250
Default value: 0xXX
Access: Write
Table 39. RSTCFG Write Sequence
Name Code
RSTKEY1 0x76
RSTCFG User value
RSTKEY2
0xB1
Rev. G | Page 44 of 97
Data Sheet ADuC7023
OTHER ANALOG PERIPHERALS
DAC
The ADuC7023 incorporates four, 12-bit voltage output DACs
on chip. Each DAC has a rail-to-rail voltage output buffer
capable of driving 5 k/100 pF.
Each DAC has two selectable ranges: 0 V to VREF (internal band
gap 2.5 V reference) and 0 V to AVDD.
The signal range is 0 V to AVDD.
By setting RSTCFG Bit 2, the DAC output pins can retain their
state during a watchdog or software reset.
MMRs Interface
Each DAC is independently configurable through a control
register and a data register. These two registers are identical for
the four DACs. Only DAC0CON (see Table 40) and DAC0DAT
(see Table 41) are described in detail in this section.
DACxCON Registers
Name Address Default Value Access
DAC0CON 0xFFFF0600 0x00 R/W
DAC1CON 0xFFFF0608 0x00 R/W
DAC2CON 0xFFFF0610 0x00 R/W
DAC3CON 0xFFFF0618 0x00 R/W
Table 40. DAC0CON MMR Bit Designations
Bit Value Name Description
7 Reserved.
6 DACBY This bit is set to bypass the DAC
output buffer.
This bit is cleared to enable the
DAC output buffer.
5 DACCLK DAC update rate.
This bit is set by the user to update
the DAC using Timer1.
This bit is cleared by the user to
update the DAC using HCLK (core
clock).
4 DACCLR DAC clear bit.
This bit is set by the user to enable
normal DAC operation.
This bit is cleared by the user to
reset data register of the DAC to 0.
3 Reserved. This bit remains at 0.
2