TDA7705 Datasheet by STMicroelectronics

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September 2013 Doc ID 15938 Rev 9 1/42
1
TDA7705
Highly integrated tuner for AM/FM car radio
Features
Fully integrated VCO for world tuning
High performance PLL for fast RDS system
AM/FM mixers with high image rejection
Integrated AM-LNA and AM-PINDIODE
Automatic self alignment for preselection and
image rejection
Digital IF signal processing, high performance
and drift-free
Integrated IF-filters with high selectivity, high
dynamic range and adaptive bandwidth control
RDS demodulation with group and block
synchronization
High performance stereodecoder with
noiseblanker
I2C/SPI bus controlled
Single 5 V supply
LQFP64 package
Description
The TDA7705 highly integrated tuner (HIT) is a
new generation of high performance tuners for
carradio applications.
It contains mixers and IF amplifiers for AM and
FM, fully integrated VCO and PLL synthesizer,
IF-processing including adaptive bandwidth
control, stereo decoder and RDS decoder on a
single chip.
The utilization of digital signal processing results
in numerous advantages against today's tuners:
very low number of external components, very
small space occupation and easy application,
very high selectivity due to digital filters, high
flexibility by software control and automatic
alignment.
LQFP64
Table 1. Device summary
Order code Package Packing
TDA7705 LQFP64 (10x10x1.4mm) Tray
TDA7705TR LQFP64 (10x10x1.4mm) Tape and reel
www.st.com
Contents TDA7705
2/42 Doc ID 15938 Rev 9
Contents
1 Block diagram and pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 Function description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 FM - mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 FM - AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3 AM - LNA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4 AM - AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.5 AM - mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.6 IF A/D converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.7 Audio D/A converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.8 VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.9 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.10 Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.11 DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.12 IO interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.13 Serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.13.1 Serial interface choice / boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.13.2 I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.13.3 SPI bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3 General key parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4.1 FM - section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4.2 AM - section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.4.3 VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4.4 Phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4.5 Tuning DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
TDA7705 Contents
Doc ID 15938 Rev 9 3/42
3.4.6 IF ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4.7 Audio DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4.8 IO interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4.9 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.4.10 SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.4.11 Warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.5 Overall system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.5.1 FM overall system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.5.2 AM MW overall system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.5.3 AM LW overall system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.5.4 AM SW overall system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.5.5 WX overall system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4 Front-end processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5 Weak signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.1 FM IF-processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.1.1 Dynamic channel selection filter (DISS) . . . . . . . . . . . . . . . . . . . . . . . . 33
5.1.2 Soft mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.1.3 Adjacent channel mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.1.4 Stereo blend- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.1.5 High cut control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.1.6 Stereo decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.2 AM IF-processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.2.1 Channel selection filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.2.2 Soft mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.2.3 High cut control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6 Application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.1 Basic application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.2 Application schematic example with SPI-bus and tuned preselection . . . 39
7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
List of tables TDA7705
4/42 Doc ID 15938 Rev 9
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. Boot mode pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6. General key parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 7. FM - section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 8. AM - section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 9. VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 10. Phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 11. Tuning DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 12. IF ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 13. Audio DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 14. IO interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 15. I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 16. SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 17. FM overall system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 18. AM MW overall system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 19. AM LW overall system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 20. AM SW overall system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 21. WX overall system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 22. Register 0x00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 23. Register 0x01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 24. Register 0x02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 25. Register 0x05 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 26. Dynamic channel selection filter (DISS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 27. Soft mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 28. Adjacent channel mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 29. Stereo blend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 30. High cut control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 31. De-emphasis filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 32. Stereo decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 33. Channel selection filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 34. Soft mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 35. High cut control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 36. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
TDA7705 List of figures
Doc ID 15938 Rev 9 5/42
List of figures
Figure 1. Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. I2C "write" sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 4. I2C "read" sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 5. SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 6. SPI "write" sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. SPI "read" sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 8. I2C bus timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 9. SPI bus timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 10. FM input set-up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 11. AM MW input set up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 12. AM LW input set-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 13. AM SW input set-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 14. WX input set-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 15. FM wide-band application / I2C control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 16. Example of FM tuned (narrow-band) application / SPI control . . . . . . . . . . . . . . . . . . . . . . 39
Figure 17. LQFP64 (10x10x1.4mm) mechanical data and package dimensions. . . . . . . . . . . . . . . . . 40
Block diagram and pins description TDA7705
6/42 Doc ID 15938 Rev 9
1 Block diagram and pins description
1.1 Block diagram
Figure 1. Functional block diagram
: 8
FREF
VCO PLL
: N
AGC
ADC
ADC
Supply
DAC
OSC
STEREO
DAC
Audio Out
SUM
NCO
DLL
DSP
AGC
AM
RDSINT
RDS
I
2
C/
SPI
: 8
FREF
VCO PLL
: N
AGC
ADC
ADC
Supply
DAC
OSC
STEREO
DAC
Audio Out
SUM
NCO
DLL
DSP
AGC
AM
RDSINT
RDS
I
2
C/
SPI
TDA7705 Block diagram and pins description
Doc ID 15938 Rev 9 7/42
1.2 Pin description
Figure 2. Pin connection (top view)
Table 2. Pin description
Pin # Pin name Function
1 LF1 PLL loopfilter output
2 PLLTEST PLL test output / GPO
3 DAC FM tuning DAC output
4 TCAGCFM FM AGC time constant
5 FMMIX1dec FM mixer decoupling
6 FMIX1in FM mixer input 1
7 FMIX2in FM mixer input 2
8 GND-RF RF Ground
9 FMPINDRV FM AGC PIN diode driver
10 VCC-RF 5V supply for RF section
11 TCAM AM AGC time constant
12 AMPINDRV AM AGC external PIN diode driver
13 PINDdec AM AGC internal PIN diode decoupling
14 PINDin AM AGC internal PIN diode input
15 GND-LNA AM LNA and internal PIN diode GND
16 LNAin AM LNA input
1
2
3
5
6
4
7
8
9
10
27
11
28 29 30 31 32
59 58 57 56 54
55 53 52 51 50 49
43
42
41
39
38
40
48
47
46
44
45
FMMIX1in
FMMIX1dec
TCAGCFM
PLLTEST
LFI
DAC
TCAM
VCC-RF
FMPINDRV
FMMIX2in
GND-RF
AMMIXin2
AMMIXin1
AMMIXdec
GND-IF
VREFdec
VREF165
GND-DIG
VCC-DIG
VCCREG12
REG-1V2
VDD-3V3
VCC-PLL
VCC-IFADC
LIFrefH
LIFrefL
DACoutR
GND-IFADC
DACoutL
GND-DAC
OSCin
OSCout
VCC-DAC
GPIO0
GPIO1
GPIO2
RDSINT
VDD-1V2
GPIO3
GND-1V2
VDD-1V2
TEST
MODE
RSTN
AC00418
22 23 24 25 26
60
GND-PLL
61
VCOdec
62
LFref
63
VCC-VCO
64
GND-VCO
LNAdec
LNAout
LNAin2
LNAout2
LNAdec2
17 18 19 20 21
37
36
34
33
35
SCL/CLK
SDA/MOSI
SPI_CS
GND-3V3
SPI_MISO
12
13
14
15
16
LNAin
GND-LNA
PINDin
AMPINDRV
PINDdec
Block diagram and pins description TDA7705
8/42 Doc ID 15938 Rev 9
17 LNAdec AM LNA decoupling
18 LNAout AM LNA output first stage
19 LNAin2 AM LNA input 2nd stage
20 LNAout2 AM LNA output
21 LNAdec2 AM LNA decoupling 2nd stage
22 AMMIXin2 AM mixer input 2
23 AMMIXin1 AM mixer input 1
24 AMMIXdec AM mixer decoupling
25 GND-IF IF and Vref GND
26 VREF165 1.65V reference voltage decoupling
27 VREFdec 3.3V reference voltage decoupling
28 GND-DIG Digital GND
29 VCC-DIG 5V supply for digital logic
30 VCCreg1V2 VCC of 1.2V regulator
31 REG1V2 1.2V regulator output
32 VDD-3V3 3.3V VDD output / decoupling
33 GND-3V3 3.3V VDD GND
34 SPI_CS SPI chip select
35 SPI_MISO SPI Data output
36 SDA / SPI_MOSI I2C bus data / SPI data input
37 SCL / SPI_CLK I2C bus Clock / SPI clock
38 VDD-1V2 1.2V DSP supply
39 RDSINT RDS interrupt
40 GPIO3 Reserved
41 GPIO2 Reserved
42 GPIO 1 Reserved
43 GPIO 0 Reserved
44 MODE For debug purpose only, connected to GND
45 RSTN Reset pin (active low)
46 TEST Test input
47 VDD-1V2 1.2V DSP supply
48 GND-1V2 Digital GND for 1.2V VDD
49 VCC-DAC 5V supply of audio DAC
50 OSCout Xtal osc output
51 OSCin Xtal osc input
Table 2. Pin description (continued)
Pin # Pin name Function
TDA7705 Block diagram and pins description
Doc ID 15938 Rev 9 9/42
52 GND-DAC Audio DAC GND
53 DACoutL Audio output left
54 DACoutR Audio output right
55 GND-IFADC IF ADC GND
56 LIFrefL IF ADC reference low
57 LIFrefH IF ADC reference high
58 VCC-IFADC 5V supply of IF ADC
59 VCC-PLL 5V supply of PLL
60 GND-PLL PLL GND
61 VCO-dec VCO decoupling
62 LFref Loopfilter reference
63 VCC-VCO 5V supply of VCO
64 GND-VCO VCO GND
Table 2. Pin description (continued)
Pin # Pin name Function
Function description TDA7705
10/42 Doc ID 15938 Rev 9
2 Function description
2.1 FM - mixers
The image-rejection mixer has two FM inputs, selectable through software. These inputs
feed stages with different gains, noise figures, and IIP3. They are optimized for best
performance in case of a passive tuned prestage and for a passive fixed bandpass without
tuning for low-cost application respectively.
The second input offers also the possibility of an easy addition of a weather-band
preselection filter.
The input frequency is downconverted to low IF with high image rejection.
The tuned application is supported by an 8-bit tuning DAC. The alignment of the DAC is
performed automatically.
2.2 FM - AGC
The programmable RFAGC senses the mixer input whereas the IFAGC senses the IFADC
input to avoid overload.
The PIN diode driver is able to drive external PIN diodes with a current value as high as
15mA.
The time constant of the FM-AGC is defined by an external capacitor.
2.3 AM - LNA
The AM-LNA is integrated with low noise and high IIP2 and IIP3. The gain of the LNA is
controlled by the AGC. The maximum gain is set with an external resistor, typically 26 dB
with 1 k.
2.4 AM - AGC
The programmable AM-RF-AGC senses the mixer inputs and controls the internal PIN diode
and LNA gain.
First the LNA gain is reduced by about 10dB, then the PIN diodes are activated to attenuate
the signal.
The time constant of the AM-AGC is defined with an external capacitor and programmable
internal currents.
2.5 AM - mixers
The image-rejection mixer has two AM inputs selectable via software. It easily supports low-
cost applications for extended frequency bands like SW, DRM.
The input frequency is converted to low IF with high image rejection.
TDA7705 Function description
Doc ID 15938 Rev 9 11/42
2.6 IF A/D converters
A high performance IQ-IFADC converts the IF-signal to digital IF for subsequent digital
signal processing.
2.7 Audio D/A converters
A stereo DAC provides the left / right audio signals after IF-processing and stereodecoding
by the DSP.
2.8 VCO
The VCO is fully integrated without any external tuning component. It covers all FM
frequency bands including EU, US , Japan, EastEU, Weatherband and AM-bands including
LW, MW, SW.
2.9 PLL
The high speed tuning PLL is able to settle within about 300 µs for fast RDS applications.
The frequency step can be as low as 5 kHz in FM and 500 Hz in AM.
2.10 Crystal oscillator
The device works with a 37.05 MHz fundamental tone crystal, and can be used also with a
3rd overtone 37.05 MHz crystal.
2.11 DSP
The DSP and its hardware accelerators perform all the digital signal processing. The main
program is fixed in ROM. Control parameters are copied in RAM and are accessible and
modifiable there, thus allowing parametric performance optimization.
It performs:
digital down-conversion of IF
bandwidth selection with variable controlled bandwidth
FM and AM noiseblanking
FM/AM demodulation with softmute, high-cut, weak signal processing and quality
detection
FM stereo decoding with stereo blend
RDS demodulation including error correction and block synchronization with generation
of an RDS interrupt for the main µP
Autonomous control of RDS-AF tests
Self alignment of preselection tuning
Function description TDA7705
12/42 Doc ID 15938 Rev 9
2.12 IO interface pins
The TDA7705 has the following IO pins:
The pins labeled GPIO0, 1, 2 and 3 (pins 43 to 40) are reserved.
The pin PLLTEST output voltage can be freely programmed via software and be used to
drive switches if needed by the application.
All the inputs are voltage-tolerant up to 3.5 V . The outputs can drive currents up to 0.5 mA
from the internal 3.3 V supply line.
2.13 Serial interface
The device is controlled with a standard I2C bus or SPI interface.
Through the serial bus the processing parameters can be modifed and the signal quality
parameters and the RDS information can be read out.
The operation of the device is handled through high level commands sent by the main car-
radio µP through the serial interface, which allow to simplify the operations carried out in the
main µP. The high level commands include among others:
set frequency (which allows to avoid computing the PLL divider factors);
start seek (the seek operation can be carried out by the TDA7705 in a completely
autonomous fashion);
RDS seek/search (jumps to AF and quality measurements are automatically
sequenced).
2.13.1 Serial interface choice / boot mode
The device can communicate with the main µP with two different standard serial protocols:
SPI and I2C. The configuration is chosen by setting the proper value (0V or 3.3V) at pins 35
and 39 and it is latched (e.g. made effective) when the RSTN line transitions from low to
high (when RSTN is low, the IC is in reset mode).
The voltage level forced to pins 35 and 39 must be released to start the system operation a
suitable time after the RSTN line has gone high.
The list of configurations is shown in the following table:
PLLTEST pin 2 general purpose output
SPI_CS pin 34 serial communication with µP
SPI_MISO pin 35 serial communication with µP
SDA/MOSI pin 36 serial communication with µP
SCL/CLK pin 37 serial communication with µP
RDSINT pin 39 serial communication with µP
RSTN pin 45 reset pin driven by µP
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TDA7705 Function description
Doc ID 15938 Rev 9 13/42
If I2C serial bus is chosen as means of communication with the controlling device, two chip
addresses are possible: 0xC2/C3 or 0xC8/C9, depending on the initial configuration of pins
35 and 39.
The status of pins 35 and 39 during the reset phase can be set to:
high, through external <10 k resistors tied to 3.3V (pin 32), or
low, by not forcing any voltage on them from outside, as 50 kohm internal pull-down
resistors are present on said pins.
To make sure the boot mode is correctly latched up at start-up, it is advisable to keep the
RSTN line low until the IC supply pins have reached their steady state, and then for an
additional time Treset (see Section 3.4.8).
2.13.2 I2C bus protocol
I2C requires two signals: clock (SCL) and data (SDA - bidirectional). The protocol requires
an acknowledge after any 8-bit transmission.
A "write" communication example is shown in the figure below, for an unspecified number of
data bytes (see the relevant technical documentation for frame structure description):
Figure 3. I2C "write" sequence
Table 3. Boot mode pin configuration
Configuration: I2C (addr. 0 x C2) I2C (addr. 0 x C8) SPI
Pin at reset operation at reset operation at reset operation
39 RDSINT 0
in
RDS interrupt
out
0
in
RDS interrupt
out
1
in
RDS interrupt
out
37 SCL x I2C SCL
in xI2C SCL
in xSPI CLK
in
36 SDA x I2C SDA
in/out xI2C SDA
in/out xSPI MOSI
in
35 (SPI_MISO) 0
in -1
in -1
in
SPI MISO
out
34 (SPI_CS) x - x - x SPI SS
in
ACK
data
STOP
clk1
clk2
clk8
clk9
clk1
clk2
START
ACK
address
a0
d0
clk8
clk9
a7
a6
SCL
SDA
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Function description TDA7705
14/42 Doc ID 15938 Rev 9
The sequence consists of the following phases:
START: SDA line transitioning from H to L with SCL fixed H. This signifies a new
transmission is starting;
data latching: on the rising SCL edge. The SDA line can transition only when SCL is
low (otherwise its transitions are interpreted as either a START or a STOP transition);
ACKnowledge: on the 9th SCL pulse the µP keeps the SDA line H, and the TDA7705
pulls it down if communication has been successful. Lack of the acknowledge pulse
generation from the TDA7705 means that the communication has failed;
a chip address byte must be sent at the beginning of the transmission. The value can
be C2 or C8 (according to the mode chosen at start-up during boot) for "write";
as many data bytes as needed can follow the address before the communication is
terminated. See the next section for details on the frame format;
STOP: SDA line transitioning from L to H with SCL H. This signifies the end of the
transmission.
Red lines represent transmissions from the TDA7705 to the µP.
A "read" communication example is shown in the figure below, for an unspecified number of
data bytes (see later on for frame structure decription):
Figure 4. I2C "read" sequence
The sequence is very similar to the "write" one and has the same constraints for start, stop,
data latching. The differences follow:
a chip address must always be sent by the µP to the TDA7705; the address must be C3
(if C2 had been selected at boot) or C9 (if C8 had been selected at boot);
a header is transmitted after the chip address (the same happens for "write") before
data are transferred from the TDA7705 to the µP. See the relevant technical
documentation for details on the frame format;
when data are transmitted from the TDA7705 to the µP, the µP keeps the SDA line H;
the ACKnowledge pulse is generated by the µP for those data bytes that are sent by the
TDA7705 to the µP. Failure of the µP to generate an ACK pulse on the 9th CLK pulse
has the same effect on the TDA7705 as a STOP.
The max. clock speed is 500 kbit/s.
2.13.3 SPI bus protocol
SPI requires four signals: clock (CLK), master output/slave input (MOSI - for communication
from the µP to the TDA7705), master input/slave output (MISO - for communication from the
TDA7705 to the µP), chip select (CS). CLK is generated by the master device and is used
for synchronization. MOSI and MISO are the data lines. The CS line is unique for each
device in an SPI bus. The µP pulls low the TDA7705 CS line to select it for communication.
The protocol does not foresee any transmission acknowledgement.
The SPI protocol has four possible modes of operation as far as data latching is concerned:
SDA
a7
a6
a0
d7
d6
d0
SCL
clk1
clk2
clk8
clk9
clk1
clk2
clk8
clk9
START
address
ACK
data
ACK
STOP
Clock Polarity (CPOl) a; Clock Phase {CPHA) MA , 1 MODE 0 MODE 1 MODE 2 MODE .1
TDA7705 Function description
Doc ID 15938 Rev 9 15/42
Figure 5. SPI modes
In the case of the TDA7705, the data are latched on the clock's rising edge, with CPOL = 1
and CPHA = 1 (mode 3 in the figure above). According to the specification of this mode, the
polarity of the CLK line when no communication is taking place is high.
A "write" communication example is shown in the figure below, for an unspecified number of
bits (see the relevant technical documentation for frame structure description):
Figure 6. SPI "write" sequence
The start condition is signaled by the CS line going low, and the stop condition by the CS
line going high. It is not allowed to toggle the CS line while the communication is going on.
A "read" communication example is shown in the figure below, for an unspecified number of
bits (see the relevant technical documentation for frame structure description ):
Figure 7. SPI "read" sequence
The red line is controlled by the TDA7705, whereas the black lines are controlled by the µP.
...
...
LSB
...
...
...
...
...
...
...
...
CS
CLK
MOSI
MSB
LSB
...
...
LSB
MSB
...
...
...
...
MISO
...
CLK
MOSI
MSB
...
CS
Electrical specifications TDA7705
16/42 Doc ID 15938 Rev 9
3 Electrical specifications
3.1 Absolute maximum ratings
3.2 Thermal data
3.3 General key parameters
Table 4. Absolute maximum ratings
Symbol Parameter Test condition Min Typ Max Units
VCC Supply voltage - - - 5.5 V
Tstg Storage temperature - -55 - 150 °C
VESD ESD withstand voltage
Human body model ±2000
V
Charged device model ±450
Charged device model, corner pins ±750
Machine model ±150
Table 5. Thermal data
Symbol Parameter Test condition Value Units
RTh j-amb
Thermal resistance
junction-to-ambient LQFP64 10x10, double-layer JEDEC PCB 55 °C/W
Table 6. General key parameters
Symbol Parameter Test condition Min Typ Max Units
VCC 5 V supply voltage - 4.7 5 5.25 V
ICC Supply current @ 5 V - - 220 295 mA
Tamb Ambient temperature range - -40 - 85 °C
VVCCREG12 VCCREG12 supply voltage see note(1) 2--V
V1V2
Digital core 1.2V supply
voltage
when supplied externally
see note (2) 1.08 1.2 1.32 V
I1V2
Digital core 1.2 V supply
current
V1V2 = 1.08 V
see note (2) --120mA
V1V2 = 1.2 V
see note (2) -80135mA
V1V2 = 1.32 V
see note (2) --150mA
1. In the typical application supplied from 5V with a series resistor.
2. When the 1.2 V supply is applied externally, and not using the internal 1.2 V regulator.
TDA7705 Electrical specifications
Doc ID 15938 Rev 9 17/42
3.4 Electrical characteristics
VCC = 4.7 V to 5.25 V; Tamb = -40 °C to +85 °C; unless otherwise specified.
3.4.1 FM - section
Table 7. FM - section
Symbol Parameter Test condition Min Typ Max Units
FM IMR mixer
Rin Input resistance - 90 130 170 k
Vnoise Input noise voltage
Mix 1, Rsource = 1.5 k,
noiseless -2.53.1
nV/Hz
Mix 2, Rsource = 800 ,
noiseless -22.5
IIP3 3rd order intercept point
Mix 1
up to Vin/tone = 90 dBµV
Mix 2
up to Vin/tone = 85 dBµV
122
118
125
121
-
dBµV
dBµV
FM AGC
RFAGC-Thr
RFAGC threshold, referred to
mixer input;
RF level
Mix 1, min setting - 87 -
dBµV
Mix 1, max setting - 93 -
Mix 2, min setting - 85 -
Mix 2, max setting - 91 -
Threshold steps - - 2 - dB
Threshold error @ Tamb = 27 °C -1.5 1.5 dB
Threshold temperature drift - 0.016 - dB/K
IFAGC-Thr
IFAGC threshold, referred to
mixer input; at tuned
frequency
RF level
Mix 1, min setting - 81 -
dBµV
Mix 1, max setting - 85 -
Mix 2, min setting - 77 -
Mix 2, max setting - 81 -
Threshold steps - - 2 - dB
Threshold error @ Tamb = 27 °C -1.5 1.5 dB
Threshold temperature drift - 0.016 - dB/K
- Pin diode source current @ Tamb = 27 °C; see note(1) 12 - - mA
- Pin diode sink current - 3 - 20 µA
-Pin diode source current in
constant current mode @ Tamb = 27 °C; see note(1) 0.4 - - mA
1. The current is generated by a PTAT (Proportional To Absolute Temperature) source, and has therefore a temperature
dependency described by: I/Io = T/To, with Io being the current at ambient temperature (25 °C) and To the ambient
temperature (25°C) expressed in Kelvin, that is 298 K.
Electrical specifications TDA7705
18/42 Doc ID 15938 Rev 9
3.4.2 AM - section
Table 8. AM - section
Symbol Parameter Test condition Min Typ Max Units
AM IMR Mixer
Rin Input resistance - 20 30 45 k
Vout_max Max. output voltage without clipping - 126 - dBµV
VN,in Input noise voltage
Mix 1, Rsource = 1 k,
noiseless -8.512
nV/Hz
Mix 2, Rsource = 1 k,
noiseless -8.512
IIP3 3rd order intercept point Mix 1,2
up to Vin/tone = 90 dBµV 126 129 - dBµV
IIP2 2nd order intercept point Mix1 1,2
up to Vin/tone = 90 dBµV - 158 - dBµV
LO hsupp LO harmonic suppression N=2,3,4,5,6 - 100 - dB
N=7,9 - 85 -
AM LNA
Gain Voltage gain Max Gain, Rext = 1 k21 25 28 dB
Min Gain (AGC controlled) - 12 -
Rin Input resistance - - 1000 k
Cin Input capacitance - - 20 pF
VN,in Input noise voltage - - 1.0 1.4 nV/Hz
IIP3 3rd order intercept point @ maximum LNA gain - 125 - dBµV
IIP2 2nd order intercept point @ maximum LNA gain - 143 - dBµV
AM PIN diode
IIP2 2nd order intercept point Full attenuation,
Csource = 80 pF, f=1 MHz - 140 - dBµV
Rmin Minimum resistance - - 50 80
Cin Input capacitance High ohmic - 12 - pF
AM AGC
AGC-Thr Referred to mixer input
RF level
Mix 1,2 min setting - 87 - dBµV
Mix 1,2 max setting - 93 -
Thr-steps
Threshold steps - - 1 -
dBThreshold error @ Tamb = 27 °C -2.5 - 2.5
Threshold temperature drift - -3 - 3
- Pin diode source current @ Tamb = 27 °C; see note(1) 2-10mA
- Pin diode sink current - 15 35 50 µA
-Pin diode source current in
constant current mode @ Tamb = 27 °C; see note(1) 1.5 2.5 3.5 mA
1. The current is generated by a PTAT (Proportional To Absolute Temperature) source, and has therefore a temperature
dependency described by: I/Io = T/To, with Io being the current at ambient temperature (25 °C) and To the ambient
temperature (25 °C) expressed in Kelvin, that is 298 K.
TDA7705 Electrical specifications
Doc ID 15938 Rev 9 19/42
3.4.3 VCO
3.4.4 Phase locked loop
3.4.5 Tuning DAC
3.4.6 IF ADC
Table 9. VCO
Symbol Parameter Test condition Min Typ Max Units
FVCO Frequency range VCO - 1100 1550 MHz
PN Phase noise of LO
Locked VCO;
values referred @ 100MHz
@ 100 Hz
@ 1 kHz
@ 10 kHz
- -100
-115
-115
-dBc/Hz
dev Deviation error (rms) FM reception, deemphasis
50µs, faudio = 20 Hz...20 kHz -5-Hz
Table 10. Phase locked loop
Symbol Parameter Test condition Min Typ Max Units
Tsettle Settling time FM f < 10 kHz - 300 - µs
FM step FM frequency step - - 5 - kHz
AM step AM frequency step - - 500 - Hz
Table 11. Tuning DAC
Symbol Parameter Test condition Min Typ Max Units
Res Resolution 8 bit - 18 - mV
Voutmin Min output voltage - - 0.6 0.7 V
Voutmax Max ouput voltage - VCC-0.2 VCC-0.1 - V
Rout Output impdedance - 1.5 2.5 3.5 k
DNL Diff. Non linearity - - - 0.5 LSB
Tconv Conversion time - - 20 - µs
Table 12. IF ADC
Symbol Parameter Test condition Min Typ Max Units
DRFM Dynamic range in FM BW = ±200 kHz - 90 - dB
VN,in FM Input noise referred to mixer input mixer 1
mixer 2 -1.1
0.7
1.9
1.2 nV/Hz
DRAM Dynamic range in AM BW = ±4 kHz - 103 - dB
VN,in AM Input noise referred to mixer input - - 6.9 12 nV/Hz
Electrical specifications TDA7705
20/42 Doc ID 15938 Rev 9
3.4.7 Audio DAC
3.4.8 IO interface pins
Table 13. Audio DAC
Symbol Parameter Test condition Min Typ Max Units
Vout Max. output voltage Full scale - 1 - Vrms
BW Bandwidth 1dB attenuation - 15 - KHz
Rout Output resistance - 600 750 900
VN, out Output noise - - 60 95 µVrms
THD Distortion -6 dBFS - 0.03 0.04 %
Table 14. IO interface pins
Symbol Parameter Test condition Min Typ Max Units
-High level output voltage (all
IOs except GPO pin 2) Iout = 500 µA 2.9 3.2 - V
-GPIOs source current (all IOs
in source mode except pin 2)
Total sourced current by all
GPIOs - - 1.25 mA
-Low level output voltage (all
IOs except GPO pin 2) Iout = -1 mA - 0.1 0.3 V
- Input voltage range - 0 - 3.5 V
- High level input voltage - 2.0 - - V
- Low level input voltage - - - 0.8 V
Treset Reset time
Minimum time during which
pin RSTN must be low so as
to reset the device
10 - - µs
Tlatch
Boot mode configuration latch
time
Minimum time during which
the voltage applied at pins 25
and 39 must be kept in order
to latch the correct boot mode
(serial bus configuration)
10 - - µs
-GPO PLLTEST (pin 2) max
source current ---1mA
-GPO PLLTEST (pin 2) max
sink current --1-mA
-
GPO PLLTEST (pin 2)
minimum high level output
voltage
Iout = 1 mA 2.8 3.1 - V
GPO PLLTEST (pin 2)
maximum high level output
voltage
Iout = 1 mA - 0.1 0.3 V
TDA7705 Electrical specifications
Doc ID 15938 Rev 9 21/42
3.4.9 I2C interface
The following parameters apply to the serial bus communication when I2C protocol has
been selected at start-up. For the other electrical characteristics of the pins, Section 3.4.8
applies. The parameters of the following table are defined as in Figure 8.
Figure 8. I2C bus timing diagram
Table 15. I2C interface
Symbol Parameter Min Max Units
fSCL SCL Clock frequency - 500 kHz
tAA SCL low to SDA data valid 0.3 - µs
tbuf
time the bus must be kept free before a new
transmisison 1.3 - µs
tHD-STA START condition hold time 0.6 - µs
tLOW Clock low period 1.3 - µs
tHIGH Clock high period 0.6 - µs
tSU-SDA START condition setup time 0.1 - µs
tHD-DAT Data input hold time 0 0.9 µs
tSU-DAT Data input setup time 0.1 - µs
tRSDA & SCL rise time - 0.3 µs
tFSDA & SCL fall time - 0.3 µs
tSU-STOP Stop condition setup time 0.6 - µs
tDH Data out time - 0.3 µs
D95AU378A
tHIGH tRtLOW tF
SCL
SDA IN
SDA OUT
tSU-STA
tHD-SDA
tHD-DAT
tSU-DAT
tSU-STOP
tbuf
tAA tDH
Electrical specifications TDA7705
22/42 Doc ID 15938 Rev 9
3.4.10 SPI interface
The following parameters apply to the serial bus communication when SPI protocol has
been selected at start-up. For the other electrical characteristics of the pins, Section 3.4.8
applies.
Figure 9. SPI bus timing diagram
3.4.11 Warning
When the TDA7705 is not powered on, the internal ESD protection diodes pull-down keep
the I2C/SPI lines connected to ground. This implies that the I2C/SPI bus connected to the
TDA7705 may not be used to drive other devices when the TDA7705 is powered off.
Table 16. SPI interface
Symbol Parameter Min Max Unit
fSCK Clock frequency - 4.0 MHz
tSU Data setup time 25 - ns
tH Data hold time 25 - ns
tWH SCK high time 50 - ns
tWL SCK low time 50 - ns
tRI Input rise time - 2 µs
tFI Input fall time - 2 µs
tV Output valid from clock low - 50 ns
tHO Output hold time 25 - ns
tDIS Output disable time 25 ns
tCS CS high time 25 - ns
tCSS CS setup time 25 - ns
tCSH CS hold time 25 - ns
VALID IN
V
IH
V
IL
t
CSS
V
IH
V
IL
V
IH
VIL
V
OH
V
OL
HI-Z
t
SU
t
H
t
WH
t
WL
t
V
t
CS
t
CSH
t
HO
t
DIS
HI-Z
SPI_SS
SPI_CLK
SPI_MOSI
SPI_MISO
t
RI
tFI
TDA7705 Electrical specifications
Doc ID 15938 Rev 9 23/42
3.5 Overall system performance
All measurements obtained with application of Figure 16 (FM tuned application / SPI
control) unless otherwise specified.
3.5.1 FM overall system performance
Antenna level equivalence: 0 dBµV = 1 µVrms (Antenna terminal voltage with 50 source).
Figure 10. FM input set-up
Input level referred to signal generator loaded with 50 (Vrf, node 'A'); no antenna dummy;
AM input not connected. Frf = 98.1 MHz, Vrf = 60 dBµV, mono modulation, fdev = 40 kHz,
faudio = 1 kHz. De-emphasis = 50 µs. Unless otherwise specified
Table 17. FM overall system performance
Parameter Test condition Min Typ Max Units
Tuning range FM Eu
(can be modified by the user)
(automatic FE alignment
available)
87.5 - 108 MHz
Tuning step FM Eu (can be modified by the user) - 100 - kHz
Tuning range FM US
(can be modified by the user)
(automatic FE alignment
available)
87.5 - 107.9 MHz
Tuning step FM US (can be modified by the user) - 200 - kHz
Tuning range FM Jp
(can be modified by the user)
(automatic FE alignment
available)
76 - 90 MHz
Tuning step FM Jp (can be modified by the user) - 100 - kHz
Tuning range FM EEu
(can be modified by the user)
(automatic FE alignment not
available)
65 - 74 MHz
Tuning step FM EEu (can be modified by the user) - 100 - kHz
Sensitivity S/N =26dB - -7 -4 dBµV
S/N @ 10 dBµV, no highcut, DISS
BW = #3 -55-dB
Ultimate S/N
@ 60 dBµV, mono 72 75 - dB
@ 60 dBµV,
Deviation = 75 kHz, mono 78 81 - dB
@ 60 dBµV, stereo 70 73 - dB
V
rf
+ 6dB
PCB
UNDER
TEST
50Ω
V
rf
+ 6dB V
rf
50Ω
50Ω
A
Electrical specifications TDA7705
24/42 Doc ID 15938 Rev 9
Distortion Deviation= 75 kHz - 0.05 - %
Max deviation THD=3% - 140 - kHz
Adjacent channel selectivity
F=100kHz, SINAD=30dB
desired 40 dBµV, dev=40kHz,
400Hz
undesired. dev=40kHz, 1KHz
-25-dB
Alternate channel selectivity
F=200 kHz, SINAD=30 dB
desired 40 dB µV,
dev=40kHz, 400 Hz
undesired. dev=40kHz, 1kHz
-63-dB
Max. strong signal interferer
Desired = 10 dBµV
SINAD = 30 dB
Undesired F = 5 MHz
dev = 40 kHz, 1 kHz
- 94 - dBµV
Max. strong signal interferer
no preselection (“wide-band”)
application
Desired = 10 dBµV
SINAD = 30 dB
Undesired F = 5 MHz
dev = 40 kHz, 1 kHz
- 88 - dBµV
3 signal performance(1)
Desired = 40 dBµV,
dev = 40 kHz, 400 Hz,
SINAD = 30 dB
Undesired1 = ±400 kHz,
dev = 40 kHz, 1 kHz
Undesired2 = ±800 kHz, no
mod
- 103 - dBµV
Desired = 40 dBµV,
dev = 40 kHz, 400 Hz,
SINAD = 30 dB
Undesired1 = ±1 MHz,
dev=40kHz, 1 kHz
Undesired2=±2MHz, no mod
- 106 - dBµV
3 signal performance(1)
no preselection (“wide-band”)
application
Desired = 40 dBµV,
dev = 40 kHz, 400 Hz,
SINAD = 30 dB
Undesired1 = ±400 kHz,
dev = 40 kHz, 1 kHz
Undesired2 = ±800 kHz, no
mod
- 103 - dBµV
Desired = 40 dBµV,
dev=40kHz, 400 Hz,
SINAD=30 dB
Undesired1 =±1 MHz,
dev=40kHz, 1 kHz
Undesired2=±2MHz, no mod
- 104 - dBµV
AM suppression m =30 % - 70 - dB
Table 17. FM overall system performance (continued)
Parameter Test condition Min Typ Max Units
TDA7705 Electrical specifications
Doc ID 15938 Rev 9 25/42
3.5.2 AM MW overall system performance
Antenna level equivalence: 0 dBµV = 1 µVrms.
Figure 11. AM MW input set up
Level referred to SG output before antenna dummy (Vrf, node 'A'); capacitive dummy
15pF+68pF, FM input not connected. Frf = 999 kHz (1000 kHz for US), Vrf =74 dBµV,
mod = 30%, faudio =400 Hz, unless otherwise specified.
Image rejection - - 80 - dB
Logarithmic field strength
indicator
@40 dBµV
read “FM_Smeter_log”
-0.33
(equiv.
to 37
dBµV)
-0.3
-0.27
(equiv.
to 43
dBµV)
--
1. Signal levels referred to combiner output.
Table 17. FM overall system performance (continued)
Parameter Test condition Min Typ Max Units
Table 18. AM MW overall system performance
Parameter Test condition Min Typ Max Units
Tuning range MW Eu/Jp (can be modified by the user) 531 - 1629 kHz
Tuning step MW Eu/Jp (can be modified by the user) - 9 - kHz
Tuning range MW US (can be modified by the user) 530 - 1710 kHz
Tuning step MW US (can be modified by the user) - 10 - kHz
Sensitivity S/N = 20 dB - 27 30 dBµV
Ultimate S/N @ 80 dBµV 63 66 - dB
AGC F.O.M. Ref.=74 dBµV
-10dB drop point 50 62 65 dB
Distortion m = 80 % - 0.1 - %
Adjacent channel selectivity F=9 kHz, SINAD = 26 dB
undesired. m=30%, 1 kHz -42-dB
Alternate channel selectivity F=18 kHz, SINAD=26 dB
undesired. m=30%, 1kHz -50-dB
PCB
UNDER
TEST
30Ω
V
rf
+ 6dB V
rf
50Ω
50Ω
15pF
68pF
A
Electrical specifications TDA7705
26/42 Doc ID 15938 Rev 9
Strong signal interferer
SNR
F= ±40 kHz
desired = 40 dBµV
undesired = 100 dBµV,
m= 30%, 1 kHz
-15-dB
F=±400kHz
desired=40 dBµV
undesired=100 dBµV,
m=30%, 1kHz
17 - - dB
Strong signal interferer
suppression
F=±40 kHz
desired=40 dBµV
undesired=110 dBµV,
m=30%, 1 kHz
-4-dB
F=±400kHz
desired=40 dBµV
undesired=110 dBµV,
m=30%, 1kHz
-4-dB
Strong signal interferer
cross-modulation
F=±40kHz
desired=80 dBµV
undesired=100 dBµV,
m=30%, 1kHz
- - 10 dB
F=±400kHz
desired=80 dBµV
undesired=100 dBµV,
m=30%, 1kHz
- - 10 dB
Image rejection - - 80 - dB
Logarithmic field strength
indicator
@60 dBµV
read “AM_Smeter_log”
0.50
(equiv.
to 57
dBµV)
0.47
0.43
(equiv.
to 63
dBµV)
-
Table 18. AM MW overall system performance (continued)
Parameter Test condition Min Typ Max Units
TDA7705 Electrical specifications
Doc ID 15938 Rev 9 27/42
3.5.3 AM LW overall system performance
Antenna level equivalence: 0 dBµV = 1 µVrms
Figure 12. AM LW input set-up
Level referred to SG output before antenna dummy (Vrf, node 'A'); capacitive dummy
15pF+68pF; FM input not connected. Frf = 216 kHz, Vrf =74 dBµV, mod = 30 %,
faudio = 400 Hz, unless otherwise specified.
Table 19. AM LW overall system performance
Parameter Test condition Min Typ Max Units
Tuning range LW (can be modified by the user) 144 - 288 kHz
Tuning step LW (can be modified by the user) - 1 - kHz
Sensitivity S/N =20 dB - 30 33 dBµV
Ultimate S/N @ 80 dBµV 63 66 - dB
AGC F.O.M. Ref.=74 dBµV
-10dB drop point 50 62 65 dB
Distortion m = 80 % - 0.1 - %
Image rejection - - 80 - dB
PCB
UNDER
TEST
30Ω
V
rf
+ 6dB V
rf
50Ω
50Ω
15pF
68pF
A
Electrical specifications TDA7705
28/42 Doc ID 15938 Rev 9
3.5.4 AM SW overall system performance
Antenna level equivalence: 0dBµV = 1µVrms
Figure 13. AM SW input set-up
Level referred to SG output before antenna dummy (Vrf, node 'A'); capacitive dummy
15pF+68pF; FM input not connected. Frf = 6000 kHz, Vrf =74 dBµV, mod = 30 %,
faudio = 400 Hz, unless otherwise specified.
Table 20. AM SW overall system performance
Parameter Test condition Min Typ Max Units
Tuning range LW (can be modified by the user) 2300 - 30000 kHz
Tuning step LW (can be modified by the user) - 1 - kHz
Sensitivity S/N =20dB - 29 32 dBµV
Ultimate S/N @ 80 dBµV 63 66 - dB
AGC F.O.M. Ref.=74 dBµV -10dB drop point 50 62 65 dB
Distortion m = 80 % - 0.3 - %
Image rejection - - 80 - dB
PCB
UNDER
TEST
30Ω
V
rf
+ 6dB V
rf
50Ω
50Ω
15pF
68pF
A
TDA7705 Electrical specifications
Doc ID 15938 Rev 9 29/42
3.5.5 WX overall system performance
Antenna level equivalence: 0 dBµV = 1 µVrms (Antenna terminal voltage with 50 source).
Figure 14. WX input set-up
Input level referred to signal generator loaded with 50 (Vrf, node 'A'); no antenna dummy;
AM input not connected. Frf =162.475 MHz, Vrf = 60 dBµV, mono modulation, fdev = 3 kHz,
faudio =400 Hz. De-emphasis = 75 µs. Application: WX using mixer input 2, in conjunction
with FM narrow-band. Unless otherwise specified.
Table 21. WX overall system performance
Parameter Test condition Min Typ Max Units
Sensitivity S/N = 26 dB - -7 - dBµV
Ultimate S/N @ 60 dBµV - 81 - dB
Distortion Deviation= 4.5 kHz - 0.8 - %
Max deviation THD = 3 % - > 5 kHz - kHz
Adjacent channel Selectivity
F= 25 kHz, SINAD = 30 dB
desired 40 dBµV,
dev =2.0 kHz, 400 Hz
undesired. dev= 3 kHz, 1 kHz
-70-dB
Alternate Channel Selectivity
F=50kHz, SINAD=30dB
desired 40 dBµV,
dev=2.0kHz, 400Hz
undesired. dev=2.0kHz, 1kHz
-70-dB
V
rf
+ 6dB
PCB
UNDER
TEST
50Ω
V
rf
+ 6dB V
rf
50Ω
50Ω
A
Front-end processing TDA7705
30/42 Doc ID 15938 Rev 9
4 Front-end processing
All the parameters in this section refer to the programmability of the FE part of the device
(registers). The part of the registers that are not described here have either fixed values or
values written by the tuner drivers, and are described in the proper technical documentation.
Table 22. Register 0x00
Register number
Register definition
MSB LSB
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AM mixer input selector
0 1 input #1
1 0 input #2
AM PIN diode
0 internal
1 external
AM AGC mode
0 LNA and PIN diode
1 PIN diode only
AM AGC time constant
0 0 slow (125 ms with 1 µF)
0 1 medium (25 ms with 1 µF)
1 1 fast (5 ms with 1 µF)
AM AGC threshold @ mixin
0 0 0 90 dBµV
0 0 1 91 dBµV
0 1 0 92 dBµV
0 1 1 93 dBµV
1 0 0 90 dBµV
1 0 1 89 dBµV
1 1 0 88 dBµV
1 1 1 87 dBµV
AM AGC attack time constant
0normal
1fast
TDA7705 Front-end processing
Doc ID 15938 Rev 9 31/42
Table 23. Register 0x01
Register number
Register definition
MSB LSB
23222120191817161514131211109876543210
FM mixer input selector
0 1 1 0 input #1
1 0 0 1 input #2
FM mixer gain
0high
1low
FM AGC time constant
0normal
1fast
FM AGC output mode
00 normal
01 constant 15 mA
10 constant 1 mA
Table 24. Register 0x02
Register number
Register definition
MSB LSB
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FM RF AGC threshold @
mixin
0 0 87 dBµV
0 1 89 dBµV
1 0 91 dBµV
1 1 93 dBµV
FM iF AGC threshold @
IFADC in
0 0 120 dBµV
0 1 122 dBµV
1 0 124 dBµV
Tuning DAC enable
0off
1on
Tuning DAC programming
(1)
00000000 0
00000001 1
…………………… …
11111110 510
11111111 511
1. Normally handled by tuner drivers.
Front-end processing TDA7705
32/42 Doc ID 15938 Rev 9
Table 25. Register 0x05
Register number
Register definition
MSB LSB
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLLTEST output status
0low
1high
TDA7705 Weak signal processing
Doc ID 15938 Rev 9 33/42
5 Weak signal processing
All the parameters in this section refer to the programmability of the DSP part of the device.
The typical values are those set by default parameters (start-up without parametric change
from main µP); the max and the min values refer to the programmability range. The values
are referred to the typical application (Figure 16: Example of FM tuned (narrow-band)
application / SPI control). Wherever the possible values are a discrete set, all the possible
programmable values are displayed.
5.1 FM IF-processing
5.1.1 Dynamic channel selection filter (DISS)
5.1.2 Soft mute
Table 26. Dynamic channel selection filter (DISS)
(discrete set)
Symbol Parameter Test condition Min Typ Max Units
DISS BW
IF filter #6
response: - 3dB
- ±150 - kHz
IF filter #5 - ±110 - kHz
IF filter #4 - ±80 - kHz
IF filter #3 - ±60 - kHz
IF filter #2 - ±45 - kHz
IF filter #1 - ±35 - kHz
IF filter #0 - ±25 - kHz
Table 27. Soft mute
(continuous set)
Symbol Parameter Test condition Min Typ Max Units
SMsp Start point vs. field strength
audio atten = 1 dB
read “FM_softmute”
no adjacent channel present
0 6 20 dBµV
SMep End point vs. field strength
audio atten = SMd + 1 dB
read “FM_softmute”
no adjacent channel present
-6 -6 10 dBµV
SMd Depth - -30 -15 0 dB
SMtauatt
Field strength LPF cut-off
frequency for soft mute
activation
- 0.1 100 4000 Hz
SMtaurel
Field strength LPF cut-off
frequency for soft mute
release
- 0.1 1 4000 Hz
Weak signal processing TDA7705
34/42 Doc ID 15938 Rev 9
5.1.3 Adjacent channel mute
5.1.4 Stereo blend-
Table 28. Adjacent channel mute
(continuous set)
Symbol Parameter Test condition Min Typ Max Units
ACMd Depth SMd 0 0 dB
Table 29. Stereo blend
(continuous set)
Symbol Parameter Test condition Min Typ Max Units
MaxSep Maximum stereo separation field strength = 80 dBµV, pilot
deviation = 6.75 kHz 04050dB
SBFSsp Start point vs. field strength separation = MaxSep - 1 dB
no multipath present 20 50 60 dBµV
SBFSep End point vs. field strength separation = 1 dB
no multipath present 20 30 60 dBµV
SBFStM2S
Field strength-related
transition time from mono to
stereo
Vrf step-like variation from
20 dBµV to 80 dBµV 0.001 3 20 s
SBFStS2M
Field strength-related
transition time from stereo to
mono
Vrf step-like variation from
80 dBµV to 20 dBµV 0.001 0.5 20 s
SBMPsp Start point vs. multipath
separation = MaxSep - 1 dB
equivalent 19 kHz AM
modulation depth;
field strength = 80 dBµV
51080%
SBMPep End point vs. multipath
separation = 1 dB
equivalent 19 kHz AM
modulation depth;
field strength = 80 dBµV
53080%
SBMPtM2S Multipath -related transition
time from mono to stereo
Vrf step-like variation from
20 dBµV to 80 dBµV 0.001 1 20 s
SBMPtS2M Multipath -related transition
time from stereo to mono
Vrf step-like variation from
80 dBµV to 20 dBµV 0.001 0.001 20 s
Pil ThrM2S Pilot detector stereo threshold
Threshold on pilot tone
deviation for mono-stereo
transition
0.8 2.74 7 kHz
Pil ThrHyst Pilot detector threshold
hysteresis
Difference in pil. det.
deviation threshold for stereo
to mono transition compared
to PilThrM2S
- 0.01 - kHz
TDA7705 Weak signal processing
Doc ID 15938 Rev 9 35/42
5.1.5 High cut control
Table 30. High cut control
(continuous set)
Symbol Parameter Test condition Min Typ Max Units
HCFSsp Start point vs. field strength
minimum RF level for widest
HC filter (filter # 7)
no multipath present
05050dBµV
HCFSep End point vs. field strength
maximum RF level for
narrowest HC filter (filter # 0)
no multipath present
03040dBµV
HCFStW2N
Field strength-related
transition time from wide to
narrow band
Vrf step-like variation from
60 dBµV to 10 dBµV
(1) -
HCFStN2W
Field strength-related
transition time from narrow to
wide band
Vrf step-like variation from
0 dBµV to 60 dBµV
(1) 14 100 s
HCMPsp Start point vs. multipath
minimum RF level for widest
HC filter (filter # 7)
equivalent 19 kHz AM
modulation depth;
field strength = 80 dBµV
5 10 150 (2) %
HCMPep End point vs. multipath
maximum RF level for
narrowest HC filter (filter # 0)
equivalent 19 kHz AM
modulation depth;
field strength = 80 dBµV
5 30 150 (2) %
HCMPtN2W
Multipath -related transition
time from narrow to wide
band
Vrf step-like variation from
20 dBµV to 80 dBµV 0.001 0.001 20 s
HCMPtW2N Multipath -related transition
time from wide to narrow
Vrf step-like variation from
80 dBµV to 20 dBµV 0.001 0.001 20 s
HCmaxBW Maximum cut-off frequency of
high cut filter bank
Filter #7, -3 dB response
frequency, input signal with
pre-emphasis
HCmin
BW 14 18 kHz
HCminBW Minimum cut-off frequency of
high cut filter bank
Filter #0, -3 dB response
frequency, input signal with
pre-emphasis
0.1 3 HCma
xBW kHz
HCnumFilt Number of discrete HC filters - - 8 (3) --
1. Depends only on field strength filter time constant.
2. Means that 100% equivalent 19 kHz AM modulation depth will not achieve full band narrowing.
3. Intermediate filters (#6 - #1) cut-off frequencies exponentially spaced between HCmaxBW and HCminBW.
Weak signal processing TDA7705
36/42 Doc ID 15938 Rev 9
5.1.6 Stereo decoder
5.2 AM IF-processing
5.2.1 Channel selection filter
5.2.2 Soft mute
Table 31. De-emphasis filter
(continuous set)
Symbol Parameter Test condition Min Typ Max Units
DEtc De-emphasis time constant 1 - - 50 - µs
De-emphasis time constant 2 - - 75 -
Table 32. Stereo decoder
Symbol Parameter Test condition Min Typ Max Units
PilSup Pilot signal suppression Pilot 9%, 19 kHz, ref=40 kHz - 60 - dB
SubcSup Subcarrier suppression
f = 38 kHz - 70 - dB
f = 57 kHz - 70 - dB
f = 76 kHz - 80 - dB
Table 33. Channel selection filter
Symbol Parameter Test condition Min Typ Max Units
CSF BW Channel selection filter BW response: - 3dB - ±3.7 - kHz
Table 34. Soft mute
(continuous set)
Symbol Parameter Test condition Min Typ Max Units
SMsp Start point vs. field strength
audio atten = 1 dB
read “FM_softmute”
no adjacent channel present
02540dBµV
SMep End point vs. field strength
audio atten = SMd + 1 dB
read “FM_softmute”
no adjacent channel present
0 0 30 dBµV
SMd Depth - -40 -24 0 dB
SMtauatt
Transition time for field
strength-dependent soft mute
activation
- 0.001 0.1 10 s
SMtaurel
Transition time for field
strength-dependent soft mute
release
- 0.001 3 10 s
TDA7705 Weak signal processing
Doc ID 15938 Rev 9 37/42
5.2.3 High cut control
Table 35. High cut control
(continuous set)
Symbol Parameter Test condition Min Typ Max Units
HCFSsp Start point vs. field strength
minimum RF level for widest
HC filter (filter # 7)
no multipath present
04050dBµV
HCFSep End point vs. field strength
maximum RF level for
narrowest HC filter (filter # 0)
no multipath present
03050dBµV
HCFStW2N
Field strength-related
transition time from wide to
narrow band
Vrf step-like variation from
60 dBµV to 10 dBµV 0.001 0.2 20 s
HCFStN2W
Field strength-related
transition time from narrow to
wide band
Vrf step-like variation from
0 dBµV to 60 dBµV 0.001 10 20 s
HCmaxBW Maximum cut-off frequency of
high cut filter bank
Filter #7, -3 dB response
frequency, input signal with
pre-emphasis
HCmin
BW 14 18 kHz
HCminBW Minimum cut-off frequency of
high cut filter bank
Filter #0, -3 dB response
frequency, input signal with
pre-emphasis
13
HCma
xBW kHz
HCnumFilt Number of discrete HC filters - 8 - -
Application schematics TDA7705
38/42 Doc ID 15938 Rev 9
6 Application schematics
6.1 Basic application schematic
Figure 15. FM wide-band application / I2C control
1. Note: components marked with a * are being considered for replacement with resistors, pending
optimization test results.
TOKO
NDK5032
TOKO
XTAL
**
*
FMANT
VRF
DACOUT_R
AMANT
RDSINT
VDIG
VDIG
SCL
SDA_MOSI
DACOUT_L
RSTN
VIF
GND-RF
GND-RF
GND-RF
GND-RF
GND-RF
DIG_GND
DIG_GND
GND-RF
DIG_GND
GND-RF
GND-RF
DIG_GND
DIG_GND
470nF
10nF
LLQ2012-FR22
PLL TEST
22pF
1uF
TDA7705
1
2
3
4
5
6
17
48
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
7
8
9
10
11
12
13
14
15
16
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
LF1
PLLTEST
DAC
TCAGCFM
FMMIX1dec
FMMIX1in
LNAdec
GND-1V2
GND-VCO
VCC-VCO
LFref
VCOdec
GND-PLL
VCC-PLL
VCC-IFADC
LIFrefH
LIFrefL
GND-IFADC
DACoutR
DACoutL
GND-DAC
OSCin
OSCout
VCC-DAC
FMMIX2in
GND-RF
FMPINDRV
VCC-RF
TCAM
AMPINDRV
PINDdec
PINDin
GND-LNA
LNAin
LNAout
LNAin2
LNAout2
LNAdec2
AMMIXin2
AMMIXin1
AMMIXdec
GND-IF
VREF165
VREFdec
GND-DIG
VCC-DIG
VCCREG12
REG-1V2
VDD-3V3
VDD-1V2
TEST
RSTN
MODE
AFS
GPIO1
GPIO2
GPIO3
RDSINT
VDD-1V2
SCL
SDA
SPI_MISO
SPI_CS
GND-3V3
220pF
LLQ2012-FR22
100nF
KP2311E
100nF
1K
1uF
22pF
1K
100nF
68uH
68pF
100
10nF
5.6K
100nF
68uH
220
1K
15pF
10nF
100nF
120pF
100nF
10nF
KP2311E
4.7nF
100nF
10nF
220nF
100nF
1uF
10nF
2.2uF
37.05MHz
1
2
1uF
1uF
100nF
1µF
1uF
27 1/2W
100nF
100nF
TDA7705 Application schematics
Doc ID 15938 Rev 9 39/42
6.2 Application schematic example with SPI-bus and tuned
preselection
Figure 16. Example of FM tuned (narrow-band) application / SPI control
1. Note: components marked with a * are being considered for replacement with resistors, pending
optimization test results.
TOKO
TOKO
NDK5032
TOKO
XTAL
*
**
FMANT
VRF
DACOUT_R
AMANT
VDIG
VIF
DACOUT_L
RDSINT
VDIG
CS
SCL
SDA_MOSI
RSTN
SPI_MISO
GND-RF
DIG_GND
DIG_GND
DIG_GND
GND-RF
GND-RF
GND-RF
GND-RF
GND-RF
GND-RF
GND-RF
DIG_GND
470nF
D3
KV1770
1 2
3
10nF
PLL TEST
1
KP2311E
21
1nF
1uF
R6 68K
TDA7705
1
2
3
4
5
6
17
48
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
7
8
9
10
11
12
13
14
15
16
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
LF1
PLLTEST
DAC
TCAGCFM
FMMIX1dec
FMMIX1in
LNAdec
GND-1V2
GND-VCO
VCC-VCO
LFref
VCOdec
GND-PLL
VCC-PLL
VCC-IFADC
LIFrefH
LIFrefL
GND-IFADC
DACoutR
DACoutL
GND-DAC
OSCin
OSCout
VCC-DAC
FMMIX2in
GND-RF
FMPINDRV
VCC-RF
TCAM
AMPINDRV
PINDdec
PINDin
GND-LNA
LNAin
LNAout
LNAin2
LNAout2
LNAdec2
AMMIXin2
AMMIXin1
AMMIXdec
GND-IF
VREF165
VREFdec
GND-DIG
VCC-DIG
VCCREG12
REG-1V2
VDD-3V3
VDD-1V2
TEST
RSTN
MODE
AFS
GPIO1
GPIO2
GPIO3
RDSINT
VDD-1V2
SCL
SDA
SPI_MISO
SPI_CS
GND-3V3
1
220pF
LLQ2012-FR39
C28
10nF
100nF
1K5
100nF
1
1uF
20pF
C31 15pF
1K
68uH
100nF
C23
12pF
68pF
10nF
5.6K
100nF
68uH
100
1K
C25 6pF
100nF
10nF
120pF
100nF
5pF
L6
E558CN-1000101
LLQ2012-FR18
4.7nF
39pF
100nF
KP2311E
21
100nF
220nF
1uF
100nF
2.2uF
1uF
37.05MHz
1
2
1uF
100nF
1µF
1uF
27 1/2W
1nF
100nF
220
100nF
at www. sl.com HHHHHH HHHHHH
Package information TDA7705
40/42 Doc ID 15938 Rev 9
7 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 17. LQFP64 (10x10x1.4mm) mechanical data and package dimensions
OUTLINE AND
MECHANICAL DATA
A
A2
A1
B
C
16
17
32
33
48
49
64
E3
D3
E1
E
D1
D
e
1
K
B
TQFP64
L
L1
Seating Plane
0.08mm
DIM.
mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 1.60 0.063
A1 0.05 0.15 0.002 0.006
A2 1.35 1.40 1.45 0.053 0.055 0.057
B 0.17 0.22 0.27
0.20
0.0066 0.0086 0.0106
0.0079
C 0.09 0.0035
D 11.80 12.00 12.20 0.464 0.472 0.480
D1 9.80 10.00 10.20 0.386 0.394 0.401
D3 7.50 0.295
e 0.50 0.0197
E 11.80 12.00 12.20 0.464 0.472 0.480
E1 9.80 10.00 10.20 0.386 0.394 0.401
E3 7.50 0.295
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 1.00 0.0393
K (min.), 3.5˚ (min.), 7˚(max.)
ccc 0.080 0.0031
LQFP64 (10 x 10 x 1.4mm)
0051434 F
ccc
TDA7705 Revision history
Doc ID 15938 Rev 9 41/42
8 Revision history
Table 36. Document revision history
Date Revision Changes
31-Jul-2007 1 Initial release.
01-Aug-2008 2 Full update datasheet.
08-May-2009 3
Document status promoted from preliminary data to datasheet.
Updated Table 1: Device summary on page 1.
Updated Section 3: Electrical specifications on page 16.
Updated Section 4: Front-end processing on page 30.
Updated Section 5: Weak signal processing on page 33.
Updated Section 6: Application schematics on page 38.
09-Jun-2009 4
Updated Table 5: Thermal data on page 16.
Updated the value of “Adjacent channel selectivity” parameter in the
Table 17: FM overall system performance.
01-Jul-2009 5 Updated Figure 17: LQFP64 (10x10x1.4mm) mechanical data and
package dimensions on page 40.
13-Jan-2010 6
Modified Table 1: Device summary on page 1
Modified Table 5: Thermal data on page 16.
Modified Section 3.5.5: WX overall system performance on page 29.
Modified Section 7: Package information on page 40.
29-Jan-2010 7
Minor text changes in Section 2.13.
Modified min. value of “tHD-DAT” parameter in Tab le 1 5: I 2C interface
on page 21.
22-Mar-2010 8 Added Section 3.4.11: Warning on page 22.
17-Sep-2013 9 Updated Disclaimer
Ts AT
TDA7705
42/42 Doc ID 15938 Rev 9
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