MPC8536DS Fact Sheet Datasheet by NXP USA Inc.

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Embedded Computing Development
MPC8536DS
Integrated media and communications processor development system
Overview
The MPC8536E Development System
(MPC8536DS) is ideal for hardware and
software development for embedded
applications. It leverages Freescale’s highly
integrated MPC8536E processor, built on
Power Architecture® technology, and
leading-edge external components.
The high level of integration in the MPC8536E
processor helps to lower system costs,
improve performance and simplify board
design. The MPC8536E processor supports:
• Dual-enhancedthree-speedEthernet
controllers (eTSEC) with IEEE® 1588
Rev 2 support
• MultiplePCIExpress® ports supporting
one x8, two x4, or one x4 and two x2
link widths
• 32-bitPCIcontroller
• Advancedpowermanagementcontroller
• ThreeintegratedUSBcontrollers
• TwointegratedSATAcontrollers
• EnhancedSerialPeripheralInterface(eSPI)
• EnhancedSecureDigitalHardware
Controller(eSDHC)
• 4-channeldirectmemoryaccess(DMA)
• Dualuniversalasynchronousreceiver/
transmitter(DUART)
• Serialperipherals
• GeneralpurposeI/O
• Systemtimers
The MPC8536E processor also integrates
an optional hardware encryption block
that supports different algorithms for high-
performance data that is critical for supporting
secure communications. Devices marked with
an E include this security engine.
Aboardsupportpackage(BSP)is
pre-installed on the MPC8536DS.
ThisBSPconsistsofabootloader
(u-boot) and a generic Power
Architecture technology system
based on the Linux® kernel.
The u-boot binary and the Linux
kernel reside in the on-board flash
memory with a file system pre-
installed on the hard disk shipped
in the MPC8536DS development
system.
TheMPC8536DSBSPgeneration
takes advantage of the Linux
TargetImageBuilder(LTIB),asuite
of tools that leverages existing
open source configuration scripts
and source code packages,
packingthemallintoasingleBSP
generation bundle. The source
code packages include boot
loader and Linux kernel sources
as well as many user-space source code
packagestobuildacompleteBSP.TheLTIB
also provides compiler packages, required
tobuildtheBSP.Freescaledevelopersuse
theLTIBtocreateBSPsforamultitudeof
Freescaledevelopmentmarkets.TheLTIB
leveragesasmanyBSPelementsaspossible
for the Freescale markets supported, while
offering the flexibility necessary to customize
components that require platform-specific
modifications.
Many third-party applications are available
for the MPC8536DS. They are typically
builtontopoftheBSPdeliveredby
Freescale and can be installed on the hard
disk. To see demonstrations or to acquire
details of Freescale’s third-party applications
for this platform, please contact your local
Freescale sales office.
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Learn More: For current information about Freescale
products and documentation, please visit
www.freescale.com.
Freescale and the Freescale logo are trademarks or registered trademarks of Freescale Semiconductor, Inc.
intheU.S.andothercountries.Allotherproductorservicenamesarethepropertyoftheirrespectiveowners.
The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are
trademarks and service marks licensed by Power.org. © Freescale Semiconductor, Inc. 2009.
Document Number: MPC8536DSFS
REV 1
MPC8536E Development System
•MPC8536E
PowerQUICC® III
processor
• 512MBDDR2 DIMM
• TwoSATAconnectors(TypeIandTypeL)
• ThreePCIExpressslots
• OnePCIslotwithdynamicsupportof
33MHzand66MHzcards
• ThreeUSBconnectors(twohostand
one device)
• TwoSDmediaslots
• FoureSPIEEPROMs(64MBtotal)
• Two10/100/1000Ethernetconnectors
• SGMIIrisercardslot(SGMII-RISER)
• Real-timeclock
• TwoRS232connectors
• JTAGheader
• 128MBNORflashmemory
• 4GBNANDflashmemory
• Powerandtemperaturemonitoringcircuitry
• Systemlogic(FPGA)
Manages system reset sequencing
Manages system bus and PCI clock
speed selections
Implements registers for system control
and monitoring
• Systemclock
SYSCLK switch can be set to one of
eight common settings in the interval
33MHz–166MHz
• DDRclock
DDRCLK switch can be set to one of
eight common settings in the interval
33MHz–166MHz
• Powersupplies
 DedicatedregulatorforVDD_VCORE
(1.1V or 1.0V)
Dedicated regulator for VDD_PLAT (1.0V)
• Documentation
Reference manual
Schematics
 Billofmaterials
 Boarderrata
Configuration guide
• Softwaretools
Linux 2.6.x kernel
 CrosscompileandnativeGNUtoolchain
 CodeWarrior™USBTAP
MPC8536DS Block Diagram
Core Accelerators I/O Connector or Slot
2 x Ethernet
USB Device
2 x USB Host
DDR2 DIMM
PCI
Type I
SATA
SGMII
Riser Slot
Type L
SATA
DDR2
SDRAM Controller
I2C (for SPD read)
Performance Monitor,
eSPI, DUART, 2 x I2C,
Timers, GPIO,
Interrupt Control
Security
Acceleration
XOR
System Bus
Advanced Power
Management Controller
SPI Flash
2 x SATA2 x SATA
2 x Gigabit
Ethernet 2 x SGMII PCI 4-ch.
DMA
4-ch.
DMA
PCI
Express
PCI
Express
PCI
Express
PCI
Express®
PCI
Express®
On-Chip NetworkOn-Chip Network
2-lane SerDes 8-lane SerDes
2 x SD Media
2 x RS-232
2 x SPI
JTAG
32 KB
L1 I-Cache
e500 Core
32 KB
L1 D-Cache
Coherency Module
512 KB
L2 Cache
PCI Express x8/x4
PCI Express x2
Enhanced Local Bus
NOR
Flash
NAND
Flash
PromJet
Emulator
Plat/DDR Clocks
System Control
Logic FPGA
DDR Regulator Core RegulatorPlat/SerDes Regulator
EN
OK
Power EN
Power OK
PCI Express x2
eSDHC
3 x USB
Host/Device
3 x USB
Host/Device

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