MC9S08FL16 Series Datasheet by NXP USA Inc.

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I Ice ‘/l'x;oHS 0" :0" freescale‘” semiconductor
Freescale Semiconductor
Data Sheet: T
echnical Data
Document Number: MC9S08FL16
Rev. 4, 5/2015
©Freescale Semiconductor, Inc., 2009-2015. All rights reserved.
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
MC9S08FL16
32-Pin SDIP
1376-02
32-Pin LQFP
873A-03
Features:
8-Bit S08 Central Processor Unit (CPU)
Up to 20 MHz CPU at 4.5 V to 5.5 V across
temperature range of –40 °C to 85 °C
HC08 instruction set with added BGND instruction
Support for up to 32 interrupt/reset sources
On-Chip Memory
Up to 16 KB flash read/program/erase over full
operating voltage and temperature
Up to 1024-byte random-access memory (RAM)
Security circuitry to prevent unauthorized access
to RAM and flash contents
Power-Saving Modes
Two low power stop modes; reduced power wait
mode
Allows clocks to remain enabled to specific
peripherals in stop3 mode
Clock Source Options
Oscillator (XOSC) — Loop-control Pierce
oscillator; crystal or ceramic resonator range of
31.25 kHz to 39.0625 kHz or 1 MHz to 16 MHz
Internal Clock Source (ICS) — Internal clock
source module containing a
frequency-locked-loop (FLL) controlled by internal
or external reference; precision trimming of
internal reference allows 0.2% resolution and 2%
deviation over temperature and voltage; supports
bus frequencies up to 10 MHz
System Protection
Watchdog computer operating properly (COP)
reset with option to run from dedicated 1 kHz
internal clock source or bus clock
Low-voltage detectionwith reset or interrupt;
selectable trip points
Illegal opcode detection with reset
Illegal address detection with reset
Flash block protection
Development Support
Single-wire background debug interface
Breakpoint capability to allow single breakpoint
setting during in-circuit debugging (plus two more
breakpoints).
On-chip in-circuit emulator (ICE) debug module
containing two comparators and nine trigger
modes.
Peripherals
•I
PC — Interrupt priority controller to provide
hardware based nested interrupt mechanism
ADC — 12-channel, 8-bit resolution; 2.5 μs
conversion time; automatic compare function;
1.7 mV/°C temperature sensor; internal bandgap
reference channel; operation in stop; optional
hardware trigger; fully functional from 4.5 V to
5.5 V
TPM — One 4-channel and one 2-channel
timer/pulse-width modulators (TPM) modules;
selectable input capture, output compare, or
buffered edge- or center-aligned PWM on each
channel
MTIM16 — One 16-bit modulo timer with optional
prescaler
•SCI — One serial communications interface
module with optional 13-bit break; LIN extensions
Input/Output
30 GPIOs including 1 output-only pin and 1
input-only pin
Package Options
32-pin SDIP
32-pin LQFP
Document Number: MC9S08FL16
Rev. 4, 5/2015
MC9S08FL16 Series
Covers: MC9S08FL16 and
MC9S08FL8
MC9S08FL16 Series Data Sheet, Rev. 4
Freescale Semiconductor2
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will
be the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://freescale.com/
The following revision history table summarizes changes contained in this document.
Rev Date Description of Changes
1 March 18, 2009 Initial public release.
2 July 20, 2009 Updated Section 5.12, “EMC Performance. and corrected Figure 1 and Ta bl e 1 .
Corrected default trim value to 31.25 kHz.
3 Nov. 29, 2010 Updated Ta b l e 7 .
4 May, 2015 Corrected pin 12 of the Figure 3.
Related Documentation
Find the most current versions of all documents at: http://www.freescale.com
Reference Manual (MC9S08FL16RM)
Contains extensive product information including modes of operation, memory,
resets and interrupts, register definition, port pins, CPU, and all module
information.
1 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 System Clock Distribution. . . . . . . . . . . . . . . . . . . . . . . 4
3 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . 9
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.2 Parameter Classification . . . . . . . . . . . . . . . . . . . 9
5.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 9
5.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . 10
5.5 ESD Protection and Latch-Up Immunity . . . . . . 11
5.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 12
5.7 Supply Current Characteristics . . . . . . . . . . . . . 17
5.8 External Oscillator (XOSC) and ICS
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.9 AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . 21
5.9.1 Control Timing . . . . . . . . . . . . . . . . . . . . . 22
5.9.2 TPM Module Timing . . . . . . . . . . . . . . . . 23
5.10 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . 24
5.11 Flash Specifications. . . . . . . . . . . . . . . . . . . . . . 26
5.12 EMC Performance . . . . . . . . . . . . . . . . . . . . . . . 27
5.12.1Radiated Emissions . . . . . . . . . . . . . . . . . 27
6 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . 27
7 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.1 Mechanical Drawings. . . . . . . . . . . . . . . . . . . . . 28
Table of Contents
DD 55 RESET \RO VREFH REFL um SSA
MCU Block Diagram
MC9S08FL16 Series Data Sheet, Rev. 4
Freescale Semiconductor 3
1 MCU Block Diagram
The block diagram, Figure 1, shows the structure of MC9S08FL16 series MCU.
Figure 1. MC9S08FL16 Series Block Diagram
2-CH TIMER/PWM
MODULE (TPM2)
VOLTAGE REGULATOR
PORT A
20 MHz INTERNAL CLOCK
SOURCE (ICS)
ANALOG-TO-DIGITAL
CONVERTER (ADC)
12-CH 8-BIT
4-CH TIMER/PWM
MODULE (TPM1)
ADP[11:0]
VDD
VSS
RESET
SERIAL COMMUNICATIONS
INTERFACE (SCI)
TxD
PTA0/ADP0
PTA1/ADP1
PTA2/ADP2
PTA3/ADP3
PTA4/BKGD/MS
PTA5/IRQ/TCLK/RESET
PTA6/TPM2CH0
PTA7/TPM2CH1
TPM2CH[1:0]
IRQ
TPM1CH[3:0]
PORT B
PTB0/RxD/ADP4
PTB1/TxD/ADP5
PTB2/ADP6
PTB3/ADP7
PTB4/TPM1CH0
PTB5/TPM1CH1
PTB6/XTAL
PTB7/EXTAL
PORT C
PTC0/ADP8
PTC1/ADP9
PTC2/ADP10
PTC3/ADP11
PTC4
PTC5
PTC6
PTC7
PORT D
PTD0
PTD1
PTD2/TPM1CH2
PTD3/TPM1CH3
PTD4
PTD5
RxD
EXTERNAL OSCILLATOR
EXTAL
XTAL
USER FLASH
USER RAM
HCS08 CORE
CPU BDC
HCS08 SYSTEM CONTROL
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
COP
LVD
MC9S08FL16 — 1,024 BYTES
MC9S08FL16 — 16,384 BYTES
IRQ
ON-CHIP ICE AND
DEBUG MODUE (DBG)
MC9S08FL8 — 8,192 BYTES
MC9S08FL8 — 768 BYTES
VREFH
VREFL
VDDA
VSSA
NOTE
1. PTA4 is output only when used as port pin.
2. PTA5 is input only when used as port pin.
16-BIT MODULO TIMER
(MTIM16)
TCLK
INTERRUPT PRIORITY
SOURCE (XOSC)
CONTROLLER (IPC)
MC9S08FL16 Series Data Sheet, Rev. 4
System Clock Distribution
Freescale Semiconductor4
2 System Clock Distribution
MC9S08FL16 series use ICS module as clock sources. The ICS module can use internal or external clock
source as reference to provide up to 20 MHz CPU clock. The output of ICS module includes,
OSCOUT — XOSC output provides external reference clock to ADC.
ICSFFCLK — ICS fixed frequency clock reference (around 32.768 kHz) provides double of the
fixed lock signal to TPMs and MTIM16.
ICSOUT — ICS CPU clock provides double of the bus clock which is basic clock reference of
peripherals.
ICSLCLK — Alternate BDC clock provides debug signal to BDC module.
The TCLK pin is an extra external clock source. When TCLK is enabled, it can provide alternate clock
source to TPMs and MTIM16. The on-chip 1 kHz clock provides clock source of COP module.
Figure 2. System Clock Distribution Diagram
ICS
CPU
÷2
ICSOUT
ICSFFCLK
BUS CLOCK
BDC
TPM2TPM1
ICSLCLK
FIXED CLOCK (XCLK)
1 kHz
ADC
FLASH RAMSCI
XOSC
EXTAL XTAL
OSCOUT
TCLK
COP
IPC
MTIM16
÷2
jjjjjjjjjjjjjjj] O KCEKCKCCKKKCCCKC S E R
Pin Assignments
MC9S08FL16 Series Data Sheet, Rev. 4
Freescale Semiconductor 5
3 Pin Assignments
This section shows the pin assignments for the MC9S08FL16 series devices.
Figure 3. MC9S08FL16 Series 32-Pin SDIP Package
PTC5 1
2
3
4
5
6
7
8
9
10
32
31
30
29
28
27
26
25
24
23
PTC4
PTA5/IRQ/TCLK/RESET
PTD2/TPM1CH2
PTA4/BKGD/MS
PTD0
PTD1
VDD
VSS
PTB7/EXTAL
PTC6
PTC7
PTA0/ADP0
PTD5
PTA1/ADP1
PTA2/ADP2
PTA3/ADP3
PTA6/TPM2CH0
PTA7/TPM2CH1
PTB0/RxD/ADP4
11
12
13
14
15
16
22
21
20
19
18
17
PTB6/XTAL
PTB5/TPM1CH1
PTD3/TPM1CH3
PTB4/TPM1CH0
PTC3/ADP11
PTC2/ADP10
PTB1/TxD/ADP5
PTB2/ADP6
PTD4
PTB3/ADP7
PTC0/ADP8
PTC1/ADP9
3333333] memE flflflflflflflfl UUUUUUUU O CCCCCCCC
MC9S08FL16 Series Data Sheet, Rev. 4
Pin Assignments
Freescale Semiconductor6
Figure 4. MC9S08FL16 Series 32-Pin LQFP Package
Table 1. Pin Availability by Package Pin-Count
Pin Number <-- Lowest Priority --> Highest
32-SDIP 32-LQFP Port Pin I/O Alt 1 I/O Alt 2 I/O Alt 3 I/O
129PTC5I/O
230PTC4I/O
3 31 PTA5 I IRQ I TCLK I RESET I
4 32 PTD2 I/O TPM1CH2 I/O
5 1 PTA4 O BKGD I MS I
62PTD0I/O
73PTD1I/O
84 V
DD I
95 V
SS I
10 6 PTB7 I/O EXTAL I
11 7 PTB6 I/O XTAL O
12 8 PTB5 I/O TPM1CH1 I/O
13 9 PTD3 I/O TPM1CH3 I/O
14 10 PTB4 I/O TPM1CH0 I/O
15 11 PTC3 I/O ADP11 I
PTA4/BKGD/MS
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
PTD0
PTD1
VDD
VSS
PTB7/EXTAL
PTB6/XTAL
PTB5/TPM1CH1
PTA1/ADP1
PTA2/ADP2
PTA3/ADP3
PTA6/TPM2CH0
PTA7/TPM2CH1
PTB0/RxD/ADP4
PTB1/TxD/ADP5
PTB2/ADP6
PTD3/TPM1CH3
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
PTB4/TPM1CH0
PTC3/ADP11
PTC2/ADP10
PTC1/ADP9
PTC0/ADP8
PTB3/ADP7
PTD4
PTD2/TPM1CH2
PTA5/IRQ/TCLK/RESET
PTC4
PTC5
PTC6
PTC7
PTA0/ADP0
PTD5
1
9
Pin Assignments
MC9S08FL16 Series Data Sheet, Rev. 4
Freescale Semiconductor 7
NOTE
When an alternative function is first enabled, it is possible to get a spurious
edge to the module. User software must clear out any associated flags before
interrupts are enabled. Table 1 illustrates the priority if multiple modules are
enabled. The highest priority module will have control over the pin.
Selecting a higher priority pin function with a lower priority function
already enabled can cause spurious edges to the lower priority module.
Disable all modules that share a pin before enabling another module.
16 12 PTC2 I/O ADP10 I
17 13 PTC1 I/O ADP9 I
18 14 PTC0 I/O ADP8 I
19 15 PTB3 I/O ADP7 I
20 16 PTD4 I/O
21 17 PTB2 I/O ADP6 I
22 18 PTB1 I/O TxD I/O ADP5 I
23 19 PTB0 I/O RxD I ADP4 I
24 20 PTA7 I/O TPM2CH1 I/O
25 21 PTA6 I/O TPM2CH0 I/O
26 22 PTA3 I/O ADP3 I
27 23 PTA2 I/O ADP2 I
28 24 PTA1 I/O ADP1 I
29 25 PTD5 I/O
30 26 PTA0 I/O ADP0 I
31 27 PTC7 I/O
32 28 PTC6 I/O
Table 1. Pin Availability by Package Pin-Count (continued)
Pin Number <-- Lowest Priority --> Highest
32-SDIP 32-LQFP Port Pin I/O Alt 1 I/O Alt 2 I/O Alt 3 I/O
MC9S08FL16 Series Data Sheet, Rev. 4
Memory Map
Freescale Semiconductor8
4 Memory Map
Figure 5 shows the memory map for the MC9S08FL16 series. On-chip memory in the MC9S08FL16
series of MCUs consists of RAM, flash program memory for nonvolatile data storage, plus I/O and
control/status registers. The registers are divided into two groups:
Direct-page registers (0x0000 through 0x003F)
High-page registers (0x1800 through 0x187F)
Figure 5. MC9S08FL16 Series Memory Map
$0040
$0000
$003F
$033F
$0340
DIRECT PAGE REGISTERS
$1800
$187F
FLASH
$FFFF
8192 BYTES
UNIMPLEMENTED
$17FF
$1880
$DFFF
$E000
RAM 768 BYTES
HIGH PAGE REGISTERS
UNIMPLEMENTED
MC9S08FL8
$0040
$0000
$003F
$043F
$0440
DIRECT PAGE REGISTERS
$1800
$187F
FLASH
$FFFF
16384 BYTES
UNIMPLEMENTED
$17FF
$1880
$BFFF
$C000
RAM 1024 BYTES
HIGH PAGE REGISTERS
UNIMPLEMENTED
MC9S08FL16
Electrical Characteristics
MC9S08FL16 Series Data Sheet, Rev. 4
Freescale Semiconductor 9
5 Electrical Characteristics
5.1 Introduction
This section contains electrical and timing specifications for the MC9S08FL16 series of microcontrollers
available at the time of publication.
5.2 Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the
customer a better understanding, the following classification is used and the parameters are tagged
accordingly in the tables where appropriate:
NOTE
The classification is shown in the column labeled “C” in the parameter
tables where appropriate.
5.3 Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not
guaranteed. Stress beyond the limits specified in Table 3 may affect device reliability or cause permanent
damage to the device. For functional operating conditions, refer to the remaining tables in this section.
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD) or the programmable
pullup resistor associated with the pin is enabled.
Table 2. Parameter Classifications
PThose parameters are guaranteed during production testing on each individual device.
CThose parameters are achieved by the design characterization by measuring a statistically relevant
sample size across process variations.
T
Those parameters are achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted. All values shown in the typical column are within this
category.
DThose parameters are derived mainly from simulations.
MC9S08FL16 Series Data Sheet, Rev. 4
Electrical Characteristics
Freescale Semiconductor10
5.4 Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package
thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in
on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the
MCU design. To take PI/O into account in power calculations, determine the difference between actual pin
voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high
pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small.
The average chip-junction temperature (TJ) in °C can be obtained from:
Table 3. Absolute Maximum Ratings
Rating Symbol Value Unit
Supply voltage VDD –0.3 to 5.8 V
Maximum current into VDD IDD 120 mA
Digital input voltage VIn –0.3 to VDD +0.3 V
Instantaneous maximum current
Single pin limit (applies to all port pins)1, 2, 3
1Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp
voltages, then use the larger of the two resistance values.
2All functional non-supply pins, except for PTA5 are internally clamped to VSS and VDD.
3Power supply must maintain regulation within operating VDD range during instantaneous and
operating maximum current conditions. If positive injection current (VIn > VDD) is greater than
IDD, the injection current may flow out of VDD and could result in external power supply going
out of regulation. Ensure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if
no system clock is present, or if the clock rate is very low (which would reduce overall power
consumption).
ID±25 mA
Storage temperature range Tstg –55 to 150 °C
Table 4. Thermal Characteristics
Rating Symbol Value Unit
Operating temperature range
(packaged) TA
TL to TH
–40 to 85 °C
Thermal resistance
Single-layer board
32-pin SDIP θJA
60 °C/W
32-pin LQFP 85
Thermal resistance
Four-layer board
32-pin SDIP θJA
35 °C/W
32-pin LQFP 56
Electrical Characteristics
MC9S08FL16 Series Data Sheet, Rev. 4
Freescale Semiconductor 11
TJ = TA + (PD × θJA)Eqn. 1
where:
TA = Ambient temperature, °C
θJA = Package thermal resistance, junction-to-ambient, °C/W
PD = Pint + PI/O
Pint = IDD × VDD, Watts — chip internal power
PI/O = Power dissipation on input and output pins — user determined
For most applications, PI/O far much smaller than Pint and can be neglected. An approximate relationship
between PD and TJ (if PI/O is neglected) is:
PD = K ÷ (TJ + 273 °C) Eqn. 2
Solving Equation 1 and Equation 2 for K gives:
K = PD × (TA + 273 °C) + θJA × (PD)2Eqn. 3
where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring
PD (at equilibrium) for an known TA. Using this value of K, the values of PD and TJ can be obtained by
solving Equation 1 and Equation 2 iteratively for any value of TA.
5.5 ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early
CMOS circuits, normal handling precautions must be taken to avoid exposure to static discharge.
Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels
of static without suffering any permanent damage.
During the device qualification, ESD stresses were performed for the human body model (HBM) and the
charge device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless instructed otherwise in the device
specification.
Table 5. ESD and Latch-Up Test Conditions
Model Description Symbol Value Unit
Human
body
Series resistance R1 1500 Ω
Storage capacitance C 100 pF
Number of pulses per pin 3
Latch-up Minimum input voltage limit –2.5 V
Maximum input voltage limit 7.5 V
MC9S08FL16 Series Data Sheet, Rev. 4
Electrical Characteristics
Freescale Semiconductor12
5.6 DC Characteristics
This section includes information about power supply requirements and I/O pin characteristics.
Table 6. ESD and Latch-Up Protection Characteristics
No. Rating1
1Parameter is achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted.
Symbol Min Max Unit
1 Human body model (HBM) VHBM ±2000 — V
2 Charge device model (CDM) VCDM ±500 — V
3Latch-up current at TA = 85 °CI
LAT ±100 — mA
Table 7. DC Characteristics
Num C Characteristic Symbol Condition Min. Typical1Max. Unit
1 P Operating voltage 4.5 5.5 V
2
COutput high
voltage
All I/O pins,
low-drive strength VOH
ILoad = –2 mA VDD – 1.5
V
PAll I/O pins,
high-drive strength ILoad = –10 mA VDD – 1.5
3DOutput high
current Max total IOH for all ports IOHT ——100mA
4
COutput low
voltage
All I/O pins,
low-drive strength VOL
ILoad = 2 mA 1.5
V
PAll I/O pins,
high-drive strength ILoad = 10 mA 1.5
5D
Output low
current Max total IOL for all ports IOLT ——100mA
6P
Input high
voltage All digital inputs VIH —0.65 × VDD ——V
7P
Input low
voltage All digital inputs VIL ——0.35 × VDD V
8C
Input
hysteresis All digital inputs Vhys —0.06 × VDD ——mV
9P
Input
leakage
current
All input only pins
(per pin) |IIn|V
In = VDD or VSS —0.1 1μA
10 P
Hi-Z
(off-state)
leakage
current
All input/output
(per pin) |IOZ|V
In = VDD or VSS —0.1 1μA
11a C
Pullup,
pulldown
resistors
All digital inputs, when
enabled (all I/O pins other
than
PTA5/IRQ/TCLK/RESET)
RPU,
RPD
17.5 36.5 52.5 kΩ
11b C
Pullup,
pulldown
resistors
(PTA5/IRQ/TCLK/RESET)
RPU,
RPD
(Note2)
17.5 36.5 52.5 kΩ
M
Electrical Characteristics
MC9S08FL16 Series Data Sheet, Rev. 4
Freescale Semiconductor 13
12 C
DC injection
current 3, 4,
5
Single pin limit
IIC VIN < VSS, VIN > VDD
–0.2 0.2 mA
Total MCU limit, includes
sum of all stressed pins –5 5 mA
13 C Input capacitance, all pins CIn ——8pF
14 C RAM retention voltage VRAM ——0.61.0V
15 C POR re-arm voltage6VPOR 0.9 1.4 2.0 V
16 D POR re-arm time tPOR —10μs
17 P
Low-voltage detection threshold —
high range
VDD falling
VDD rising
VLVD 173.9
4.0
4.0
4.1
4.1
4.2
V
18
C
Low-voltage warning threshold —
high range 1
VDD falling
VDD rising
VLVW 3 4.5
4.6
4.6
4.7
4.7
4.8
V
P
Low-voltage warning threshold —
high range 0
VDD falling
VDD rising
VLVW 2 74.2
4.3
4.3
4.4
4.4
4.5
V
19 C Low-voltage inhibit reset/recover
hysteresis Vhys 100 — mV
20 C Bandgap voltage reference8VBG — 1.21 — V
1Typical values are measured at 25 °C. Characterized, not tested.
2The specified resistor value is the actual value internal to the device. The pullup or pulldown value may appear higher when
measured externally on the pin.
3All functional non-supply pins, except for PTA5 are internally clamped to VSS and VDD.
4Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values for positive and negative clamp voltages, then use the larger of the two values.
5Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current
conditions. If the positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could
result in external power supply going out of regulation. Ensure that external VDD load will shunt current greater than maximum
injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is
present, or if clock rate is very low (which would reduce overall power consumption).
6Maximum is highest voltage that POR is guaranteed.
7When VDD is in between the minimun of this parameter and 4.5 V, the CPU, RAM, LVD and flash are full functional, but the
performance of other modules may be reduced.
8Factory trimmed at VDD = 5.0 V, Temp = 25 °C
Table 7. DC Characteristics (continued)
Num C Characteristic Symbol Condition Min. Typical1Max. Unit
MC9S08FL16 Series Data Sheet, Rev. 4
Electrical Characteristics
Freescale Semiconductor14
Figure 6. Typical IOH Vs VDD–VOH (VDD = 5.0 V) (High Drive)
Typical IOH vs. VDD-VOH VDD = 5 V (High Drive)
0.000
5.000
10.000
15.000
20.000
25.000
30.000
35.000
40.000
45.000
50.000
0 0.3 0.5 0.8 1 1.3 2
V
mA
-40C
0C
25C
55C
85C
+$+++
Electrical Characteristics
MC9S08FL16 Series Data Sheet, Rev. 4
Freescale Semiconductor 15
Figure 7. Typical IOH Vs VDD–VOH (VDD = 5.0 V) (Low Drive)
Typical IOH vs. VDD-VOH VDD = 5V (Low Drive)
0.000
1.000
2.000
3.000
4.000
5.000
6.000
7.000
8.000
9.000
10.000
0 0.3 0.5 0.8 1 1.3 2
V
mA
-40C
0C
25C
55C
85C
5% / /
MC9S08FL16 Series Data Sheet, Rev. 4
Electrical Characteristics
Freescale Semiconductor16
Figure 8. Typical IOH Vs VOL (VDD = 5.0 V) (High Drive)
Typical IOL vs. VOL VDD = 5 V (High Drive)
0.000
5.000
10.000
15.000
20.000
25.000
30.000
35.000
40.000
45.000
50.000
0 0.3 0.5 0.8 1 1.3 2
V
mA
-40C
0C
25C
55C
85C
+HM
Electrical Characteristics
MC9S08FL16 Series Data Sheet, Rev. 4
Freescale Semiconductor 17
Figure 9. Typical IOH Vs VOL (VDD = 5.0 V) (Low Drive)
5.7 Supply Current Characteristics
This section includes information about power supply current in various operating modes.
Typical IOL vs. VOL VDD = 5V (Low Drive)
0.000
2.000
4.000
6.000
8.000
10.000
12.000
14.000
0 0.3 0.5 0.8 1 1.3 2
V
mA
-40C
0C
25C
55C
85C
MC9S08FL16 Series Data Sheet, Rev. 4
Electrical Characteristics
Freescale Semiconductor18
Table 8. Supply Current Characteristics
Num C Parameter Symbol Bus
Freq
VDD
(V) Typical1
1Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value.
Max Unit Temp
1
P
Run supply current
FEI mode, all modules off RIDD
10 MHz
5
5.66
5.75
5.80
mA
–40 °C
25 °C
85 °C
–40 °C
25 °C
85 °C
P1 MHz
1.61
1.65
1.78
2
C
Wait mode supply current
FEI mode, all modules off WIDD
10 MHz
5
2.79
2.86
2.88
μA
–40 °C
25 °C
85 °C
–40 °C
25 °C
85 °C
C1 MHz
1.05
1.06
1.06
3
C Stop2 mode supply current S2IDD 5 1.06 μA 40 to 85 °C
CStop3 mode supply current
no clocks active S3IDD 5 1.17 μA –40 to 85 °C
4 C ADC adder to stop3 5 163.88 μA 25 °C
5C
ICS adder to stop3
EREFSTEN = 1 ——51.25μA 25 °C
6 C LVD adder to stop3 5 161.3 μA 25 °C
Electrical Characteristics
MC9S08FL16 Series Data Sheet, Rev. 4
Freescale Semiconductor 19
5.8 External Oscillator (XOSC) and ICS Characteristics
Refer to Figure 11 for crystal or resonator circuits.
Table 9. XOSC and ICS Specifications (Temperature Range = –40 to 85 °C Ambient)
Num C Characteristic Symbol Min Typical1Max Unit
1C
Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1)
Low range (RANGE = 0)
High range (RANGE = 1) FEE or FBE mode2
High range (RANGE = 1), high gain (HGO = 1), FBELP
mode
High range (RANGE = 1), low power (HGO = 0), FBELP
mode
flo
fhi
fhi
fhi
32
1
1
1
38.4
5
16
8
kHz
MHz
MHz
MHz
2 D Load capacitors C1
C2See Note3
3D
Feedback resistor
Low range (32 kHz to 38.4 kHz)
High range (1 MHz to 16 MHz)
RF10
1
MΩ
MΩ
4D
Series resistor — Low range
Low gain (HGO = 0)
High gain (HGO = 1)
RS
0
100
kΩ
5D
Series resistor — High range
Low Gain (HGO = 0)
High Gain (HGO = 1)
8 MHz
4 MHz
1 MHz
RS
0
0
0
0
10
20
kΩ
6C
Crystal startup time4, 5
Low range, low power
Low range, high power
High range, low power
High range, high power
tCSTL
tCSTH
200
400
5
15
ms
7 T Internal reference start-up time tIRST 60 100 μs
8D
Square wave input clock frequency (EREFS = 0, ERCLKEN
= 1)
FEE or FBE mode2
FBELP mode
fextal 0.03125
0
5
20
MHz
MHz
9 P Average internal reference frequency — trimmed fint_t 31.25 — kHz
10 P DCO output frequency range — trimmed6
Low range (DRS = 00) fdco_t 16 20 MHz
11 C
Total deviation of DCO output from trimmed frequency4
Over full voltage and temperature range
Over fixed voltage and temperature range of 0 to 70°C
Δfdco_t –1.0 to 0.5
±0.5
± 2
± 1
%fdco
12 C FLL acquisition time4,7 tAcquire 1ms
MC9S08FL16 Series Data Sheet, Rev. 4
Electrical Characteristics
Freescale Semiconductor20
Figure 10. Typical Crystal or Resonator Circuit
13 C Long term jitter of DCO output clock (averaged over 2 ms
interval) 8CJitter 0.02 0.2 %fdco
1Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value.
2When ICS is configured for FEE or FBE mode, input clock source must be divisible using RDIV to within the range of
31.25 kHz to 39.0625 kHz.
3See crystal or resonator manufacturer’s recommendation.
4This parameter is characterized and not tested on each device.
5Proper PC board layout procedures must be followed to achieve specifications.
6The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device.
7This specification applies to any time the FLL reference source or reference divider is changed, trim value changed, DMX32
bit is changed, DRS bit is changed, or changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If
a crystal/resonator is being used as the reference, this specification assumes it is already running.
8Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBus.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for
a given interval.
Table 9. XOSC and ICS Specifications (Temperature Range = –40 to 85 °C Ambient) (continued)
Num C Characteristic Symbol Min Typical1Max Unit
XOSC
EXTAL XTAL
Crystal or Resonator
R
S
C2
RF
C1
Electrical Characteristics
MC9S08FL16 Series Data Sheet, Rev. 4
Freescale Semiconductor 21
Figure 11. Deviation of DCO Output from Trimmed Frequency (20 MHz, 5.0 V)
5.9 AC Characteristics
This section describes timing characteristics for each peripheral system.
-2.00%
-1.50%
-1.00%
-0.50%
0.00%
0.50%
1.00%
-60 -40 -20 0 20 40 60 80 100 120
Temperature
Deviation (%)
MC9S08FL16 Series Data Sheet, Rev. 4
Electrical Characteristics
Freescale Semiconductor22
5.9.1 Control Timing
Figure 12. Reset Timing
Table 10. Control Timing
Num C Rating Symbol Min Typical1
1Typical values are based on characterization data at VDD = 5.0 V, 25 °C unless otherwise stated.
Max Unit
1D
Bus frequency (tcyc = 1/fBus)f
Bus dc 10 MHz
2 D Internal low power oscillator period tLPO 700 1300 μs
3D
External reset pulse width2
2This is the shortest pulse that is guaranteed to be recognized as a reset pin request.
textrst 100 — ns
4 D Reset low drive trstdrv 34 × tcyc ——ns
5D
BKGD/MS setup time after issuing background debug
force reset to enter user or BDM modes tMSSU 500 — ns
6D
BKGD/MS hold time after issuing background debug
force reset to enter user or BDM modes3
3To enter BDM mode following a POR, BKGD/MS must be held low during the power-up and for a hold time of tMSH after VDD
rises above VLVD.
tMSH 100 μs
7D
IRQ pulse width
Asynchronous path2
Synchronous path4
4This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized.
tILIH, tIHIL 100
1.5 × tcyc
ns
8D
Keyboard interrupt pulse width
Asynchronous path2
Synchronous path4tILIH, tIHIL
100
1.5 × tcyc
ns
9C
Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)5
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
5Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40 °C to 85 °C.
tRise, tFall
16
23
ns
Port rise and fall time —
High output drive (PTxDS = 1) (load = 50 pF)5
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
tRise, tFall
5
9
ns
textrst
RESET PIN
Electrical Characteristics
MC9S08FL16 Series Data Sheet, Rev. 4
Freescale Semiconductor 23
Figure 13. IRQ/KBIPx Timing
5.9.2 TPM Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that
can be used as the optional external source to the timer counter. These synchronizers operate from the
current bus rate clock.
Figure 14. Timer External Clock
Figure 15. Timer Input Capture Pulse
Table 11. TPM Input Timing
No. C Function Symbol Min Max Unit
1 D External clock frequency fTCLK 0f
Bus/4 Hz
2 D External clock period tTCLK 4—t
cyc
3 D External clock high time tclkh 1.5 — tcyc
4 D External clock low time tclkl 1.5 — tcyc
5 D Input capture pulse width tICPW 1.5 — tcyc
tIHIL
KBIPx
tILIH
IRQ/KBIPx
tTCLK
tclkh
tclkl
TCLK
tICPW
TPMCHn
tICPW
TPMCHn
S‘MPLIF‘ED r\\\\\\\\\ \ \\\\\\\\ \\\\\\\\\\ \\\\\\\\\\
MC9S08FL16 Series Data Sheet, Rev. 4
Electrical Characteristics
Freescale Semiconductor24
5.10 ADC Characteristics
Figure 16. ADC Input Impedance Equivalency Diagram
Table 12. 8-Bit ADC Operating Conditions
Characteristic Conditions Symb Min Typical1
1Typical values assume VDDA = 5.0 V, Temp = 25 °C, fADCK= 1.0 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
Max Unit Comment
Supply voltage Absolute VDDA 4.5 — 5.5 V
Delta to VDD (VDD – VDDA)2
2DC potential difference.
ΔVDDA –100 0 100 mV
Ground voltage Delta to VSS (VSS – VSSA)2ΔVSSA –100 0 100 mV
Input voltage VADIN VREFL —V
REFH V
Input
capacitance —C
ADIN —4.55.5pF
Input resistance RADIN —3 5kΩ
Analog source
resistance 8-bit mode (all valid fADCK)R
AS ——10kΩExternal to MCU
ADC conversion
clock frequency
High speed (ADLPC = 0) fADCK
0.4 8.0 MHz
Low power (ADLPC = 1) 0.4 4.0
+
+
V
AS
R
AS
C
AS
V
ADIN
Z
AS
Pad
leakage
due to
input
protection
Z
ADIN
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
R
ADIN
ADC SAR
ENGINE
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
INPUT PIN
R
ADIN
C
ADIN
INPUT PIN
R
ADIN
INPUT PIN
R
ADIN
Electrical Characteristics
MC9S08FL16 Series Data Sheet, Rev. 4
Freescale Semiconductor 25
Table 13. 8-Bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA)
C Characteristic Conditions Symb Min Typ1Max Unit Comment
T
Supply Current
ADLPC=1
ADLSMP=1
ADCO=1
IDDA —133—μA
T
Supply Current
ADLPC=1
ADLSMP=0
ADCO=1
IDDA —218—μA
T
Supply Current
ADLPC=0
ADLSMP=1
ADCO=1
IDDA —327—μA
P
Supply Current
ADLPC=0
ADLSMP=0
ADCO=1
IDDA —0.582 1 mA
C Supply Current Stop, Reset, Module Off IDDA —0.011 1 μA
P
ADC
Asynchronous
Clock Source
High Speed (ADLPC = 0)
fADACK
23.35
MHz tADACK =
1/fADACK
Low Power (ADLPC = 1) 1.25 2 3.3
P
Conversion
Time (Including
sample time)
Short Sample (ADLSMP = 0)
tADC
—20—
ADCK
cycles See reference
manual for
conversion
time variances
Long Sample (ADLSMP = 1) 40
P Sample Time
Short Sample (ADLSMP = 0)
tADS
—3.5—
ADCK
cycles
Long Sample (ADLSMP = 1) 23.5
DTemp Sensor
Slope
–40°C– 25°C
m
—3.266—
mV/°C
25°C– 125°C—3.638
DTemp Sensor
Voltage 25 °CV
TEMP25 —1.396— mV
P
Tot a l
Unadjusted
Error
8-bit mode ETUE ±0.5 ±1.0 LSB2Includes
quantization
PDifferential
Non-Linearity 8-bit mode3DNL ±0.3 ±0.5 LSB2
TIntegral
Non-Linearity 8-bit mode INL ±0.3 ±0.5 LSB2
PZero-Scale
Error 8-bit mode EZS ±0.5 ±0.5 LSB2VADIN = VSSA
TFull-Scale
Error 8-bit mode EFS ±0.5 ±0.5 LSB2VADIN = VDDA
MC9S08FL16 Series Data Sheet, Rev. 4
Electrical Characteristics
Freescale Semiconductor26
5.11 Flash Specifications
This section provides details about program/erase times and program-erase endurance for the flash
memory.
Program and erase operations do not require any special power sources other than the normal VDD supply.
For more detailed information about program/erase operations, see the Memory section.
DQuantization
Error 8-bit mode EQ——±0.5 LSB2
DInput Leakage
Error 8-bit mode EIL ±0.1 ±1LSB2Pad leakage2
* RAS
1Typical values assume VDDA = 5.0 V, Temp = 25 °C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
2Based on input pad leakage current. Refer to pad electricals.
Table 14. Flash Characteristics
C Characteristic Symbol Min Typical Max Unit
DSupply voltage for program/erase
–40 °C to 85 °CV
prog/erase 4.5 5.5 V
D Supply voltage for read operation VRead 4.5 — 5.5 V
D Internal FCLK frequency1
1 The frequency of this clock is controlled by a software setting.
fFCLK 150 200 kHz
D Internal FCLK period (1/FCLK) tFcyc 5—6.67μs
P Byte program time (random location)2tprog 9t
Fcyc
P Byte program time (burst mode)2tBurst 4t
Fcyc
P Page erase time2
2These values are hardware state machine controlled. User code does not need to count cycles. This information supplied
for calculating approximate time to program and erase.
tPage 4000 tFcyc
P Mass erase time2tMass 20,000 tFcyc
Byte program current3
3The program and erase currents are additional to the standard run IDD. These values are measured at room temperatures
with VDD = 5.0 V, bus frequency = 4.0 MHz.
RIDDBP —4—mA
Page erase current3RIDDPE —6—mA
C
Program/erase endurance4
TL to TH = –40 °C to 85 °C
T = 25 °C
4Typical endurance for flash was evaluated for this product family on the 9S12Dx64. For additional information on how
Freescale defines typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile
Memory.
— 10,000 — cycles
C Data retention5tD_ret 5 100 — years
Table 13. 8-Bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
C Characteristic Conditions Symb Min Typ1Max Unit Comment
Ordering Information
MC9S08FL16 Series Data Sheet, Rev. 4
Freescale Semiconductor 27
5.12 EMC Performance
Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the
MCU resides. Board design and layout, circuit topology choices, location and characteristics of external
components as well as MCU software operation all play a significant role in EMC performance. The
system designer should consult Freescale applications notes such as AN2321, AN1050, AN1263,
AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC performance.
5.12.1 Radiated Emissions
Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell
method in accordance with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed
with the microcontroller installed on a custom EMC evaluation board while running specialized EMC test
software. The radiated emissions from the microcontroller are measured in a TEM cell in two package
orientations (the North and East).
The maximum radiated RF emissions of the tested configuration in all orientations are less than or equal
to the reported emissions levels.
6 Ordering Information
This section contains ordering information for MC9S08FL16 series devices. See below for an example of
the device numbering system.
5Typical data retention values are based on intrinsic capability of the technology measured at high temperature and
de-rated to 25°C using the Arrhenius equation. For additional information on how Freescale defines typical data retention,
please refer to Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory.
Table 15. Radiated Emissions, Electric Field
Parameter Symbol Conditions Frequency fOSC/fBUS
Level1
(Max)
1Data based on qualification test results.
Unit
Radiated emissions,
electric field
VRE_TEM VDD = 5.0 V
TA = 25 οC
package type
32-pin LQFP
0.15 – 50 MHz 4 MHz crystal
19 MHz bus
9dBμV
50 – 150 MHz 5
150 – 500 MHz 2
500 – 1000 MHz 1
IEC Level N
SAE Level 1
Table 16. Device Numbering System
Device Number1Memory
Available Packages2
FLASH RAM
MC9S08FL16 16 KB 1024 32 SDIP
32 LQFP
MC9S08FL8 8 KB 768
MC9S08FL16 Series Data Sheet, Rev. 4
Package Information
Freescale Semiconductor28
Example of the device numbering system:
7 Package Information
7.1 Mechanical Drawings
The following pages are mechanical drawings for the packages described in Table 17.
1See the reference manual, MC9S08FL16 Series Reference Manual, for a complete
description of modules included on each device.
2See Table 17 for package information.
Table 17. Package Descriptions
Pin Count Package Type Abbreviation Designator Case No. Document No.
32 Low Quad Flat Package LQFP LC 873A-03 98ASH70029A
32 Shrink Dual In-line Package SDIP BM 1376-02 98ASA99330D
MC
Temperature range
Family
Memory
Status
Core
(C =–40 °C to 85 °C)
(9 = Flash-based)
9S08 XX
(MC = Fully Qualified) Package designator (see Ta b l e 1 7 )
Approximate flash size in KB
FL 16 C
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© 2009-2015 Freescale Semiconductor, Inc.
Document Number MC9S08FL16
Revision 4, 5/2015

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