VIPER25 Datasheet by STMicroelectronics

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July 2010 Doc ID 15585 Rev 4 1/40
40
VIPER25
Off-line high voltage converters
Features
800 V avalanche rugged power section
Quasi-resonant (QR) control for valley
switching operation
Standby power < 50 mW at 265 Vac
Limiting current with adjustable set point
Adjustable and accurate overvoltage
protection
On-board soft-start
Safe auto-restart after a fault condition
Hysteretic thermal shutdown
Applications
Adapters for PDA, camcorders, shavers,
cellular phones, cordless phones, videogames
Auxiliary power supply for LCD/PDP TV,
monitors, audio systems, computer, industrial
systems, LED driver, No el-cap LED driver,
utility power meter
SMPS for set-top boxes, DVD players and
recorders, white goods
Description
The device is an off-line converter with an 800 V
rugged power section, a PWM control, double
levels of overcurrent protection, overvoltage and
overload protections, hysteretic thermal
protection, soft-start and safe auto-restart after
any fault condition removal. Burst mode operation
and device very low consumption helps to meet
the standby energy saving regulations. The quasi-
resonant feature reduces EMI filter cost. Brown-
out and brown-in function protects the switch
mode power supply when the rectified input
voltage level is below the normal minimum level
specified for the system. The high voltage start-up
circuit is embedded in the device.
Figure 1. Typical topology
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Table 1. Device summary
Order codes Package Packaging
VIPER25LN / VIPER25HN DIP-7 Tube
VIPER25HD / VIPER25LD SO16 narrow Tube
VIPER25HDTR / VIPER25LDTR Tape and reel
www.st.com
Contents VIPER25
2/40 Doc ID 15585 Rev 4
Contents
1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Typical power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5 Typical electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6 Typical circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7 Operation description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.1 Power section and gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.2 High voltage startup generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.3 Power-up description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.4 Power-down description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.5 Auto-restart description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.6 Quasi-resonant operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.7 Frequency foldback function and valley skipping mode . . . . . . . . . . . . . . 22
7.8 Double blanking time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.9 Starter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.10 Current limit set point and feed-forward option . . . . . . . . . . . . . . . . . . . . . 24
7.11 Overvoltage protection (OVP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.12 Summary on ZCD pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.13 Feedback and overload protection (OLP) . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.14 Burst-mode operation at no load or very light load . . . . . . . . . . . . . . . . . . 32
7.15 Brown-out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.16 2nd level over current protection and hiccup mode . . . . . . . . . . . . . . . . . 34
VIPER25 Contents
Doc ID 15585 Rev 4 3/40
8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Block diagram VIPER25
4/40 Doc ID 15585 Rev 4
1 Block diagram
Figure 2. Block diagram
2 Typical power
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Table 2. Typical power
Part number
230 VAC 85-265 VAC
Adapter(1)
1. Typical continuous power in non ventilated enclosed adapter measured at 50 °C ambient.
Open frame(2)
2. Maximum practical continuous power in an open frame design at 50 °C ambient, with adequate heat
sinking.
Adapter(1) Open frame(2)
VIPER25 18 W 20 W 10 W 12 W
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VIPER25 Pin settings
Doc ID 15585 Rev 4 5/40
3 Pin settings
Figure 3. Connection diagram (top view)
Note: The copper area for heat dissipation has to be designed under the DRAIN pins.
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Table 3. Pin description
Pin n.
Name Function
DIP-7 SO16
1 1...2 GND This pin represents the device ground and the source of the power section.
-4N.A.
Not available for user. It can be connected to GND (pins 1-2) or left not
connected.
25VDD
Supply voltage of the control section. This pin also provides the charging
current of the external capacitor during power-up.
36ZCD
This is a multifunction pin.
1. Input for the zero current detection circuit for transformer demagnetization
sensing. (i.e. RLIM, RFF
, ROVP and DOVP
, Figure 32)
2. User defined drain current limit set-point and voltage feed forward.The
resistor, RLIM, connected between ZCD pin and GND causes the current
IZCD and then it limits the static maximum drain current.
3. The resistor RFF
, between ZCD pin and the auxiliary winding, performs
the feed-forward operation and then the drain current limitation changes
according to the converter input voltage.
4. Output overvoltage protection. A voltage exceeding VOVP threshold,
(see Table 8 on page 8), shuts the IC down reducing the device
consumption. This function is strobed and digitally filtered for high noise
immunity.
47FB
Control input for duty cycle control. Internal current generator provides bias
current for loop regulation. A voltage below the threshold VFBbm activates
the burst-mode operation. A level close to the threshold VFBlin means that
we are approaching the cycle-by-cycle over-current set point.
58BR
Brownout protection input with hysteresis. A voltage below the threshold
VBRth shuts down (not latch) the device and lowers the power consumption.
Device operation restarts as the voltage exceeds the threshold VBRth +
VBRhyst. It can be connected to ground when not used.
7,8 13...16 DRAIN
High voltage drain pin. The built-in high voltage switched start-up bias
current is drawn from this pin too. Pins connected to the metal frame to
facilitate heat dissipation.
Electrical data VIPER25
6/40 Doc ID 15585 Rev 4
4 Electrical data
4.1 Maximum ratings
4.2 Thermal data
Table 4. Absolute maximum ratings
Symbol Pin
(DIP7) Parameter
Value
Unit
Min. Max.
VDRAIN 7, 8 Drain-to-source (ground) voltage 800 V
EAV 7, 8 Repetitive avalanche energy
(limited by TJ = 150 °C) 5mJ
IAR 7, 8 Repetitive avalanche current
(limited by TJ = 150 °C) 1.5 A
IDRAIN 7, 8 Pulse drain current (limited by TJ = 150 °C) 3 A
VZCD 3 Control input pin voltage (with IZCD = 1 mA) -0.3 Self limited V
VFB 4 Feedback voltage -0.3 5.5 V
VBR 5 Brown-out input pin voltage (with IBR = 0.5 mA) -0.3 Self limited V
VDD 2 Supply voltage (IDD = 25 mA) -0.3 Self limited V
IDD 2 Input current 25 mA
PTOT
Power dissipation at TA < 40 °C (DIP-7) 1 W
Power dissipation at TA < 60 °C (SO16N) 1.5 W
TJOperating junction temperature range -40 150 °C
TSTG Storage temperature -55 150 °C
Table 5. Thermal data
Symbol Parameter Max. value
SO16N
Max. value
DIP7 Unit
RthJP
Thermal resistance junction pin
(Dissipated power = 1 W) 25 35 °C/W
RthJA
Thermal resistance junction ambient
(Dissipated power = 1 W) 60 100 °C/W
RthJA
Thermal resistance junction ambient (1)
(Dissipated power = 1 W)
1. When mounted on a standard single side FR4 board with 100 mm2 (0.155 sq in) of Cu (35 μm thick)
50 80 °C/W
VIPER25 Electrical data
Doc ID 15585 Rev 4 7/40
4.3 Electrical characteristics
(TJ = -25 to 125 °C, VDD = 14 V (a); unless otherwise specified)
a. Adjust VDD above VDDon start-up threshold before settings to 14 V.
Table 6. Power section
Symbol Parameter Test condition Min. Typ. Max. Unit
VBVDSS Break-down voltage IDRAIN = 1 mA, VFB = GND
TJ = 25 °C 800 V
IOFF OFF state drain current VDRAIN = max rating,
VFB = GND 60 μA
RDS(on)
Drain-source on state
resistance
IDRAIN = 0.2 A, VFB = 3 V,
VBR = GND, TJ = 25 °C 7Ω
IDRAIN = 0.2 A, VFB = 3 V,
VBR = GND, TJ = 125 °C 14 Ω
COSS
Effective (energy related)
output capacitance VDRAIN = 0 to 640 V 40 pF
Table 7. Supply section
Symbol Parameter Test condition Min. Typ. Max. Unit
Voltage
VDRAIN_START Drain-source start voltage 60 80 100 V
IDDch Start-up charging current
VDRAIN = 120 V,
VBR = GND, VFB = GND,
VDD = 4 V
-2 -3 -4 mA
VDRAIN = 120 V,
VBR = GND, VFB = GND,
VDD = 4 V after fault.
-0.4 -0.6 -0.8 mA
VDD Operating voltage range After turn-on 8.5 23.5 V
VDDclamp VDD clamp voltage IDD = 20 mA 23.5 V
VDDon VDD start-up threshold VDRAIN = 120 V,
VBR = GND, VFB = GND
13 14 15 V
VDDoff
VDD under voltage
shutdown threshold 7.588.5V
VDD(RESTART)
VDD restart voltage
threshold
VDRAIN = 120 V,
VBR = GND, VFB = GND 44.55 V
Current
IDD0
Operating supply current,
not switching
VFB = GND, FSW = 0 k H z ,
VBR = GND, VDD = 10 V 0.9 mA
IDD1
Operating supply current,
switching VDRAIN = 120 V, 3.5 mA
IDD_FAULT
Operating supply current,
with protection tripping 400 μA
IDD_OFF
Operating supply current
with VDD < VDDoff
VDD = 7 V 270 μA
Electrical data VIPER25
8/40 Doc ID 15585 Rev 4
Table 8. Controller section
Symbol Parameter Test condition Min. Typ. Max. Unit
Feedback pin
VFBolp Over load shutdown threshold 4.5 4.8 5.2 V
VFBlin Linear dynamics upper limit 3.2 3.3 3.4 V
VFBbm Burst mode threshold Voltage falling 0.6 V
VFBbmhys Burst mode hysteresis Voltage rising 100 mV
IFB Feedback sourced current VFB = 0.3 V -150 -200 -280 uA
3.3 V < VFB < 4.8 V -3 uA
RFB(DYN) Dynamic resistance VFB < 3.3 V 14 19 kΩ
HFB ΔVFB / ΔID26V/A
ZCD pin
VZCDCLh Upper clamp voltage IZCD = 1 mA 5 5.5 6 V
VZCDAth Arming voltage threshold Positive-going edge 0.8 V
VZCDTth Triggering voltage threshold Negative-going edge 0.6 V
IZCD Internal pull-up -10 µA
TBLANK
Turn-on inhibit time after
MOSFET’s turn-off
VZCD < 1 V 6.3 µs
VZCD >1 V 2.5 µs
Current limitation
IDlim Max drain current limitation
VFB = 4 V,
IZCD = -10 µA
TJ = 25 °C
0.66 0.7 0.74 A
tSS Soft start time VIPER25L 3.5 ms
VIPER25H 4.2 ms
tSU Start up time VIPER25L 7.5 15 ms
VIPER25H 9.5 18 ms
TON_MIN Minimum turn ON time 220 400 480 ns
td Propagation delay 100 ns
tLEB Leading edge blanking 300 ns
ID_BM
Peak drain current during
burst mode VFB = 0.6 V 160 mA
Overcurrent protection (2nd OCP)
IDMAX Second overcurrent threshold 1.2 A
Overvoltage protection
VOVP
Overvoltage protection
threshold 3.8 4.2 4.6 V
TSTROBE
Overvoltage protection strobe
time 2.2 μs
VIPER25 Electrical data
Doc ID 15585 Rev 4 9/40
Oscillator section
FOSClim
Internal frequency limit VIPER25L 122 136 150 kHz
Internal frequency limit VIPER25H 200 225 250 kHz
FSTARTER Starter frequency
VFB=1 V,
VZCD<VZCDT th
t<tSU
1/4
FOSClim
kHz
VFB=1 V,
VZCD<VZCDT th
t>tSU
1/8
FOSClim
kHz
FOSCmin
VFB = 1 V,
VZCD > VZCDA_th
1/64
FOSClim
kHz
Brown-out protection
VBRth Brown-out threshold Voltage falling 0.41 0.45 0.49 V
VBRhyst
Voltage hysteresis above
VBRth
Violate rising 50 mV
IBRhyst Current hysteresis 7 12 μA
VBRclamp Clamp voltage IBR = 250 µA 3 V
VDIS Brown-out disable voltage 50 150 mV
Thermal shutdown
TSD
Thermal shutdown
temperature 150 160 °C
THYST Thermal shutdown hysteresis 30 °C
Table 8. Controller section (continued)
Symbol Parameter Test condition Min. Typ. Max. Unit
Electrical data VIPER25
10/40 Doc ID 15585 Rev 4
Figure 4. Minimum turn-on time test circuit
Figure 5. Brown-out threshold test circuits
Figure 6. OVP threshold test circuits
Note: Adjust VDD above VDDon start-up threshold before settings to 14 V
14 V
3.5 V
50 Ω
30 V
GND
ZCD
FB
VDD
DRAIN
BR
DRAIN
VDRAIN
IDRAIN
IDlim
Time
Time
TONmin
90 %
10 %
GND
ZCD
FB
VDD
DRAIN
BR
DRAIN
14 V
2 V
10 kΩ
30 V
IBRhyst
VBRth+VBRhyst
VBRth
VBR
IBR
VDIS
IBRhyst
IDRAIN
Time
Time
Time
GND
ZCD
FB
VDD
DRAIN
BR
DRAIN
VOVP
VZCD
VDRAIN
14 V
2 V
10 kΩ
30 V
Time
Time
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VIPER25 Typical electrical characteristics
Doc ID 15585 Rev 4 11/40
5 Typical electrical characteristics
Figure 7. Current limit vs TJ Figure 8. Drain start voltage vs TJ
Figure 9. HFB vs TJFigure 10. Brown-out threshold vs TJ
Figure 11. Brown-out hysteresis vs TJFigure 12. Brown-out hysteresis current
vs TJ
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Typical electrical characteristics VIPER25
12/40 Doc ID 15585 Rev 4
Figure 13. Operating supply current
(no switching) vs TJ
Figure 14. Operating supply current
(switching) vs TJ
Figure 15. VZCD vs IZCD Figure 16. Current limit vs IZCD
Figure 17. Power MOSFET on-resistance
vs TJ
Figure 18. Power MOSFET break down
voltage vs TJ
300
350
400
450
500
0.0 50.0 100.0 150.0 200.0 250.0
IZCD (μA)
VZCD (mV)
mm; umc m Doc ID 15585 Flev A
VIPER25 Typical electrical characteristics
Doc ID 15585 Rev 4 13/40
Figure 19. Thermal shutdown
T
J
V
DD
I
DRAIN
V
DDon
time
V
DDoff
V
DD(RESTART)
T
SD
time
time
T
SD
-T
HYST
Shut down after over temperature
Normal operation Normal operation
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Typical circuits VIPER25
14/40 Doc ID 15585 Rev 4
6 Typical circuits
Figure 20. Min-features QR flyback application
Figure 21. Full-features QR flyback application
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VIPER25 Operation description
Doc ID 15585 Rev 4 15/40
7 Operation description
VIPER25 is a high-performance low-voltage PWM controller IC with an 800 V, avalanche
rugged power section.
The controller includes the current-mode PWM logic and the ZCD (zero current detect)
circuit for QR operation, the start-up circuitry with soft-start feature, an oscillator for
frequency foldback function, the current limit circuit with adjustable set point, the second
overcurrent circuit, the burst mode management circuit, the brown-out circuit, the UVLO
circuit, the auto-restart circuit and the thermal shutdown circuit.
The current limit set-point is set by the ZCD pin. The burst mode operation guaranties high
performance in the stand-by mode and helps in the energy saving norm accomplishment
All the fault protections are built in auto-restart mode with very low repetition rate to prevent
IC's over heating.
7.1 Power section and gate driver
The power section is implemented with an avalanche ruggedness N-channel MOSFET,
which guarantees safe operation within the specified energy rating as well as high dv/dt
capability. The power section has a BVDSS of 800 V min. and a typical RDS(on)
of 7 Ω at 25 °C.
The integrated SenseFET structure allows a virtually loss-less current sensing.
The gate driver is designed to supply a controlled gate current during both turn-on and turn-
off in order to minimize common mode EMI. Under UVLO conditions an internal pull-down
circuit holds the gate low in order to ensure that the Power section cannot be turned on
accidentally.
7.2 High voltage startup generator
The HV current generator is supplied through the DRAIN pin and it is enabled only if the
input bulk capacitor voltage is higher than VDRAIN_START threshold, reported on Table 7 on
page 7. When the HV current generator is ON, the IDDch current (see Table 7 on page 7) is
delivered to the capacitor on the VDD pin. In case of Auto-restart mode after a fault event,
the IDDch current is reduced to 0.6 mA, in order to have a slow duty cycle during the restart
phase.
Operation description VIPER25
16/40 Doc ID 15585 Rev 4
7.3 Power-up description
If the input voltage rises up till the device start level, VDRAIN_START, the VDD voltage begins to
grow due to the IDDch current (see Table 7 on page 7) coming from the internal high voltage
start-up circuit. If the VDD voltage reaches the VDDon threshold (See Table 7 on page 7) the
power MOSFET starts switching and the HV current generator is turned OFF, see Figure 23
on page 17.
The IC is powered by the energy stored in the capacitor on the VDD pin, CVDD, until when
the self-supply circuit (typically an auxiliary winding of the transformer and a steering diode)
develops a voltage high enough to sustain the operation.
CVDD capacitor must be sized enough to avoid fast discharge and keep the needed voltage
value higher than VDDoff threshold. In fact, a too low capacitance value could terminate the
switching operation before the controller receives any energy from the auxiliary winding.
The following formula can be used for the VDD capacitor calculation:
Equation 1
The tSSaux is the time needed for the steady state of the auxiliary voltage. This time is
estimated by applicator according to the output stage configurations (transformer, output
capacitances, etc.).
During normal operation, the power MOSFET is switched ON immediately after transformer
demagnetization, detected by the VIPER25, through the voltage VZCD sensed on the ZCD
pin. At power up the initial output voltage is zero and then the voltage VZCD is not high
enough to correctly arm the internal ZCD circuit. In this case, the power MOSFET is turned
ON with a fixed frequency determined by the internal oscillator. This fixed switching
frequency is FSTARTER (see Table 8 on page 8). As soon as the voltage on ZCD pin is able
to arm the ZCD circuit (i.e. its positive value exceeds VZCDAth), the turn-on of the power
MOSFET is driven by this circuit and is no more related to the internal oscillator (except for
the frequency fold-back function).
The start-up phase is managed by a dedicated internal logic and is activated every time the
device exits from UVLO because the VDD voltage exceeds the threshold VDDon. An internal
timing (tSU, see Table 8 on page 8) defines the end of the start-up phase.
During the first part of the start-up phase soft start takes place: the drain peak current is
increased cycle-by-cycle from zero as far as the maximum value, IDlim, (see Figure 24 or
Figure 25 on page 18). The duration of soft-start is tSS, (tSS < tSU, see Table 8 on page 8),
During soft-start and until the output voltage reaches its regulated value, the feedback loop
is open. To prevent an improper activation of the OLP function (see the Section 7.13 on
page 28) during soft-start and until the start-up phase is over (t = tSU), the feedback voltage
is clamped at VFBlin.(see Figure 24 on page 18).
In this way, the feedback voltage can exceed VFBlin and ramp up as far as the overload
threshold, VFBolp (see Figure 25 on page 18), which would activate the OLP function, only at
the end of the start-up phase (t > tSU) if the output voltage is still below the regulated value.
DDoffDDon
SSauxDDch
VDD VV
tI
C
=
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VIPER25 Operation description
Doc ID 15585 Rev 4 17/40
As soon as the output voltage reaches the regulated value, the regulation loop takes over
and the drain current is regulated below its limit, IDlim, by the feedback voltage, which settles
at a value lower than the threshold VFBlin
Figure 22. IDD current during start-up and burst mode
Figure 23. Timing diagram: normal power-up and power-down sequences
BURST MODE
NORMAL MODE
START- UP NORMAL MODE
I
DDch
(-3 mA)
I
DD1
I
DD0
I
DD
V
FBbm
V
FB
V
DRAIN
V
FBbmhys
V
FBlin
V
FBolp
V
DD
V
DDoff
V
DDon
t
t
t
t
IDD
V
DD
VDRAIN
V
DDon
time
VIN
V
DRAIN_START
Power-on Power-off
Normal operation
regulation is lost here
V
IN
< V
DRAIN_START
HV startup is no more activated
V
DDoff
V
DD(RESTART)
I
DDch
(3mA)
time
time
time
18/40 ' Ln" Vam Regu‘aked vame Figure 25. Timing diagram: Start-up phase and soft start (case 2) Imam —>1 Doc ID 15585 Rev 4
Operation description VIPER25
18/40 Doc ID 15585 Rev 4
Figure 24. Timing diagram: Start-up phase and soft start (case 1)
Figure 25. Timing diagram: Start-up phase and soft start (case 2)
V
FB
VFBlin
VFBolp
I
DRAIN
IDlim
V
OUT
t
t
t
tSS (soft start)
tSU (start up phase)
Regulated value
V
FB
V
FBlin
V
FBolp
I
DRAIN
I
Dlim
V
OUT
t
t
T
OLP-delay
t
t
SS
(soft start)
t
SU
(start up phase)
Regulated value
Timing diagram: behavior after sh no 95 an
VIPER25 Operation description
Doc ID 15585 Rev 4 19/40
7.4 Power-down description
At converter power-down, the system loses regulation as soon as the input voltage is so low
that the peak current limitation is reached. The VDD voltage drops and when it falls below
the VDDoff threshold the power MOSFET is switched OFF, the energy transfers to the IC is
interrupted and consequently the VDD voltages decreases, see Figure 23 on page 17. Later,
if the VIN is lower than the threshold VDRAIN_START
, the start-up sequence is inhibited and
the power-down completed. This feature is useful to prevent converter’s restart attempts and
ensures monotonic output voltage decay during the system power-down.
7.5 Auto-restart description
If after a converter power-down, the VIN is higher than VDRAIN_START, the power-up
sequence is not inhibited and will be activated only when the VDD voltage drops down the
VDD(RESTART) threshold (reported on Table 7 on page 7). This means that the HV start-up
current generator restarts the VDD capacitor charging only when the VDD voltage drops
below VDD(RESTART). The scenario above described is for instance a power-down because
of a fault condition. After a fault condition, the charging current, IDDch, is reduced to 0.6 mA
instead of 3 mA of the normal power-up converter phase. This feature together with the low
VDD(RESTART) threshold (reported on Table 7 on page 7) ensures that, after a fault, the
restart attempts of the IC has a very long repetition rate and the converter works safely with
extremely low power throughput. The Figure 26 shows the IC behavioral after a short circuit
event.
Figure 26. Timing diagram: behavior after short circuit
I
DD
V
DD
V
DS
V
DDon
time
Short circuit occurs here
V
DDoff
V
DD(RESTART)
I
DDch
(0.6mA)
time
time
time
V
FB
V
FBolp
V
FBlin
T
REPETITION
0.3 x T
REPETITION
Operation description VIPER25
20/40 Doc ID 15585 Rev 4
7.6 Quasi-resonant operation
The control core of the VIPER25 is a current-mode PWM controller with a the zero current
detection circuit designed for Quasi-Resonant (QR) operation, a technique that provides the
benefits of minimum turn-on losses, low EMI emission and safe behavior in case of short
circuit. At heavy load the converter operates in quasi-resonant mode: operation lies in
synchronizing MOSFET's turn-on to the transformer’s demagnetization by detecting the
resulting negative-going edge of the voltage across any winding of the transformer. The
system works close to the boundary between discontinuous (DCM) and continuous
conduction (CCM) of the transformer and the switching frequency will be different for
different line/load conditions. See the hyperbolic-like portion reported in Figure 27 on
page 21.
At medium/ light load, depending also from the converter input voltage, the device enters in
Valley-skipping mode. The internal oscillator, synchronized to MOSFET’s turn-on, defines
the maximum operating frequency of the converter, FOSClim.
The VIPER25 is available as type ‘L’ or type ‘H’, depending from the value of FOSClim, see
Table 8 on page 8. During the normal operation the converter works with a frequency below
FOSClim, so the ‘L’ type is suitable for application where the priority is on the EMI filter
minimization. The ‘H’ type is suitable when an extended QR operation range is a plus or the
priority is the transformer size reduction.
As the load is reduced, and the switching frequency tends to exceeds the limit FOSClim,
MOSFET’s turn-on will not any more occur on the first valley but on the second one, the third
one and so on, see Figure 29 on page 22. In this way a “frequency clamp” effect is achieved,
piecewise linear portion in Figure 27 on page 21.
When the load is extremely light or disconnected, the converter enters in burst mode
operation, see the relevant Section 7.14 on page 32. Decreasing the load will then result in
frequency reduction, which can go down even to few hundred hertz, thus minimizing all
frequency-related losses and making it easier to comply with energy saving regulations or
recommendations. Being the peak current low enough, no issue of audible noise.
The above mentioned way of operation is based on the ZCD pin. This pin is the input of the
integrated ZCD circuit which allows the power section turn-on at the end of the transformer
demagnetization. The input signal for the ZCD is obtained as a partition of the auxiliary
voltage used to supply the device, see Figure 28 on page 21.
When the integrated triggering circuit senses the negative going edge of the voltage VZCD,
going below the threshold VZCDTth, the power MOSFET is turned on with a delay that helps
to achieve the minimum drain-source voltage during the switch on. The mentioned triggering
circuit has to be previously armed by a positive going edge of the voltage VZCD, exceeding
the threshold VZCDAth. See the Table 8 on page 8.
After the MOSFET turn-off there is a typical noise generated by the transformer's leakage
inductance resonance ringing and coupled with the ZCD pin. The blanking time, TBLANK,
helps to filter this noise avoiding false triggers of the ZCD circuit.
VIPER25 Operation description
Doc ID 15585 Rev 4 21/40
Figure 27. Switching frequency vs output load
Figure 28. Zero current detection circuit and oscillator circuit
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Operation description VIPER25
22/40 Doc ID 15585 Rev 4
7.7 Frequency foldback function and valley skipping mode
The switching frequency, in Quasi Resonant mode, is not fixed and it depends on both the
load and the converter’s input voltage. The switching frequency increases when the load
decreases, or when the input voltage mains increases, and vice versa. In principle it could
reach an infinite value. To avoid that, the VIPER25 taps the maximum switching frequency of
the application by its control logic.
The frequency limit is realized with an internal oscillator switching at 136 kHz for VIPER25L
or at 225 kHz for the VIPER25H, sees the parameter FOSClim on Table 8 on page 8. This
oscillator is synchronized with power MOSFET turn-on. When the power MOSFET is off, if
the first negative-going edge voltage of the ZCD pin, resulting from transformer’s
demagnetization, appears after at least one oscillator cycle has been completed, the
MOSFET is turned ON and the oscillator re-synchronized.
Otherwise, if the first negative-going edge voltage appears before completing one oscillator
cycle, the signal is ignored. Due to the ringing of the drain voltage, the ZCD pin will
experience another positive-going edge voltage that arms the circuit and a subsequent
negative-going edge voltage. Again, if this appears before the oscillator cycle is complete, it
is ignored, otherwise the MOSFET is turned ON and the oscillator re-synchronized. In this
way, one or more drain ringing cycles will be skipped (Figure 29 on page 22 shows the so
called “valley-skipping mode”) and the switching frequency will be prevented from exceeding
the limit FOSClim.
Figure 29. Drain ringing cycle skipping as the load is progressively reduced
When the system operates in valley skipping-mode, uneven switching cycles may be
observed under some line/load conditions, due to the fact that the OFF-time of the power
MOSFET is allowed to change with discrete steps of one ringing cycle, while the OFF-time
needed for cycle-by-cycle energy balance could fall in between. Thus one or more longer
switching cycles will be compensated by one or more shorter cycles and vice versa. This
mechanism is natural and there is no appreciable effect on the converter’s performances
and on its output voltage.
The operation described so far does not consider the blanking time TBLANK after power
MOSFET's turn OFF. Actually TBLANK does not come into play as long as the following
condition is met:
Equation 2
where D is the MOSFET duty cycle. If this condition is not met, the time during which
MOSFET's turn-ON is inhibited is extended beyond TOSClim by a fraction of TBLANK. As a
consequence, the maximum switching frequency will be a little lower than the internal limit
set by the oscillator and valley-skipping mode will take place slightly earlier than expected.
Pin = P in'
(limit condit ion) Pin = P in'' < Pin' Pin = P in''' < P in''
t
VDS
TFW
Tos c
TV
T
ON
t
VDS
T
osc
t
VDS
Tos c
limOSCBLANK
limOSC
BLANK FT1
T
T
1D =
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VIPER25 Operation description
Doc ID 15585 Rev 4 23/40
7.8 Double blanking time
The blanking time, TBLANK, can have two different values: the lower one is 2,5 μs (typical
value) and the higher one is 6,3 μs (typical value). The value is linked to the voltage VZCD,
sampled during the time TSTROBE defined as for the over voltage protection (see the
relevant Section 7.11 on page 26). The time TBLANK has the lower value if is detected VZCD
< 1V or it has the higher value if is detected VZCD > 1V, refer to Table 8 on page 8 and
Figure 30 on page 23.
The higher value of the blanking time is normally activated during the start-up phase or in
case of output short circuit; when the output voltage of the converter is quite lower than the
regulated value. In this condition can happens that during the demagnetization of the
transformer, the VZCD is very close to the arming and triggering thresholds (VZCDAth and
VZCDTth) and the ZCD circuit can be erroneously trigged, leading the system to work at
higher frequency and in continuous mode. This false trigger is inhibited by the selection of
the higher value of TBLANK when VZCD is lower than 1 V.
During the normal operation, in steady state condition, the voltage VZCD during the
demagnetization is higher than 1V and the selected TBLANK value is the lower one. The
Figure 30 shows the typical waveforms during the power up and the linked TBLANK selection.
Figure 30. Double TBLANK timing diagram
Vaux
1
V
t
0
ZC
(pin 3)
1.5 0.5
TBL ANK
C
t
t
t
t
t
t
D
A
TST R O B E
6.3μs
2. 5 μs
F
Dela
y
Mosfet switched on by the starte
r
Quasi Resonant Operation
limOS C
F
4
t
0.8
V
0. 6
V
Operation description VIPER25
24/40 Doc ID 15585 Rev 4
7.9 Starter
If the amplitude of the voltage on ZCD pin at the end of one oscillator cycle is smaller than
the VZCDAth arming threshold, in which case MOSFET's turn-ON could not be triggered, the
system would stop.
This is what normally happens during converter’s power-up or under overload/short circuit
conditions.
During the converter’s startup phase, the voltage on ZCD pin is not high enough to arm the
triggering circuit. Thus, the converter operates at a fixed frequency, FSTARTER (see Tabl e 8
on page 8). As the voltage developed across the auxiliary winding becomes high enough to
arm the ZCD circuit, MOSFET's turn-ON is locked to transformer demagnetization, hence
setting up quasi-resonant operation.
As protection, in case the ZCD voltage is permanently above the threshold VZCDAth, the
switching frequency is reduced to the minimum value, FOSCmin, reported on Ta bl e 8 o n
page 8.
7.10 Current limit set point and feed-forward option
The VIPER25 is a current mode converter and the drain current is limited cycle by cycle
according to the FB pin voltage value that is related with the feedback loop response and
the load. When the drain current, sensed by the integrated Sense-FET, reaches the current
limitation, after the internal propagation delay, the MOSFET is switched OFF. The current
limitation cannot exceed a certain value, IDlim, that can be adjusted acting on the current
sunk from the ZCD pin during MOSFET’s ON-time.
Usually a resistor, RLIM, connected from ZCD pin to ground is used to fix this sunk current
and then the peak drain current set-point: the lower the resistor is, the lower IDlim will be.
For a QR fly-back converter the power capability strongly depends on the input voltage. In
wide-range applications at maximum line the power capability can be more than twice the
value at minimum line, as shown by the upper curve in the diagram of Figure 31 on page 25.
To reduce this dependence, the current limit IDlim has to be reduced according to the
increment of the input voltage, implementing the so called line feed-forward. It’s realized with
a resistor, RFF
, connected between the ZCD pin and the auxiliary winding, see the Figure 32
on page 26. Since the voltage across the auxiliary winding during MOSFET’s on-time is
proportional to the input voltage through the auxiliary-to-primary turns ratio NAUX /NP
, a
current proportional to the input voltage is sunk from the ZCD pin, thus lowering the over
current set point.
|:=; © g E Vm
VIPER25 Operation description
Doc ID 15585 Rev 4 25/40
Figure 31. Typical power capability vs input voltage in quasi-resonant converter’s
In order to proper select the value of the resistance RFF (see Figure 32 on page 26), once
are known the proper IDlim set points at minimum and at the maximum converter input
voltage. The following approximated formula calculates the value of the resistor RFF
Equation 3
Where:
Vin_Max and Vin_min are the maximum and minimum converter rectified input voltage
naux is the primary to auxiliary winding turn ratio
IZCD1, and IZCD2 are the currents needed to sink from the ZCD pin, in order to obtain
the selected IDlim set points, respectively at Vin_max and Vin_min, the graph IDlim vs IZCD
current is reported on Figure 16 on page 12).
The RLIM Value can be calculated from the following formula knowing the RFF value:
Equation 4
Where:
VZCD1 and VZCD2 are the ZCD pin voltages when the sunk current is IZCD1 and IZCD2
respectively (see Figure 15 on page 12).
Vin
Vinmi n
P
inli m
@
V
inmi n
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aux
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aux
min_in
1ZCD
1ZCD
LIM
R
V
n
V
I
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,
R
V
n
V
I
V
MaxR
Operation description VIPER25
26/40 Doc ID 15585 Rev 4
Figure 32. ZCD pin typical external configuration
7.11 Overvoltage protection (OVP)
The VIPER25 has integrated the logic for the monitor of the output voltage using as input
signal the voltage VZCD during the OFF time of the power MOSFET. This is the time when
the voltage from the auxiliary winding tracks the output voltage, through the turn ratio NAUX /
NSEC.
The ZCD pin has to be connected to the auxiliary winding through the diode DOVP and the
resistors ROVP and RLIM as shows the Figure 32 on page 26. When, during the OFF time,
the voltage VZCD exceeds, four consecutive times, the reference voltage VOVP (reported on
Table 8 on page 8) the over voltage protection will stop the power MOSFET and the
converter enters the auto-restart mode.
In order to bypass the noise after the turn off of the power MOSFET, the voltage VZCD is
sampled inside a short window after the time TSTROBE, see the Table 8 on page 8 and
Figure 33 on page 27. The sampled signal, if higher than VOVP
, trigger the internal OVP
digital signal and increments the internal counter. The same counter is reset every time the
signal OVP is not triggered in one oscillator cycle.
Referring to the Figure 32, the resistors divider ratio kOVP will be given by:
Equation 5
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VIPER25 Operation description
Doc ID 15585 Rev 4 27/40
Equation 6
Where:
VOVP is the OVP threshold (see Table 8 on page 8)
VOUT OVP is the converter output voltage value to activate the OVP (set by designer)
designer
NAUX is the auxiliary winding turns
NSEC is the secondary winding turns
VDSEC is the secondary diode forward voltage
VDAUX is the auxiliary diode forward voltage
ROVP together RLIM make the output voltage divider
Than, fixed RLIM, according to the desired IDlim, the ROVP can be calculating by:
Equation 7
The resistor values will be such that the current sourced and sunk by the ZCD pin be within
the rated capability of the internal clamp.
Figure 33. OVP timing diagram
kOVP
RLIM
RLIM ROVP
+
----------------------------------=
ROVP RLIM
1k
OVP
kOVP
-----------------------
×=
t
VA
U
X
V
OVP
t
t
t
STROBE
t
COUNTER
RESET
t
COUNTER
STATUS t
0
ZCD
2 µs 0.5 µs
OVP
FAULT
0 0 0 0 11 22 00 11
22 3 3
40
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0 0 0 0 11 22 00 11
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40
ERULIAF POOL KCABDEEFECNABRUTSID YRAROPMETNOITAREPO LAMRON t
Operation description VIPER25
28/40 Doc ID 15585 Rev 4
7.12 Summary on ZCD pin
Referring to the Figure 32 on page 26, the circuitry connected to the ZCD pin enables to
implement the following functions:
1. Current limit, IDlim, set point
2. Line feed-forward compensation
3. Output overvoltage protection (OVP)
4. Zero current detection for QR operation
Chosen RLIM, RFF and ROVP as described in previous paragraphs this function are
automatically defined.
Ta bl e 9 refers to the Figure 32 and list the external resistance combinations needed to
activate one or more functions associated to the ZCD pin.
7.13 Feedback and overload protection (OLP)
The feedback pin (FB) controls the PWM operation, enters the burst mode and manages the
delayed overload protection.
The thresholds VFBbm and VFBlin (reported on Table 8 on page 8) are respectively the low
and the high limit of the PWM operations, where the drain current is sensed trough the
integrated resistor RSENSE and applied to the comparator PWM. The PWM logic turns OFF
the power MOSFET as soon as the sensed voltage is equal to the voltage applied to the FB
pin and trough the integrated resistors network, see the Figure 2 on page 4 and Figure 20
on page 14.
As shows the IC block diagram reported in Figure 2 on page 4, in parallel with the PWM
comparator there is the OCP comparator that limits the drain current as maximum to the
value IDlim, reported on Table8 on page8.
In case of higher load the voltage VFB increases, when it reaches the threshold VFBlin the
drain current is limited to IDlim and the internal current starts the charge of the capacitor CFB.
As soon as the voltage VFB reaches the threshold VFBolp, see Figure 36 on page 31, the
protection turns off the IC. After, the auto-restart mode is activated using the low value of the
current IDDch, see Table 7 on page 7.
Table 9. ZCD pin configurations
Function / component RLIM ROVP RFF DOVP
IDlim set point See Equation 4 Required for ZCD Not required Yes
OVP 22 kΩSee equation 7 Not required Yes
Line feed-forward 22 kΩRequired for ZCD See Equation 3 Ye s
IDlim set point and OVP See Equation 4
with RFF = See equation 7 Not required Yes
OVP and line feed-forward 22 kΩSee equation 7 See Equation 3 Ye s
IDlim set point and line feed-forward See Equation 4 Required for ZCD See Equation 3 Ye s
IDlim reduction+ OVP +
Line feed-forward See Equation 4 See equation 7 See Equation 3 Ye s
VIPER25 Operation description
Doc ID 15585 Rev 4 29/40
The time, from the high load detection, VFB = VFBlin, to the over load turn-off, VFB = VFBolp,
depends from the value of the capacitor CFB and from the internal charge current, IFB. The
OLP delay time can be calculating by the formula:
Equation 8
The current, IFB, is 3 μA as minimum value. The components connected to the FB pin are
also a part of the compensation loop, so they have to be selected taking into account the
proper delay and loop stability consideration. The Figure 34 on page 30 and Figure 35 on
page 30 show two different feedback networks.
In the Figure 33 on page 27, the capacitor, CFB, connected to FB pin is used as part of the
circuit to compensate the feedback loop but also as element to delay the OLP shut down
owing to the time needed to charge the capacitor (see the Equation 8).
After the start-up time, tSU, during which the feedback voltage is fixed at VFBlin, the output
capacitor could not be at its nominal value and the controller interpreter this situation as an
over load condition. In this case, the OLP delay helps to avoid an incorrect device shut down
during the start-up. See the relevant Section 7.3 on page 16.
Owing to the above considerations, the OLP delay time must be long enough to by-pass the
initial output voltage transient and check the over load condition only when the output
voltage is in steady state. The output transient time depends from the value of the output
capacitor and from the load.
When the value of the CFB capacitor calculated for the loop stability is too low and cannot
ensure enough OLP delay, an alternative compensation network can be used and it is
showed in Figure 35 on page 30.
Using this alternative compensation network, two poles (fPFB, fPFB1) and one zero (fZFB) are
introduced by the capacitors CFB and CFB1 and the resistor RFB1.
The capacitor CFB introduces a pole (fPFB) at higher frequency than fZB and fPFB1. This pole
is usually used to compensate the high frequency zero due to the ESR (Equivalent Series
Resistor) of the output capacitance of the fly-back converter.
The mathematical expressions of these poles and zero frequency, considering the scheme
in Figure 35 on page 30 are reported by the equations below:
Equation 9
Equation 10
TOLP delayCFB
VFBolp VFBlin
3μA
----------------------------------------
×=
1FB1FB
ZFB RC2
1
fπ
=
()
1FB)DYN(FBFB
1FB)DYN(FB
PFB RRC2
RR
fπ
+
=
30/40 Figure 35. L.l ..”_| |_. FB pin configuration E] Doc
Operation description VIPER25
30/40 Doc ID 15585 Rev 4
Equation 11
The RFB(DYN) is the dynamic resistance seen by the FB pin and reported on Ta bl e 8 o n
page 8.
The CFB1 capacitor fixes the OLP delay and usually CFB1 results much higher than CFB. The
Equation 8 on page 29 can be still used to calculate the OLP delay time but CFB1 has to be
considered instead of CFB. Using the alternative compensation network, the designer can
satisfy, in all case, the loop stability and the enough OLP delay time alike.
Figure 34. FB pin configuration
Figure 35. FB pin configuration
()
)DYN(FB1FB1FB
1PFB RRC2
1
f+π
=
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BURST
PWM
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Cfb
To PWM Logic
BURST-MODE
REFERENCES
BURST-MODE
LOGIC
+
-
PWM
+
-
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To disable logic
4.8V
From sense FET
PWM
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BURST
To disable logic
+
-
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To PWM Logic
BURST-MODE
LOGIC
Cfb1
Rfb1
Cfb
BURST-MODE
REFERENCES
VIPER25 Operation description
Doc ID 15585 Rev 4 31/40
Figure 36. Timing diagram: Overload protection
t
t
t
t
SOFT
START
START UP
OVER LOAD
Warning
OVER LOAD
Warning
I
OUT
V
OUT
I
DRAIN
V
FB
STOP
OPERATION
I
Dlim
V
FBlin
V
FBolp
7.15 32/40 Brown-out protection Brown»out protection is a not-iafched shufdown function activafed when a condition of under volfage is detecfed. The Brown»out comparafor is internaily referenced to VBRm fhreshoid, see Table 8 on page 8, and disables fhe PWM if the voltage appiied af the B is below this infernal reference. Under this condifion fhe power MOSFET is turned off. me Brown ouf condition is present, fhe VDD voltage confinuously oscillafes between fh VDDon and the UVLO fhresholds, as shown in me fiming diagram of Figure 38 on page volfage hysferesis is present fo improve fhe noise immunity. The switching operation is restarfed as the volfage on before said voifage hysferesis. See Figure 5 on page The Brown»out comparafor is provided also wifh a on has fo set the rectified inpuf voltage above which the brown ouf event, VINO", and me recfiiied inpuf voifage switched off, VINO". Thanks to the IBRhyS‘, see Table 8 be sef separafeiy. Doc ID 15585 Rev 4
Operation description VIPER25
32/40 Doc ID 15585 Rev 4
7.14 Burst-mode operation at no load or very light load
When the load decrease the feedback loop reacts lowering the feedback pin voltage. If it
falls down the burst mode threshold, VFBbm, the power MOSFET is not more allowed to be
switched on. After the MOSFET stops, as a result of the feedback reaction to the energy
delivery stop, the feedback pin voltage increases and exceeding the level, VFBbm +
VFBbmhys, the power MOSFET starts switching again. The burst mode thresholds are
reported on Ta b l e 8 and Figure 37 shows this behavior. Systems alternates period of time
where power MOSFET is switching to period of time where power MOSFET is not switching;
this device working mode is the burst mode. The power delivered to output during switching
periods exceeds the load power demands; the excess of power is balanced from not
switching period where no power is processed. The advantage of burst mode operation is
an average switching frequency much lower then the normal operation working frequency,
up to some hundred of hertz, minimizing all frequency related losses. During the burst-mode
the drain current peak is clamped to the level, ID_BM, reported on Ta b l e 8 .
Figure 37. Burst mode timing diagram, light load management
7.15 Brown-out protection
Brown-out protection is a not-latched shutdown function activated when a condition of mains
under voltage is detected. The Brown-out comparator is internally referenced to VBRth
threshold, see Table 8 on page 8, and disables the PWM if the voltage applied at the BR pin
is below this internal reference. Under this condition the power MOSFET is turned off. Until
the Brown out condition is present, the VDD voltage continuously oscillates between the
VDDon and the UVLO thresholds, as shown in the timing diagram of Figure 38 on page 33. A
voltage hysteresis is present to improve the noise immunity.
The switching operation is restarted as the voltage on the pin is above the reference plus the
before said voltage hysteresis. See Figure 5 on page 10.
The Brown-out comparator is provided also with a current hysteresis, IBRhyst. The designer
has to set the rectified input voltage above which the power MOSFET starts switching after
brown out event, VINon, and the rectified input voltage below which the power MOSFET is
switched off, VINoff. Thanks to the IBRhyst, see Table 8 on page 8, these two thresholds can
be set separately.
time
time
time
V
COMP
V
FBbm
+V
FBbmhys
V
FBbm
I
DD1
I
DD0
I
DD
I
DRAIN
I
D_BM
Burst Mode
my. le Vim Vim Vnm sum an v VD5 Vow Fixed the Vim“ and the Vim,“ levels, with reference to Figure 38, the lollowmg relationships can be established for the calculation of the resistors RH and RL: Equation 12 Equation 13 For a proper operation of this function, VIN on must be less than the peak voltage at minimum mains and ViN a" less than the minimum voltage on the input bulk capacitor at minimum mains and maximum load. The BFi pin is a high impedance input connected to high value resistors, thus it is prone to pick up noise, which might alter the OFF threshold when the converter operates or gives origin to undesired switch»off of the device during ESD tests. It is possible to bypass the pin to ground with a small film capacitor (e.g. 1»1O nF) to prevent any malfunctioning of this kind. If the brown»out function is not used the BR pin has to be connected to GND, ensuring that the voltage is lower than the minimum of ans threshold (50 mV, see Table 8). In order to Doc ID 15585 Flev 4 33/40
VIPER25 Operation description
Doc ID 15585 Rev 4 33/40
Fixed the VINon and the VINoff levels, with reference to Figure 38, the following relationships
can be established for the calculation of the resistors RH and RL:
Equation 12
Equation 13
For a proper operation of this function, VIN on must be less than the peak voltage at
minimum mains and VIN off less than the minimum voltage on the input bulk capacitor at
minimum mains and maximum load.
The BR pin is a high impedance input connected to high value resistors, thus it is prone to
pick up noise, which might alter the OFF threshold when the converter operates or gives
origin to undesired switch-off of the device during ESD tests.
It is possible to bypass the pin to ground with a small film capacitor (e.g. 1-10 nF) to prevent
any malfunctioning of this kind.
If the brown-out function is not used the BR pin has to be connected to GND, ensuring that
the voltage is lower than the minimum of VDIS threshold (50 mV, see Ta bl e 8 ). In order to
Figure 38. Brown-out protection: BR external setting and timing diagram
-
+
Disable
C
BR
V
DIS
-
+
V
in_OK
V
BRth
R
H
I
BRhyst
R
L
V
IN_DC
VDD
+
V
OUT
V
IN
V
INon
V
INoff
V
DRAIN_START
V
BR
V
in_OK
I
BR
V
BRth
I
BRhyst
V
DD
V
DDon
V
DDoff
V
DS
V
DD(RESTART)
BRhyst
BRth
BRthINoff
BRhystINoffINon
BRhyst
BRhyst
LI
V
VV
VVV
I
V
R×
+=
BRhyst
BRhyst
L
L
BRhyst
BRhystINoffINon
H
I
V
R
R
I
VVV
R
+
×
=
Secundary made ‘5 snarled here / ”Hal
Operation description VIPER25
34/40 Doc ID 15585 Rev 4
enable the brown-out function the BR pin voltage has to be higher than the maximum of
VDIS threshold (150 mV, see Ta b l e 8 ).
7.16 2nd level over current protection and hiccup mode
The VIPER25 is protected against short circuit of the secondary rectifier, short circuit on the
secondary winding or a hard-saturation of fly-back transformer. Such as anomalous
condition is invoked when the drain current exceed the threshold IDMAX, see Tabl e 8 o n
page 8.
To distinguish a real malfunction from a disturbance (e.g. induced during ESD tests) a
“warning state” is entered after the first signal trip. If in the subsequent switching cycle the
signal is not tripped, a temporary disturbance is assumed and the protection logic will be
reset in its idle state; otherwise if the IDMAX threshold is exceeded for two consecutive
switching cycles a real malfunction is assumed and the power MOSFET is turned OFF.
The shutdown condition is latched as long as the device is supplied. While it is disabled, no
energy is transferred from the auxiliary winding; hence the voltage on the VDD capacitor
decays till the VDD under voltage threshold (VDDoff), which clears the latch.
The start up HV current generator is still off, until VDD voltage goes below its restart voltage,
VDD(RESTART). After this condition the VDD capacitor is charged again by 600 µA current,
and the converter switching restarts if the VDDon occurs. If the fault condition is not removed
the device enters in auto-restart mode. This behavioral results in a low-frequency
intermittent operation (Hiccup-mode operation), with very low stress on the power circuit.
See the timing diagram of Figure 39.
Figure 39. Hiccup-mode OCP: timing diagram
Vcc
VDRAIN
IDRAIN
Secondary diode is shorted here
t
t
t
DMAX
on
off
(RESTART)
Secondary diode is shorted here
t
t
t
I
VDD
VDD
VDD
VDD
VIPER25 Package mechanical data
Doc ID 15585 Rev 4 35/40
8 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Note: 1 The leads size is comprehensive of the thickness of the leads finishing material.
2 Dimensions do not include mold protrusion, not to exceed 0,25 mm in total (both side).
3 Package outline exclusive of metal burrs dimensions.
4 Datum plane “H” coincident with the bottom of lead, where lead exits body.
5 Ref. POA mother doc. 0037880
Table 10. DIP-7 mechanical data
Dim.
mm
Typ. Min. Max.
A 5.33
A1 0.38
A2 3.30 2.92 4.95
b 0.46 0.36 0.56
b2 1.52 1.14 1.78
c 0.25 0.20 0.36
D 9.27 9.02 10.16
E 7.87 7.62 8.26
E1 6.35 6.10 7.11
e 2.54
eA 7.62
eB 10.92
L 3.30 2.92 3.81
M (1)(2)
1. Creepage distance > 800 V
2. Creepage distance as shown in the 664-1 CEI / IEC standard
2.508
N 0.50 0.40 0.60
N1 0.60
O (2)(3)
3. Creepage distance 250 V
0.548
GAUGE PLANE 0 35 notes 5 , 8 .M. notes 7 , a
Package mechanical data VIPER25
36/40 Doc ID 15585 Rev 4
Figure 40. DIP-7 package dimensions
VIPER25 Package mechanical data
Doc ID 15585 Rev 4 37/40
Table 11. SO16 narrow mechanical data
Dim.
Databook (mm.)
Min. Typ. Max.
A 1.75
A1 0.1 0.25
A2 1.25
b 0.31 0.51
c 0.17 0.25
D 9.8 9.9 10
E 5.8 6 6.2
E1 3.8 3.9 4
e 1.27
h 0.25 0.5
L 0.4 1.27
k 0 8
ccc 0.1
k, \Vi «(Ls > 7! mzjl 56 5; m3 mzjn 025mm .mwx;
Package mechanical data VIPER25
38/40 Doc ID 15585 Rev 4
Figure 41. SO16 package dimensions
VIPER25 Revision history
Doc ID 15585 Rev 4 39/40
9 Revision history
Table 12. Document revision history
Date Revision Changes
17-Apr-2009 1Initial release
09-Jun-2009 2 Updated application paragraph in coverpage and Table 8 on
page 8
26-Aug-2009 3 Content reworked to improve readability, no technical changes
21-Jul-2010 4 Updated Table 8 on page 8 and Figure 38 on page 33
VIPER25
40/40 Doc ID 15585 Rev 4
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