PIC16F882-84/86-87 Datasheet by Microchip Technology

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6‘ MICROCHIP
2006-2015 Microchip Technology Inc. DS40001291H-page 1
PIC16F882/883/884/886/887
High-Performance RISC CPU
Only 35 Instructions to Learn:
- All single-cycle instructions except branches
Operating Speed:
- DC – 20 MHz oscillator/clock input
- DC – 200 ns instruction cycle
Interrupt Capability
8-Level Deep Hardware Stack
Direct, Indirect and Relative Addressing modes
Special Microcontroller Features
Precision Internal Oscillator:
- Factory calibrated to ±1%
- Software selectable frequency range of
8 MHz to 31 kHz
- Software tunable
- Two-Speed Start-up mode
- Crystal fail detect for critical applications
- Clock mode switching during operation for
power savings
Power-Saving Sleep mode
Wide Operating Voltage Range (2.0V-5.5V)
Industrial and Extended Temperature Range
Power-on Reset (POR)
Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)
Brown-out Reset (BOR) with Software Control
Option
Enhanced Low-Current Watchdog Timer (WDT)
with On-Chip Oscillator (software selectable
nominal 268 seconds with full prescaler) with
software enable
Multiplexed Master Clear with Pull-up/Input Pin
Programmable Code Protection
High Endurance Flash/EEPROM Cell:
- 100,000 write Flash endurance
- 1,000,000 write EEPROM endurance
- Flash/Data EEPROM retention: > 40 years
Program Memory Read/Write during run time
In-Circuit Debugger (on board)
Low-Power Features
Standby Current:
- 50 nA @ 2.0V, typical
Operating Current:
-11A @ 32 kHz, 2.0V, typical
-220A @ 4 MHz, 2.0V, typical
Watchdog Timer Current:
-1A @ 2.0V, typical
Peripheral Features
24/35 I/O Pins with Individual Direction Control:
- High current source/sink for direct LED drive
- Interrupt-on-Change pin
- Individually programmable weak pull-ups
- Ultra Low-Power Wake-up (ULPWU)
Analog Comparator Module with:
- Two analog comparators
- Programmable on-chip voltage reference
(CVREF) module (% of VDD)
- Fixed Voltage Reference (0.6V)
- Comparator inputs and outputs externally
accessible
- SR Latch mode
- External Timer1 Gate (count enable)
A/D Converter:
- 10-bit resolution and 11/14 channels
Timer0: 8-bit Timer/Counter with 8-bit
Programmable Prescaler
Enhanced Timer1:
- 16-bit timer/counter with prescaler
- External Gate Input mode
- Dedicated low-power 32 kHz oscillator
Timer2: 8-bit Timer/Counter with 8-bit Period
Register, Prescaler and Postscaler
Enhanced Capture, Compare, PWM+ Module:
- 16-bit Capture, max. resolution 12.5 ns
- Compare, max. resolution 200 ns
- 10-bit PWM with 1, 2 or 4 output channels,
programmable “dead time”, max. frequency
20 kHz
- PWM output steering control
Capture, Compare, PWM Module:
- 16-bit Capture, max. resolution 12.5 ns
- 16-bit Compare, max. resolution 200 ns
- 10-bit PWM, max. frequency 20 kHz
Enhanced USART Module:
- Supports RS-485, RS-232, and LIN 2.0
- Auto-Baud Detect
- Auto-Wake-Up on Start bit
In-Circuit Serial ProgrammingTM (ICSPTM) via Two
Pins
Master Synchronous Serial Port (MSSP) Module
supporting 3-wire SPI (all 4 modes) and I2C™
Master and Slave Modes with I2C Address Mask
28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers
PIC16F882/883/884/886/887
DS40001291H-page 2 2006-2015 Microchip Technology Inc.
PIC16F882/883/884/886/887 Family Types
Device
Program
Memory Data Memory
I/O 10-bit A/D
(ch) ECCP/
CCP EUSART MSSP Comparators Timers
8/16-bit
Flash
(words) SRAM
(bytes) EEPROM
(bytes)
PIC16F882 2048 128 128 24 11 1/1 1 1 2 2/1
PIC16F883 4096 256 256 24 11 1/1 1 1 2 2/1
PIC16F884 4096 256 256 35 14 1/1 1 1 2 2/1
PIC16F886 8192 368 256 24 11 1/1 1 1 2 2/1
PIC16F887 8192 368 256 35 14 1/1 1 1 2 2/1
33333333333333 DKKKKKKKKKKKKK
2006-2015 Microchip Technology Inc. DS40001291H-page 3
PIC16F882/883/884/886/887
Pin Diagrams – PIC16F882/883/886, 28-Pin PDIP, SOIC, SSOP
10
11
2
3
4
5
6
1
8
7
9
12
13
14 15
16
17
18
19
20
23
24
25
26
27
28
22
21
PIC16F882/883/886
RE3/MCLR/VPP
RA0/AN0/ULPWU/C12IN0-
RA1/AN1/C12IN1-
RA2/AN2/VREF-/CVREF/C2IN+
RA3/AN3/VREF+/C1IN+
RA4/T0CKI/C1OUT
RA5/AN4/SS/C2OUT
VSS
RA7/OSC1/CLKIN
RA6/OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/P1A/CCP1
RC3/SCK/SCL
RB7/ICSPDAT
RB6/ICSPCLK
RB5/AN13/T1G
RB4/AN11/P1D
RB3/AN9/PGM/C12IN2-
RB2/AN8/P1B
RB1/AN10/P1C/C12IN3-
RB0/AN12/INT
VDD
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
PIC16F882/883/884/886/887
DS40001291H-page 4 2006-2015 Microchip Technology Inc.
TABLE 1: 28-PIN PDIP, SOIC, SSOP ALLOCATION TABLE (PIC16F882/883/886)
I/O
28-Pin PDIP/SOIC/SSOP
Analog
Comparators
Timers
ECCP
EUSART
MSSP
Interrupt
Pull-up
Basic
RA0 2AN0/ULPWU C12IN0- — —
RA1 3 AN1 C12IN1-
RA2 4AN2 C2IN+ — VREF-/CVREF
RA3 5 AN3 C1IN+ VREF+
RA4 6 — C1OUT T0CKI — —
RA5 7 AN4 C2OUT SS —— —
RA6 10 OSC2/CLKOUT
RA7 9 OSC1/CLKIN
RB0 21 AN12 IOC/INT Y —
RB1 22 AN10 C12IN3- P1C IOC Y
RB2 23 AN8 P1B IOC Y —
RB3 24 AN9 C12IN2- IOC Y PGM
RB4 25 AN11 P1D IOC Y —
RB5 26 AN13 T1G IOC Y
RB6 27 IOC YICSPCLK
RB7 28 IOC Y ICSPDAT
RC0 11 T1OSO/T1CKI — —
RC1 12 T1OSI CCP2
RC2 13 CCP1/P1A — —
RC3 14 SCK/SCL
RC4 15 SDI/SDA — —
RC5 16 SDO
RC6 17 TX/CK — —
RC7 18 RX/DT
RE3 1 — Y(1) MCLR/VPP
—20 — — VDD
— 8 VSS
—19 — — VSS
Note 1: Pull-up activated only with external MCLR configuration.
2006-2015 Microchip Technology Inc. DS40001291H-page 5
PIC16F882/883/884/886/887
Pin Diagrams – PIC16F882/883/886, 28-Pin QFN
16
2
7
1
3
6
5
4
15
21
19
20
17
18
22
28
26
27
23
24
25
14
8
10
9
13
12
11
PIC16F882/883/886
RA1/AN1/C12IN1-
RA0/AN0/ULPWU/C12IN0-
RE3/MCLR/VPP
RB7/ICSPDAT
RB6/ICSPCLK
RB5/AN13/T1G
RB4/AN11/P1D
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/P1A/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RA2/AN2/VREF-/CVREF/C2IN+
RA3/AN3/VREF+/C1IN+
RA4/T0CKI/C1OUT
RA5/AN4/SS/C2OUT
VSS
RA7/OSC1/CLKIN
RA6/OSC2/CLKOUT
RB3/AN9/PGM/C12IN2-
RB2/AN8/P1B
RB1/AN10/P1C/C12IN3-
RB0/AN12/INT
VDD
VSS
RC7/RX/DT
PIC16F882/883/884/886/887
DS40001291H-page 6 2006-2015 Microchip Technology Inc.
TABLE 2: 28-PIN QFN ALLOCATION TABLE (PIC16F882/883/886)
I/O
28-Pin QFN
Analog
Comparators
Timers
ECCP
EUSART
MSSP
Interrupt
Pull-up
Basic
RA0 27 AN0/ULPWU C12IN0- — —
RA1 28 AN1 C12IN1-
RA2 1AN2 C2IN+ — VREF-/CVREF
RA3 2 AN3 C1IN+ VREF+
RA4 3 — C1OUT T0CKI — —
RA5 4 AN4 C2OUT SS —— —
RA6 7 OSC2/CLKOUT
RA7 6 OSC1/CLKIN
RB0 18 AN12 IOC/INT Y —
RB1 19 AN10 C12IN3- P1C IOC Y
RB2 20 AN8 P1B IOC Y —
RB3 21 AN9 C12IN2- IOC Y PGM
RB4 22 AN11 P1D IOC Y —
RB5 23 AN13 T1G IOC Y
RB6 24 IOC YICSPCLK
RB7 25 IOC Y ICSPDAT
RC0 8 T1OSO/T1CKI — —
RC1 9 T1OSI CCP2
RC2 10 CCP1/P1A — —
RC3 11 SCK/SCL
RC4 12 SDI/SDA — —
RC5 13 SDO
RC6 14 TX/CK — —
RC7 15 RX/DT
RE3 26 — Y(1) MCLR/VPP
—17 — — VDD
— 5 VSS
—16 — — VSS
Note 1: Pull-up activated only with external MCLR configuration.
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2006-2015 Microchip Technology Inc. DS40001291H-page 7
PIC16F882/883/884/886/887
Pin Diagrams – PIC16F884/887, 40-Pin PDIP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PIC16F884/887
RE3/MCLR/VPP
RA0/AN0/ULPWU/C12IN0-
RA1/AN1/C12IN1-
RA2/AN2/VREF-/CVREF/C2IN+
RA3/AN3/VREF+/C1IN+
RA4/T0CKI/C1OUT
RA5/AN4/SS/C2OUT
RE0/AN5
RE1/AN6
RE2/AN7
VDD
VSS
RA7/OSC1/CLKIN
RA6/OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/P1A/CCP1
RC3/SCK/SCL
RD0
RD1
RB7/ICSPDAT
RB6/ICSPCLK
RB5/AN13/T1G
RB4/AN11
RB3/AN9/PGM/C12IN2-
RB2/AN8
RB1/AN10/C12IN3-
RB0/AN12/INT
VDD
VSS
RD7/P1D
RD6/P1C
RD5/P1B
RD4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3
RD2
PIC16F882/883/884/886/887
DS40001291H-page 8 2006-2015 Microchip Technology Inc.
TABLE 3: 40-PIN PDIP ALLOCATION TABLE (PIC16F884/887)
I/O
40-Pin PDIP
Analog
Comparators
Timers
ECCP
EUSART
MSSP
Interrupt
Pull-up
Basic
RA0 2AN0/ULPWU C12IN0- — —
RA1 3 AN1 C12IN1-
RA2 4AN2 C2IN+ — VREF-/CVREF
RA3 5 AN3 C1IN+ VREF+
RA4 6 — C1OUT T0CKI — —
RA5 7 AN4 C2OUT SS —— —
RA6 14 OSC2/CLKOUT
RA7 13 OSC1/CLKIN
RB0 33 AN12 IOC/INT Y —
RB1 34 AN10 C12IN3- IOC Y
RB2 35 AN8 IOC Y —
RB3 36 AN9 C12IN2- IOC Y PGM
RB4 37 AN11 IOC Y —
RB5 38 AN13 T1G IOC Y
RB6 39 IOC YICSPCLK
RB7 40 IOC Y ICSPDAT
RC0 15 T1OSO/T1CKI — —
RC1 16 T1OSI CCP2
RC2 17 CCP1/P1A — —
RC3 18 SCK/SCL
RC4 23 SDI/SDA — —
RC5 24 SDO
RC6 25 TX/CK — —
RC7 26 RX/DT
RD0 19 — —
RD1 20
RD2 21 — —
RD3 22
RD4 27 — —
RD5 28 P1B
RD6 29 P1C — —
RD7 30 P1D
RE0 8AN5 — —
RE1 9 AN6
RE2 10 AN7 — —
RE3 1 Y(1) MCLR/VPP
11 — — VDD
—32 — — VDD
12 — — VSS
—31 — — VSS
Note 1: Pull-up activated only with external MCLR configuration.
2006-2015 Microchip Technology Inc. DS40001291H-page 9
PIC16F882/883/884/886/887
Pin Diagrams – PIC16F884/887, 44-Pin QFN
10
11
2
3
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
37
5
4
PIC16F884/887
RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN
VSS
VSS
NC
VDD
RE2/AN7
RE1/AN6
RE0/AN5
RA5/AN4/SS/C2OUT
RA4/T0CKI/C1OUT
RC7/RX/DT
RD4
RD5/P1B
RD6/P1C
RD7/P1D
VSS
VDD
VDD
RB0/AN12/INT
RB1/AN10/C12IN3-
RB2/AN8
RB3/AN9/PGM/C12IN2-
NC
RB4/AN11
RB5/AN13/T1G
RB6/ICSPCLK
RB7/ICSPDAT
RE3/MCLR/VPP
RA0/AN0/ULPWU/C12IN0-
RA1/AN1/C12IN1-
RA2/AN2/VREF-/CVREF/C2IN+
RA3/AN3//VREF+/C1IN+
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3
RD2
RD1
RD0
RC3/SCK/SCL
RC2/P1A/CCP1
RC1/T1OSCI/CCP2
RC0/T1OSO/T1CKI
PIC16F882/883/884/886/887
DS40001291H-page 10 2006-2015 Microchip Technology Inc.
TABLE 4: 44-PIN QFN ALLOCATION TABLE (PIC16F884/887)
I/O
44-Pin QFN
Analog
Comparators
Timers
ECCP
EUSART
MSSP
Interrupt
Pull-up
Basic
RA0 19 AN0/ULPWU C12IN0- — —
RA1 20 AN1 C12IN1-
RA2 21 AN2 C2IN+ — VREF-/CVREF
RA3 22 AN3 C1IN+ VREF+
RA4 23 C1OUT T0CKI — —
RA5 24 AN4 C2OUT SS —— —
RA6 33 OSC2/CLKOUT
RA7 32 OSC1/CLKIN
RB0 9AN12 IOC/INT Y —
RB1 10 AN10 C12IN3- IOC Y
RB2 11 AN8 IOC Y —
RB3 12 AN9 C12IN2- IOC Y PGM
RB4 14 AN11 IOC Y —
RB5 15 AN13 T1G IOC Y
RB6 16 IOC YICSPCLK
RB7 17 IOC Y ICSPDAT
RC0 34 T1OSO/T1CKI — —
RC1 35 T1OSI CCP2
RC2 36 CCP1/P1A — —
RC3 37 SCK/SCL
RC4 42 SDI/SDA — —
RC5 43 SDO
RC6 44 TX/CK — —
RC7 1 RX/DT
RD0 38 — —
RD1 39
RD2 40 — —
RD3 41
RD4 2 — —
RD5 3 P1B
RD6 4 — P1C — —
RD7 5 P1D
RE0 25 AN5 — —
RE1 26 AN6
RE2 27 AN7 — —
RE3 18 Y(1) MCLR/VPP
— 7 VDD
—8 — — VDD
28 — — VDD
—6 — — VSS
30 — — VSS
—31 — — VSS
13 NC (no connect)
29 NC (no connect)
Note 1: Pull-up activated only with external MCLR configuration.
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2006-2015 Microchip Technology Inc. DS40001291H-page 11
PIC16F882/883/884/886/887
Pin Diagrams – PIC16F884/887, 44-Pin TQFP
10
11
2
3
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
37
5
4
PIC16F884/887
NC
RC0/T1OSO/T1CKI
RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN
VSS
VDD
RE2/AN7
RE1/AN6
RE0/AN5
RA5/AN4/SS/C2OUT
RA4/T0CKI/C1OUT
RC7/RX/DT
RD4
RD5/P1B
RD6/P1C
RD7/P1D
VSS
VDD
RB0/AN12/INT
RB1/AN10/C12IN3-
RB2/AN8
RB3/AN9/PGM/C12IN2-
NC
NC
RB4/AN11
RB5/AN13/T1G
RB6/ICSPCLK
RB7/ICSPDAT
RE3/MCLR/VPP
RA0/AN0/ULPWU/C12IN0-
RA1/AN1/C12IN1-
RA2/AN2/VREF-/CVREF/C2IN+
RA3/AN3//VREF+/C1IN+
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3
RD2
RD1
RD0
RC3/SCK/SCL
RC2/P1A/CCP1
RC1/T1OSCI/CCP2
NC
PIC16F882/883/884/886/887
DS40001291H-page 12 2006-2015 Microchip Technology Inc.
TABLE 5: 44-PIN TQFP ALLOCATION TABLE (PIC16F884/887)
I/O
44-Pin TQFP
Analog
Comparators
Timers
ECCP
EUSART
MSSP
Interrupt
Pull-up
Basic
RA0 19 AN0/ULPWU C12IN0- — —
RA1 20 AN1 C12IN1-
RA2 21 AN2 C2IN+ — VREF-/CVREF
RA3 22 AN3 C1IN+ VREF+
RA4 23 C1OUT T0CKI — —
RA5 24 AN4 C2OUT SS —— —
RA6 31 OSC2/CLKOUT
RA7 30 OSC1/CLKIN
RB0 8AN12 IOC/INT Y —
RB1 9 AN10 C12IN3- IOC Y
RB2 10 AN8 IOC Y —
RB3 11 AN9 C12IN2- IOC Y PGM
RB4 14 AN11 IOC Y —
RB5 15 AN13 T1G IOC Y
RB6 16 IOC YICSPCLK
RB7 17 IOC Y ICSPDAT
RC0 32 T1OSO/T1CKI — —
RC1 35 T1OSI CCP2
RC2 36 CCP1/P1A — —
RC3 37 SCK/SCL
RC4 42 SDI/SDA — —
RC5 43 SDO
RC6 44 TX/CK — —
RC7 1 RX/DT
RD0 38 — —
RD1 39
RD2 40 — —
RD3 41
RD4 2 — —
RD5 3 P1B
RD6 4 — P1C — —
RD7 5 P1D
RE0 25 AN5 — —
RE1 26 AN6
RE2 27 AN7 — —
RE3 18 Y(1) MCLR/VPP
— 7 VDD
—28 — — VDD
— 6 VSS
13 NC (no connect)
29 — — VSS
34 NC (no connect)
33 NC (no connect)
12 NC (no connect)
Note 1: Pull-up activated only with external MCLR configuration.
2006-2015 Microchip Technology Inc. DS40001291H-page 13
PIC16F882/883/884/886/887
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 14
2.0 Memory Organization................................................................................................................................................................. 22
3.0 I/O Ports ..................................................................................................................................................................................... 40
4.0 Oscillator Module (With Fail-Safe Clock Monitor)....................................................................................................................... 63
5.0 Timer0 Module ........................................................................................................................................................................... 75
6.0 Timer1 Module with Gate Control............................................................................................................................................... 78
7.0 Timer2 Module ........................................................................................................................................................................... 83
8.0 Comparator Module.................................................................................................................................................................... 85
9.0 Analog-to-Digital Converter (ADC) Module ................................................................................................................................ 99
10.0 Data EEPROM and Flash Program Memory Control............................................................................................................... 110
11.0 Capture/Compare/PWM Modules (CCP1 and CCP2).............................................................................................................. 121
12.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 148
13.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 175
14.0 Special Features of the CPU.................................................................................................................................................... 205
15.0 Instruction Set Summary.......................................................................................................................................................... 226
16.0 Development Support............................................................................................................................................................... 235
17.0 Electrical Specifications............................................................................................................................................................ 239
18.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 270
19.0 Packaging Information.............................................................................................................................................................. 298
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PIC16F882/883/884/886/887
DS40001291H-page 14 2006-2015 Microchip Technology Inc.
1.0 DEVICE OVERVIEW
The PIC16F882/883/884/886/887 devices are covered
by this data sheet. The PIC16F882/883/886 devices are
available in 28-pin PDIP, SOIC, SSOP and QFN
packages. The PIC16F884/887 are available in a 40-pin
PDIP and 44-pin QFN and TQFP packages. Figure 1-1
shows the block diagram of the PIC16F882/883/886
devices and Figure 1-2 shows a block diagram of the
PIC16F884/887 devices. Table 1-1 and Table 1-2 show
the corresponding pinout descriptions.
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2006-2015 Microchip Technology Inc. DS40001291H-page 15
PIC16F882/883/884/886/887
FIGURE 1-1: PIC16F882/883/886 BLOCK DIAGRAM
Flash
Program
Memory
13 Data Bus 8
Program
Bus
Instruction Reg
Program Counter
RAM
File
Registers
Direct Addr 7
RAM Addr 9
Addr MUX
Indirect
Addr
FSR Reg
STATUS Reg
MUX
ALU
W Reg
Instruction
Decode and
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
8
8
8
3
8-Level Stack 128(2)/256(1)/
2K(2)/4K(1)/
(13-Bit)
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
MCLR VSS
Brown-out
Reset
Timer0 Timer1
Data
EEPROM
128(2)/
EEDATA
EEADDR
T0CKI T1CKI
Configuration
Internal
Oscillator
T1G
VDD
8
Timer2 ECCP
Block
2 Analog ComparatorsVREF+
and Reference
Analog-To-Digital Converter
(ADC)
AN0
AN1
AN2
AN3
AN4
AN8
AN9
AN10
AN11
AN12
AN13
C1IN+
C12IN0-
C12IN1-
C12IN2-
C12IN3-
C1OUT
C2IN+
C2OUT
CCP1/P1A
P1B
P1C
P1D
PORTA
PORTC
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
PORTB
EUSART
TX/CK
RX/DT
PORTE
RE3
RA0
RA1
RA2
RA3
RA4
RA5
RA6
RA7
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7
Timer1
32 kHz
Oscillator
Master Synchronous
Serial Port (MSSP)
CCP2
CCP2
SDO
SDI/SDA
SCK/SCL
SS
VREF-
14
Note 1: PIC16F883 only.
2: MemHigh only.
VREF+
VREF-
CVREF
In-Circuit
Debugger
(ICD)
T1OSI
T1OSO
8K X 14
368 Bytes
256 Bytes
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PIC16F882/883/884/886/887
DS40001291H-page 16 2006-2015 Microchip Technology Inc.
FIGURE 1-2: PIC16F884/PIC16F887 BLOCK DIAGRAM
PORTD
RD0
RD1
RD2
RD3
RD4
RD5
RD6
RD7
Flash
Program
Memory
13 Data Bus 8
Program
Bus
Instruction Reg
Program Counter
RAM
File
Registers
Direct Addr 7
RAM Addr 9
Addr MUX
Indirect
Addr
FSR Reg
STATUS Reg
MUX
ALU
W Reg
Instruction
Decode and
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
8
8
8
3
8-Level Stack 256(1)/368 Bytes
4K(1)/8K X 14
(13-Bit)
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
MCLR VSS
Brown-out
Reset
Timer0 Timer1
Data
EEPROM
256 Bytes
EEDATA
EEADDR
T0CKI T1CKI
Configuration
Internal
Oscillator
T1G
VDD
8
Timer2 ECCP
Block
2 Analog Comparators
and Reference
Analog-To-Digital Converter
(ADC)
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
AN12
AN13
PORTA
PORTC
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
PORTB
EUSART
PORTE
RA0
RA1
RA2
RA3
RA4
RA5
RA6
RA7
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7
Timer1
32 kHz
Oscillator
Master Synchronous
Serial Port (MSSP)
CCP2
CCP2
14
Note 1: PIC16F884 only.
RE0
RE1
RE2
RE3
SDO
SDI/SDA
SCK/SCL
SS
CCP1/P1A
P1B
P1C
P1D
TX/CK
RX/DT
VREF+
VREF-
VREF+
VREF-
CVREF
C1IN+
C12IN0-
C12IN1-
C12IN2-
C12IN3-
C1OUT
C2IN+
C2OUT
In-Circuit
Debugger
(ICD)
T1OSI
T1OSO
2006-2015 Microchip Technology Inc. DS40001291H-page 17
PIC16F882/883/884/886/887
TABLE 1-1: PIC16F882/883/886 PINOUT DESCRIPTION
Name Function Input
Type Output
Type Description
RA0/AN0/ULPWU/C12IN0- RA0 TTL CMOS General purpose I/O.
AN0 AN A/D Channel 0 input.
ULPWU AN Ultra Low-Power Wake-up input.
C12IN0- AN Comparator C1 or C2 negative input.
RA1/AN1/C12IN1- RA1 TTL CMOS General purpose I/O.
AN1 AN A/D Channel 1 input.
C12IN1- AN Comparator C1 or C2 negative input.
RA2/AN2/VREF-/CVREF/C2IN+ RA2 TTL CMOS General purpose I/O.
AN2 AN A/D Channel 2.
VREF- AN A/D Negative Voltage Reference input.
CVREF AN Comparator Voltage Reference output.
C2IN+ AN Comparator C2 positive input.
RA3/AN3/VREF+/C1IN+ RA3 TTL General purpose I/O.
AN3 AN A/D Channel 3.
VREF+ AN Programming voltage.
C1IN+ AN Comparator C1 positive input.
RA4/T0CKI/C1OUT RA4 TTL CMOS General purpose I/O.
T0CKI ST Timer0 clock input.
C1OUT CMOS Comparator C1 output.
RA5/AN4/SS/C2OUT RA5 TTL CMOS General purpose I/O.
AN4 AN A/D Channel 4.
SS ST Slave Select input.
C2OUT CMOS Comparator C2 output.
RA6/OSC2/CLKOUT RA6 TTL CMOS General purpose I/O.
OSC2 XTAL Master Clear with internal pull-up.
CLKOUT CMOS FOSC/4 output.
RA7/OSC1/CLKIN RA7 TTL CMOS General purpose I/O.
OSC1 XTAL — Crystal/Resonator.
CLKIN ST External clock input/RC oscillator connection.
RB0/AN12/INT RB0 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
AN12 AN A/D Channel 12.
INT ST External interrupt.
RB1/AN10/P1C/C12IN3- RB1 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
AN10 AN A/D Channel 10.
P1C CMOS PWM output.
C12IN3- AN Comparator C1 or C2 negative input.
RB2/AN8/P1B RB2 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
AN8 AN A/D Channel 8.
P1B CMOS PWM output.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels
HV = High Voltage XTAL = Crystal
PIC16F882/883/884/886/887
DS40001291H-page 18 2006-2015 Microchip Technology Inc.
RB3/AN9/PGM/C12IN2- RB3 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
AN9 AN A/D Channel 9.
PGM ST Low-voltage ICSP™ Programming enable pin.
C12IN2- AN Comparator C1 or C2 negative input.
RB4/AN11/P1D RB4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
AN11 AN A/D Channel 11.
P1D CMOS PWM output.
RB5/AN13/T1G RB5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
AN13 AN A/D Channel 13.
T1G ST Timer1 Gate input.
RB6/ICSPCLK RB6 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
ICSPCLK ST Serial Programming Clock.
RB7/ICSPDAT RB7 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
ICSPDAT ST CMOS ICSP™ Data I/O.
RC0/T1OSO/T1CKI RC0 ST CMOS General purpose I/O.
T1OSO CMOS Timer1 oscillator output.
T1CKI ST Timer1 clock input.
RC1/T1OSI/CCP2 RC1 ST CMOS General purpose I/O.
T1OSI ST Timer1 oscillator input.
CCP2 ST CMOS Capture/Compare/PWM2.
RC2/P1A/CCP1 RC2 ST CMOS General purpose I/O.
P1A CMOS PWM output.
CCP1 ST CMOS Capture/Compare/PWM1.
RC3/SCK/SCL RC3 ST CMOS General purpose I/O.
SCK ST CMOS SPI clock.
SCL ST OD I2C™ clock.
RC4/SDI/SDA RC4 ST CMOS General purpose I/O.
SDI ST SPI data input.
SDA ST OD I2C data input/output.
RC5/SDO RC5 ST CMOS General purpose I/O.
SDO CMOS SPI data output.
RC6/TX/CK RC6 ST CMOS General purpose I/O.
TX CMOS EUSART asynchronous transmit.
CK ST CMOS EUSART synchronous clock.
RC7/RX/DT RC7 ST CMOS General purpose I/O.
RX ST EUSART asynchronous input.
DT ST CMOS EUSART synchronous data.
RE3/MCLR/VPP RE3 TTL General purpose input.
MCLR ST Master Clear with internal pull-up.
VPP HV Programming voltage.
VSS VSS Power Ground reference.
VDD VDD Power Positive supply.
TABLE 1-1: PIC16F882/883/886 PINOUT DESCRIPTION (CONTINUED)
Name Function Input
Type Output
Type Description
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels
HV = High Voltage XTAL = Crystal
2006-2015 Microchip Technology Inc. DS40001291H-page 19
PIC16F882/883/884/886/887
TABLE 1-2: PIC16F884/887 PINOUT DESCRIPTION
Name Function Input
Type Output
Type Description
RA0/AN0/ULPWU/C12IN0- RA0 TTL CMOS General purpose I/O.
AN0 AN A/D Channel 0 input.
ULPWU AN Ultra Low-Power Wake-up input.
C12IN0- AN Comparator C1 or C2 negative input.
RA1/AN1/C12IN1- RA1 TTL CMOS General purpose I/O.
AN1 AN A/D Channel 1 input.
C12IN1- AN Comparator C1 or C2 negative input.
RA2/AN2/VREF-/CVREF/C2IN+ RA2 TTL CMOS General purpose I/O.
AN2 AN A/D Channel 2.
VREF- AN A/D Negative Voltage Reference input.
CVREF AN Comparator Voltage Reference output.
C2IN+ AN Comparator C2 positive input.
RA3/AN3/VREF+/C1IN+ RA3 TTL CMOS General purpose I/O.
AN3 AN A/D Channel 3.
VREF+ AN A/D Positive Voltage Reference input.
C1IN+ AN Comparator C1 positive input.
RA4/T0CKI/C1OUT RA4 TTL CMOS General purpose I/O.
T0CKI ST Timer0 clock input.
C1OUT CMOS Comparator C1 output.
RA5/AN4/SS/C2OUT RA5 TTL CMOS General purpose I/O.
AN4 AN A/D Channel 4.
SS ST Slave Select input.
C2OUT CMOS Comparator C2 output.
RA6/OSC2/CLKOUT RA6 TTL CMOS General purpose I/O.
OSC2 XTAL Crystal/Resonator.
CLKOUT CMOS FOSC/4 output.
RA7/OSC1/CLKIN RA7 TTL CMOS General purpose I/O.
OSC1 XTAL — Crystal/Resonator.
CLKIN ST External clock input/RC oscillator connection.
RB0/AN12/INT RB0 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
AN12 AN A/D Channel 12.
INT ST External interrupt.
RB1/AN10/C12IN3- RB1 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
AN10 AN A/D Channel 10.
C12IN3- AN Comparator C1 or C2 negative input.
RB2/AN8 RB2 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
AN8 AN A/D Channel 8.
RB3/AN9/PGM/C12IN2- RB3 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
AN9 AN A/D Channel 9.
PGM ST Low-voltage ICSP™ Programming enable pin.
C12IN2- AN Comparator C1 or C2 negative input.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels
HV = High Voltage XTAL = Crystal
PIC16F882/883/884/886/887
DS40001291H-page 20 2006-2015 Microchip Technology Inc.
RB4/AN11 RB4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
AN11 AN A/D Channel 11.
RB5/AN13/T1G RB5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
AN13 AN A/D Channel 13.
T1G ST Timer1 Gate input.
RB6/ICSPCLK RB6 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
ICSPCLK ST Serial Programming Clock.
RB7/ICSPDAT RB7 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
ICSPDAT ST TTL ICSP™ Data I/O.
RC0/T1OSO/T1CKI RC0 ST CMOS General purpose I/O.
T1OSO XTAL Timer1 oscillator output.
T1CKI ST Timer1 clock input.
RC1/T1OSI/CCP2 RC1 ST CMOS General purpose I/O.
T1OSI XTAL Timer1 oscillator input.
CCP2 ST CMOS Capture/Compare/PWM2.
RC2/P1A/CCP1 RC2 ST CMOS General purpose I/O.
P1A ST CMOS PWM output.
CCP1 CMOS Capture/Compare/PWM1.
RC3/SCK/SCL RC3 ST CMOS General purpose I/O.
SCK ST CMOS SPI clock.
SCL ST OD I2C™ clock.
RC4/SDI/SDA RC4 ST CMOS General purpose I/O.
SDI ST SPI data input.
SDA ST OD I2C data input/output.
RC5/SDO RC5 ST CMOS General purpose I/O.
SDO CMOS SPI data output.
RC6/TX/CK RC6 ST CMOS General purpose I/O.
TX CMOS EUSART asynchronous transmit.
CK ST CMOS EUSART synchronous clock.
RC7/RX/DT RC7 ST CMOS General purpose I/O.
RX ST EUSART asynchronous input.
DT ST CMOS EUSART synchronous data.
RD0 RD0 TTL CMOS General purpose I/O.
RD1 RD1 TTL CMOS General purpose I/O.
RD2 RD2 TTL CMOS General purpose I/O.
RD3 RD3 TTL CMOS General purpose I/O.
RD4 RD4 TTL CMOS General purpose I/O.
RD5/P1B RD5 TTL CMOS General purpose I/O.
P1B CMOS PWM output.
RD6/P1C RD6 TTL CMOS General purpose I/O.
P1C CMOS PWM output.
TABLE 1-2: PIC16F884/887 PINOUT DESCRIPTION (CONTINUED)
Name Function Input
Type Output
Type Description
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels
HV = High Voltage XTAL = Crystal
2006-2015 Microchip Technology Inc. DS40001291H-page 21
PIC16F882/883/884/886/887
RD7/P1D RD7 TTL CMOS General purpose I/O.
P1D AN PWM output.
RE0/AN5 RE0 TTL CMOS General purpose I/O.
AN5 AN A/D Channel 5.
RE1/AN6 RE1 TTL CMOS General purpose I/O.
AN6 AN A/D Channel 6.
RE2/AN7 RE2 TTL CMOS General purpose I/O.
AN7 AN A/D Channel 7.
RE3/MCLR/VPP RE3 TTL General purpose input.
MCLR ST Master Clear with internal pull-up.
VPP HV Programming voltage.
VSS VSS Power Ground reference.
VDD VDD Power Positive supply.
TABLE 1-2: PIC16F884/887 PINOUT DESCRIPTION (CONTINUED)
Name Function Input
Type Output
Type Description
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels
HV = High Voltage XTAL = Crystal
PIC16F882/883/884/886/887
DS40001291H-page 22 2006-2015 Microchip Technology Inc.
2.0 MEMORY ORGANIZATION
2.1 Program Memory Organization
The PIC16F882/883/884/886/887 devices have a 13-bit
program counter capable of addressing a 2K x 14
(0000h-07FFh) for the PIC16F882, 4K x 14 (0000h-
0FFFh) for the PIC16F883/PIC16F884, and 8K x 14
(0000h-1FFFh) for the PIC16F886/PIC16F887 program
memory space. Accessing a location above these
boundaries will cause a wrap-around within the first 8K x
14 space. The Reset vector is at 0000h and the interrupt
vector is at 0004h (see Figures 2-2 and 2-3).
FIGURE 2-1: PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16F882
FIGURE 2-2: PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16F883/PIC16F884
FIGURE 2-3: PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16F886/PIC16F887
PC<12:0>
13
0000h
0004h
0005h
07FFh
Stack Level 1
Stack Level 8
Reset Vector
Interrupt Vector
CALL, RETURN
RETFIE, RETLW
Stack Level 2
Page 0
On-Chip
Program
Memory
PC<12:0>
13
0000h
0004h
0005h
07FFh
0800h
Stack Level 1
Stack Level 8
Reset Vector
Interrupt Vector
CALL, RETURN
RETFIE, RETLW
Stack Level 2
Page 0
Page 1 0FFFh
On-Chip
Program
Memory
PC<12:0>
13
0000h
0004h
0005h
07FFh
0800h
17FFh
Stack Level 1
Stack Level 8
Reset Vector
Interrupt Vector
CALL, RETURN
RETFIE, RETLW
Stack Level 2
Page 0
Page 1
Page 2
Page 3
0FFFh
1000h
1FFFh
1800h
On-Chip
Program
Memory
2006-2015 Microchip Technology Inc. DS40001291H-page 23
PIC16F882/883/884/886/887
2.2 Data Memory Organization
The data memory (see Figures 2-2 and 2-3) is
partitioned into four banks which contain the General
Purpose Registers (GPR) and the Special Function
Registers (SFR). The Special Function Registers are
located in the first 32 locations of each bank. The
General Purpose Registers, implemented as static RAM,
are located in the last 96 locations of each Bank.
Register locations F0h-FFh in Bank 1, 170h-17Fh in
Bank 2 and 1F0h-1FFh in Bank 3, point to addresses
70h-7Fh in Bank 0. The actual number of General
Purpose Resisters (GPR) implemented in each Bank
depends on the device. Details are shown in Figures 2-5
and 2-6. All other RAM is unimplemented and returns ‘0
when read. RP<1:0> of the STATUS register are the
bank select bits:
RP1 RP0
00Bank 0 is selected
01Bank 1 is selected
10Bank 2 is selected
11Bank 3 is selected
2.2.1 GENERAL PURPOSE REGISTER
FILE
The register file is organized as 128 x 8 in the
PIC16F882, 256 x 8 in the PIC16F883/PIC16F884, and
368 x 8 in the PIC16F886/PIC16F887. Each register is
accessed, either directly or indirectly, through the File
Select Register (FSR) (see Section 2.4 “Indirect
Addressing, INDF and FSR Registers”).
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral functions for controlling the
desired operation of the device (see Table 2-1). These
registers are static RAM.
The special registers can be classified into two sets:
core and peripheral. The Special Function Registers
associated with the “core” are described in this section.
Those related to the operation of the peripheral
features are described in the section of that peripheral
feature.
PIC16F882/883/884/886/887
DS40001291H-page 24 2006-2015 Microchip Technology Inc.
FIGURE 2-4: PIC16F882 SPECIAL FUNCTION REGISTERS
File File File File
Address Address Address Address
Indirect addr. (1) 00h Indirect addr. (1) 80h Indirect addr. (1) 100h Indirect addr. (1) 180h
TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h
PCL 02h PCL 82h PCL 102h PCL 182h
STATUS 03h STATUS 83h STATUS 103h STATUS 183h
FSR 04h FSR 84h FSR 104h FSR 184h
PORTA 05h TRISA 85h WDTCON 105h SRCON 185h
PORTB 06h TRISB 86h PORTB 106h TRISB 186h
PORTC 07h TRISC 87h CM1CON0 107h BAUDCTL 187h
08h 88h CM2CON0 108h ANSEL 188h
PORTE 09h TRISE 89h CM2CON1 109h ANSELH 189h
PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah
INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh
PIR1 0Ch PIE1 8Ch EEDAT 10Ch EECON1 18Ch
PIR2 0Dh PIE2 8Dh EEADR 10Dh EECON2(1) 18Dh
TMR1L 0Eh PCON 8Eh EEDATH 10Eh Reserved 18Eh
TMR1H 0Fh OSCCON 8Fh EEADRH 10Fh Reserved 18Fh
T1CON 10h OSCTUNE 90h 110h 190h
TMR2 11h SSPCON2 91h 111h 191h
T2CON 12h PR2 92h 112h 192h
SSPBUF 13h SSPADD 93h 113h 193h
SSPCON 14h SSPSTAT 94h 114h 194h
CCPR1L 15h WPUB 95h 115h 195h
CCPR1H 16h IOCB 96h 116h 196h
CCP1CON 17h VRCON 97h 117h 197h
RCSTA 18h TXSTA 98h 118h 198h
TXREG 19h SPBRG 99h 119h 199h
RCREG 1Ah SPBRGH 9Ah 11Ah 19Ah
CCPR2L 1Bh PWM1CON 9Bh 11Bh 19Bh
CCPR2H 1Ch ECCPAS 9Ch 11Ch 19Ch
CCP2CON 1Dh PSTRCON 9Dh 11Dh 19Dh
ADRESH 1Eh ADRESL 9Eh 11Eh 19Eh
ADCON0 1Fh ADCON1 9Fh 11Fh 19Fh
General
Purpose
Registers
96 Bytes
20h General
Purpose
Registers
32 Bytes
A0h
BFh
120h 1A0h
C0h
EFh 16Fh 1EFh
accesses
70h-7Fh
F0h accesses
70h-7Fh
170h accesses
70h-7Fh
1F0h
7Fh FFh 17Fh 1FFh
Bank 0 Bank 1 Bank 2 Bank 3
Unimplemented data memory locations, read as ‘0’.
Note 1: Not a physical register.
2006-2015 Microchip Technology Inc. DS40001291H-page 25
PIC16F882/883/884/886/887
FIGURE 2-5: PIC16F883/PIC16F884 SPECIAL FUNCTION REGISTERS
File File File File
Address Address Address Address
Indirect addr. (1) 00h Indirect addr. (1) 80h Indirect addr. (1) 100h Indirect addr. (1) 180h
TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h
PCL 02h PCL 82h PCL 102h PCL 182h
STATUS 03h STATUS 83h STATUS 103h STATUS 183h
FSR 04h FSR 84h FSR 104h FSR 184h
PORTA 05h TRISA 85h WDTCON 105h SRCON 185h
PORTB 06h TRISB 86h PORTB 106h TRISB 186h
PORTC 07h TRISC 87h CM1CON0 107h BAUDCTL 187h
PORTD(2) 08h TRISD(2) 88h CM2CON0 108h ANSEL 188h
PORTE 09h TRISE 89h CM2CON1 109h ANSELH 189h
PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah
INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh
PIR1 0Ch PIE1 8Ch EEDAT 10Ch EECON1 18Ch
PIR2 0Dh PIE2 8Dh EEADR 10Dh EECON2(1) 18Dh
TMR1L 0Eh PCON 8Eh EEDATH 10Eh Reserved 18Eh
TMR1H 0Fh OSCCON 8Fh EEADRH 10Fh Reserved 18Fh
T1CON 10h OSCTUNE 90h 110h 190h
TMR2 11h SSPCON2 91h 111h 191h
T2CON 12h PR2 92h 112h 192h
SSPBUF 13h SSPADD 93h 113h 193h
SSPCON 14h SSPSTAT 94h 114h 194h
CCPR1L 15h WPUB 95h 115h 195h
CCPR1H 16h IOCB 96h 116h 196h
CCP1CON 17h VRCON 97h 117h 197h
RCSTA 18h TXSTA 98h 118h 198h
TXREG 19h SPBRG 99h 119h 199h
RCREG 1Ah SPBRGH 9Ah 11Ah 19Ah
CCPR2L 1Bh PWM1CON 9Bh 11Bh 19Bh
CCPR2H 1Ch ECCPAS 9Ch 11Ch 19Ch
CCP2CON 1Dh PSTRCON 9Dh 11Dh 19Dh
ADRESH 1Eh ADRESL 9Eh 11Eh 19Eh
ADCON0 1Fh ADCON1 9Fh 11Fh 19Fh
General
Purpose
Registers
96 Bytes
20h General
Purpose
Registers
80 Bytes
A0h General
Purpose
Registers
80 Bytes
120h 1A0h
EFh 16Fh 1EFh
accesses
70h-7Fh F0h accesses
70h-7Fh 170h accesses
70h-7Fh 1F0h
7Fh FFh 17Fh 1FFh
Bank 0Bank 1Bank 2Bank 3
Unimplemented data memory locations, read as ‘0’.
Note 1: Not a physical register.
2: PIC16F884 only.
PIC16F882/883/884/886/887
DS40001291H-page 26 2006-2015 Microchip Technology Inc.
FIGURE 2-6: PIC16F886/PIC16F887 SPECIAL FUNCTION REGISTERS
File File File File
Address Address Address Address
Indirect addr. (1) 00h Indirect addr. (1) 80h Indirect addr. (1) 100h Indirect addr. (1) 180h
TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h
PCL 02h PCL 82h PCL 102h PCL 182h
STATUS 03h STATUS 83h STATUS 103h STATUS 183h
FSR 04h FSR 84h FSR 104h FSR 184h
PORTA 05h TRISA 85h WDTCON 105h SRCON 185h
PORTB 06h TRISB 86h PORTB 106h TRISB 186h
PORTC 07h TRISC 87h CM1CON0 107h BAUDCTL 187h
PORTD(2) 08h TRISD(2) 88h CM2CON0 108h ANSEL 188h
PORTE 09h TRISE 89h CM2CON1 109h ANSELH 189h
PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah
INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh
PIR1 0Ch PIE1 8Ch EEDAT 10Ch EECON1 18Ch
PIR2 0Dh PIE2 8Dh EEADR 10Dh EECON2(1) 18Dh
TMR1L 0Eh PCON 8Eh EEDATH 10Eh Reserved 18Eh
TMR1H 0Fh OSCCON 8Fh EEADRH 10Fh Reserved 18Fh
T1CON 10h OSCTUNE 90h
General
Purpose
Registers
16 Bytes
110h
General
Purpose
Registers
16 Bytes
190h
TMR2 11h SSPCON2 91h 111h 191h
T2CON 12h PR2 92h 112h 192h
SSPBUF 13h SSPADD 93h 113h 193h
SSPCON 14h SSPSTAT 94h 114h 194h
CCPR1L 15h WPUB 95h 115h 195h
CCPR1H 16h IOCB 96h 116h 196h
CCP1CON 17h VRCON 97h 117h 197h
RCSTA 18h TXSTA 98h 118h 198h
TXREG 19h SPBRG 99h 119h 199h
RCREG 1Ah SPBRGH 9Ah 11Ah 19Ah
CCPR2L 1Bh PWM1CON 9Bh 11Bh 19Bh
CCPR2H 1Ch ECCPAS 9Ch 11Ch 19Ch
CCP2CON 1Dh PSTRCON 9Dh 11Dh 19Dh
ADRESH 1Eh ADRESL 9Eh 11Eh 19Eh
ADCON0 1Fh ADCON1 9Fh 11Fh 19Fh
General
Purpose
Registers
96 Bytes
20h
3Fh
General
Purpose
Registers
80 Bytes
A0h
General
Purpose
Registers
80 Bytes
120h
General
Purpose
Registers
80 Bytes
1A0h
40h
6Fh EFh 16Fh 1EFh
70h accesses
70h-7Fh F0h accesses
70h-7Fh 170h accesses
70h-7Fh 1F0h
7Fh FFh 17Fh 1FFh
Bank 0Bank 1Bank 2Bank 3
Unimplemented data memory locations, read as ‘0’.
Note 1: Not a physical register.
2: PIC16F887 only.
2006-2015 Microchip Technology Inc. DS40001291H-page 27
PIC16F882/883/884/886/887
TABLE 2-1: PIC16F882/883/884/886/887 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR Value on all
other Resets
Bank 0
00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx
01h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu
02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000
03h STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu(5)
04h FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu
05h PORTA(3) RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx xxxx 0000 0000
06h PORTB(3) RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 0000 0000
07h PORTC(3) RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 0000 0000
08h PORTD(3,4) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx 0000 0000
09h PORTE(3) — — —RE3RE2
(4) RE1(4) RE0(4) ---- xxxx ---- 0000
0Ah PCLATH — — Write Buffer for upper 5 bits of Program Counter ---0 0000 ---0 0000
0Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF(1) 0000 000x 0000 000u
0Ch PIR1 ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 0000 0000
0Dh PIR2 OSFIF C2IF C1IF EEIF BCLIF ULPWUIF CCP2IF 0000 00-0 0000 0000
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu
11h TMR2 Timer2 Module Register 0000 0000 0000 0000
12h T2CON TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON(2) WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
15h CCPR1L Capture/Compare/PWM Register 1 Low Byte (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM Register 1 High Byte (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 0000
19h TXREG EUSART Transmit Data Register 0000 0000 0000 0000
1Ah RCREG EUSART Receive Data Register 0000 0000 0000 0000
1Bh CCPR2L Capture/Compare/PWM Register 2 Low Byte (LSB) xxxx xxxx uuuu uuuu
1Ch CCPR2H Capture/Compare/PWM Register 2 High Byte (MSB) xxxx xxxx uuuu uuuu
1Dh CCP2CON DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 000
1Eh ADRESH A/D Result Register High Byte xxxx xxxx uuuu uuuu
1Fh ADCON0 ADCS1 ADCS0 CHS3 CHS2 CHS1 CHS0 GO/
DONE ADON 0000 0000 00-0 0000
Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: MCLR and WDT Reset do not affect the previous value data latch. The RBIF bit will be cleared upon Reset but will set again if the
mismatch exists.
2: When SSPCON register bits SSPM<3:0> = 1001, any reads or writes to the SSPADD SFR address are accessed through the SSPMSK
register. See Registers 13-2 and 13-4 for more details.
3: Port pins with analog functions controlled by the ANSEL and ANSELH registers will read ‘0’ immediately after a Reset even though the data
latches are either undefined (POR) or unchanged (other Resets).
4: PIC16F884/PIC16F887 only.
5: See Table 14-5 for Reset value for specific condition.
PIC16F882/883/884/886/887
DS40001291H-page 28 2006-2015 Microchip Technology Inc.
TABLE 2-2: PIC16F882/883/884/886/887 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR Value on all
other Resets
Bank 1
80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx
81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
82h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000
83h STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu(5)
84h FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu
85h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111
86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111
87h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
88h TRISD(3) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 1111 1111
89h TRISE — — TRISE3 TRISE2(3) TRISE1(3) TRISE0(3) ---- 1111 ---- 1111
8Ah PCLATH Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF(1) 0000 000x 0000 000u
8Ch PIE1 ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 0000 0000
8Dh PIE2 OSFIE C2IE C1IE EEIE BCLIE ULPWUIE CCP2IE 0000 00-0 0000 0000
8Eh PCON ULPWUE SBOREN —PORBOR --01 --qq --0u --uu(4,6)
8Fh OSCCON IRCF2 IRCF1 IRCF0 OSTS HTS LTS SCS -110 q000 -110 q000
90h OSCTUNE TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 ---u uuuu
91h SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000
92h PR2 Timer2 Period Register 1111 1111 1111 1111
93h SSPADD(2) Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000
93h SSPMSK(2) MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 1111 1111 1111 1111
94h SSPSTAT SMP CKE D/A PSR/WUA BF 0000 0000 0000 0000
95h WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 1111 1111
96h IOCB IOCB7 IOCB6 IOCB5 IOCB4 IOCB3 IOCB2 IOCB1 IOCB0 0000 0000 0000 0000
97h VRCON VREN VROE VRR VRSS VR3 VR2 VR1 VR0 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 -010
99h SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000
9Ah SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000 0000 0000
9Bh PWM1CON PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 0000 0000 0000 0000
9Ch ECCPAS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 0000 0000
9Dh PSTRCON STRSYNC STRD STRC STRB STRA ---0 0001 ---0 0001
9Eh ADRESL A/D Result Register Low Byte xxxx xxxx uuuu uuuu
9Fh ADCON1 ADFM —VCFG1VCFG0 0-00 ---- 0-00 ----
Legend: = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: MCLR and WDT Reset do not affect the previous value data latch. The RBIF bit will be cleared upon Reset but will set again if the mismatch
exists.
2: Accessible only when SSPCON register bits SSPM<3:0> = 1001.
3: PIC16F884/PIC16F887 only.
4: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.
5: See Table 14-5 for Reset value for specific condition.
6: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.
2006-2015 Microchip Technology Inc. DS40001291H-page 29
PIC16F882/883/884/886/887
TABLE 2-3: PIC16F882/883/884/886/887 SPECIAL FUNCTION REGISTERS SUMMARY BANK 2
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR Value on all
other Resets
Bank 2
100h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx
101h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu
102h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000
103h STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu(3)
104h FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu
105h WDTCON — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000 ---0 1000
106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 0000 0000
107h CM1CON0 C1ON C1OUT C1OE C1POL C1R C1CH1 C1CH0 0000 -000 0000 0-00
108h CM2CON0 C2ON C2OUT C2OE C2POL C2R C2CH1 C2CH0 0000 -000 0000 0-00
109h CM2CON1 MC1OUT MC2OUT C1RSEL C2RSEL T1GSS C2SYNC 0000 --10 0000 0--0
10Ah PCLATH — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
10Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF(1) 0000 000x 0000 000u
10Ch EEDAT EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 0000 0000
10Dh EEADR EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 0000 0000
10Eh EEDATH EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0 --00 0000 --00 0000
10Fh EEADRH EEADRH4(2) EEADRH3 EEADRH2 EEADRH1 EEADRH0 ---- 0000 ---0 0000
Legend: = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: MCLR and WDT Reset does not affect the previous value data latch. The RBIF bit will be cleared upon Reset but will set again if the
mismatch exists.
2: PIC16F886/PIC16F887 only.
3: See Table 14-5 for Reset value for specific condition.
TABLE 2-4: PIC16F882/883/884/886/887 SPECIAL FUNCTION REGISTERS SUMMARY BANK 3
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR Value on all
other Resets
Bank 3
180h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx
181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
182h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000
183h STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu(3)
184h FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu
185h SRCON SR1 SR0 C1SEN C2REN PULSS PULSR FVREN 0000 00-0 0000 00-0
186h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111
187h BAUDCTL ABDOVF RCIDL SCKP BRG16 WUE ABDEN 01-0 0-00 01-0 0-00
188h ANSEL ANS7(2) ANS6(2) ANS5(2) ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111
189h ANSELH ANS13 ANS12 ANS11 ANS10 ANS9 ANS8 --11 1111 1111 1111
18Ah PCLATH — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF(1) 0000 000x 0000 000u
18Ch EECON1 EEPGD WRERR WREN WR RD x--- x000 ---- q000
18Dh EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- ---- ----
Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: MCLR and WDT Reset does not affect the previous value data latch. The RBIF bit will be cleared upon Reset but will set again if the
mismatch exists.
2: PIC16F884/PIC16F887 only.
3: See Table 14-5 for Reset value for specific condition.
PIC16F882/883/884/886/887
DS40001291H-page 30 2006-2015 Microchip Technology Inc.
2.2.2.1 STATUS Register
The STATUS register, shown in Register 2-1, contains:
the arithmetic status of the ALU
the Reset status
the bank select bits for data memory (GPR and
SFR)
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
For example, CLRF STATUS, will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as ‘000u u1uu’ (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any Status bits. For other instructions not affect-
ing any Status bits, see Section 15.0 “Instruction Set
Summary”
REGISTER DEFINITIONS: STATUS
Note 1: The C and DC bits operate as a Borrow
and Digit Borrow out bit, respectively, in
subtraction.
REGISTER 2-1: STATUS: STATUS REGISTER
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO PD ZDC
(1) C(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h-1FFh)
0 = Bank 0, 1 (00h-FFh)
bit 6-5 RP<1:0>: Register Bank Select bits (used for direct addressing)
00 = Bank 0 (00h-7Fh)
01 = Bank 1 (80h-FFh)
10 = Bank 2 (100h-17Fh)
11 = Bank 3 (180h-1FFh)
bit 4 TO: Time-out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 3 PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(1)
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit 0 C: Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second
operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the
source register.
2006-2015 Microchip Technology Inc. DS40001291H-page 31
PIC16F882/883/884/886/887
2.2.2.2 OPTION Register
The OPTION register, shown in Register 2-2, is a
readable and writable register, which contains various
control bits to configure:
Timer0/WDT prescaler
External INT interrupt
•Timer0
Weak pull-ups on PORTB
REGISTER DEFINITIONS: OPTION REGISTER
Note: To achieve a 1:1 prescaler assignment for
Timer0, assign the prescaler to the WDT
by setting PSA bit of the OPTION register
to ‘1’. See Section 6.3 “Timer1 Pres-
caler”.
REGISTER 2-2: OPTION_REG: OPTION REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual PORT latch values
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of INT pin
0 = Interrupt on falling edge of INT pin
bit 5 T0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (FOSC/4)
bit 4 T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS<2:0>: Prescaler Rate Select bits
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Bit Value Timer0 Rate WDT Rate
PIC16F882/883/884/886/887
DS40001291H-page 32 2006-2015 Microchip Technology Inc.
2.2.2.3 INTCON Register
The INTCON register, shown in Register 2-3, is a
readable and writable register, which contains the various
enable and flag bits for TMR0 register overflow, PORTB
change and external INT pin interrupts.
REGISTER DEFINITIONS: INTERRUPT CONTROL
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.
REGISTER 2-3: INTCON: INTERRUPT CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE PEIE T0IE INTE RBIE(1) T0IF(2) INTF RBIF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts
0 = Disables all interrupts
bit 6 PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5 T0IE: Timer0 Overflow Interrupt Enable bit
1 = Enables the Timer0 interrupt
0 = Disables the Timer0 interrupt
bit 4 INTE: INT External Interrupt Enable bit
1 = Enables the INT external interrupt
0 = Disables the INT external interrupt
bit 3 RBIE: PORTB Change Interrupt Enable bit(1)
1 = Enables the PORTB change interrupt
0 = Disables the PORTB change interrupt
bit 2 T0IF: Timer0 Overflow Interrupt Flag bit(2)
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1 INTF: INT External Interrupt Flag bit
1 = The INT external interrupt occurred (must be cleared in software)
0 = The INT external interrupt did not occur
bit 0 RBIF: PORTB Change Interrupt Flag bit
1 = When at least one of the PORTB general purpose I/O pins changed state (must be cleared in software)
0 = None of the PORTB general purpose I/O pins have changed state
Note 1: IOCB register must also be enabled.
2: T0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should be initialized before clearing
T0IF bit.
2006-2015 Microchip Technology Inc. DS40001291H-page 33
PIC16F882/883/884/886/887
2.2.2.4 PIE1 Register
The PIE1 register contains the interrupt enable bits, as
shown in Register 2-4.
REGISTER DEFINITIONS: PIE1
Note: Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
REGISTER 2-4: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0
bit 6 ADIE: A/D Converter (ADC) Interrupt Enable bit
1 = Enables the ADC interrupt
0 = Disables the ADC interrupt
bit 5 RCIE: EUSART Receive Interrupt Enable bit
1 = Enables the EUSART receive interrupt
0 = Disables the EUSART receive interrupt
bit 4 TXIE: EUSART Transmit Interrupt Enable bit
1 = Enables the EUSART transmit interrupt
0 = Disables the EUSART transmit interrupt
bit 3 SSPIE: Master Synchronous Serial Port (MSSP) Interrupt Enable bit
1 = Enables the MSSP interrupt
0 = Disables the MSSP interrupt
bit 2 CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1 TMR2IE: Timer2 to PR2 Match Interrupt Enable bit
1 = Enables the Timer2 to PR2 match interrupt
0 = Disables the Timer2 to PR2 match interrupt
bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit
1 = Enables the Timer1 overflow interrupt
0 = Disables the Timer1 overflow interrupt
PIC16F882/883/884/886/887
DS40001291H-page 34 2006-2015 Microchip Technology Inc.
2.2.2.5 PIE2 Register
The PIE2 register contains the interrupt enable bits, as
shown in Register 2-5.
REGISTER DEFINITIONS: PIE2
Note: Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
REGISTER 2-5: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0
OSFIE C2IE C1IE EEIE BCLIE ULPWUIE — CCP2IE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 OSFIE: Oscillator Fail Interrupt Enable bit
1 = Enables oscillator fail interrupt
0 = Disables oscillator fail interrupt
bit 6 C2IE: Comparator C2 Interrupt Enable bit
1 = Enables Comparator C2 interrupt
0 = Disables Comparator C2 interrupt
bit 5 C1IE: Comparator C1 Interrupt Enable bit
1 = Enables Comparator C1 interrupt
0 = Disables Comparator C1 interrupt
bit 4 EEIE: EEPROM Write Operation Interrupt Enable bit
1 = Enables EEPROM write operation interrupt
0 = Disables EEPROM write operation interrupt
bit 3 BCLIE: Bus Collision Interrupt Enable bit
1 = Enables Bus Collision interrupt
0 = Disables Bus Collision interrupt
bit 2 ULPWUIE: Ultra Low-Power Wake-up Interrupt Enable bit
1 = Enables Ultra Low-Power Wake-up interrupt
0 = Disables Ultra Low-Power Wake-up interrupt
bit 1 Unimplemented: Read as ‘0
bit 0 CCP2IE: CCP2 Interrupt Enable bit
1 = Enables CCP2 interrupt
0 = Disables CCP2 interrupt
fl #0 slavemnasmr ‘20 Mas|ev Capmve made Cnmgare mode PWM mode
2006-2015 Microchip Technology Inc. DS40001291H-page 35
PIC16F882/883/884/886/887
2.2.2.6 PIR1 Register
The PIR1 register contains the interrupt flag bits, as
shown in Register 2-6.
REGISTER DEFINITIONS: PIR1
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
REGISTER 2-6: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1
U-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as0
bit 6 ADIF: A/D Converter Interrupt Flag bit
1 = A/D conversion complete (must be cleared in software)
0 = A/D conversion has not completed or has not been started
bit 5 RCIF: EUSART Receive Interrupt Flag bit
1 = The EUSART receive buffer is full (cleared by reading RCREG)
0 = The EUSART receive buffer is not full
bit 4 TXIF: EUSART Transmit Interrupt Flag bit
1 = The EUSART transmit buffer is empty (cleared by writing to TXREG)
0 = The EUSART transmit buffer is full
bit 3 SSPIF: Master Synchronous Serial Port (MSSP) Interrupt Flag bit
1 = The MSSP interrupt condition has occurred, and must be cleared in software before returning from the Interrupt Service Rou-
tine. The conditions that will set this bit are:
SPI A transmission/reception has taken place
I2 C Slave/Master
A transmission/reception has taken place
I2 C Master
The initiated Start condition was completed by the MSSP module
The initiated Stop condition was completed by the MSSP module
The initiated restart condition was completed by the MSSP module
The initiated Acknowledge condition was completed by the MSSP module
A Start condition occurred while the MSSP module was idle (Multi-master system)
A Stop condition occurred while the MSSP module was idle (Multi-master system)
0 = No MSSP interrupt condition has occurred
bit 2 CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode
bit 1 TMR2IF: Timer2 to PR2 Interrupt Flag bit
1 = A Timer2 to PR2 match occurred (must be cleared in software)
0 = No Timer2 to PR2 match occurred
bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit
1 = The TMR1 register overflowed (must be cleared in software)
0 = The TMR1 register did not overflow
Cagluve mode Comgare mode PWM mode
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2.2.2.7 PIR2 Register
The PIR2 register contains the interrupt flag bits, as
shown in Register 2-7.
REGISTER DEFINITIONS: PIR2
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
REGISTER 2-7: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0
OSFIF C2IF C1IF EEIF BCLIF ULPWUIF — CCP2IF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 OSFIF: Oscillator Fail Interrupt Flag bit
1 = System oscillator failed, clock input has changed to INTOSC (must be cleared in software)
0 = System clock operating
bit 6 C2IF: Comparator C2 Interrupt Flag bit
1 = Comparator output (C2OUT bit) has changed (must be cleared in software)
0 = Comparator output (C2OUT bit) has not changed
bit 5 C1IF: Comparator C1 Interrupt Flag bit
1 = Comparator output (C1OUT bit) has changed (must be cleared in software)
0 = Comparator output (C1OUT bit) has not changed
bit 4 EEIF: EE Write Operation Interrupt Flag bit
1 = Write operation completed (must be cleared in software)
0 = Write operation has not completed or has not started
bit 3 BCLIF: Bus Collision Interrupt Flag bit
1 = A bus collision has occurred in the MSSP when configured for I2C Master mode
0 = No bus collision has occurred
bit 2 ULPWUIF: Ultra Low-Power Wake-up Interrupt Flag bit
1 = Wake-up condition has occurred (must be cleared in software)
0 = No Wake-up condition has occurred
bit 1 Unimplemented: Read as ‘0
bit 0 CCP2IF: CCP2 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode
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2.2.2.8 PCON Register
The Power Control (PCON) register (see Register 2-8)
contains flag bits to differentiate between a:
Power-on Reset (POR)
Brown-out Reset (BOR)
Watchdog Timer Reset (WDT)
External MCLR Reset
The PCON register also controls the Ultra Low-Power
Wake-up and software enable of the BOR.
REGISTER DEFINITIONS: PCON
REGISTER 2-8: PCON: POWER CONTROL REGISTER
U-0 U-0 R/W-0 R/W-1 U-0 U-0 R/W-0 R/W-x
ULPWUE SBOREN(1) —PORBOR
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0
bit 5 ULPWUE: Ultra Low-Power Wake-up Enable bit
1 = Ultra Low-Power Wake-up enabled
0 = Ultra Low-Power Wake-up disabled
bit 4 SBOREN: Software BOR Enable bit(1)
1 = BOR enabled
0 = BOR disabled
bit 3-2 Unimplemented: Read as ‘0
bit 1 POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Note 1: BOREN<1:0> = 01 in the Configuration Word Register 1 for this bit to control the BOR.
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2.3 PCL and PCLATH
The Program Counter (PC) is 13 bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC<12:8>) is not directly
readable or writable and comes from PCLATH. On any
Reset, the PC is cleared. Figure 2-7 shows the two
situations for the loading of the PC. The upper example
in Figure 2-7 shows how the PC is loaded on a write to
PCL (PCLATH<4:0> PCH). The lower example in
Figure 2-7 shows how the PC is loaded during a CALL or
GOTO instruction (PCLATH<4:3> PCH).
FIGURE 2-7: LOADING OF PC IN
DIFFERENT SITUATIONS
2.3.1 MODIFYING PCL
Executing any instruction with the PCL register as the
destination simultaneously causes the Program
Counter PC<12:8> bits (PCH) to be replaced by the
contents of the PCLATH register. This allows the entire
contents of the program counter to be changed by
writing the desired upper five bits to the PCLATH
register. When the lower eight bits are written to the
PCL register, all 13 bits of the program counter will
change to the values contained in the PCLATH register
and those being written to the PCL register.
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL). Care should be
exercised when jumping into a look-up table or
program branch table (computed GOTO) by modifying
the PCL register. Assuming that PCLATH is set to the
table start address, if the table length is greater than
255 instructions or if the lower eight bits of the memory
address rolls over from 0xFF to 0x00 in the middle of
the table, then PCLATH must be incremented for each
address rollover that occurs between the table
beginning and the target location within the table.
For more information refer to Application Note AN556,
Implementing a Table Read” (DS00556).
2.3.2 STACK
The PIC16F882/883/884/886/887 devices have an
8-level x 13-bit wide hardware stack (see Figures 2-2
and 2-3). The stack space is not part of either program
or data space and the Stack Pointer is not readable or
writable. The PC is PUSHed onto the stack when a
CALL instruction is executed or an interrupt causes a
branch. The stack is POPed in the event of a RETURN,
RETLW or a RETFIE instruction execution. PCLATH is
not affected by a PUSH or POP operation.
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
2.4 Indirect Addressing, INDF and
FSR Registers
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
Indirect addressing is possible by using the INDF
register. Any instruction using the INDF register actually
accesses data pointed to by the File Select Register
(FSR). Reading INDF itself indirectly will produce 00h.
Writing to the INDF register indirectly results in a no
operation (although Status bits may be affected). An
effective 9-bit address is obtained by concatenating the
8-bit FSR and the IRP bit of the STATUS register, as
shown in Figure 2-8.
A simple program to clear RAM location 20h-2Fh using
indirect addressing is shown in Example 2-1.
EXAMPLE 2-1: INDIRECT ADDRESSING
PC
12 8 7 0
5PCLATH<4:0>
PCLATH
Instruction with
ALU Result
GOTO, CALL
OPCODE<10:0>
8
PC
12 11 10 0
11
PCLATH<4:3>
PCH PCL
87
2
PCLATH
PCH PCL
PCL as
Destination
Note 1: There are no Status bits to indicate stack
overflow or stack underflow conditions.
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions or the vectoring to an
interrupt address.
MOVLW 0x20 ;initialize pointer
MOVWF FSR ;to RAM
NEXT CLRF INDF ;clear INDF register
INCF FSR ;inc pointer
BTFSS FSR,4 ;all done?
GOTO NEXT ;no clear next
CONTINUE ;yes continue
{E
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FIGURE 2-8: DIRECT/INDIRECT ADDRESSING PIC16F882/883/884/886/887
Note: For memory map detail, see Figures 2-2 and 2-3.
Data
Memory
Indirect AddressingDirect Addressing
Bank Select Location Select
RP1 RP0 6 0
From Opcode IRP File Select Register
70
Bank Select Location Select
00 01 10 11
180h
1FFh
00h
7Fh
Bank 0 Bank 1 Bank 2 Bank 3
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3.0 I/O PORTS
There are as many as 35 general purpose I/O pins
available. Depending on which peripherals are
enabled, some or all of the pins may not be available as
general purpose I/O. In general, when a peripheral is
enabled, the associated pin may not be used as a
general purpose I/O pin.
3.1 PORTA and the TRISA Registers
PORTA is a 8-bit wide, bidirectional port. The
corresponding data direction register is TRISA
(Register 3-2). Setting a TRISA bit (= 1) will make the
corresponding PORTA pin an input (i.e., disable the
output driver). Clearing a TRISA bit (= 0) will make the
corresponding PORTA pin an output (i.e., enables
output driver and puts the contents of the output latch
on the selected pin). Example 3-1 shows how to
initialize PORTA.
Reading the PORTA register (Register 3-1) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then
written to the PORT data latch.
The TRISA register (Register 3-2) controls the PORTA
pin output drivers, even when they are being used as
analog inputs. The user should ensure the bits in the
TRISA register are maintained set when using them as
analog inputs. I/O pins configured as analog input always
read ‘0’.
EXAMPLE 3-1: INITIALIZING PORTA
Note: The ANSEL register must be initialized to
configure an analog channel as a digital
input. Pins configured as analog inputs
will read 0’.
BANKSEL PORTA ;
CLRF PORTA ;Init PORTA
BANKSEL ANSEL ;
CLRF ANSEL ;digital I/O
BANKSEL TRISA ;
MOVLW 0Ch ;Set RA<3:2> as inputs
MOVWF TRISA ;and set RA<5:4,1:0>
;as outputs
REGISTER 3-1: PORTA: PORTA REGISTER
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 RA<7:0>: PORTA I/O Pin bit
1 = Port pin is > VIH
0 = Port pin is < VIL
REGISTER 3-2: TRISA: PORTA TRI-STATE REGISTER
R/W-1(1) R/W-1(1) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 TRISA<7:0>: PORTA Tri-State Control bit
1 = PORTA pin configured as an input (tri-stated)
0 = PORTA pin configured as an output
Note 1: TRISA<7:6> always reads ‘1’ in XT, HS and LP Oscillator modes.
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3.2 Additional Pin Functions
RA0 also has an Ultra Low-Power Wake-up option. The
next three sections describe these functions.
3.2.1 ANSEL REGISTER
The ANSEL register (Register 3-3) is used to configure
the Input mode of an I/O pin to analog. Setting the
appropriate ANSEL bit high will cause all digital reads
on the pin to be read as 0’ and allow analog functions
on the pin to operate correctly.
The state of the ANSEL bits has no affect on digital out-
put functions. A pin with TRIS clear and ANSEL set will
still operate as a digital output, but the Input mode will
be analog. This can cause unexpected behavior when
executing read-modify-write instructions on the
affected port.
REGISTER 3-3: ANSEL: ANALOG SELECT REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
ANS7(2) ANS6(2) ANS5(2) ANS4 ANS3 ANS2 ANS1 ANS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set 0’ = Bit is cleared x = Bit is unknown
bit 7-0 ANS<7:0>: Analog Select bits
Analog select between analog or digital function on pins AN<7:0>, respectively.
1 = Analog input. Pin is assigned as analog input(1).
0 = Digital I/O. Pin is assigned to port or special function.
Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and
interrupt-on-change if available. The corresponding TRIS bit must be set to Input mode in order to allow
external control of the voltage on the pin.
2: Not implemented on MemHigh.
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3.2.2 ULTRA LOW-POWER WAKE-UP
The Ultra Low-Power Wake-up (ULPWU) on RA0 allows
a slow falling voltage to generate an interrupt-on-change
on RA0 without excess current consumption. The mode
is selected by setting the ULPWUE bit of the PCON
register. This enables a small current sink, which can be
used to discharge a capacitor on RA0.
Follow these steps to use this feature:
a) Charge the capacitor on RA0 by configuring the
RA0 pin to output (= 1).
b) Configure RA0 as an input.
c) Set the ULPWUIE bit of the PIE2 register to
enable interrupt.
d) Set the ULPWUE bit of the PCON register to
begin the capacitor discharge.
e) Execute a SLEEP instruction.
When the voltage on RA0 drops below VIL, an interrupt
will be generated which will cause the device to
wake-up and execute the next instruction. If the GIE bit
of the INTCON register is set, the device will then call
the interrupt vector (0004h).
This feature provides a low-power technique for
periodically waking up the device from Sleep. The
time-out is dependent on the discharge time of the RC
circuit on RA0. See Example 3-2 for initializing the
Ultra Low-Power Wake-up module.
A series resistor between RA0 and the external
capacitor provides overcurrent protection for the
RA0/AN0/ULPWU/C12IN0- pin and can allow for
software calibration of the time-out (see Figure 3-1). A
timer can be used to measure the charge time and
discharge time of the capacitor. The charge time can
then be adjusted to provide the desired interrupt delay.
This technique will compensate for the affects of
temperature, voltage and component accuracy. The
Ultra Low-Power Wake-up peripheral can also be
configured as a simple Programmable Low Voltage
Detect or temperature sensor.
EXAMPLE 3-2: ULTRA LOW-POWER
WAKE-UP INITIALIZATION
Note: For more information, refer to AN879,
Using the Microchip Ultra Low-Power
Wake-up Module” Application Note
(DS00879).
BANKSEL PORTA ;
BSF PORTA,0 ;Set RA0 data latch
BANKSEL ANSEL ;
BCF ANSEL,0 ;RA0 to digital I/O
BANKSEL TRISA ;
BCF TRISA,0 ;Output high to
CALL CapDelay ;charge capacitor
BANKSEL PIR2 ;
BCF PIR2,ULPWUIF ;Clear flag
BANKSEL PCON
BSF PCON,ULPWUE ;Enable ULP Wake-up
BSF TRISA,0 ;RA0 to input
BSF PIE2, ULPWUIE ;Enable interrupt
MOVLW B’11000000’ ;Enable peripheral
MOVWF INTCON ;interrupt
SLEEP ;Wait for IOC
NOP ;
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3.2.3 PIN DESCRIPTIONS AND
DIAGRAMS
Each PORTA pin is multiplexed with other functions. The
pins and their combined functions are briefly described
here. For specific information about individual functions
such as the comparator or the A/D Converter (ADC),
refer to the appropriate section in this data sheet.
3.2.3.1 RA0/AN0/ULPWU/C12IN0-
Figure 3-1 shows the diagram for this pin. This pin is
configurable to function as one of the following:
a general purpose I/O
an analog input for the ADC
a negative analog input to Comparator C1 or C2
an analog input for the Ultra Low-Power Wake-up
FIGURE 3-1: BLOCK DIAGRAM OF RA0
I/O Pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
RD
WR
WR
RD
To Comparator
Analog(1)
Input Mode
01
IULP
Data Bus
PORTA
TRISA
TRISA
PORTA
Note 1: ANSEL determines Analog Input mode.
-
+V
TRG
ULPWUE
To A/D Converter
VSS
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3.2.3.2 RA1/AN1/C12IN1-
Figure 3-2 shows the diagram for this pin. This pin is
configurable to function as one of the following:
a general purpose I/O
an analog input for the ADC
a negative analog input to Comparator C1 or C2
FIGURE 3-2: BLOCK DIAGRAM OF RA1
3.2.3.3 RA2/AN2/VREF-/CVREF/C2IN+
Figure 3-3 shows the diagram for this pin. This pin is
configurable to function as one of the following:
a general purpose I/O
an analog input for the ADC
a negative voltage reference input for the ADC
and CVREF
a comparator voltage reference output
a positive analog input to Comparator C2
FIGURE 3-3: BLOCK DIAGRAM OF RA2
I/O Pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
Analog(1)
Input Mode
Data Bus
RD
PORTA
WR
PORTA
WR
TRISA
RD
TRISA
To A/D Converter
Note 1: ANSEL determines Analog Input mode.
To Comparator
I/O Pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
Analog(1)
Input Mode
Data Bus
RD
PORTA
WR
PORTA
WR
TRISA
RD
TRISA
To Comparator (VREF-)
Note 1: ANSEL determines Analog Input mode.
To Comparator (positive input)
CVREF
VROE
To A/D Converter (VREF-)
To A/D Converter (analog channel)
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3.2.3.4 RA3/AN3/VREF+/C1IN+
Figure 3-4 shows the diagram for this pin. This pin is
configurable to function as one of the following:
a general purpose input
an analog input for the ADC
a positive voltage reference input for the ADC and
CVREF
a positive analog input to Comparator C1
FIGURE 3-4: BLOCK DIAGRAM OF RA3
3.2.3.5 RA4/T0CKI/C1OUT
Figure 3-5 shows the diagram for this pin. This pin is
configurable to function as one of the following:
a general purpose I/O
a clock input for Timer0
a digital output from Comparator C1
FIGURE 3-5: BLOCK DIAGRAM OF RA4
I/O Pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
Analog(1)
Input Mode
Data Bus
RD
PORTA
WR
PORTA
WR
TRISA
RD
TRISA
Note 1: ANSEL determines Analog Input mode.
To Comparator (VREF+)
To Comparator (positive input)
To A/D Converter (VREF+)
To A/D Converter (analog channel)
I/O Pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
Data Bus
RD
PORTA
WR
PORTA
WR
TRISA
RD
TRISA
0
1
C1OUT
C1OUT
Enable
To Timer0
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3.2.3.6 RA5/AN4/SS/C2OUT
Figure 3-6 shows the diagram for this pin. This pin is
configurable to function as one of the following:
a general purpose I/O
an analog input for the ADC
a slave select input
a digital output from Comparator C2
FIGURE 3-6: BLOCK DIAGRAM OF RA5
3.2.3.7 RA6/OSC2/CLKOUT
Figure 3-7 shows the diagram for this pin. This pin is
configurable to function as one of the following:
a general purpose I/O
a crystal/resonator connection
a clock output
FIGURE 3-7: BLOCK DIAGRAM OF RA6
I/O Pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
Analog(1)
Input Mode
Data Bus
RD
PORTA
WR
PORTA
WR
TRISA
RD
TRISA
0
1
C2OUT
C2OUT
Enable
To SS Input
To A/D Converter
Note 1: ANSEL determines Analog Input mode.
I/O Pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
Data Bus
RD
PORTA
WR
PORTA
WR
TRISA
RD
TRISA
FOSC/4
OSC2
CLKOUT
0
1
CLKOUT
Enable
Enable
INTOSCIO/
EXTRCIO/EC(1)
CLKOUT
Enable
Note 1: With I/O option.
Circuit
Oscillator
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3.2.3.8 RA7/OSC1/CLKIN
Figure 3-8 shows the diagram for this pin. This pin is
configurable to function as one of the following:
a general purpose I/O
a crystal/resonator connection
a clock input
FIGURE 3-8: BLOCK DIAGRAM OF RA7
TABLE 3-1: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
I/O Pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
Data Bus
RD
PORTA
WR
PORTA
WR
TRISA
RD
TRISA
INTOSC
Mode
OSC1
CLKIN
Circuit
Oscillator
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
ADCON0 ADCS1 ADCS0 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 104
ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 41
CM1CON0 C1ON C1OUT C1OE C1POL C1R C1CH1 C1CH0 89
CM2CON0 C2ON C2OUT C2OE C2POL C2R C2CH1 C2CH0 90
CM2CON1 MC1OUT MC2OUT C1RSEL C2RSEL T1GSS C2SYNC 92
PCON —ULPWUESBOREN—PORBOR 37
OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 31
PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 40
SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 177
TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 40
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.
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3.3 PORTB and TRISB Registers
PORTB is an 8-bit wide, bidirectional port. The
corresponding data direction register is TRISB
(Register 3-6). Setting a TRISB bit (= 1) will make the
corresponding PORTB pin an input (i.e., put the
corresponding output driver in a High-Impedance mode).
Clearing a TRISB bit (= 0) will make the corresponding
PORTB pin an output (i.e., enable the output driver and
put the contents of the output latch on the selected pin).
Example 3-3 shows how to initialize PORTB.
Reading the PORTB register (Register 3-5) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then written
to the PORT data latch.
The TRISB register (Register 3-6) controls the PORTB
pin output drivers, even when they are being used as
analog inputs. The user should ensure the bits in the
TRISB register are maintained set when using them as
analog inputs. I/O pins configured as analog input always
read ‘0’. Example 3-3 shows how to initialize PORTB.
EXAMPLE 3-3: INITIALIZING PORTB
3.4 Additional PORTB Pin Functions
PORTB pins RB<7:0> on the device family device have
an interrupt-on-change option and a weak pull-up
option. The following three sections describe these
PORTB pin functions.
Every PORTB pin on this device family has an
interrupt-on-change option and a weak pull-up option.
3.4.1 ANSELH REGISTER
The ANSELH register (Register 3-4) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELH bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
The state of the ANSELH bits has no affect on digital
output functions. A pin with TRIS clear and ANSELH
set will still operate as a digital output, but the Input
mode will be analog. This can cause unexpected
behavior when executing read-modify-write
instructions on the affected port.
3.4.2 WEAK PULL-UPS
Each of the PORTB pins has an individually configurable
internal weak pull-up. Control bits WPUB<7:0> enable or
disable each pull-up (see Register 3-7). Each weak
pull-up is automatically turned off when the port pin is
configured as an output. All pull-ups are disabled on a
Power-on Reset by the RBPU bit of the OPTION register.
3.4.3 INTERRUPT-ON-CHANGE
All of the PORTB pins are individually configurable as an
interrupt-on-change pin. Control bits IOCB<7:0> enable
or disable the interrupt function for each pin. Refer to
Register 3-8. The interrupt-on-change feature is
disabled on a Power-on Reset.
For enabled interrupt-on-change pins, the present value
is compared with the old value latched on the last read
of PORTB to determine which bits have changed or
mismatched the old value. The ‘mismatch’ outputs of
the last read are OR’d together to set the PORTB
Change Interrupt flag bit (RBIF) in the INTCON register.
This interrupt can wake the device from Sleep. The user,
in the Interrupt Service Routine, clears the interrupt by:
a) Any read or write of PORTB. This will end the
mismatch condition.
b) Clear the flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading or writing PORTB will end the mismatch
condition and allow flag bit RBIF to be cleared. The latch
holding the last read value is not affected by a MCLR nor
Brown-out Reset. After these Resets, the RBIF flag will
continue to be set if a mismatch is present.
Note: The ANSELH register must be initialized
to configure an analog channel as a digital
input. Pins configured as analog inputs
will read ‘0’.
BANKSEL PORTB ;
CLRF PORTB ;Init PORTB
BANKSEL TRISB ;
MOVLW B‘11110000’ ;Set RB<7:4> as inputs
;and RB<3:0> as outputs
MOVWF TRISB ;
Note: If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RBIF
interrupt flag may not get set. Furthermore,
since a read or write on a port affects all bits
of that port, care must be taken when using
multiple pins in Interrupt-on-Change mode.
Changes on one pin may not be seen while
servicing changes on another pin.
2006-2015 Microchip Technology Inc. DS40001291H-page 49
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REGISTER 3-4: ANSELH: ANALOG SELECT HIGH REGISTER
U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
ANS13 ANS12 ANS11 ANS10 ANS9 ANS8
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set 0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as0
bit 5-0 ANS<13:8>: Analog Select bits
Analog select between analog or digital function on pins AN<13:8>, respectively.
1 = Analog input. Pin is assigned as analog input(1).
0 = Digital I/O. Pin is assigned to port or special function.
Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and
interrupt-on-change if available. The corresponding TRIS bit must be set to Input mode in order to allow
external control of the voltage on the pin.
REGISTER 3-5: PORTB: PORTB REGISTER
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 RB<7:0>: PORTB I/O Pin bit
1 = Port pin is > VIH
0 = Port pin is < VIL
REGISTER 3-6: TRISB: PORTB TRI-STATE REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 TRISB<7:0>: PORTB Tri-State Control bit
1 = PORTB pin configured as an input (tri-stated)
0 = PORTB pin configured as an output
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DS40001291H-page 50 2006-2015 Microchip Technology Inc.
REGISTER 3-7: WPUB: WEAK PULL-UP PORTB REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 WPUB<7:0>: Weak Pull-up Register bit
1 = Pull-up enabled
0 = Pull-up disabled
Note 1: Global RBPU bit of the OPTION register must be cleared for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is in configured as an output.
REGISTER 3-8: IOCB: INTERRUPT-ON-CHANGE PORTB REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IOCB7 IOCB6 IOCB5 IOCB4 IOCB3 IOCB2 IOCB1 IOCB0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 IOCB<7:0>: Interrupt-on-Change PORTB Control bit
1 = Interrupt-on-change enabled
0 = Interrupt-on-change disabled
2006-2015 Microchip Technology Inc. DS40001291H-page 51
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3.4.4 PIN DESCRIPTIONS AND
DIAGRAMS
Each PORTB pin is multiplexed with other functions. The
pins and their combined functions are briefly described
here. For specific information about individual functions
such as the SSP, I2C or interrupts, refer to the appropriate
section in this data sheet.
3.4.4.1 RB0/AN12/INT
Figure 3-9 shows the diagram for this pin. This pin is
configurable to function as one of the following:
a general purpose I/O
an analog input for the ADC
an external edge triggered interrupt
3.4.4.2 RB1/AN10/P1C(1)/C12IN3-
Figure 3-9 shows the diagram for this pin. This pin is
configurable to function as one of the following:
a general purpose I/O
an analog input for the ADC
a PWM output(1)
an analog input to Comparator C1 or C2
3.4.4.3 RB2/AN8/P1B(1)
Figure 3-9 shows the diagram for this pin. This pin is
configurable to function as one of the following:
a general purpose I/O
an analog input for the ADC
a PWM output(1)
3.4.4.4 RB3/AN9/PGM/C12IN2-
Figure 3-9 shows the diagram for this pin. This pin is
configurable to function as one of the following:
a general purpose I/O
an analog input for the ADC
Low-voltage In-Circuit Serial Programming enable
pin
an analog input to Comparator C1 or C2
FIGURE 3-9: BLOCK DIAGRAM OF
RB<3:0>
Note 1: P1C is available on PIC16F882/883/886
only.
Note 1: P1B is available on PIC16F882/883/886
only.
I/O Pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
VDD
Weak
Analog(1)
Input Mode
Data Bus
WR
WPUB
RD
WPUB
WR
PORTB
WR
TRISB
RD
TRISB
To A/D Converter
RB0/INT
Analog(1)
Input Mode
RBPU
Note 1: ANSELH determines Analog Input mode.
RB3/PGM
To Comparator (RB1, RB3)
D
Q
CK
Q
D
EN
Q
D
EN
Q
RD PORTB
RD
PORTB
WR
IOCB
RD
IOCB
Interrupt-on-
Change
Q3
1
0
CCP1OUT Enable
CCP1OUT
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DS40001291H-page 52 2006-2015 Microchip Technology Inc.
3.4.4.5 RB4/AN11/P1D(1)
Figure 3-10 shows the diagram for this pin. This pin is
configurable to function as one of the following:
a general purpose I/O
an analog input for the ADC
a PWM output(1)
3.4.4.6 RB5/AN13/T1G
Figure 3-10 shows the diagram for this pin. This pin is
configurable to function as one of the following:
a general purpose I/O
an analog input for the ADC
a Timer1 gate input
3.4.4.7 RB6/ICSPCLK
Figure 3-10 shows the diagram for this pin. This pin is
configurable to function as one of the following:
a general purpose I/O
In-Circuit Serial Programming clock
3.4.4.8 RB7/ICSPDAT
Figure 3-10 shows the diagram for this pin. This pin is
configurable to function as one of the following:
a general purpose I/O
In-Circuit Serial Programming data
Note 1: P1D is available on PIC16F882/883/886
only.
2006-2015 Microchip Technology Inc. DS40001291H-page 53
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FIGURE 3-10: BLOCK DIAGRAM OF RB<7:4>
TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
ANSELH ANS13 ANS12 ANS11 ANS10 ANS9 ANS8 49
CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 122
CM2CON1 MC1OUT MC2OUT C1RSEL C2RSEL —T1GSSC2SYNC 92
IOCB IOCB7 IOCB6 IOCB5 IOCB4 IOCB3 IOCB2 IOCB1 IOCB0 50
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 32
OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 31
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 49
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 49
WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 50
Legend: x = unknown, u = unchanged, = unimplemented read as ‘0’. Shaded cells are not used by PORTB.
I/O Pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
VDD
D
EN
Q
D
EN
Q
Weak
Data Bus
WR
WPUB
RD
WPUB
RD PORTB
RD
PORTB
WR
PORTB
WR
TRISB
RD
TRISB
WR
IOCB
RD
IOCB
Interrupt-on-
Analog(1) Input Mode
RBPU
Change
Q3
Available on PIC16F882/PIC16F883/PIC16F886 only.
Note 1: ANSELH determines Analog Input mode.
2: Applies to RB<7:6> pins only).
3: Applies to RB5 pin only.
To A/D Converter
1
0
CCP1OUT Enable
CCP1OUT 0
1
1
0
Analog(1)
Input Mode
To Timer1 T1G(3)
ICSP™(2)
To ICSPCLK (RB6) and ICSPDAT (RB7)
PIC16F882/883/884/886/887
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3.5 PORTC and TRISC Registers
PORTC is a 8-bit wide, bidirectional port. The
corresponding data direction register is TRISC
(Register 3-10). Setting a TRISC bit (= 1) will make the
corresponding PORTC pin an input (i.e., put the
corresponding output driver in a High-Impedance mode).
Clearing a TRISC bit (= 0) will make the corresponding
PORTC pin an output (i.e., enable the output driver and
put the contents of the output latch on the selected pin).
Example 3-4 shows how to initialize PORTC.
Reading the PORTC register (Register 3-9) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then written
to the PORT data latch.
The TRISC register (Register 3-10) controls the PORTC
pin output drivers, even when they are being used as
analog inputs. The user should ensure the bits in the
TRISC register are maintained set when using them as
analog inputs. I/O pins configured as analog input always
read ‘0’.
EXAMPLE 3-4: INITIALIZING PORTC
BANKSEL PORTC ;
CLRF PORTC ;Init PORTC
BANKSEL TRISC ;
MOVLW B‘00001100’ ;Set RC<3:2> as inputs
MOVWF TRISC ;and set RC<7:4,1:0>
;as outputs
REGISTER 3-9: PORTC: PORTC REGISTER
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 RC<7:0>: PORTC General Purpose I/O Pin bit
1 = Port pin is > VIH
0 = Port pin is < VIL
REGISTER 3-10: TRISC: PORTC TRI-STATE REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1(1) R/W-1(1)
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 TRISC<7:0>: PORTC Tri-State Control bit
1 = PORTC pin configured as an input (tri-stated)
0 = PORTC pin configured as an output
Note 1: TRISC<1:0> always reads ‘1’ in LP Oscillator mode.
2006-2015 Microchip Technology Inc. DS40001291H-page 55
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3.5.1 RC0/T1OSO/T1CKI
Figure 3-11 shows the diagram for this pin. This pin is
configurable to function as one of the following:
a general purpose I/O
a Timer1 oscillator output
a Timer1 clock input
FIGURE 3-11: BLOCK DIAGRAM OF RC0
3.5.2 RC1/T1OSI/CCP2
Figure 3-12 shows the diagram for this pin. This pin is
configurable to function as one of the following:
a general purpose I/O
a Timer1 oscillator input
a Capture input and Compare/PWM output for
Comparator C2
FIGURE 3-12: BLOCK DIAGRAM OF RC1
3.5.3 RC2/P1A/CCP1
Figure 3-13 shows the diagram for this pin. This pin is
configurable to function as one of the following:
a general purpose I/O
a PWM output
a Capture input and Compare output for
Comparator C1
FIGURE 3-13: BLOCK DIAGRAM OF RC2
I/O Pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
Data Bus
RD
PORTC
WR
PORTC
WR
TRISC
RD
TRISC
To Timer1 clock input
T1OSCEN Circuit
Timer1 Oscillator
I/O Pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
Data Bus
RD
PORTC
WR
PORTC
WR
TRISC
RD
TRISC
To CCP2
CCP2
CCP2CON
0
1
1
0
T1OSCEN
T1OSCEN Circuit
Timer1 Oscillator
T1OSI
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
Data bus
WR
PORTC
WR
TRISC
RD
TRISC
To Enhanced CCP1
RD
PORTC
CCP1/P1A
CCP1CON
0
1
1
0I/O Pin
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3.5.4 RC3/SCK/SCL
Figure 3-14 shows the diagram for this pin. This pin is
configurable to function as one of the following:
a general purpose I/O
a SPI clock
•an I
2C™ clock
FIGURE 3-14: BLOCK DIAGRAM OF RC3
3.5.5 RC4/SDI/SDA
Figure 3-15 shows the diagram for this pin. This pin is
configurable to function as one of the following:
a general purpose I/O
a SPI data I/O
•an I
2C data I/O
FIGURE 3-15: BLOCK DIAGRAM OF RC4
3.5.6 RC5/SDO
Figure 3-16 shows the diagram for this pin. This pin is
configurable to function as one of the following:
a general purpose I/O
a serial data output
FIGURE 3-16: BLOCK DIAGRAM OF RC5
I/O Pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
Data Bus
RD
PORTC
WR
PORTC
WR
TRISC
RD
TRISC
To SSPSR
SSPEN
0
1
1
0
SCK
I/O Pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
Data Bus
RD
PORTC
WR
PORTC
WR
TRISC
RD
TRISC
To SSPSR
SSPEN
0
1
1
0
SDI/SDA
I/O Pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
Data Bus
RD
PORTC
WR
PORTC
WR
TRISC
RD
TRISC
Port/SDO
0
1
1
0
SDO
Select
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3.5.7 RC6/TX/CK
Figure 3-17 shows the diagram for this pin. This pin is
configurable to function as one of the following:
a general purpose I/O
an asynchronous serial output
a synchronous clock I/O
FIGURE 3-17: BLOCK DIAGRAM OF RC6
3.5.8 RC7/RX/DT
Figure 3-18 shows the diagram for this pin. This pin is
configurable to function as one of the following:
a general purpose I/O
an asynchronous serial input
a synchronous serial data I/O
FIGURE 3-18: BLOCK DIAGRAM OF RC7
TABLE 3-3: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
I/O Pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
Data Bus
RD
PORTC
WR
PORTC
WR
TRISC
RD
TRISC
SPEN
TXEN
CK
TX
SYNC
EUSART
EUSART
0
1
1
0
0
1
1
0
I/O Pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
Data Bus
RD
PORTC
WR
PORTC
WR
TRISC
RD
TRISC
SPEN
SYNC
EUSART
0
1
1
0
DT
EUSART RX/DT
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 122
CCP2CON DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 123
PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 54
PSTRCON — — STRSYNC STRD STRC STRB STRA 144
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 158
SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 177
T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 81
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 54
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by
PORTC.
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3.6 PORTD and TRISD Registers
PORTD(1) is a 8-bit wide, bidirectional port. The
corresponding data direction register is TRISD
(Register 3-12). Setting a TRISD bit (= 1) will make the
corresponding PORTD pin an input (i.e., put the
corresponding output driver in a High-Impedance mode).
Clearing a TRISD bit (= 0) will make the corresponding
PORTD pin an output (i.e., enable the output driver and
put the contents of the output latch on the selected pin).
Example 3-5 shows how to initialize PORTD.
Reading the PORTD register (Register 3-11) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then written
to the PORT data latch.
The TRISD register (Register 3-12) controls the PORTD
pin output drivers, even when they are being used as
analog inputs. The user should ensure the bits in the
TRISD register are maintained set when using them as
analog inputs. I/O pins configured as analog input always
read ‘0’.
EXAMPLE 3-5: INITIALIZING PORTD
Note 1: PORTD is available on PIC16F884/887
only.
BANKSEL PORTD ;
CLRF PORTD ;Init PORTD
BANKSEL TRISD ;
MOVLW B‘00001100’ ;Set RD<3:2> as inputs
MOVWF TRISD ;and set RD<7:4,1:0>
;as outputs
REGISTER 3-11: PORTD: PORTD REGISTER
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 RD<7:0>: PORTD General Purpose I/O Pin bit
1 = Port pin is > VIH
0 = Port pin is < VIL
REGISTER 3-12: TRISD: PORTD TRI-STATE REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 TRISD<7:0>: PORTD Tri-State Control bit
1 = PORTD pin configured as an input (tri-stated)
0 = PORTD pin configured as an output
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3.6.1 RD<4:0>
Figure 3-19 shows the diagram for these pins. These
pins are configured to function as general purpose
I/O’s.
FIGURE 3-19: BLOCK DIAGRAM OF
RD<4:0>
3.6.2 RD5/P1B(1)
Figure 3-20 shows the diagram for this pin. This pin is
configurable to function as one of the following:
a general purpose I/O
a PWM output
3.6.3 RD6/P1C(1)
Figure 3-20 shows the diagram for this pin. This pin is
configurable to function as one of the following:
a general purpose I/O
a PWM output
3.6.4 RD7/P1D(1)
Figure 3-20 shows the diagram for this pin. This pin is
configurable to function as one of the following:
a general purpose I/O
a PWM output
FIGURE 3-20: BLOCK DIAGRAM OF
RD<7:5>
TABLE 3-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Note: RD<4:0> is available on PIC16F884/887
only.
Note 1: RD5/P1B is available on PIC16F884/887
only. See RB2/AN8/P1B for this function
on PIC16F882/883/886.
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
Data Bus
WR
PORTD
WR
TRISD
RD
TRISD
RD
PORTD
I/O Pin
Note 1: RD6/P1C is available on PIC16F884/887
only. See RB1/AN10/P1C/C12IN3- for
this function on PIC16F882/883/886.
Note 1: RD7/P1D is available on PIC16F884/887
only. See RB4/AN11/P1D for this function
on PIC16F882/883/886.
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
Data Bus
WR
PORTD
WR
TRISD
RD
TRISD
RD
PORTD
CCP1
PSTRCON
0
1
1
0I/O Pin
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 58
PSTRCON — — STRSYNC STRD STRC STRB STRA 144
TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 58
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by
PORTD.
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3.7 PORTE and TRISE Registers
PORTE(1) is a 4-bit wide, bidirectional port. The
corresponding data direction register is TRISE. Setting a
TRISE bit (= 1) will make the corresponding PORTE pin
an input (i.e., put the corresponding output driver in a
High-Impedance mode). Clearing a TRISE bit (= 0) will
make the corresponding PORTE pin an output (i.e.,
enable the output driver and put the contents of the
output latch on the selected pin). The exception is RE3,
which is input only and its TRIS bit will always read as
1’. Example 3-6 shows how to initialize PORTE.
Reading the PORTE register (Register 3-13) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then
written to the PORT data latch. RE3 reads ‘0’ when
MCLRE = 1.
The TRISE register (Register 3-14) controls the PORTE
pin output drivers, even when they are being used as
analog inputs. The user should ensure the bits in the
TRISE register are maintained set when using them as
analog inputs. I/O pins configured as analog input always
read ‘0’.
EXAMPLE 3-6: INITIALIZING PORTE
Note 1: RE<2:0> pins are available on
PIC16F884/887 only.
Note: The ANSEL register must be initialized to
configure an analog channel as a digital
input. Pins configured as analog inputs
will read 0’.
BANKSEL PORTE ;
CLRF PORTE ;Init PORTE
BANKSEL ANSEL ;
CLRF ANSEL ;digital I/O
BCF STATUS,RP1 ;Bank 1
BANKSEL TRISE ;
MOVLW B‘00001100’ ;Set RE<3:2> as inputs
MOVWF TRISE ;and set RE<1:0>
;as outputs
REGISTER 3-13: PORTE: PORTE REGISTER
U-0 U-0 U-0 U-0 R-x R/W-x R/W-x R/W-x
RE3 RE2 RE1 RE0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 Unimplemented: Read as ‘0
bit 3-0 RD<3:0>: PORTE General Purpose I/O Pin bit
1 = Port pin is > VIH
0 = Port pin is < VIL
REGISTER 3-14: TRISE: PORTE TRI-STATE REGISTER
U-0 U-0 U-0 U-0 R-1(1) R/W-1 R/W-1 R/W-1
TRISE3 TRISE2 TRISE1 TRISE0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 Unimplemented: Read as ‘0
bit 3-0 TRISE<3:0>: PORTE Tri-State Control bit
1 = PORTE pin configured as an input (tri-stated)
0 = PORTE pin configured as an output
Note 1: TRISE<3> always reads1’.
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3.7.1 RE0/AN5(1)
This pin is configurable to function as one of the
following:
a general purpose I/O
an analog input for the ADC
3.7.2 RE1/AN6(1)
This pin is configurable to function as one of the
following:
a general purpose I/O
an analog input for the ADC
3.7.3 RE2/AN7(1)
This pin is configurable to function as one of the
following:
a general purpose I/O
an analog input for the ADC
FIGURE 3-21: BLOCK DIAGRAM OF
RE<2:0>
3.7.4 RE3/MCLR/VPP
Figure 3-22 shows the diagram for this pin. This pin is
configurable to function as one of the following:
a general purpose input
as Master Clear Reset with weak pull-up
FIGURE 3-22: BLOCK DIAGRAM OF RE3
Note 1: RE0/AN5 is available on PIC16F884/887
only.
Note 1: RE1/AN6 is available on PIC16F884/887
only.
Note 1: RE2/AN7 is available on PIC16F884/887
only.
I/O Pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
Analog(1)
Input Mode
Data Bus
RD
PORTE
WR
PORTE
WR
TRISE
RD
TRISE
To A/D Converter
Note 1: ANSEL determines Analog Input mode.
Input
VSS
Data Bus
RD
PORTE
Reset MCLRE
RD
TRISE VSS
MCLRE
VDD
Weak
MCLRE
Pin
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TABLE 3-5: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on
Page
ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 41
PORTE ——— RE3 RE2 RE1 RE0 60
TRISE ——— TRISE3 TRISE2 TRISE1 TRISE0 60
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by
PORTE
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4.0 OSCILLATOR MODULE (WITH
FAIL-SAFE CLOCK MONITOR)
4.1 Overview
The oscillator module has a wide variety of clock
sources and selection features that allow it to be used
in a wide range of applications while maximizing perfor-
mance and minimizing power consumption. Figure 4-1
illustrates a block diagram of the oscillator module.
Clock sources can be configured from external
oscillators, quartz crystal resonators, ceramic resonators
and Resistor-Capacitor (RC) circuits. In addition, the
system clock source can be configured from one of two
internal oscillators, with a choice of speeds selectable via
software. Additional clock features include:
Selectable system clock source between external
or internal via software.
Two-Speed Start-up mode, which minimizes
latency between external oscillator start-up and
code execution.
Fail-Safe Clock Monitor (FSCM) designed to
detect a failure of the external clock source (LP,
XT, HS, EC or RC modes) and switch
automatically to the internal oscillator.
The oscillator module can be configured in one of eight
clock modes.
1. EC – External clock with I/O on OSC2/CLKOUT.
2. LP – 32 kHz Low-Power Crystal mode.
3. XT – Medium Gain Crystal or Ceramic Resonator
Oscillator mode.
4. HS – High Gain Crystal or Ceramic Resonator
mode.
5. RC – External Resistor-Capacitor (RC) with
FOSC/4 output on OSC2/CLKOUT.
6. RCIO – External Resistor-Capacitor (RC) with
I/O on OSC2/CLKOUT.
7. INTOSC – Internal oscillator with FOSC/4 output
on OSC2 and I/O on OSC1/CLKIN.
8. INTOSCIO – Internal oscillator with I/O on
OSC1/CLKIN and OSC2/CLKOUT.
Clock Source modes are configured by the FOSC<2:0>
bits in the Configuration Word Register 1 (CONFIG1).
The internal clock can be generated from two internal
oscillators. The HFINTOSC is a calibrated high-
frequency oscillator. The LFINTOSC is an uncalibrated
low-frequency oscillator.
FIGURE 4-1: SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM
(CPU and Peripherals)
OSC1
OSC2
Sleep
External Oscillator
LP, XT, HS, RC, RCIO, EC
System Clock
Postscaler
MUX
MUX
8 MHz
4 MHz
2 MHz
1 MHz
500 kHz
125 kHz
250 kHz
IRCF<2:0>
111
110
101
100
011
010
001
000
31 kHz
Power-up Timer (PWRT)
FOSC<2:0>
(Configuration Word Register 1)
SCS<0>
(OSCCON Register)
Internal Oscillator
(OSCCON Register)
Watchdog Timer (WDT)
Fail-Safe Clock Monitor (FSCM)
HFINTOSC
8 MHz
LFINTOSC
31 kHz
INTOSC
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4.2 Oscillator Control
The Oscillator Control (OSCCON) register (Figure 4-1)
controls the system clock and frequency selection
options. The OSCCON register contains the following
bits:
Frequency selection bits (IRCF)
Frequency Status bits (HTS, LTS)
System clock control bits (OSTS, SCS)
REGISTER DEFINITIONS: OSCILLATOR CONTROL
REGISTER 4-1: OSCCON: OSCILLATOR CONTROL REGISTER
U-0 R/W-1 R/W-1 R/W-0 R-1 R-0 R-0 R/W-0
IRCF2 IRCF1 IRCF0 OSTS(1) HTS LTS SCS
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set 0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0
bit 6-4 IRCF<2:0>: Internal Oscillator Frequency Select bits
111 = 8 MHz
110 = 4 MHz (default)
101 = 2 MHz
100 = 1 MHz
011 = 500 kHz
010 = 250 kHz
001 = 125 kHz
000 = 31 kHz (LFINTOSC)
bit 3 OSTS: Oscillator Start-up Time-out Status bit(1)
1 = Device is running from the clock defined by FOSC<2:0> of the CONFIG1 register
0 = Device is running from the internal oscillator (HFINTOSC or LFINTOSC)
bit 2 HTS: HFINTOSC Status bit (High Frequency – 8 MHz to 125 kHz)
1 = HFINTOSC is stable
0 = HFINTOSC is not stable
bit 1 LTS: LFINTOSC Stable bit (Low Frequency – 31 kHz)
1 = LFINTOSC is stable
0 = LFINTOSC is not stable
bit 0 SCS: System Clock Select bit
1 = Internal oscillator is used for system clock
0 = Clock source defined by FOSC<2:0> of the CONFIG1 register
Note 1: Bit resets to0’ with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe
mode is enabled.
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4.3 Clock Source Modes
Clock Source modes can be classified as external or
internal.
External Clock modes rely on external circuitry for
the clock source. Examples are: oscillator mod-
ules (EC mode), quartz crystal resonators or
ceramic resonators (LP, XT and HS modes) and
Resistor-Capacitor (RC) mode circuits.
Internal clock sources are contained internally
within the oscillator module. The oscillator module
has two internal oscillators: the 8 MHz High-
Frequency Internal Oscillator (HFINTOSC) and
the 31 kHz Low-Frequency Internal Oscillator
(LFINTOSC).
The system clock can be selected between external or
internal clock sources via the System Clock Select
(SCS) bit of the OSCCON register. See Section 4.6
“Clock Switching” for additional information.
4.4 External Clock Modes
4.4.1 OSCILLATOR START-UP TIMER
(OST)
If the oscillator module is configured for LP, XT or HS
modes, the Oscillator Start-up Timer (OST) counts
1024 oscillations from OSC1. This occurs following a
Power-on Reset (POR) and when the Power-up Timer
(PWRT) has expired (if configured), or a wake-up from
Sleep. During this time, the program counter does not
increment and program execution is suspended. The
OST ensures that the oscillator circuit, using a quartz
crystal resonator or ceramic resonator, has started and
is providing a stable system clock to the oscillator
module. When switching between clock sources, a
delay is required to allow the new clock to stabilize.
These oscillator delays are shown in Table 4-1.
In order to minimize latency between external oscillator
start-up and code execution, the Two-Speed Clock
Start-up mode can be selected (see Section 4.7 “Two-
Speed Clock Start-up Mode”).
TABLE 4-1: OSCILLATOR DELAY EXAMPLES
4.4.2 EC MODE
The External Clock (EC) mode allows an externally
generated logic level as the system clock source. When
operating in this mode, an external clock source is
connected to the OSC1 input and the OSC2 is available
for general purpose I/O. Figure 4-2 shows the pin
connections for EC mode.
The Oscillator Start-up Timer (OST) is disabled when
EC mode is selected. Therefore, there is no delay in
operation after a Power-on Reset (POR) or wake-up
from Sleep. Because the PIC® MCU design is fully
static, stopping the external clock input will have the
effect of halting the device while leaving all data intact.
Upon restarting the external clock, the device will
resume operation as if no time had elapsed.
FIGURE 4-2: EXTERNAL CLOCK (EC)
MODE OPERATION
Switch From Switch To Frequency Oscillator Delay
Sleep/POR LFINTOSC
HFINTOSC 31 kHz
125 kHz to 8 MHz Oscillator Warm-up Delay (TWARM)
Sleep/POR EC, RC DC – 20 MHz 2 cycles
LFINTOSC (31 kHz) EC, RC DC – 20 MHz 1 cycle of each
Sleep/POR LP, XT, HS 32 kHz to 20 MHz 1024 Clock Cycles (OST)
LFINTOSC (31 kHz) HFINTOSC 125 kHz to 8 MHz 1 s (approx.)
OSC1/CLKIN
OSC2/CLKOUT(1)
I/O
Clock from
Ext. System PIC® MCU
Note 1: Alternate pin functions are listed in the
Section 1.0 “Device Overview.
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4.4.3 LP, XT, HS MODES
The LP, XT and HS modes support the use of quartz
crystal resonators or ceramic resonators connected to
OSC1 and OSC2 (Figure 4-3). The mode selects a low,
medium or high gain setting of the internal inverter-
amplifier to support various resonator types and speed.
LP Oscillator mode selects the lowest gain setting of the
internal inverter-amplifier. LP mode current consumption
is the least of the three modes. This mode is designed to
drive only 32.768 kHz tuning-fork type crystals (watch
crystals).
XT Oscillator mode selects the intermediate gain
setting of the internal inverter-amplifier. XT mode
current consumption is the medium of the three modes.
This mode is best suited to drive resonators with a
medium drive level specification.
HS Oscillator mode selects the highest gain setting of the
internal inverter-amplifier. HS mode current consumption
is the highest of the three modes. This mode is best
suited for resonators that require a high drive setting.
Figure 4-3 and Figure 4-4 show typical circuits for
quartz crystal and ceramic resonators, respectively.
FIGURE 4-3: QUARTZ CRYSTAL
OPERATION (LP, XT OR
HS MODE)
FIGURE 4-4: CERAMIC RESONATOR
OPERATION
(XT OR HS MODE)
Note 1: A series resistor (RS) may be required for
quartz crystals with low drive level.
2: The value of RF varies with the Oscillator mode
selected (typically between 2 M to 10 M.
C1
C2
Quartz
RS(1)
OSC1/CLKIN
RF(2) Sleep
To Internal
Logic
PIC® MCU
Crystal
OSC2/CLKOUT
Note 1: Quartz crystal characteristics vary
according to type, package and
manufacturer. The user should consult the
manufacturer data sheets for specifications
and recommended application.
2: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
3: For oscillator design assistance, reference
the following Microchip Applications Notes:
• AN826, “Crystal Oscillator Basics and
Crystal Selection for rfPIC® and PIC®
Devices” (DS00826)
• AN849, “Basic PIC® Oscillator Design
(DS00849)
• AN943, “Practical PIC® Oscillator
Analysis and Design” (DS00943)
• AN949, “Making Your Oscillator Work
(DS00949)
Note 1: A series resistor (RS) may be required for
ceramic resonators with low drive level.
2: The value of RF varies with the Oscillator mode
selected (typically between 2 M to 10 M.
3: An additional parallel feedback resistor (RP)
may be required for proper ceramic resonator
operation.
C1
C2 Ceramic RS(1)
OSC1/CLKIN
RF(2) Sleep
To Internal
Logic
PIC® MCU
RP(3)
Resonator
OSC2/CLKOUT
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4.4.4 EXTERNAL RC MODES
The external Resistor-Capacitor (RC) modes support
the use of an external RC circuit. This allows the
designer maximum flexibility in frequency choice while
keeping costs to a minimum when clock accuracy is not
required. There are two modes: RC and RCIO.
In RC mode, the RC circuit connects to OSC1. OSC2/
CLKOUT outputs the RC oscillator frequency divided
by 4. This signal may be used to provide a clock for
external circuitry, synchronization, calibration, test or
other application requirements. Figure 4-5 shows the
external RC mode connections.
FIGURE 4-5: EXTERNAL RC MODES
In RCIO mode, the RC circuit is connected to OSC1.
OSC2 becomes an additional general purpose I/O pin.
The RC oscillator frequency is a function of the supply
voltage, the resistor (REXT) and capacitor (CEXT) values
and the operating temperature. Other factors affecting
the oscillator frequency are:
threshold voltage variation
component tolerances
packaging variations in capacitance
The user also needs to take into account variation due
to tolerance of external RC components used.
4.5 Internal Clock Modes
The oscillator module has two independent, internal
oscillators that can be configured or selected as the
system clock source.
1. The HFINTOSC (High-Frequency Internal
Oscillator) is factory calibrated and operates at
8 MHz. The frequency of the HFINTOSC can be
user-adjusted via software using the OSCTUNE
register (Register 4-2).
2. The LFINTOSC (Low-Frequency Internal
Oscillator) is uncalibrated and operates at
31 kHz.
The system clock speed can be selected via software
using the Internal Oscillator Frequency Select bits
IRCF<2:0> of the OSCCON register.
The system clock can be selected between external or
internal clock sources via the System Clock Selection
(SCS) bit of the OSCCON register. See Section 4.6
“Clock Switching” for more information.
4.5.1 INTOSC AND INTOSCIO MODES
The INTOSC and INTOSCIO modes configure the
internal oscillators as the system clock source when
the device is programmed using the oscillator selection
or the FOSC<2:0> bits in the Configuration Word
Register 1 (CONFIG1).
In INTOSC mode, OSC1/CLKIN is available for general
purpose I/O. OSC2/CLKOUT outputs the selected
internal oscillator frequency divided by 4. The CLKOUT
signal may be used to provide a clock for external
circuitry, synchronization, calibration, test or other
application requirements.
In INTOSCIO mode, OSC1/CLKIN and OSC2/CLKOUT
are available for general purpose I/O.
4.5.2 HFINTOSC
The High-Frequency Internal Oscillator (HFINTOSC) is
a factory calibrated 8 MHz internal clock source. The
frequency of the HFINTOSC can be altered via
software using the OSCTUNE register (Register 4-2).
The output of the HFINTOSC connects to a postscaler
and multiplexer (see Figure 4-1). One of seven
frequencies can be selected via software using the
IRCF<2:0> bits of the OSCCON register. See
Section 4.5.4 “Frequency Select Bits (IRCF)” for
more information.
The HFINTOSC is enabled by selecting any frequency
between 8 MHz and 125 kHz by setting the IRCF<2:0>
bits of the OSCCON register 000. Then, set the
System Clock Source (SCS) bit of the OSCCON
register to ‘1 or enable Two-Speed Start-up by setting
the IESO bit in the Configuration Word Register 1
(CONFIG1) to 1’.
The HF Internal Oscillator (HTS) bit of the OSCCON
register indicates whether the HFINTOSC is stable or not.
OSC2/CLKOUT(1)
CEXT
REXT
PIC® MCU
OSC1/CLKIN
FOSC/4 or
Internal
Clock
VDD
VSS
Recommended values: 10 k REXT 100 k, <3V
3 k REXT 100 k, 3-5V
CEXT > 20 pF, 2-5V
Note 1: Alternate pin functions are listed in the
Section 1.0 “Device Overview”.
2: Output depends upon RC or RCIO Clock
mode.
I/O(2)
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4.5.2.1 OSCTUNE Register
The HFINTOSC is factory calibrated but can be
adjusted in software by writing to the OSCTUNE
register (Register 4-2).
The default value of the OSCTUNE register is ‘0’. The
value is a 5-bit two’s complement number.
When the OSCTUNE register is modified, the
HFINTOSC frequency will begin shifting to the new
frequency. Code execution continues during this shift.
There is no indication that the shift has occurred.
OSCTUNE does not affect the LFINTOSC frequency.
Operation of features that depend on the LFINTOSC
clock source frequency, such as the Power-up Timer
(PWRT), Watchdog Timer (WDT), Fail-Safe Clock
Monitor (FSCM) and peripherals, are not affected by the
change in frequency.
REGISTER 4-2: OSCTUNE: OSCILLATOR TUNING REGISTER
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TUN4 TUN3 TUN2 TUN1 TUN0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set 0’ = Bit is cleared x = Bit is unknown
bit 7-5 Unimplemented: Read as ‘0
bit 4-0 TUN<4:0>: Frequency Tuning bits
01111 = Maximum frequency
01110 =
00001 =
00000 = Oscillator module is running at the factory-calibrated frequency.
11111 =
10000 = Minimum frequency
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4.5.3 LFINTOSC
The Low-Frequency Internal Oscillator (LFINTOSC) is
an uncalibrated 31 kHz internal clock source.
The output of the LFINTOSC connects to a postscaler
and multiplexer (see Figure 4-1). Select 31 kHz, via
software, using the IRCF<2:0> bits of the OSCCON
register. See Section 4.5.4 “Frequency Select Bits
(IRCF)” for more information. The LFINTOSC is also the
frequency for the Power-up Timer (PWRT), Watchdog
Timer (WDT) and Fail-Safe Clock Monitor (FSCM).
The LFINTOSC is enabled by selecting 31 kHz
(IRCF<2:0> bits of the OSCCON register = 000) as the
system clock source (SCS bit of the OSCCON
register = 1), or when any of the following are enabled:
Two-Speed Start-up IESO bit of the Configuration
Word Register 1 = 1 and IRCF<2:0> bits of the
OSCCON register = 000
Power-up Timer (PWRT)
Watchdog Timer (WDT)
Fail-Safe Clock Monitor (FSCM)
The LF Internal Oscillator (LTS) bit of the OSCCON
register indicates whether the LFINTOSC is stable or
not.
4.5.4 FREQUENCY SELECT BITS (IRCF)
The output of the 8 MHz HFINTOSC and 31 kHz
LFINTOSC connects to a postscaler and multiplexer
(see Figure 4-1). The Internal Oscillator Frequency
Select bits IRCF<2:0> of the OSCCON register select
the frequency output of the internal oscillators. One of
eight frequencies can be selected via software:
•8 MHz
4 MHz (Default after Reset)
•2 MHz
•1 MHz
500 kHz
250 kHz
125 kHz
31 kHz (LFINTOSC)
4.5.5 HFINTOSC AND LFINTOSC CLOCK
SWITCH TIMING
When switching between the LFINTOSC and the
HFINTOSC, the new oscillator may already be shut
down to save power (see Figure 4-6). If this is the case,
there is a delay after the IRCF<2:0> bits of the
OSCCON register are modified before the frequency
selection takes place. The LTS and HTS bits of the
OSCCON register will reflect the current active status
of the LFINTOSC and HFINTOSC oscillators. The
timing of a frequency selection is as follows:
1. IRCF<2:0> bits of the OSCCON register are
modified.
2. If the new clock is shut down, a clock start-up
delay is started.
3. Clock switch circuitry waits for a falling edge of
the current clock.
4. CLKOUT is held low and the clock switch
circuitry waits for a rising edge in the new clock.
5. CLKOUT is now connected with the new clock.
LTS and HTS bits of the OSCCON register are
updated as required.
6. Clock switch is complete.
See Figure 4-1 for more details.
If the internal oscillator speed selected is between
8 MHz and 125 kHz, there is no start-up delay before
the new frequency is selected. This is because the old
and new frequencies are derived from the HFINTOSC
via the postscaler and multiplexer.
Start-up delay specifications are located in the
oscillator tables of Section 17.0 “Electrical
Specifications”.
Note: Following any Reset, the IRCF<2:0> bits
of the OSCCON register are set to110
and the frequency selection is set to
4 MHz. The user can modify the IRCF bits
to select a different frequency.
K N I—Vl—Vl—V
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FIGURE 4-6: INTERNAL OSCILLATOR SWITCH TIMING
HFINTOSC
LFINTOSC
IRCF <2:0>
System Clock
HFINTOSC
LFINTOSC
IRCF <2:0>
System Clock
00
00
Start-up Time 2-cycle Sync Running
2-cycle Sync Running
HFINTOSC LFINTOSC (FSCM and WDT disabled)
HFINTOSC LFINTOSC (Either FSCM or WDT enabled)
LFINTOSC
HFINTOSC
IRCF <2:0>
System Clock
= 0¼ 0
Start-up Time 2-cycle Sync Running
LFINTOSC HFINTOSC LFINTOSC turns off unless WDT or FSCM is enabled
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4.6 Clock Switching
The system clock source can be switched between
external and internal clock sources via software using
the System Clock Select (SCS) bit of the OSCCON
register.
4.6.1 SYSTEM CLOCK SELECT (SCS) BIT
The System Clock Select (SCS) bit of the OSCCON
register selects the system clock source that is used for
the CPU and peripherals.
When the SCS bit of the OSCCON register = 0,
the system clock source is determined by
configuration of the FOSC<2:0> bits in the
Configuration Word Register 1 (CONFIG1).
When the SCS bit of the OSCCON register = 1,
the system clock source is chosen by the internal
oscillator frequency selected by the IRCF<2:0>
bits of the OSCCON register. After a Reset, the
SCS bit of the OSCCON register is always
cleared.
4.6.2 OSCILLATOR START-UP TIME-OUT
STATUS (OSTS) BIT
The Oscillator Start-up Time-out Status (OSTS) bit of
the OSCCON register indicates whether the system
clock is running from the external clock source, as
defined by the FOSC<2:0> bits in the Configuration
Word Register 1 (CONFIG1), or from the internal clock
source. In particular, OSTS indicates that the Oscillator
Start-up Timer (OST) has timed out for LP, XT or HS
modes.
4.7 Two-Speed Clock Start-up Mode
Two-Speed Start-up mode provides additional power
savings by minimizing the latency between external
oscillator start-up and code execution. In applications
that make heavy use of the Sleep mode, Two-Speed
Start-up will remove the external oscillator start-up
time from the time spent awake and can reduce the
overall power consumption of the device.
This mode allows the application to wake-up from
Sleep, perform a few instructions using the INTOSC
as the clock source and go back to Sleep without
waiting for the primary oscillator to become stable.
When the oscillator module is configured for LP, XT or
HS modes, the Oscillator Start-up Timer (OST) is
enabled (see Section 4.4.1 “Oscillator Start-up Timer
(OST)). The OST will suspend program execution until
1024 oscillations are counted. Two-Speed Start-up
mode minimizes the delay in code execution by
operating from the internal oscillator as the OST is
counting. When the OST count reaches 1024 and the
OSTS bit of the OSCCON register is set, program
execution switches to the external oscillator.
4.7.1 TWO-SPEED START-UP MODE
CONFIGURATION
Two-Speed Start-up mode is configured by the
following settings:
IESO (of the Configuration Word Register 1) = 1;
Internal/External Switchover bit (Two-Speed
Start-up mode enabled).
SCS (of the OSCCON register) = 0.
FOSC<2:0> bits in the Configuration Word
Register 1 (CONFIG1) configured for LP, XT or
HS mode.
Two-Speed Start-up mode is entered after:
Power-on Reset (POR) and, if enabled, after
Power-up Timer (PWRT) has expired, or
Wake-up from Sleep.
If the external clock oscillator is configured to be
anything other than LP, XT or HS mode, then Two-
speed Start-up is disabled. This is because the external
clock oscillator does not require any stabilization time
after POR or an exit from Sleep.
Note: Any automatic clock switch, which may
occur from Two-Speed Start-up or Fail-
Safe Clock Monitor, does not update the
SCS bit of the OSCCON register. The user
can monitor the OSTS bit of the OSCCON
register to determine the current system
clock source.
Note: Executing a SLEEP instruction will abort
the oscillator start-up time and will cause
the OSTS bit of the OSCCON register to
remain clear.
W X
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4.7.2 TWO-SPEED START-UP
SEQUENCE
1. Wake-up from Power-on Reset or Sleep.
2. Instructions begin execution by the internal
oscillator at the frequency set in the IRCF<2:0>
bits of the OSCCON register.
3. OST enabled to count 1024 clock cycles.
4. OST timed out, wait for falling edge of the
internal oscillator.
5. OSTS is set.
6. System clock held low until the next falling edge
of new clock (LP, XT or HS mode).
7. System clock is switched to external clock
source.
4.7.3 CHECKING TWO-SPEED CLOCK
STATUS
Checking the state of the OSTS bit of the OSCCON
register will confirm if the microcontroller is running
from the external clock source, as defined by the
FOSC<2:0> bits in the Configuration Word Register 1
(CONFIG1), or the internal oscillator.
FIGURE 4-7: TWO-SPEED START-UP
0 1 1022 1023
PC + 1
TOSTT
HFINTOSC
OSC1
OSC2
Program Counter
System Clock
PC - N PC
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4.8 Fail-Safe Clock Monitor
The Fail-Safe Clock Monitor (FSCM) allows the device
to continue operating should the external oscillator fail.
The FSCM can detect oscillator failure any time after
the Oscillator Start-up Timer (OST) has expired. The
FSCM is enabled by setting the FCMEN bit in the
Configuration Word Register 1 (CONFIG1). The FSCM
is applicable to all external Oscillator modes (LP, XT,
HS, EC, RC and RCIO).
FIGURE 4-8: FSCM BLOCK DIAGRAM
4.8.1 FAIL-SAFE DETECTION
The FSCM module detects a failed oscillator by
comparing the external oscillator to the FSCM sample
clock. The sample clock is generated by dividing the
LFINTOSC by 64. See Figure 4-8. Inside the fail
detector block is a latch. The external clock sets the
latch on each falling edge of the external clock. The
sample clock clears the latch on each rising edge of the
sample clock. A failure is detected when an entire half-
cycle of the sample clock elapses before the primary
clock goes low.
4.8.2 FAIL-SAFE OPERATION
When the external clock fails, the FSCM switches the
device clock to an internal clock source and sets the bit
flag OSFIF of the PIR2 register. Setting this flag will
generate an interrupt if the OSFIE bit of the PIE2
register is also set. The device firmware can then take
steps to mitigate the problems that may arise from a
failed clock. The system clock will continue to be
sourced from the internal clock source until the device
firmware successfully restarts the external oscillator
and switches back to external operation.
The internal clock source chosen by the FSCM is
determined by the IRCF<2:0> bits of the OSCCON
register. This allows the internal oscillator to be
configured before a failure occurs.
4.8.3 FAIL-SAFE CONDITION CLEARING
The Fail-Safe condition is cleared after a Reset,
executing a SLEEP instruction or toggling the SCS bit
of the OSCCON register. When the SCS bit is toggled,
the OST is restarted. While the OST is running, the
device continues to operate from the INTOSC selected
in OSCCON. When the OST times out, the Fail-Safe
condition is cleared and the device will be operating
from the external clock source. The Fail-Safe condition
must be cleared before the OSFIF flag can be cleared.
4.8.4 RESET OR WAKE-UP FROM SLEEP
The FSCM is designed to detect an oscillator failure
after the Oscillator Start-up Timer (OST) has expired.
The OST is used after waking up from Sleep and after
any type of Reset. The OST is not used with the EC or
RC Clock modes so that the FSCM will be active as
soon as the Reset or wake-up has completed. When
the FSCM is enabled, the Two-Speed Start-up is also
enabled. Therefore, the device will always be executing
code while the OST is operating.
External
LFINTOSC ÷ 64
S
R
Q
31 kHz
(~32 s) 488 Hz
(~2 ms)
Clock Monitor
Latch
Clock
Failure
Detected
Oscillator
Clock
Q
Sample Clock
Note: Due to the wide range of oscillator start-up
times, the Fail-Safe circuit is not active
during oscillator start-up (i.e., after exiting
Reset or Sleep). After an appropriate
amount of time, the user should check the
OSTS bit of the OSCCON register to verify
the oscillator start-up and that the system
clock switchover has successfully
completed.
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FIGURE 4-9: FSCM TIMING DIAGRAM
TABLE 4-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
TABLE 4-3: SUMMARY OF CONFIGURATION WORD ASSOCIATED WITH CLOCK SOURCES
OSCFIF
System
Clock
Output
Sample Clock
Failure
Detected
Oscillator
Failure
Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
(Q)
Test Test Test
Clock Monitor Output
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
OSCCON IRCF2 IRCF1 IRCF0 OSTS HTS LTS SCS 64
OSCTUNE — — TUN4 TUN3 TUN2 TUN1 TUN0 68
PIE2 OSFIE C2IE C1IE EEIE BCLIE ULPWUIE CCP2IE 34
PIR2 OSFIF C2IF C1IF EEIF BCLIF ULPWUIF CCP2IF 36
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by
oscillators.
Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 Register
on Page
CONFIG1(1) 13:8 DEBUG LVP FCMEN IESO BOREN 1 BOREN0 206
7:0 CPD CP MCLRE PWRTE WDTE FOSC 2 FOSC 1 FOSC 0
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by
oscillators.
Note 1: See Configuration Word Register 1 (Register 14-1) for operation of all register bits.
WED
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5.0 TIMER0 MODULE
The Timer0 module is an 8-bit timer/counter with the
following features:
8-bit timer/counter register (TMR0)
8-bit prescaler (shared with Watchdog Timer)
Programmable internal or external clock source
Programmable external clock edge selection
Interrupt on overflow
Figure 5-1 is a block diagram of the Timer0 module.
5.1 Timer0 Operation
When used as a timer, the Timer0 module can be used
as either an 8-bit timer or an 8-bit counter.
5.1.1 8-BIT TIMER MODE
When used as a timer, the Timer0 module will
increment every instruction cycle (without prescaler).
Timer mode is selected by clearing the T0CS bit of the
OPTION register to ‘0’.
When TMR0 is written, the increment is inhibited for
two instruction cycles immediately following the write.
5.1.2 8-BIT COUNTER MODE
When used as a counter, the Timer0 module will
increment on every rising or falling edge of the T0CKI
pin. The incrementing edge is determined by the T0SE
bit of the OPTION register. Counter mode is selected by
setting the T0CS bit of the OPTION register to ‘1’.
FIGURE 5-1: TIMER0/WDT PRESCALER BLOCK DIAGRAM
Note: The value written to the TMR0 register
can be adjusted, in order to account for
the two instruction cycle delay when
TMR0 is written.
T0CKI
T0SE
pin
TMR0
Watchdog
Timer
WDT
Time-out
PS<2:0>
WDTE
Data Bus
Set Flag bit T0IF
on Overflow
T0CS
Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register.
2: SWDTEN and WDTPS<3:0> are bits in the WDTCON register.
3: WDTE bit is in the Configuration Word Register1.
0
1
0
1
0
1
8
8
8-bit
Prescaler
0
1
FOSC/4
PSA
PSA
PSA
16-bit
Prescaler 16
WDTPS<3:0>
31 kHz
INTOSC
SWDTEN
Sync
2 Tcy
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5.1.3 SOFTWARE PROGRAMMABLE
PRESCALER
A single software programmable prescaler is available
for use with either Timer0 or the Watchdog Timer
(WDT), but not both simultaneously. The prescaler
assignment is controlled by the PSA bit of the OPTION
register. To assign the prescaler to Timer0, the PSA bit
must be cleared to a ‘0’.
There are eight prescaler options for the Timer0 mod-
ule ranging from 1:2 to 1:256. The prescale values are
selectable via the PS<2:0> bits of the OPTION register.
In order to have a 1:1 prescaler value for the Timer0
module, the prescaler must be assigned to the WDT
module.
The prescaler is not readable or writable. When
assigned to the Timer0 module, all instructions writing to
the TMR0 register will clear the prescaler.
When the prescaler is assigned to WDT, a CLRWDT
instruction will clear the prescaler along with the WDT.
5.1.3.1 Switching Prescaler Between
Timer0 and WDT Modules
As a result of having the prescaler assigned to either
Timer0 or the WDT, it is possible to generate an
unintended device Reset when switching prescaler
values. When changing the prescaler assignment from
Timer0 to the WDT module, the instruction sequence
shown in Example 5-1, must be executed.
EXAMPLE 5-1: CHANGING PRESCALER
(TIMER0 WDT)
When changing the prescaler assignment from the
WDT to the Timer0 module, the following instruction
sequence must be executed (see Example 5-2).
EXAMPLE 5-2: CHANGING PRESCALER
(WDT TIMER0)
5.1.4 TIMER0 INTERRUPT
Timer0 will generate an interrupt when the TMR0
register overflows from FFh to 00h. The T0IF interrupt
flag bit of the INTCON register is set every time the
TMR0 register overflows, regardless of whether or not
the Timer0 interrupt is enabled. The T0IF bit must be
cleared in software. The Timer0 interrupt enable is the
T0IE bit of the INTCON register.
5.1.5 USING TIMER0 WITH AN
EXTERNAL CLOCK
When Timer0 is in Counter mode, the synchronization
of the T0CKI input and the Timer0 register is accom-
plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, the
high and low periods of the external clock source must
meet the timing requirements as shown in the
Section 17.0 “Electrical Specifications”.
BANKSEL TMR0 ;
CLRWDT ;Clear WDT
CLRF TMR0 ;Clear TMR0 and
;prescaler
BANKSEL OPTION_REG ;
BSF OPTION_REG,PSA ;Select WDT
CLRWDT ;
;
MOVLW b’11111000’ ;Mask prescaler
ANDWF OPTION_REG,W ;bits
IORLW b’00000101’ ;Set WDT prescaler
MOVWF OPTION_REG ;to 1:32
Note: The Timer0 interrupt cannot wake the
processor from Sleep since the timer is
frozen during Sleep.
CLRWDT ;Clear WDT and
;prescaler
BANKSEL OPTION_REG ;
MOVLW b’11110000’ ;Mask TMR0 select and
ANDWF OPTION_REG,W ;prescaler bits
IORLW b’00000011’ ;Set prescale to 1:16
MOVWF OPTION_REG ;
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REGISTER DEFINITIONS: OPTION REGISTER
REGISTER 5-1: OPTION_REG: OPTION REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual PORT latch values
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of INT pin
0 = Interrupt on falling edge of INT pin
bit 5 T0CS: TMR0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (FOSC/4)
bit 4 T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS<2:0>: Prescaler Rate Select bits
Note 1: A dedicated 16-bit WDT postscaler is available. See Section 14.5 “Watchdog Timer (WDT)” for more
information.
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
BIT VALUE TMR0 RATE WDT RATE
TABLE 5-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
TMR0 Timer0 Module Register 75
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 32
OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 77
TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 40
Legend: = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the
Timer0 module.
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6.0 TIMER1 MODULE WITH GATE
CONTROL
The Timer1 module is a 16-bit timer/counter with the
following features:
16-bit timer/counter register pair (TMR1H:TMR1L)
Programmable internal or external clock source
3-bit prescaler
Optional LP oscillator
Synchronous or asynchronous operation
Timer1 gate (count enable) via comparator or
T1G pin
Interrupt on overflow
Wake-up on overflow (external clock,
Asynchronous mode only)
Time base for the Capture/Compare function
Special Event Trigger (with ECCP)
Comparator output synchronization to Timer1
clock
Figure 6-1 is a block diagram of the Timer1 module.
6.1 Timer1 Operation
The Timer1 module is a 16-bit incrementing counter
which is accessed through the TMR1H:TMR1L register
pair. Writes to TMR1H or TMR1L directly update the
counter.
When used with an internal clock source, the module is
a timer. When used with an external clock source, the
module can be used as either a timer or counter.
6.2 Clock Source Selection
The TMR1CS bit of the T1CON register is used to select
the clock source. When TMR1CS = 0, the clock source
is FOSC/4. When TMR1CS = 1, the clock source is
supplied externally.
FIGURE 6-1: TIMER1 BLOCK DIAGRAM
Clock Source TMR1CS
FOSC/4 0
T1CKI pin 1
Note 1: ST Buffer is low power type when using LP osc, or high speed type when using T1CKI.
2: Timer1 register increments on rising edge.
3: Synchronize does not operate while in Sleep.
4: SYNCC2OUT is synchronized when the C2SYNC bit of the CM2CON1 register is set.
TMR1H TMR1L
Oscillator T1SYNC
T1CKPS<1:0>
FOSC/4
Internal
Clock
Prescaler
1, 2, 4, 8
1
0
0
1
Synchronized
clock input
2
Set flag bit
TMR1IF on
Overflow TMR1(2)
TMR1GE
TMR1ON
T1OSCEN
1
0
SYNCC2OUT(4)
T1GSS
T1GINV
To C2 Comparator Module
Timer1 Clock
TMR1CS
T1OSI
T1OSO/T1CKI
(1)
EN
INTOSC
Without CLKOUT
Synchronize(3)
det
T1G
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6.2.1 INTERNAL CLOCK SOURCE
When the internal clock source is selected the
TMR1H:TMR1L register pair will increment on multiples
of FOSC as determined by the Timer1 prescaler.
6.2.2 EXTERNAL CLOCK SOURCE
When the external clock source is selected, the Timer1
module may work as a timer or a counter.
When counting, Timer1 is incremented on the rising
edge of the external clock input T1CKI. In addition, the
Counter mode clock can be synchronized to the
microcontroller system clock or run asynchronously.
If an external clock oscillator is needed (and the
microcontroller is using the INTOSC without CLKOUT),
Timer1 can use the LP oscillator as a clock source.
In Counter mode, a falling edge must be registered by
the counter prior to the first incrementing rising edge
after one or more of the following conditions (see
Figure 6-2):
Timer1 is enabled after POR or BOR Reset
A write to TMR1H or TMR1L
T1CKI is high when Timer1 is disabled and when
Timer1 is re-enabled T1CKI is low.
6.3 Timer1 Prescaler
Timer1 has four prescaler options allowing 1, 2, 4 or 8
divisions of the clock input. The T1CKPS bits of the
T1CON register control the prescale counter. The
prescale counter is not directly readable or writable;
however, the prescaler counter is cleared upon a write to
TMR1H or TMR1L.
6.4 Timer1 Oscillator
A low-power 32.768 kHz oscillator is built-in between
pins T1OSI (input) and T1OSO (amplifier output). The
oscillator is enabled by setting the T1OSCEN control
bit of the T1CON register. The oscillator will continue to
run during Sleep.
The Timer1 oscillator is identical to the LP oscillator.
The user must provide a software time delay to ensure
proper oscillator start-up.
TRISC0 and TRISC1 bits are set when the Timer1
oscillator is enabled. RC0 and RC1 bits read as ‘0’ and
TRISC0 and TRISC1 bits read as ‘1’.
6.5 Timer1 Operation in
Asynchronous Counter Mode
If control bit T1SYNC of the T1CON register is set, the
external clock input is not synchronized. The timer
continues to increment asynchronous to the internal
phase clocks. The timer will continue to run during
Sleep and can generate an interrupt on overflow,
which will wake-up the processor. However, special
precautions in software are needed to read/write the
timer (see Section 6.5.1 “Reading and Writing
Timer1 in Asynchronous Counter Mode”).
6.5.1 READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER
MODE
Reading TMR1H or TMR1L while the timer is running
from an external asynchronous clock will ensure a valid
read (taken care of in hardware). However, the user
should keep in mind that reading the 16-bit timer in two
8-bit values itself, poses certain problems, since the
timer may overflow between the reads.
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write
contention may occur by writing to the timer registers,
while the register is incrementing. This may produce an
unpredictable value in the TMR1H:TTMR1L register
pair.
6.6 Timer1 Gate
Timer1 gate source is software configurable to be the
T1G pin or the output of Comparator C2. This allows the
device to directly time external events using T1G or
analog events using Comparator C2. See the
CM2CON1 register (Register 8-3) for selecting the
Timer1 gate source. This feature can simplify the
software for a Delta-Sigma A/D converter and many
other applications. For more information on Delta-Sigma
A/D converters, see the Microchip web site
(www.microchip.com).
Timer1 gate can be inverted using the T1GINV bit of
the T1CON register, whether it originates from the T1G
pin or Comparator C2 output. This configures Timer1 to
measure either the active-high or active-low time
between events.
Note: The oscillator requires a start-up and
stabilization time before use. Thus,
T1OSCEN should be set and a suitable
delay observed prior to enabling Timer1.
Note: When switching from synchronous to
asynchronous operation, it is possible to
skip an increment. When switching from
asynchronous to synchronous operation,
it is possible to produce a single spurious
increment.
Note: TMR1GE bit of the T1CON register must
be set to use the Timer1 gate.
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6.7 Timer1 Interrupt
The Timer1 register pair (TMR1H:TMR1L) increments
to FFFFh and rolls over to 0000h. When Timer1 rolls
over, the Timer1 interrupt flag bit of the PIR1 register is
set. To enable the interrupt on rollover, you must set
these bits:
Timer1 interrupt enable bit of the PIE1 register
PEIE bit of the INTCON register
GIE bit of the INTCON register
The interrupt is cleared by clearing the TMR1IF bit in
the Interrupt Service Routine.
6.8 Timer1 Operation During Sleep
Timer1 can only operate during Sleep when setup in
Asynchronous Counter mode. In this mode, an external
crystal or clock source can be used to increment the
counter. To set up the timer to wake the device:
TMR1ON bit of the T1CON register must be set
TMR1IE bit of the PIE1 register must be set
PEIE bit of the INTCON register must be set
The device will wake-up on an overflow and execute
the next instruction. If the GIE bit of the INTCON
register is set, the device will call the Interrupt Service
Routine (0004h).
6.9 ECCP Capture/Compare Time
Base
The ECCP module uses the TMR1H:TMR1L register
pair as the time base when operating in Capture or
Compare mode.
In Capture mode, the value in the TMR1H:TMR1L
register pair is copied into the CCPRxH:CCPRxL
register pair on a configured event.
In Compare mode, an event is triggered when the value
CCPRxH:CCPRxL register pair matches the value in
the TMR1H:TMR1L register pair. This event can be a
Special Event Trigger.
See Section 11.0 “Capture/Compare/PWM Modules
(CCP1 and CCP2)” for more information.
6.10 ECCP Special Event Trigger
If an ECCP is configured to trigger a special event, the
trigger will clear the TMR1H:TMR1L register pair. This
special event does not cause a Timer1 interrupt. The
ECCP module may still be configured to generate a
ECCP interrupt.
In this mode of operation, the CCPRxH:CCPRxL
register pair effectively becomes the period register for
Timer1.
Timer1 should be synchronized to the FOSC to utilize
the Special Event Trigger. Asynchronous operation of
Timer1 can cause a Special Event Trigger to be
missed.
In the event that a write to TMR1H or TMR1L coincides
with a Special Event Trigger from the ECCP, the write
will take precedence.
For more information, see Section 11.0 “Capture/
Compare/PWM Modules (CCP1 and CCP2)”.
6.11 Comparator Synchronization
The same clock used to increment Timer1 can also be
used to synchronize the comparator output. This
feature is enabled in the Comparator module.
When using the comparator for Timer1 gate, the
comparator output should be synchronized to Timer1.
This ensures Timer1 does not miss an increment if the
comparator changes.
For more information, see Section 8.0 “Comparator
Module”.
FIGURE 6-2: TIMER1 INCREMENTING EDGE
Note: The TMR1H:TTMR1L register pair and
the TMR1IF bit should be cleared before
enabling interrupts.
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
Note 1: Arrows indicate counter increments.
2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of
the clock.
\ITMR1ON : U. \ITMR1ON : 1. TMR1CS: 1. TMR1CS: U.
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6.12 Timer1 Control Register
The Timer1 Control register (T1CON), shown in
Register 6-1, is used to control Timer1 and select the
various features of the Timer1 module.
REGISTER DEFINITIONS: TIMER1 CONTROL
REGISTER 6-1: T1CON: TIMER1 CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
T1GINV(1) TMR1GE(2) T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set 0’ = Bit is cleared x = Bit is unknown
bit 7 T1GINV: Timer1 Gate Invert bit(1)
1 = Timer1 gate is active-high (Timer1 counts when gate is high)
0 = Timer1 gate is active-low (Timer1 counts when gate is low)
bit 6 TMR1GE: Timer1 Gate Enable bit(2)
If TMR1ON = 0:
This bit is ignored
If TMR1ON = 1:
1 = Timer1 counting is controlled by the Timer1 Gate function
0 = Timer1 is always counting
bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale Value
10 = 1:4 Prescale Value
01 = 1:2 Prescale Value
00