ATA6827 Datasheet by Microchip Technology

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A IIIEI. 41—meg
Features
Supply Voltage up to 40V
RDSon Typically 0.8Ω at 25°C, Maximum 1.8Ω at 200°C
Up to 1.0A Output Current
Three Half-bridge Outputs Formed by Three High-side and Three Low-side Drivers
Capable to Switch all Kinds of Loads Such as DC Motors, Bulbs, Resistors, Capacitors
and Inductors
No Shoot-through Current
Outputs Short-circuit Protected
Overtemperature Protection for Each Switch and Overtemperature Prewarning
Undervoltage Protection
Various Diagnostic Functions Such as Shorted Output, Open-load, Overtemperature
and Power-supply Fail Detection
Serial Data Interface, Daisy Chain Capable, up to 2 MHz Clock Frequency
QFN18 Package
1. Description
The ATA6827 is a fully protected driver IC specially designed for high temperature
applications. In mechatronic solutions, for example turbo charger or exhaust gas recir-
culation systems, many flaps have to be controlled by DC motor driver ICs which are
located very close to the hot engine or actuator where ambient temperatures up to
150°C are usual. Due to the advantages of SOI technology junction temperatures up
to 200°C are allowed. This enables new cost effective board design possibilities to
achieve complex mechatronic solutions.
The ATA6827 is a fully protected Triple Half-Bridge to control up to 3 different loads by
a microcontroller in automotive and industrial applications. Each of the 3 high-side and
3 low-side drivers is capable to drive currents up to 1.0A. The drivers are internally
connected to form 3 half-bridges and can be controlled separately from a standard
serial data interface. Therefore, all kinds of loads such as bulbs, resistors, capacitors
and inductors can be combined. The IC design especially supports the application of
H-bridges to drive DC motors.
Protection is guaranteed regarding short-circuit conditions, overtemperature and
undervoltage. Various diagnostic functions and a very low quiescent current in
standby mode opens a wide range of applications. Automotive qualification gives
added value and enhanced quality for exacting requirements of automotive
applications.
High
Temperature
Triple
Half-bridge
Driver with
Serial Input
Control
ATA6827
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A1—IIIEI.® DDDDDDDDDDDDDDD DDDDDDDDDDDDDDDD
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ATA6827
Figure 1-1. Block Diagram
Fault
detector
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S
2
L
S
2
H
S
1
L
S
1
Control
logic
5
CLK
7
DO
8
INH
3
CS
4
DI
Input register
Ouput register Serial interface
H
S
3
L
S
3
H
S
2
L
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2
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1
S
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D
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Fault
detector
Power on
reset
Charge
pump
UV
protection
Thermal
protection
Fault
detector
VS
10
VCC
9
GND
6
GND
18
GND
17
GND
14
OUT3F
1
OUT1F
15
OUT2F
12
VS
11
2
OUT3S
13
OUT2S
16
OUT1S
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2. Pin Configuration
Figure 2-1. Pinning QFN18
OUT3S
OUT3F
CS
DI
CLK
GND
OUT2F
VS
VS
VCC
INH
DO
PGND3
PGND1
OUT1S
OUT1F
PGND2
OUT2S
1
2
3
4
5
6
12
11
10
9
8
7
18 17 16 15 1314
Table 2-1. Pin Description
Pin Symbol Function
1 OUT3S Used only for final testing, to be connected to OUT3F
2OUT3F Half-bridge output 3
3CS Chip select input; 5-V CMOS logic level input with internal pull up;
low = serial communication is enabled, high = disabled
4DI Serial data input; 5-V CMOS logic level input with internal pull down; receives serial data from the control
device; DI expects a 16-bit control word with LSB being transferred first
5CLK Serial clock input; 5-V CMOS logic level input with internal pull down;
controls serial data input interface and internal shift register (fmax = 2 MHz)
6GND Ground; reference potential
7DO
Serial data output; 5-V CMOS logic level tri-state output for output (status) register data; sends 16-bit
status information to the microcontroller (LSB is transferred first); output will remain tri-stated unless
device is selected by CS = low, therefore, several ICs can operate on one data output line only.
8 INH Inhibit input; 5-V logic input with internal pull down; low = standby, high = normal operation
9VCC Logic supply voltage (5 V)
10 VS Power supply for output stages OUT1, OUT2 and OUT3, internal supply
11 VS Power supply for output stages OUT1, OUT2 and OUT3, internal supply
12 OUT2F Half-bridge output 2
13 OUT2S Used only for final testing, to be connected to OUT2F
14 PGND2 Power Ground OUT2
15 OUT1F Half-bridge output 1
16 OUT1S Used only for final testing, to be connected to OUT13F
17 PGND1
PGND3 Power Ground OUT1 and OUT3
18 PGND1
PGND3 Power Ground OUT1 and OUT3
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3. Functional Description
3.1 Serial Interface
Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchronized
to CLK and are accepted on the falling edge of the CLK signal. LSB (bit 0, SRR) has to be trans-
ferred first. Execution of new input data is enabled on the rising edge of the CS signal. When CS
is high, pin DO is in tri-state condition. This output is enabled on the falling edge of CS. Output
data will change their state with the rising edge of CLK and stay stable until the next rising edge
of CLK appears. LSB (bit 0, TP) is transferred first.
Figure 3-1. Data Transfer
SRR LS1 HS1 LS2 HS2 LS3 HS3 n. u. n. u. n. u. n. u. n. u. n. u. OCS n. u. n. u.
CS
DI
CLK
DO
TP S1L S1H S2L S2H S3L S3H n. u. n. u. n. u. n. u. n. u. n. u. SCD OPL PSF
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Table 3-1. Input Data Protocol
Bit Input Register Function
0SRR
Status register reset (high = reset; the bits PSF, OPL and SCD in the
output data register are set to low)
1LS1 Controls output LS1 (high = switch output LS1 on)
2HS1 Controls output HS1 (high = switch output HS1 on)
3LS2 See LS1
4HS2 See HS1
5LS3 See LS1
6HS3 See HS1
7n. u. Not used
8n. u. Not used
9n. u. Not used
10 n. u. Not used
11 n. u. Not used
12 n. u. Not used
13 OCS Overcurrent shutdown (high = overcurrent shutdown is active)
14 n. u. Not used
15 n. u. Not used
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Table 3-2. Output Data Protocol
Bit
Output (Status)
Register Function
0 TP Temperature prewarning: high = warning
1Status LS1 High = output is on, low = output is off; not affected by SRR
2Status HS1 High = output is on, low = output is off; not affected by SRR
3Status LS2 Description see LS1
4Status HS2 Description see HS1
5Status LS3 Description see LS1
6Status HS3 Description see HS1
7n. u. Not used
8n. u. Not used
9n. u. Not used
10 n. u. Not used
11 n. u. Not used
12 n. u. Not used
13 SCD
Short circuit detected: set high when at least one high-side or low-side
switch is switched off by a short-circuit condition. Bits 1 to 6 can be used
to detect the shorted switch.
14 OPL
Open load detected: set high, when at least one active high-side or
low-side switch sinks/sources a current below the open load threshold
current.
15 PSF Power-supply fail: undervoltage at pin VS detected
After power-on reset, the input register has the following status:
Bit 15 Bit 14 Bit 13
(OCS)
Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6
(HS3)
Bit 5
(LS3)
Bit 4
(HS2)
Bit 3
(LS2)
Bit 2
(HS1)
Bit 1
(LS1)
Bit 0
(SRR)
xxHxxxxxxLLLLLLL
The following patterns are used to enable internal test modes of the IC. It is not recommended to use these patterns during
normal operation.
Bit 15 Bit 14 Bit 13
(OCS)
Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6
(HS3)
Bit 5
(LS3)
Bit 4
(HS2)
Bit 3
(LS2)
Bit 2
(HS1)
Bit 1
(LS1)
Bit 0
(SRR)
HHHHHLLLLLLLLLLL
HHHLLHHLLLLLLLLL
HHHLLLLHHLLLLLLL
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3.2 Power-supply Fail
In case of undervoltage at pin VS, the Power-Supply Fail bit (PSF) in the output register is set
and all outputs are disabled. To detect an undervoltage, its duration has to be longer than the
undervoltage detection delay time tdUV. The outputs are enabled immediately when supply volt-
age recovers to a normal operating value. The PSF bit stays high until it is reset by the SRR
(Status Register Reset) bit in the input register.
3.3 Open-load Detection
If the current through a high-side or low-side switch in the ON-state stays below the open-load
detection threshold, the open-load detection bit (OPL) in the output register is set.
The OPL bit stays high until it is reset by the SRR bit in the input register. To detect an open
load, its duration has to be longer than the open-load detection delay time tdSd.
3.4 Overtemperature Protection
If the junction temperature of one or more output stages exceeds the thermal prewarning thresh-
old, TjPW set, the temperature prewarning bit (TP) in the output register is set. When the
temperature falls below the thermal prewarning threshold, TjPW reset, the bit TP is reset. The TP
bit can be read without transferring a complete 16-bit data word. The status of TP is available at
pin DO with the falling edge of CS. After the microcontroller has read this information, CS is set
high and the data transfer is interrupted without affecting the status of input and output registers.
If the junction temperature of one or more output stages exceeds the thermal shutdown thresh-
old, Tj switch off, all outputs are disabled and the corresponding bits in the output register are set to
low. The outputs can be enabled again when the temperature falls below the thermal shutdown
threshold, Tjswitch on and the SRR bit in the input register is set to high. Hysteresis of thermal pre-
warning and shutdown threshold avoids oscillations.
3.5 Short-circuit Protection
The output currents are limited by a current regulator. Overcurrent detection is activated by writ-
ing a high to the OCS (Overcurrent Shutdown) bit in the input register. When the current in an
output stage exceeds the overcurrent limitation and shutdown threshold, it is switched off after a
delay time (tdSd). The short-circuit detection bit (SCD) is set and the corresponding status bit in
the output register is set to low. For OCS = low the overcurrent shutdown is inactive. The SCD
bit is also set if the current exceeds the overcurrent limitation and shutdown threshold, but the
outputs are not affected. By writing a high to the SRR bit in the input register the SCD bit is reset
and the disabled outputs are enabled.
3.6 Inhibit
Applying 0V to pin 8 (INH) inhibits the ATA6827.
All output switches are then turned off and switched to tri-state. The data in the output register is
deleted. The output switches can be activated again by switching pin 8 (INH) to 5V which initi-
ates an internal power-on reset.
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4. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
All values refer to GND pins.
Parameters Pin Symbol Value Unit
Supply voltage 10, 11 VVS –0.3 to +40 V
Supply voltage
t < 0.5s; IS > –2A 10, 11 VVS –1 V
Logic supply voltage 9 VVCC –0.3 to +7 V
Logic input voltage 3, 4, 5, 8 VCS,VDI, VCLK, VINH –0.3 to VVCC + 0.3 V
Logic output voltage 7 VDO –0.3 to VVCC + 0.3 V
Input current 3, 4, 5, 8 ICS, IDI, ICLK, IINH –10 to +10 mA
Output current 7 IDO –10 to +10 mA
Output current 2, 12, 15 IOut3, IOut2, IOut1 Internally limited, see output specification
Output voltage 2, 12, 15 IOut3, IOut2, IOut1 –0.3 to +40 V
Reverse conducting current
(tpulse =150 µs) 2, 12, 15 IOut3, IOut2, IOut1 17 A
Junction temperature range Tj–40 to +200 °C
Storage temperature range TSTG –55 to +200 °C
Ambient temperature range Ta–40 to +150 °C
5. Thermal Resistance
Parameters Test Conditions Symbol Value Unit
Junction case Rthjc 5K/W
Junction ambient (1) RthJA 40 K/W
Notes: 1. Depends on PCB board design
6. Operating Range
Parameters Symbol Value Unit
Supply voltage VVS VUV(2) to 40 V
Logic supply voltage VVCC 4.75 to 5.25 V
Logic input voltage VCS,VDI, VCLK, VINH –0.3 to VVCC V
Serial interface clock frequency fCLK 2MHz
Junction temperature range Tj–40 to +200 °C
Note: Threshold for undervoltage detection
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7. Noise and Surge Immunity
Parameters Test Conditions Value
Conducted interferences ISO 7637-1 Level 4(1)
Interference suppression VDE 0879 Part 2 Level 5
ESD (Human Body Model) ESD S 5.1 2 kV
CDM (Charged Device Model) ESD STM 5.3.1-1999 all pins 500V
Note: Test pulse 5: Vsmax = 40V
8. Electrical Characteristics
7.5V < VVS < 40V; 4.75V < VVCC < 5.25 V; INH = High; –40°C Tj200°C; Ta150°C; unless otherwise specified, all values refer to
GND pins.
No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
1 Current Consumption
1.1 Quiescent current VS VVS < 20V, INH = low 10, 11 IVS 160 µA A
1.2 Quiescent current VCC 4.75 V < VVCC < 5.25V,
INH = low 9 IVCC 15 40 µA A
1.3 Supply current VS VVS < 20V normal
operating, all outputs off 10, 11 IVS 4 6 mA A
1.4 Supply current VCC 4.75V < VVCC < 5.25V,
normal operating 9 IVCC 350 500 µA A
1.5 Discharge current VS VVS = 32.5V,
INH = low 10, 11 IVS 0.5 5.5 mA A
1.6 Discharge current VS VVS = 40V,
INH = low 10, 11 IVS 2.0 10 mA A
2 Undervoltage Detection, Power-on Reset
2.1 Power-on reset
threshold 9 VVCC 3.1 3.9 4.5 V A
2.2 Power-on reset
delay time After switching on VCC tdPor 30 95 190 µs A
2.3 Undervoltage-detection
threshold VCC = 5V 10, 11 VUv 5.5 7.1 V A
2.4 Undervoltage-detection
hysteresis VCC = 5V 10, 11 ΔVUv 0.6 V A
2.5 Undervoltage-detection
delay time tdUV 10 40 µs A
3 Thermal Prewarning and Shutdown
3.1 Thermal prewarning set TjPW set 170 195 220 °C B
3.2 Thermal prewarning
reset TjPW reset 155 180 205 °C B
3.3 Thermal prewarning
hysteresis ΔTjPW 15 °C B
3.4 Thermal shutdown off Tj switch off 200 225 250 °C B
3.5 Thermal shutdown on Tj switch on 185 210 235 °C B
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note: 1. Delay time between rising edge of the input signal at pin CS after data transmission and switch on output stages to 90% of
final level. Device not in standby for t > 1 ms
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3.6 Thermal shutdown
hysteresis ΔTj switch off 15 °C B
3.7
Ratio thermal shutdown
off/thermal prewarning
set
Tj switch off/
TjPW set 1.05 1.15 B
3.8
Ratio thermal shutdown
on/thermal prewarning
reset
Tj switch on/
TjPW reset 1.05 1.15 B
4 Output Specification (OUT1-OUT3)
4.1
On resistance
IOut 1-3 = –0.9A 2, 12,
15 RDSOn1-3 1.8 ΩA
4.2 IOut 1-3 = +0.9A 2, 12,
15 RDSOn1-3 1.8 ΩA
4.3 High-side output
leakage current
VOut 1-3 = 0V,
output stages off
2, 12,
15 IOut1-3 –60 µA A
4.4 Low-side output
leakage current
VOut 1-3 = VVS,
output stages off
2, 12,
15 IOut1-3 300 µA A
4.5
High-side switch
reverse diode forward
voltage
IOut 1-3 = 1.5A 2, 12,
15 VOut1-3 – VVS 2 V A
4.6 Low-side switch reverse
diode forward voltage IOut 1-3 = –1.5A 2, 12,
15 VOut 1-3 –2 V A
4.7
High-side overcurrent
limitation and shutdown
threshold
7.5V < VS < 20V 2, 12,
15 IOut1-3 1.0 1.3 1.7 AA A
4.8
Low-side overcurrent
limitation and shutdown
threshold
7.5V < VS < 20V 2, 12,
15 IOut1-3 –1.7 –1.3 –1.0 A A
4.18
High-side overcurrent
limitation and shutdown
threshold
20V < VS < 40V 2, 12,
15 IOut1-3 1.0 1.3 2.0 AA A
4.19
Low-side overcurrent
limitation and shutdown
threshold
20V < VS < 40V 2, 12,
15 IOut1-3 –2.0 –1.3 –1.0 A A
4.9 Overcurrent shutdown
delay time
2, 12,
15 tdSd 10 40 µs A
4.10 High-side open-load
detection threshold
2, 12,
15 IOut1-3 –55 –30 –5 mA A
4.11 Low-side open-load
detection threshold
2, 12,
15 IOut1-3 530 55 mA A
4.12 Open-load detection
delay time tdSd 200 600 µs A
8. Electrical Characteristics (Continued)
7.5V < VVS < 40V; 4.75V < VVCC < 5.25 V; INH = High; –40°C Tj200°C; Ta150°C; unless otherwise specified, all values refer to
GND pins.
No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note: 1. Delay time between rising edge of the input signal at pin CS after data transmission and switch on output stages to 90% of
final level. Device not in standby for t > 1 ms
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4.13 High-side output switch
on delay(1) VVS = 13V
RLoad = 30Ωtdon 20 µs A
4.14 Low-side output switch
on delay(1) VVS = 13V
RLoad = 30Ωtdon 20 µs A
4.15 High-side output switch
off delay(1) VVS = 13V
RLoad = 30Ωtdoff 20 µs A
4.16 Low-side output switch
off delay(1) VVS = 13V
RLoad = 30Ωtdoff sA
4.17
Dead time between
corresponding high-
and low-side switches
VVS = 13V
RLoad = 30Ωtdon – tdoff 1µs A
5 Logic Inputs DI, CLK, CS, INH
5.1 Input voltage low-level
threshold
3, 4, 5,
8VIL 0.3 ×
VVCC V A
5.2 Input voltage high-level
threshold
3, 4, 5,
8VIH 0.7 ×
VVCC V A
5.3 Hysteresis of input
voltage
3, 4, 5,
8ΔVI50 700 mV B
5.4 Pull-down current pin
DI, CLK, INH VDI, VCLK, VINH = VCC 4, 5, 8 IPD 570 µA A
5.5 Pull-up current
Pin CS VCS = 0V 3 IPU –70 –5 µA A
6 Serial Interface – Logic Output DO
6.1 Output-voltage low level IDOL = 2 mA 7 VDOL 0.4 V A
6.2 Output-voltage high
level IDOL = –2 mA 7 VDOH VVCC
–0.7V V A
6.3 Leakage current
(tri-state)
VCS = VCC
0V < VDO < VVCC 7 IDO –15 +15 µA A
7Inhibit Input - Timing
7.1
Delay time from
standby to normal
operation
tdINH 100 µs A
8. Electrical Characteristics (Continued)
7.5V < VVS < 40V; 4.75V < VVCC < 5.25 V; INH = High; –40°C Tj200°C; Ta150°C; unless otherwise specified, all values refer to
GND pins.
No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note: 1. Delay time between rising edge of the input signal at pin CS after data transmission and switch on output stages to 90% of
final level. Device not in standby for t > 1 ms
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9. Serial Interface – Timing
No. Parameters Test Conditions Pin Timing Chart No.(1) Symbol Min. Typ. Max. Unit Type*
8.1 DO enable after CS
falling edge CDO = 100 pF 7 1 tENDO 200 ns D
8.2 DO disable after CS
rising edge CDO = 100 pF 7 2 tDISDO 200 ns D
8.3 DO fall time CDO = 100 pF 7 - tDOf 100 ns D
8.4 DO rise time CDO = 100 pF 7 - tDOr 100 ns D
8.5 DO valid time CDO = 100 pF 7 10 tDOVal 200 ns D
8.6 CS setup time 3 4 tCSSethl 225 ns D
8.7 CS setup time 3 8 tCSSetlh 225 ns D
8.8 CS high time 3 9 tCSh 500 ns D
8.9 CLK high time 5 5 tCLKh 225 ns D
8.10 CLK low time 5 6 tCLKl 225 ns D
8.11 CLK period time 5 - tCLKp 500 ns D
8.12 CLK setup time 5 7 tCLKSethl 225 ns D
8.13 CLK setup time 5 3 tCLKSetlh 225 ns D
8.14 DI setup time 4 11 tDIset 40 ns D
8.15 DI hold time 4 12 tDIHold 40 ns D
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note: 1. Serial Interface Timing with Chart Numbers
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Figure 9-1. Serial Interface Timing with Chart Numbers
1
DO
CS
CLK
CS
DO
CLK
Output DO: High level = 0.8 × VCC, low level = 0.2 × VCC
Inputs DI, CLK, CS: High level = 0.7 × VCC, low level = 0.3 × VCC
DI
11
5
6 8
10 12
3
9
2
4
7
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10. Application Circuit
Figure 10-1. Application Circuit
11. Application Notes
It is strongly recommended to connect the blocking capacitors at VCC and VS as close as possi-
ble to the power supply and GND pins.
Recommended value for capacitors at VS:
Electrolytic capacitor C > 22 µF in parallel with a ceramic capacitor C = 100 nF. The value for
electrolytic capacitor depends on external loads, conducted interferences and reverse conduct-
ing current IOut1,2,3 (see Section 4. “Absolute Maximum Ratings” on page 7).
Recommended value for capacitors at VCC:
Electrolytic capacitor C > 10 µF in parallel with a ceramic capacitor C = 100 nF.
To reduce thermal resistance it is recommended to place cooling areas on the PCB as close as
possible to the GND pins and to the die pad.
VCC
VCC
VCC
+
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detector
Fault
detector
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S
2
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S
2
H
S
1
L
S
1
Control
logic
5
CLK
7
DO
8
INH
U5021M
Watchdog
Enable
Reset
Trigger
3
CS
4
DI
Input register
Ouput register Serial interface
H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
L
S
1
S
R
R
H
S
3
L
S
3
O
S
C
P
S
F
Fault
detector
Micro-
controller
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C
D
Fault
detector
Fault
detector
Power on
reset
Charge
pump
UV
protection
Thermal
protection
Fault
detector
VS
VS
13V
VBatt
5V
VCC
BYT41D
+
10
VCC
9
GND
6
GND
18
GND
17
GND
14
OUT3F
2
OUT1F
15
OUT2F
MM
12
VS
11
113 16
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13. Package Information
14. Revision History
12. Ordering Information
Extended Type Number Package Remarks
ATA6827-PIQW QFN18, 4 mm × 4 mm Taped and reeled, Pb-free
specifications
according to DIN
technical drawings
0.4±0.1
18
1
6
Pin 1 identification
13 18
12
7
1
6
Package: VQFN_4 x 4_18L
Exposed pad 2.7 x 3.175
Dimensions in mm
Not indicated tolerances ±0.05
Issue: 1; 26.04.07
Drawing-No.: 6.543-5133.01-4
0.2
2.5
0.175
0.5 nom.
Z
2.5
2.7±0.15
3.175±0.15
Z 10:1
0.9±0.1
0.23±0.07
4
Top
Bottom
Please note that the following page numbers referred to in this section refer to the specific revision
mentioned, not to this document.
Revision No. History
4912E-auto-02/10 Section 5 “Thermal Resistance” on page 7 changed
4912D-auto-06/07
Put datasheet in a new template
Package drawing changed
Block diagram changed
Pinning drawing changed
Pin Description table changed
Application circuit drawing changed
.1 lllEl®
4912E–AUTO–02/10
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