T6818, ATA6828 Datasheet by Microchip Technology

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A IIIEI. 41m —«a
Features
Supply Voltage up to 40 V
RDSon Typically 0.5 at 25°C, Maximum 1.1 at 150°C
Up to 1.5 A Output Current
Three Half-bridge Outputs Formed by Three High-side and Three Low-side Drivers
Capable to Switch all Kinds of Loads Such as DC Motors, Bulbs, Resistors, Capacitors
and Inductors
No Shoot-through Current
Very Low Quiescent Current IS < 5 µA in Standby Mode versus Total
Temperature Range
Outputs Short-circuit Protected
Overtemperature Protection for Each Switch and Overtemperature
Prewarning
Undervoltage Protection
Various Diagnostic Functions Such as Shorted Output, Open-load, Overtemperature
and Power-supply Fail Detection
Serial Data Interface, Daisy Chain Capable, up to 2 MHz Clock Frequency
SO14 Power Package
1. Description
The T6818/ATA6828 are fully protected driver interfaces designed in 0.8-µm BCD-
MOS technology. They are used to control up to 3 different loads by a microcontroller
in automotive and industrial applications.
Each of the 3 high-side and 3 low-side drivers is capable to drive currents up to 1.5 A.
The drivers are internally connected to form 3 half-bridges and can be controlled sep-
arately from a standard serial data interface. Therefore, all kinds of loads such as
bulbs, resistors, capacitors and inductors can be combined. The IC design especially
supports the application of H-bridges to drive DC motors.
Protection is guaranteed regarding short-circuit conditions, overtemperature and und-
ervoltage. Various diagnostic functions and a very low quiescent current in
stand-by-mode opens a wide range of applications. Automotive qualification (protec-
tion against conducted interferences, EMC protection and 2-kV ESD protection) gives
added value and enhanced quality for exacting requirements of automotive
applications.
Triple Half-
bridge DMOS
Output Driver
with Serial Input
Control
T6818/ATA6828
Rev. 4530G–BCD–09/05
2 .1 ma; DDDDDDDDDDDDDDD DDDDDDDDDDDDDDDD
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4530G–BCD–09/05
T6818/ATA6828
Figure 1-1. Block Diagram
DI
CLK
INH
DO
CS UV
protection
Serial interface
Input register
Output register
H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
L
S
1
S
R
R
O
C
Sn.n. n. n.n.n.
P
S
F
O
P
L
S
C
D
n.
u. H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
L
S
1
T
P
OUT3
VS
VCC
Thermal
protection
Control
logic Power-on
reset
Charge
pump
OUT2 OUT1
n.n.
u.
GND
n.
u.
n.
u.
n.
u.
n.
u.
n.
u.
u. u. u. u. u. u. u. 3
11
1
7
8
14
21213
5
6
4
10
9
GND
GND
GND
Fault
detect
Fault
detect
Fault
detect
Fault
detect Fault
detect Fault
detect
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4530G–BCD–09/05
T6818/ATA6828
2. Pin Configuration
Figure 2-1. Pining SO14/PSO14
GND
OUT3
VS
CS
DI
CLK
GND
GND
OUT1
OUT2
VCC
INH
DO
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
Table 2-1. Pin Description
Pin Symbol Function
1GND
T6818: ground; reference potential; internal connection to pin 7, 8 and 14; cooling tab
ATA6828: additional connection to heat slug
2OUT3
Half-bridge output 3; formed by internally connected power MOS high-side switch 3 and low-side switch 3
with internal reverse diodes; short circuit protection; overtemperature protection; diagnosis for short and
open load
3VS Power supply for output stages OUT1, OUT2 and OUT3, internal supply
4CS Chip select input; 5-V CMOS logic level input with internal pull up;
low = serial communication is enabled, high = disabled
5DI Serial data input; 5-V CMOS logic level input with internal pull down; receives serial data from the control
device; DI expects a 16-bit control word with LSB being transferred first
6CLK Serial clock input; 5-V CMOS logic level input with internal pull down; controls serial data input interface
and internal shift register (f
max
= 2 MHz)
7GND Ground; see pin 1
8GND Ground; see pin 1
9DO
Serial data output; 5-V CMOS logic level tri-state output for output (status) register data; sends 16-bit
status information to the microcontroller (LSB is transferred first); output will remain tri-stated unless
device is selected by CS = low, therefore, several ICs can operate on one data output line only.
10 INH Inhibit input; 5-V logic input with internal pull down; low = standby, high = normal operation
11 VCC Logic supply voltage (5 V)
12 OUT2 Half-bridge output 2; see pin 2
13 OUT1 Half-bridge output 1; see pin 2
14 GND Ground; see pin 1
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4530G–BCD–09/05
T6818/ATA6828
3. Functional Description
3.1 Serial Interface
Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchronized
to CLK and are accepted on the falling edge of the CLK signal. LSB (bit 0, SRR) has to be trans-
ferred first. Execution of new input data is enabled on the rising edge of the CS signal. When CS
is high, pin DO is in tri-state condition. This output is enabled on the falling edge of CS. Output
data will change their state with the rising edge of CLK and stay stable until the next rising edge
of CLK appears. LSB (bit 0, TP) is transferred first.
Figure 3-1. Data Transfer
SRR LS1 HS1 LS2 HS2 LS3 HS3 n. u. n. u. n. u. n. u. n. u. n. u. OCS n. u. n. u.
CS
DI
CLK
DO TP S1L S1H S2L S2H S3L S3H n. u. n. u. n. u. n. u. n. u. n. u. SCD OPL PSF
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Table 3-1. Input Data Protocol
Bit Input Register Function
0SRR
Status register reset (high = reset; the bits PSF, OPL and SCD in the
output data register are set to low)
1LS1 Controls output LS1 (high = switch output LS1 on)
2HS1 Controls output HS1 (high = switch output HS1 on)
3LS2 See LS1
4HS2 See HS1
5LS3 See LS1
6HS3 See HS1
7n. u. Not used
8n. u. Not used
9n. u. Not used
10 n. u. Not used
11 n. u. Not used
12 n. u. Not used
13 OCS Overcurrent shutdown (high = overcurrent shutdown is active)
14 n. u. Not used
15 n. u. Not used
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T6818/ATA6828
Table 3-2. Output Data Protocol
Bit
Output (Status)
Register Function
0 TP Temperature prewarning: high = warning
1Status LS1 High = output is on, low = output is off; not affected by SRR
2Status HS1 High = output is on, low = output is off; not affected by SRR
3Status LS2 Description see LS1
4Status HS2 Description see HS1
5Status LS3 Description see LS1
6Status HS3 Description see HS1
7n. u. Not used
8n. u. Not used
9n. u. Not used
10 n. u. Not used
11 n. u. Not used
12 n. u. Not used
13 SCD
Short circuit detected: set high when at least one high-side or low-side
switch is switched off by a short-circuit condition. Bits 1 to 6 can be used
to detect the shorted switch.
14 OPL
Open load detected: set high, when at least one active high-side or low-
side switch sinks/sources a current below the open load threshold
current.
15 PSF Power-supply fail: undervoltage at pin VS detected
After power-on reset, the input register has the following status:
Bit 15 Bit 14 Bit 13
(OCS)
Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6
(HS3)
Bit 5
(LS3)
Bit 4
(HS2)
Bit 3
(LS2)
Bit 2
(HS1)
Bit 1
(LS1)
Bit 0
(SRR)
xxHxxxxxxLLLLLLL
The following patterns are used to enable internal test modes of the IC. It is not recommended to use these patterns during
normal operation.
Bit 15 Bit 14 Bit 13
(OCS)
Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6
(HS3)
Bit 5
(LS3)
Bit 4
(HS2)
Bit 3
(LS2)
Bit 2
(HS1)
Bit 1
(LS1)
Bit 0
(SRR)
HHHHHLLLLLLLLLLL
HHHLLHHLLLLLLLLL
HHHLLLLHHLLLLLLL
.1 ma;
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T6818/ATA6828
3.2 Power-supply Fail
In case of undervoltage at pin VS, the Power-Supply Fail bit (PSF) in the output register is set
and all outputs are disabled. To detect an undervoltage, its duration has to last longer than the
undervoltage detection delay time tdUV. The outputs are enabled immediately when supply volt-
age recovers normal operation value. The PSF bit stays high until it is reset by the SRR bit in the
input register.
3.3 Open-load Detection
If the current through a high-side or low-side switch in ON-state stays below the open-load
detection threshold, the open-load detection bit (OPL) in the output register is set.
The OPL bit stays high until it is reset by the SRR bit in the input register. To detect an open
load, its duration has to last longer than the open-load detection delay time tdSd.
3.4 Overtemperature Protection
If the junction temperature of one or more output stages exceeds the thermal prewarning thresh-
old, TjPW set, the temperature prewarning bit (TP) in the output register is set. When the
temperature falls below the thermal prewarning threshold, TjPW reset, the bit TP is reset. The TP
bit can be read without transferring a complete 16-bit data word. The status of TP is available at
pin DO with the falling edge of CS. After the microcontroller has read this information, CS is set
high and the data transfer is interrupted without affecting the status of input and output registers.
If the junction temperature of one or more output stages exceeds the thermal shutdown thresh-
old, Tj switch off, all outputs are disabled and the corresponding bits in the output register are set to
low. The outputs can be enabled again when the temperature falls below the thermal shutdown
threshold, Tjswitch on and the SRR bit in the input register is set to high. Hysteresis of thermal pre-
warning and shutdown threshold avoids oscillations.
3.5 Short-circuit Protection
The output currents are limited by a current regulator. Overcurrent detection is activated by writ-
ing a high to the OCS bit in the input register. When the current in an output stage exceeds the
overcurrent limitation and shutdown threshold, it is switched off after a delay time (tdSd). The
short-circuit detection bit (SCD) is set and the corresponding status bit in the output register is
set to low. For OCS = low the overcurrent shutdown is inactive. The SCD bit is also set if the cur-
rent exceeds the overcurrent limitation and shutdown threshold, but the outputs are not affected.
By writing a high to the SRR bit in the input register the SCD bit is reset and the disabled outputs
are enabled.
3.6 Inhibit
0 V applied to pin 10 (INH) inhibits the T6818/ATA6828.
All output switches are then turned off and switched to tri-state. The data in the output register
are deleted. The current consumption is reduced to less than 5 µA at pin VS and less than 25 µA
at pin VCC. The output switches can be activated again by switching pin 10 (INH) to 5 V which
initiates an internal power-on reset.
41m
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4530G–BCD–09/05
T6818/ATA6828
Note: 1. Threshold for undervoltage detection
4. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
All values refer to GND pins.
Parameters Pin Symbol Value Unit
Supply voltage 3 V
VS
–0.3 to +40 V
Supply voltage
t < 0.5 s; I
S
> –2 A 3V
VS
–1 V
Logic supply voltage 11 V
VCC
–0.3 to +7 V
Logic input voltage 4 to 6, 10 V
CS
,V
DI
, V
CLK
, V
INH
–0.3 to V
VCC
+0.3 V
Logic output voltage 9 V
DO
–0.3 to V
VCC
+0.3 V
Input current 4 to 6, 10 I
CS
,I
DI
, I
CLK
,
I
INH
–10 to +10 mA
Output current 9 I
DO
–10 to +10 mA
Output current 2, 12 and 13 I
Out3
, I
Out2,
I
Out1
Internally limited, see output specification
Output voltage 2, 12 and 13 I
Out3
, I
Out2,
I
Out1
–0.3 to +40 V
Reverse conducting current
(t
pulse
= 150 µs)
2, 12 and 13
towards pin 3 I
Out3
, I
Out2,
I
Out1
17 A
Junction temperature range T
J
–40 to +150 °C
Storage temperature range T
STG
–55 to +150 °C
5. Thermal Resistance
Parameters Test Conditions Symbol Value Unit
T6818
Junction pin Measured to GND
Pins 1, 7, 8 and 14 R
thJP
30 K/W
Junction ambient R
thJA
65 K/W
ATA6828
Junction pin Measured to heat slug
GND pins 1, 7, 8 and 14 R
thJP
5K/W
Junction ambient R
thJA
30 K/W
6. Operating Range
Parameters Symbol Value Unit
Supply voltage V
VS
V
UV(1)
to 40 V
Logic supply voltage V
VCC
4.75 to 5.25 V
Logic input voltage V
CS
,V
DI
, V
CLK
,
V
INH
–0.3 to V
VCC
V
Serial interface clock frequency f
CLK
2MHz
Junction temperature range T
j
–40 to +150 °C
.1 ma;
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4530G–BCD–09/05
T6818/ATA6828
Note: 1. Test pulse 5: V
smax
= 40 V
7. Noise and Surge Immunity
Parameters Test Conditions Value
Conducted interferences ISO 7637-1 Level 4
(1)
Interference suppression VDE 0879 Part 2 Level 5
ESD (Human Body Model) ESD S 5.1 2 kV
ESD (Machine Model) JEDEC A115A 200 V
8. Electrical Characteristics
7.5 V < V
VS
< 40 V; 4.75 V < V
VCC
< 5.25 V; INH = High; –40°C < T
j
< 150
°
C; unless otherwise specified, all values refer to GND pins.
No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
1 Current Consumption
1.1 Quiescent current VS V
VS
< 20 V, INH = low 3 I
VS
1 5 µA A
1.2 Quiescent current VCC 4.75 V < V
VCC
< 5.25 V,
INH = low 11 I
VCC
15 25 µA A
1.3 Supply current VS V
VS
< 20 V normal
operating, all outputs off 3 I
VS
4 6 mA A
1.4 Supply current VCC 4.75 V < V
VCC
< 5.25 V,
normal operating 11 I
VCC
350 500 µA A
1.5 Discharge current VS V
VS
= 32.5 V,
INH = low 3 I
VS
0.5 5.5 mA A
1.6 Discharge current VS V
VS
= 40 V,
INH = low 3 I
VS
2.5 10 mA A
2 Undervoltage Detection, Power-on Reset
2.1 Power-on reset
threshold 11 V
VCC
3.2 3.9 4.4 V A
2.2 Power-on reset
delay time After switching on V
CC
t
dPor
30 95 190 µs A
2.3 Undervoltage-detection
threshold V
CC
= 5 V 3 V
Uv
5.6 7.0 V A
2.4 Undervoltage-detection
hysteresis V
CC
= 5 V 3
V
Uv
0.6 V A
2.5 Undervoltage-detection
delay time t
dUV
10 40 µs A
3 Thermal Prewarning and Shutdown
3.1 Thermal prewarning set T
jPW set
120 145 170 °C B
3.2 Thermal prewarning
reset T
jPW reset
105 130 155 °C B
3.3 Thermal prewarning
hysteresis
T
jPW
15 °C B
3.4 Thermal shutdown off T
j switch off
150 175 200 °C B
3.5 Thermal shutdown on T
j switch on
135 160 185 °C B
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note: 1. Delay time between rising edge of input signal at pin CS after data transmission and switch on output stages to 90% of final
level. Device not in standby for t > 1 ms
41m
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4530G–BCD–09/05
T6818/ATA6828
3.6 Thermal shutdown
hysteresis
T
j switch off
15
°
CB
3.7
Ratio thermal shutdown
off/thermal prewarning
set
T
j switch off/
T
jPW set
1.05 1.2 B
3.8
Ratio thermal shutdown
on/thermal prewarning
reset
T
j switch on/
T
jPW reset
1.05 1.2 B
4 Output Specification (OUT1-OUT3)
4.1
On resistance
I
Out 1-3
= –1.3 A 2, 12,
13 R
DSOn1-3
1.1
A
4.2 I
Out 1-3
= 1.3 A 2, 12,
13 R
DSOn1-3
1.1
A
4.3 High-side output
leakage current
V
Out 1-3
= 0 V
,
output stages off
2, 12,
13 I
Out1-3
–15 µA A
4.4 Low-side output
leakage current
V
Out 1-3
= V
VS,
output stages off
2, 12,
13 I
Out1-3
200 µA A
4.5
High-side switch
reverse diode forward
voltage
I
Out 1-3
= 1.5 A 2, 12,
13 V
Out1-3
– V
VS
1.5 V A
4.6 Low-side switch reverse
diode forward voltage I
Out 1-3
= –1.5 A 2, 12,
13 V
Out 1-3
–1.5 V A
4.7
High-side overcurrent
limitation and shutdown
threshold
2, 12,
13 I
Out1-3
–2.5 –2 –1.5 A A
4.8
Low-side overcurrent
limitation and shutdown
threshold
2, 12,
13 I
Out1-3
1.5 22.5 A A
4.9 Overcurrent shutdown
delay time t
dSd
10 40 µs A
4.10 High-side open-load
detection threshold
2, 12,
13 I
Out1-3
–45 –30 –15 mA A
4.11 Low-side open-load
detection threshold
2, 12,
13 I
Out1-3
15 30 45 mA A
4.12 Open-load detection
delay time t
dSd
200 600 µs A
4.13 High-side output switch
on delay
(1)
V
VS
= 13 V
R
Load
= 30
t
don
20 µs A
4.14 Low-side output switch
on delay
(1)
V
VS
= 13 V
R
Load
= 30
t
don
20 µs A
4.15 High-side output switch
off delay
(1)
V
VS
= 13 V
R
Load
= 30
t
doff
20 µs A
8. Electrical Characteristics (Continued)
7.5 V < V
VS
< 40 V; 4.75 V < V
VCC
< 5.25 V; INH = High; –40°C < T
j
< 150
°
C; unless otherwise specified, all values refer to GND pins.
No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note: 1. Delay time between rising edge of input signal at pin CS after data transmission and switch on output stages to 90% of final
level. Device not in standby for t > 1 ms
.1 ma;
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4530G–BCD–09/05
T6818/ATA6828
4.16 Low-side output switch
off delay
(1)
V
VS
= 13 V
R
Load
= 30
t
doff
sA
4.17
Dead time between
corresponding high-
and low-side switches
V
VS
= 13 V
R
Load
= 30
t
don
– t
doff
1µs A
5 Logic Inputs DI, CLK, CS, INH
5.1 Input voltage low-level
threshold 4-6, 10 V
IL
0.3
×
V
VCC
V A
5.2 Input voltage high-level
threshold 4-6, 10 V
IH
0.7
×
V
VCC
V A
5.3 Hysteresis of input
voltage 4-6, 10
V
I
50 700 mV B
5.4 Pull-down current pin
DI, CLK, INH V
DI
, V
CLK,
V
INH
= V
CC
5, 6, 10 I
PD
10 65 µA A
5.5 Pull-up current
Pin CS V
CS
= 0 V 4 I
PU
–65 –10 µA A
6 Serial Interface – Logic Output DO
6.1 Output-voltage low level I
DOL
= 2 mA 9 V
DOL
0.4 V A
6.2 Output-voltage high
level I
DOL
= –2 mA 9 V
DOH
V
VCC
0.7 V V A
6.3 Leakage current
(tri-state)
V
CS
= V
CC
0V < V
DO
< V
VCC
9 I
DO
–10 10 µA A
7Inhibit Input — Timing
7.1
Delay time from
standby to normal
operation
t
dINH
100 µs A
8. Electrical Characteristics (Continued)
7.5 V < V
VS
< 40 V; 4.75 V < V
VCC
< 5.25 V; INH = High; –40°C < T
j
< 150
°
C; unless otherwise specified, all values refer to GND pins.
No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note: 1. Delay time between rising edge of input signal at pin CS after data transmission and switch on output stages to 90% of final
level. Device not in standby for t > 1 ms
41m
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T6818/ATA6828
9. Serial Interface – Timing
No. Parameters Test Conditions Pin Timing Chart No.(1) Symbol Min. Typ. Max. Unit Type*
8.1 DO enable after CS
falling edge C
DO
= 100 pF 9 1 t
ENDO
200 ns D
8.2 DO disable after CS
rising edge C
DO
= 100 pF 9 2 t
DISDO
200 ns D
8.3 DO fall time C
DO
= 100 pF 9 t
DOf
100 ns D
8.4 DO rise time C
DO
= 100 pF 9 t
DOr
100 ns D
8.5 DO valid time C
DO
= 100 pF 9 10 t
DOVal
200 ns D
8.6 CS setup time 4 4 t
CSSethl
225 ns D
8.7 CS setup time 4 8 t
CSSetlh
225 ns D
8.8 CS high time 4 9 t
CSh
500 ns D
8.9 CLK high time 6 5 t
CLKh
225 ns D
8.10 CLK low time 6 6 t
CLKl
225 ns D
8.11 CLK period time 6 t
CLKp
500 ns D
8.12 CLK setup time 6 7 t
CLKSethl
225 ns D
8.13 CLK setup time 6 3 t
CLKSetlh
225 ns D
8.14 DI setup time 5 11 t
DIset
40 ns D
8.15 DI hold time 5 12 t
DIHold
40 ns D
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note: 1. See Figure 9-1 on page 12
12 CS CLK DI CLK DO
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4530G–BCD–09/05
T6818/ATA6828
Figure 9-1. Serial Interface Timing with Chart Numbers
CS
DO
1 2
CS
CLK
4
5
6
7
9
83
DI
CLK
DO
10 12
11
Inputs DI, CLK, CS: High level = 0.7 × V
CC
, low level = 0.3 × V
CC
Output DO: High level = 0.8 × V
CC
, low level = 0.2 × V
CC
DDDDEDDDDDDDDD DDDDDDDDDDDDDDDD Protection Control logic Powerron reset Thermal tedion Application Notes It is strongly recommended to connect the blocking capacitors at VCC and VS as close a ble to the power supply and GND pins. Recommended value for capacitors at V5: Electrolytic capacitor C > 22 uF in parallel with a ceramic capacitor C trolytic capacitor depends on external loads, conducted interlerence current low 2.3 (see “Absolute Maximum Ratings" on page 7). Recommended value for capacitors at VCC: Electrolytic capacitor C > 10 uF in parallel with a ceramic capacitor C mal resistance it is recommended to place cooling are GND pins. Negative spikes at the output pins (eg. ne switched olf with a high side driver) may T6818/ATA6828. In this condition, all outp is not acceptable or compatible With your ing on required outputs again, the SFlFi bit ovenemperature lunction. film—El ASGDGrECDwQ/DS —ti
13
4530G–BCD–09/05
T6818/ATA6828
10. Application Circuit
10.1 Application Notes
It is strongly recommended to connect the blocking capacitors at VCC and VS as close as possi-
ble to the power supply and GND pins.
Recommended value for capacitors at VS:
Electrolytic capacitor C > 22 µF in parallel with a ceramic capacitor C = 100 nF. Value for elec-
trolytic capacitor depends on external loads, conducted interferences and reverse conducting
current IOut1,2,3 (see Absolute Maximum Ratings” on page 7).
Recommended value for capacitors at VCC:
Electrolytic capacitor C > 10 µF in parallel with a ceramic capacitor C = 100 nF. To reduce ther-
mal resistance it is recommended to place cooling areas on the PCB as close as possible to the
GND pins. Negative spikes at the output pins (e.g. negative spikes caused by an inductive load
switched off with a high side driver) may activate the overtemperature protection function of the
T6818/ATA6828. In this condition, all outputs will be switched off simultaneously. If this behavior
is not acceptable or compatible with your application functionally, it is necessary, that for switch-
ing on required outputs again, the SRR bit (Status Register Reset) is set, to ensure a reset of the
overtemperature function.
DI
CLK
INH
DO
CS
UV
protection
Serial interface
Input register
Output register
H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
L
S
1
S
R
R
O
C
Sn.n. n. n.n.n.
P
S
F
O
P
L
S
C
D
n.
u. H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
L
S
1
T
P
OUT3
VS
VCC
Thermal
protection
Control
logic Power-on
reset
Charge
pump
OUT2 OUT1
n.n.
u.
GND
n.
u. n.
u. n.
u. n.
u. n.
u.
u. u. u. u. u. u. u.
3
11
1
7
8
14
21213
5
6
4
10
9
GND
GND
GND
Fault
detect
Fault
detect
Fault
detect
Fault
detect Fault
detect Fault
detect
5 V
++
13 V
BYT41D
V
S
+
V
Batt
Microcontroller
U5021M
Watchdog
V
CC
Reset
Trigger
Enable
MM
V
CC
V
CC
V
CC
.1 ma;
14
4530G–BCD–09/05
T6818/ATA6828
12. Package Information
11. Ordering Information
Extended Type Number Package Remarks
T6818-TUSY SO14 Power package, tubed, lead-free
T6818-TUQY SO14 Power package, taped and reeled, lead-free
ATA6828-T2SY PSO14 Power package with heat slug, tubed, lead-free
ATA6828-T2QY PSO14 Power package with heat slug, taped and reeled, lead-free
technical drawings
according to DIN
specifications
Package SO14
Dimensions in mm
0.25
0.10
8.75
0.4
1.27
7.62
1.4
5.2
4.8
3.7
3.8
6.15
5.85
0.
2
14 8
17
41m —«a
15
4530G–BCD–09/05
T6818/ATA6828
13. Revision History
Package: PSO14
with heat slug
Dimensions in mm
heat slug exposed
17
14 8
6.86
2.54-0.5
0.4 A
A
B
B
specifications
according to DIN
technical drawings
0.41
1.27 nom.
6 x 1.27 = 7.62 nom.
1.62 max.
0.1 max.
0.23
1.52 max.
8.75±0.1
3.99 max.
4.27±0.4
6±0.2
Issue: 2; 18.08.05
Drawing-No.: 6.541-5051.01-4
Please note that the following page numbers referred to in this section refer to the specific revision
mentioned, not to this document.
Revision No. History
4530G-BCD-09/05
Complete datasheet: T6828 changed in ATA6828
Ordering Information on page 14 changed
Package drawing on page 15 changed
4530F-BCD-03/05
Lead-free Logo on page 1 added
Table “Ordering Information” on page 14 changed
4530E-BCD-07/04
Table “Ordering Information” on page 14 changed
4530D-BCD-04/04
Features on page 1 changed
41m —®
Printed on recycled paper.
4530G–BCD–09/05
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