ATF22V10CZ, CQZ Datasheet by Microchip Technology

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A IIIEI. A1—IIIEI.®
Features
Industry-standard Architecture
12ns Maximum Pin-to-pin Delay
Zero Power – 100µA Maximum Standby Power (Input Transition Detection)
CMOS and TTL Compatible Inputs and Outputs
Advanced Electrically ErasableTechnology
– Reprogrammable
100% Tested
Latch Feature Holds Inputs to Previous Logic State
High-reliability CMOS Process
20 Year Data Retention
100 Erase/Write Cycles
2,000V ESD Protection
200mA Latchup Immunity
Industrial Temperature Ranges
Dual-in-line and Surface Mount Standard Pinouts
PCI Compliant
Green Package Options (Pb/Halide-free/RoHS Compliant) Available
1. Description
The Atmel®ATF22V10CZ/CQZ is a high-performance CMOS (electrically erasable)
programmable logic device (PLD) which utilizes The Atmel proven electrically eras-
able Flash memory technology. Speeds down to 12ns with zero standby power
dissipation are offered. All speed ranges are specified over the full 5V ±10% range for
industrial temperature ranges; 5V ±5% for commercial range 5-volt devices. The
ATF22V10CZ/CQZ provides a low voltage and edge-sensing “zero” power CMOS
PLD solution with “zero” standby power (5µA typical). The ATF22V10CZ/CQZ pro-
vides a “zero” power CMOS PLD solution with 5V operating voltages, powering down
automatically to the zero power-mode through The Atmel patented Input Transition
Detection (ITD) circuitry when the device is idle, offering “zero” (100µA worst case)
standby power. This feature allows the user to manage total system power to meet
specific application requirements and enhance reliability. Pin “keeper” circuits on input
and output pins eliminate static power consumed by pull-up resistors. The “CQZ” com-
bines the low high-frequency ICC of the “Q” design with the “Z” feature.
The ATF22V10CZ/CQZ incorporates a superset of the generic architectures, which
allows direct replacement of the 22V10 family and most 24-pin combinatorial PLDs.
Ten outputs are each allocated 8 to 16 product terms. Three different modes of opera-
tion, configured automatically with software, allow highly complex logic functions to be
realized.
High-performance
Electrically
Erasable
Programmable
Logic Device
Atmel ATF22V10CZ
Atmel ATF22V10CQZ
ATF22V10CZ is
Not Recommended for New
Design. Replaced by
ATF22V10CQZ.
0778L–PLD–8/10
12 INPUT PINS PROGRAMMABLE INTERCONNECT AND COMEINATOHIAL LOGIC ARRAY .11m—EI. —® OE PRobucT TERMS ‘— fig, 3 TO m PRODUCT TERMS LOGIC OPTION «up m In nwnovs) OUTPUT OPTION HHHHHHHHHHHH O UUUUUUUUUUUU nnnnnnn uuuuuuu uuuuuuu rmrmrmrmrmrm 10 HO PINS uuuuuuuuuuuu
2
0778L–PLD–8/10
Atmel ATF22V10C(Q)Z
Figure 1-1. Block Diagram
2. Pin Configurations
Table 2-1. Pin Configurations (All Pinouts Top View)
Pin Name Function
CLK Clock
IN Logic Inputs
I/O Bi-directional Buffers
VCC +5V Supply
Figure 2-1. TSSOP Figure 2-2. DIP/SOIC
Figure 2-3. PLCC
Note: For PLCC, P1, P8, P15 and P22 can be
left unconnected. For superior perfor-
mance, connect VCC to pin 1 and GND
to 8, 15, and 22
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CLK/IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CLK/IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN
5
6
7
8
9
10
11
25
24
23
22
21
20
19
IN
IN
IN
GND*
IN
IN
IN
I/O
I/O
I/O
GND*
I/O
I/O
I/O
4
3
2
1
28
27
26
12
13
14
15
16
17
18
IN
IN
GND
GND*
IN
I/O
I/O
IN
IN
CLK/IN
VCC*
VCC
I/O
I/O
A1—IIIEI.®
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0778L–PLD–8/10
Atmel ATF22V10C(Q)Z
3. Absolute Maximum Ratings*
4. DC and AC Operating Conditions
4.1 DC Characteristics
Note: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec
Temperature Under Bias .................. -40°C to +85°C *NOTICE: Stresses beyond those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Note: 1. Minimum voltage is -0.6V DC, which may undershoot to -
2.0V for pulses of less than 20ns. Maximum output pin volt-
age is VCC + 0.75V DC, which may overshoot to 7.0V for
pulses of less than 20ns.
Storage Temperature...................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground...........................-2.0V to +7.0V(1)
Voltage on Input Pins
with Respect to Ground
During Programming......................-2.0V to +14.0V(1)
Programming Voltage with
Respect to Ground.........................-2.0V to +14.0V(1)
Commercial Industrial
Operating Temperature (Ambient) 0C-70C -40C-85C
VCC Power Supply 5V±5% 5V± 10%
Symbol Parameter Condition Min Typ Max Units
IIL
Input or I/O Low
Leakage Current 0VIN VIL (Max)
3.5 VIN VCC
-10 µA
IIH
Input or I/O High
Leakage Current 10 µA
ICC
Clocked Power
Supply Current
VCC = Max
Outputs Open,
f = 15MHz
CZ-12, 15 Com 90 150 mA
CZ-15 Ind 90 180 mA
CQZ-20 Com 40 60 mA
CQZ-20 Ind 40 80 mA
ISB
Power Supply Current,
Standby
VCC = Max
VIN = MAX
Outputs Open
CZ-12, 15 Com 5 100 µA
CZ-15 Ind 5 120 µA
CQZ-20 Com 5 100 µA
CQZ-20 Ind 5 120 µA
IOS(1) Output Short Circuit
Current VOUT = 0.5V -130 mA
VIL Input Low Voltage -0.5 0.8 V
VIH Input High Voltage 2.0 VCC +0.75 V
VOL Output Low Voltage
VIN =V
IH or VIL
VCC = Min,
IOL = 16mA
0.5 V
VOH Output High Voltage
VIN =V
IH or VIL
VCCIO = Min,
IOH = -4.0mA
2.4 V
VVVVV Elm
4
0778L–PLD–8/10
Atmel ATF22V10C(Q)Z
4.2 AC Waveforms
4.3 AC Characteristics(1)
Note: 1. See ordering information for valid part numbers
INPUTS, I/O
REG. FEEDBACK
SYNCH. PRESET
CP
ASYNCH. RESET
REGISTERED
OUTPUTS
COMBINATORIAL
OUTPUTS VALID VALID
VALID VALID VALID
VALID
OUTPUT
DISABLED
OUTPUT
DISABLED
tS tH
tW tW
tP
tAR
tAW
tAPtCO
tPD
tER tEA
tEAtER
Symbol Parameter
-12 -15 -20
UnitsMin Max Min Max Min Max
tPD Input or Feedback to Non-registered Output 3 12 3 15 3 20 ns
tCF Clock to Feedback 6 4.5 8 ns
tCO Clock to Output 2 8 2 8 2 12 ns
tSInput or Feedback Setup Time 10 10 14 ns
tHInput Hold Time 0 0 0 ns
tWClock Width 6 6 10 ns
fMAX
External Feedback 1/(tS+t
CO)
Internal Feedback 1/(tS+t
CF)
No Feedback 1/(tP)
55.5
62
83.3
55.5
69
83.3
38.5
45.5
50.0
MHz
MHz
MHz
tEA Input to Output Enable - Product Term 3 12 3 15 3 20 ns
tER Input to Output Disable - Product Term 2 15 3 15 3 20 ns
tPZX OE Pin to Output Enable 2 12 2 15 2 20 ns
tPXZ OE Pin to Output Disable 2 15 2 15 2 20 ns
tAP
Input or I/O to Asynchronous Reset of
Register 310 315322ns
tSP Setup Time, Synchronous Preset 10 10 14 ns
tAW Asynchronous Reset Width 7 8 20 ns
tAR Asynchronous Reset Recovery Time 5 6 20 ns
tSPR
Synchronous Preset to Clock Recovery
Time 10 10 14 ns
3.0V AC AC DRMNG MEASUREMENT LEVELS LEVEL 0 av nt, 9 5n: 5 av R1=aoosz OUTPUT PIN R2:39012‘ _ CL:50pF E L A1—IIIEI.®
5
0778L–PLD–8/10
Atmel ATF22V10C(Q)Z
4.4 Input Test Waveforms
4.4.1 Input Test Waveforms and Measurement Levels
4.4.2 Output Test Loads
Note: Similar competitors devices are specified with slightly different loads. These load differences may affect output signals’
delay and slew rate. Atmel devices are tested with sufficient margins to meet compatible device specification
conditions.
4.5 Pin Capacitance
Table 4-1. Pin Capacitance (f = 1MHz, T = 25C(1)
Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested
4.6 Power-up Reset
The registers in the Atmel®ATF22V10CZ/CQZ are designed to reset during power-up. At a point delayed slightly
from VCC crossing VRST, all registers will be reset to the low state. The output state will depend on the polarity of the
buffer.
This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the
uncertainty of how VCC actually rises in the system, the following conditions are required:
1. The VCC rise must be monotonic and start below 0.7V
2. The clock must remain stable during TPR
3. After TPR occurs, all input and feedback setup times must be met before driving the clock pin high
4.7 Preload of Register Outputs
The ATF22V10CZ/CQZ’s registers are provided with circuitry to allow loading of each register with either a high or
a low. This feature will simplify testing since any state can be forced into the registers to control test sequencing. A
JEDEC file with preload is generated when a source file with vectors is compiled. Once downloaded, the JEDEC
file preload sequence will be done automatically by most of the approved programmers after the programming.
Typ Max Units Conditions
CIN 810 pF V
IN = 0V; f = 1.0MHz
CI/O 810 pF V
OUT = 0V; f = 1.0MHz
A1—IIIEI.® VRST
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0778L–PLD–8/10
Atmel ATF22V10C(Q)Z
5. Electronic Signature Word
There are 64-bits of programmable memory that are always available to the user, even if the device is secured.
These bits can be used for user-specific data.
6. Security Fuse Usage
A single fuse is provided to prevent unauthorized copying of the Atmel®ATF22V10CZ/CQZ fuse patterns. Once
programmed, fuse verify and preload are inhibited. However, the 64-bit User Signature remains accessible. The
security fuse should be programmed last, as its effect is immediate.
7. Programming/Erasing
Programming/erasing is performed using standard PLD programmers. See CMOS PLD Programming Hardware
and Software Support for information on software/programming.
Figure 7-1. Programming/Erasing Timing
Table 7-1. Programming/Erasing
Parameter Description Typ Max Units
TPR
Power-up
Reset Time 600 1000 ns
VRST
Power-up
Reset Voltage 3.8 4.5 V
CLOCK
VRST
POWER
REGISTERED
OUTPUTS tS
tPR
tW
.11m—EI.
7
0778L–PLD–8/10
Atmel ATF22V10C(Q)Z
8. Input and I/O Pull-ups
All Atmel®ATF22V10CZ/CQZ family members have internal input and I/O pin-keeper circuits. Therefore, whenever
inputs or I/Os are not being driven externally, they will maintain their last driven state. This ensures that all logic
array inputs and device outputs are at known states. These are relatively weak active circuits that can be easily
overridden by TTL-compatible drivers (see input and I/O diagrams below).
Figure 8-1. Input Diagram
Figure 8-2. I/O Diagram
100K
VCC
ESD
PROTECTION
CIRCUIT
INPUT
100K
V
CC
V
CC
DATA
OE
I/O
INPUT
A IIIEI. —®
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0778L–PLD–8/10
Atmel ATF22V10C(Q)Z
9. Compiler Mode Selection
Table 9-1. Compiler Mode Selection
10. Functional Logic Diagram Description
The Functional Logic Diagram describes the Atmel®ATF22V10CZ/CQZ architecture.
The ATF22V10CZ/CQZ has 12 inputs and 10 I/O macrocells. Each macrocell can be configured into one of four
output configurations: active high/low, registered/combinatorial output.The universal architecture of the
ATF22V10CZ/CQZ can be programmed to emulate most 24-pin PAL devices.
Unused product terms are automatically disabled by the compiler to decrease power consumption. A security fuse,
when programmed, protects the contents of the ATF22V10CZ/CQZ. Eight bytes (64-fuses) of User Signature are
accessible to the user for purposes such as storing project name, part number, revision or date. The User
Signature is accessible regardless of the state of the security fuse.
PAL Mode
(5828 Fuses)
GAL Mode
(5892 Fuses)
Synario Atmel ATF22V10C (DIP)
Atmel ATF22V10C (PLCC)
Atmel ATF22V10C DIP (UES)
Atmel ATF22V10C PLCC (UES)
WINCUPL P22V10
P22V10LCC
G22V10
G22V10LCC
muvl um 5n :1 Wm an,“ r as; m ~u m v-m :s‘ u rm :u: ‘ w ‘ m M a new ‘ 5 m r. w «,1: name new mm mm
9
0778L–PLD–8/10
Atmel ATF22V10C(Q)Z
Figure 10-1. Functional Logic Diagram
A1—IIIEI.®
10
0778L–PLD–8/10
Atmel ATF22V10C(Q)Z
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
4.5 4.8 5.0 5.3 5.5
ICC (µA)
SUPPLY VOLTAGE (V)
ATMEL ATF22V10CZ/CQZ
ICC vs. SUPPLY VOLTAGE (TA= 25°C)
STAND-BY
0.4
0.6
0.8
1.0
1.2
1.4
-40.0 0.0 25.0 75.0
TEMPERATURE (C)
NORMALIZED ICC VS. TEMP
NORMALIZED ICC
0.000
20.000
40.000
60.000
80.000
100.000
120.000
140.000
0.0 0.5 2.5 5.0 7.5 10.0 25.0 37.5 50.0
ICC (mA)
FREQUENCY (MHz)
ATMEL ATF22V10CZ SUPPLY CURRENT vs.
INPUT FREQUENCY (VCC = 5.0V, TA= 25°C)
0.000
10.000
20.000
30.000
40.000
50.000
0.0 0.5 2.5 5.0 7.5 10.0 25.0 37.5 50.0
FREQUENCY (MHz)
ATMEL ATF22V10CQZ SUPPLY CURRENT
VS. INPUT FREQUENCY (VCC = 5V, TA= 25°C)
ICC (mA)
-50
-40
-30
-20
-10
0
4.0 4.5 5.0 5.5 6.0
IOH (mA)
SUPPLY VOLTAGE (V)
ATMEL ATF22V10CZ/CQZ OUTPUT SOURCE
CURRENT VS SUPPLY VOLTAGE (VOH = 2.4V)
-90.0
-80.0
-70.0
-60.0
-50.0
-40.0
-30.0
-20.0
-10.0
0.0
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00
V
OH
(V)
ATMEL ATF22V10CZ/CQZ OUTPUT SOURCE
CURRENT VS. OUTPUT VOLTAGE (V
CC
= 5V, T
A
= 25°C)
I
OH
(mA)
36
38
40
42
44
46
48
4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (V)
ATMEL ATF22V10CZ/CQZ OUTPUT
SINK CURRENT vs. SUPPLY VOLTAGE (VOL = 0.5V)
IOL (mA)
0.0
20.0
40.0
60.0
80.0
100.0
120.0
140.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
IOL (mA)
SUPPLY VOLTAGE (V)
ATMEL ATF22V10CZ/CQZ OUTPUT SINK
CURRENT VS. SUPPLY VOLTAGE (VOL = 0.5V)
.1 mg
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0778L–PLD–8/10
Atmel ATF22V10C(Q)Z
-120
-100
-80
-60
-40
-20
0
0.0 -0.2-0.4-0.6-0.8-1.0
INPUT VOLTAGE (V)
ATMEL ATF22V10CZ/CQZ INPUT CLAMP
CURRENT VS INPUT VOLTAGE (VCC = 5V, TA= 35°C)
INPUT CURRENT (mA)
-30
-20
-10
0
10
20
30
40
0.0 1.0 2.0 3.0 4.0 5.0 6.0
INPUT VOLTAGE (V)
ATMEL ATF22V10CZ/CQZ INPUT CURRENT
VS INPUT VOLTAGE (VCC = 5V, T
A= 25°C)
INPUT CURRENT (uA)
0.8
0.9
1.0
1.1
1.2
4.5 4.8 5.0 5.3 5.5
SUPPLY VOLTAGE (V)
NORMALIZED TPD vs. VCC
NORMALIZED TPD
0.8
0.9
1.0
1.1
-40.0 0.0 25.0 75.0
TEMPERATURE (C)
NORMALIZED TPD vs. TEMP
NORMALIZED TPD
0.8
0.9
1.0
1.1
1.2
1.3
4.5 4.8 5.0 5.3 5.5
SUPPLY VOLTAGE (V)
NORMALIZED TCO vs. VCC
NORMALIZED TCO
0.8
0.9
1.0
1.1
-40.0 0.0 25.0 75.0
TEMPERATURE (V)
NORMALIZED TCO VS TEMP
NORMALIZED TCO
0.8
0.9
1.0
1.1
1.2
4.5 4.8 5.0 5.3 5.5
SUPPLY VOLTAGE (V)
NORMALIZED TSU VS VCC
NORMALIZED TSU
0.8
0.9
1.0
1.1
1.2
-40.0 0.0 25.0 75.0
TEMPERATURE (C)
NORMALIZED TSU vs. TEMP
NORMALIZED TSU
A IIIEI. —®
12
0778L–PLD–8/10
Atmel ATF22V10C(Q)Z
-2
0
2
4
6
8
0 50 100 150 200 250 300
OUTPUT LOADING (PF)
ATMEL ATF22V10C
DELTA TPD vs. OUTPUT LOADING
DELTA TPD (ns)
0.00
1.00
2.00
3.00
4.00
5.00
6.00
7.00
8.00
50 100 150 200 250 300
NUMBER OF OUTPUTS LOADING
ATMEL ATF22V10C
DELTA TCO VS. OUTPUT LOADING
DELTA TCO (ns)
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
NUMBER OF OUTPUTS SWITCHING
DELTA TPD vs. # OF OUTPUT SWITCHING
DELTA TPD (ns)
-0.3
-0.2
-0.2
-0.1
-0.1
0.0
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
NUMBER OF OUTPUTS SWITCHING
DELTA TCO vs. # OF OUTPUT SWITCHING
DELTA TCO (ns)
11—mEI.®
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Atmel ATF22V10C(Q)Z
11. Ordering Information
11.1 Standard Package Options
Note: Shaded parts are being obsoleted and are not recommended for new designs. Customers should transition to ROHS
offering
11.2 Atmel ATF22V10CQZ Green Package Options (Pb/Halide-free/RoHS Compliant)
11.3 Using “C” Product for Industrial
To use commercial product for Industrial temperature ranges, down-grade one speed grade from the “I” to the “C”
device (7ns “C” = 10ns “I”) and de-rate power by 30%.
tPD
(ns)
tS
(ns)
tCO
(ns) Ordering Code Package Operation Range
12 10 8
ATF22V10CZ-12JC
ATF22V10CZ-12PC
ATF22V10CZ-12SC
ATF22V10CZ-12XC
28J
24P3
24S
24X
Commercial
(0Cto70C)
15 10 8
ATF22V10CZ-15JC
ATF22V10CZ-15PC
ATF22V10CZ-15SC
28J
24P3
24S
Commercial
(0Cto70C)
ATF22V10CZ-15JI
ATF22V10CZ-15PI
ATF22V10CZ-15SI
28J
24P3
24S
Industrial
(-40C to +85C)
20 14 12
ATF22V10CQZ-20JC
ATF22V10CQZ-20PC
ATF22V10CQZ-20SC
ATF22V10CQZ-20XC
28J
24P3
24S
24X
Commercial
(0Cto70C)
ATF22V10CQZ-20JI
ATF22V10CQZ-20PI
ATF22V10CQZ-20SI
ATF22V10CQZ-20XI
28J
24P3
24S
24X
Industrial
(-40C to +85C)
tPD
(ns)
tS
(ns)
tCO
(ns) Ordering Code Package Operation Range
20 14 12
ATF22V10CQZ-20JU
ATF22V10CQZ-20PU
ATF22V10CQZ-20SU
ATF22V10CQZ-20XU
28J
24P3
24S
24X
Industrial
(-40C to +85C)
Package Type
28J 28-lead, Plastic J-leaded Chip Carrier (PLCC)
24P3 24-pin, 0.300", Plastic Dual Inline Package (PDIP)
24S 24-lead, 0.300" Wide, Plastic Gull-Wing Small Outline (SOIC)
24X 24-lead, 4.4mm Wide, Plastic Thin Shrink Small Outline (TSSOP)
A IIIEI. —® illn—B,
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Atmel ATF22V10C(Q)Z
12. Packaging Information
12.1 28J – PLCC
TITLE DRAWING NO. REV.
B
28J, 28-lead, Plastic J-leaded Chip Carrier (PLCC) 28J
10/04/01
1.14(0.045) X 45° PIN NO. 1
IDENTIFIER
1.14(0.045) X 45°
0.51(0.020)MAX
0.318(0.0125)
0.191(0.0075)
A2
45° MAX (3X)
A
A1
B1 D2/E2
B
e
E1 E
D1
D
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
Notes: 1. This package conforms to JEDEC reference MS-018, Variation AB.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102mm) maximum.
A 4.191 4.572
A1 2.286 3.048
A2 0.508
D 12.319 12.573
D1 11.430 11.582 Note 2
E 12.319 12.573
E1 11.430 11.582 Note 2
D2/E2 9.906 10.922
B 0.660 0.813
B1 0.330 0.533
e 1.270 TYP
Package Drawing Contact:
packagedrawings@atmel.com
A1—IIIEI.®
15
0778L–PLD–8/10
Atmel ATF22V10C(Q)Z
12.2 24P3 – PDIP
TITLE DRAWING NO. REV.
24P3, 24-lead (0.300"/7.62mm Wide) Plastic Dual
Inline Package (PDIP) D
24P3
6/1/04
PIN
1
E1
A1
B
E
B1
C
L
SEATING PLANE
A
D
e
eB
eC
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A 5.334
A1 0.381
D 31.623 32.131 Note 2
E 7.620 8.255
E1 6.096 7.112 Note 2
B 0.356 0.559
B1 1.270 1.651
L 2.921 3.810
C 0.203 0.356
eB 10.922
eC 0.000 1.524
e 2.540 TYP
Notes: 1. This package conforms to JEDEC reference MS-001, Variation AF.
2. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25mm (0.010").
Package Drawing Contact:
packagedrawings@atmel.com
A1—IIIEI.® HH \HHH Hflfi u 8/ \ O UH HUU UH
16
0778L–PLD–8/10
Atmel ATF22V10C(Q)Z
12.3 24S – SOIC
08
PIN1ID
PIN 1
06/17/2002
TITLE DRAWING NO. REV.
24S, 24-lead (0.300" body) Plastic Gull Wing Small
Outline (SOIC) B
24S
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A – 2.65
A1 0.10 0.30
D 10.00 – 10.65
D1 7.40 7.60
E 15.20 – 15.60
B 0.33 – 0.51
L 0.40 – 1.27
L1 0.23 0.32
e 1.27 BSC
B
D
D1
e
E
A
A1
L1
L
Package Drawing Contact:
packagedrawings@atmel.com
PIN1 “134 A1—IIIEI.®
17
0778L–PLD–8/10
Atmel ATF22V10C(Q)Z
12.4 24X – TSSOP
0.30(0.012)
0.19(0.007)
4.48(0.176)
4.30(0.169)
6.50(0.256)
6.25(0.246)
0.65(0.0256)BSC
7.90(0.311)
7.70(0.303)
0.15(0.006)
0.05(0.002)
0.20(0.008)
0.09(0.004)
0.75(0.030)
0.45(0.018)
08
1.20(0.047)MAX
Dimensions in Millimeter and (Inches)*
JEDEC STANDARD MO-153 AD
Controlling dimension: millimeters
PIN 1
04/11/2001
TITLE DRAWING NO. REV.
24X, 24-lead (4.4mm body width) Plastic Thin Shrink
Small Outline Package (TSSOP) A
24X
Package Drawing Contact:
packagedrawings@atmel.com
A IIIEI. —®
18
0778L–PLD–8/10
Atmel ATF22V10C(Q)Z
13. Revision History
Doc. Rev. Date Comments
0778L 08/2010 Change tS(ns) from 4.5 to 10 in Standard Package Options.
06/2014 The ATF22V10CZ is obsolete. Replaced by ATF22V10CQZ.
0778K 07/2010 Remove Commercial Temperature Range
For ISB, change 25µA Max to 100µA max for commercial grade parts and 50µA Max to 120µA for
Industrial grade parts
Shade Standard Package Options and add note, “Shaded parts are not recommended for new
designs. Customers should transition to ROHS offering”
Remove Atmel ATF22V10CZ-15XC and Atmel ATF22V10CZ-15XI from Standard Package
Options
0778J 11/2005 Add Green Package options
.1 lllEl®
0778L–PLD–8/10
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