ADSP-21061(L) Datasheet by Analog Devices Inc.

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ANALOG DEVICES
a
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Commercial Grade
SHARC DSP Microcomputer
ADSP-21061/ADSP-21061L
Rev. D Document Feedback
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However, no responsibility is assumed by Analog Devices for its use, nor for any
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SUMMARY
High performance signal processor for communications,
graphics, and imaging applications
Super Harvard Architecture
Four independent buses for dual data fetch, instruction
fetch, and nonintrusive I/O
32-bit IEEE floating-point computation units—multiplier,
ALU, and shifter
Dual-ported on-chip SRAM and integrated I/O peripherals—a
complete system-on-a-chip
Integrated multiprocessing features
KEY FEATURES—PROCESSOR CORE
50 MIPS, 20 ns instruction rate, single-cycle instruction
execution
120 MFLOPS peak, 80 MFLOPS sustained performance
Dual data address generators with modulo and bit-reverse
addressing
Efficient program sequencing with zero-overhead looping:
single-cycle loop setup
IEEE JTAG Standard 1149.1 test access port and on-chip
emulation
32-bit single-precision and 40-bit extended-precision IEEE
floating-point data formats or 32-bit fixed-point data
format
240-lead MQFP package, thermally enhanced MQFP, 225-ball
plastic ball grid array (PBGA)
Lead (Pb) free packages. For more information, see Ordering
Guide on Page 52.
Figure 1. Functional Block Diagram
MULT BARREL
SERIAL PORTS
(2)
4
6
6
IOP
REGISTERS
(MEMORY
MAPPED)
CONTROL,
STATUS AND
DATA BUFFERS
I/O PROCESSOR
TIMER INSTRUCTION
CACHE
ADDR DATA DATA ADDR
ADDR DATA ADDR
TWO INDEPENDENT
DUAL-PORTED BLOCKS
PROCESSOR PORT I/O PORT
DUAL-PORTED SRAM
JTAG
TEST AND
EMULATION
7
HOST PORT
ADDR BUS
MUX
IOA
17
IOD
48
MULTIPROCESSOR
INTERFACE
EXTERNAL
PORT
DATA BUS
MUX
48
32
24
DM ADDRESS BUS
PM DATA BUS
DM DATA BUS
BUS
CONNECT
(PX)
DAG1
32
48
40/32
CORE PROCESSOR
PROGRAM
SEQUENCER
BLOCK 0
BLOCK 1
8 4 32
DAG2
8 4 24
32 48-BIT
PM ADDRESS BUS
DATA
CONTROLLER
DMA
DATA
REGISTER
FILE
16 40-BIT
S
ALU
SHIFTER
Rev. D | Page 2 of 52 | May 2013
ADSP-21061/ADSP-21061L
TABLE OF CONTENTS
Summary ............................................................... 1
Key FeaturesProcessor Core ................................. 1
General Description ................................................. 3
SHARC Family Core Architecture ............................ 3
Memory and I/O Interface Features ........................... 4
Porting Code From the ADSP-21060 or
ADSP-21062 ..................................................... 7
Development Tools ............................................... 7
Additional Information .......................................... 8
Related Signal Chains ............................................ 8
Pin Function Descriptions ......................................... 9
Target Board Connector For EZ-ICE Probe ............... 12
ADSP-21061 Specifications ...................................... 14
Operating Conditions (5 V) ................................... 14
Electrical Characteristics (5 V) ............................... 14
Internal Power Dissipation (5 V) ............................ 15
External Power Dissipation (5 V) ............................ 16
ADSP-21061L Specifications ..................................... 17
Operating Conditions (3.3 V) ................................. 17
Electrical Characteristics (3.3 V) ............................. 17
Internal Power Dissipation (3.3 V) .......................... 18
External Power Dissipation (3.3 V) .......................... 19
Absolute Maximum Ratings ................................... 20
ESD Caution ...................................................... 20
Package Marking Information ................................ 20
Timing Specifications ........................................... 20
Test Conditions .................................................. 43
Environmental Conditions .................................... 46
225-Ball PBGA Pin Configurations ............................. 47
240-Lead MQFP Pin Configurations ........................... 49
Outline Dimensions ................................................ 50
Surface-Mount Design .......................................... 52
Ordering Guide ..................................................... 52
REVISION HISTORY
5/13—Rev C to Rev D
Updated Development Tools .......................................7
Added Related Signal Chains .......................................8
Removed the ADSP-21061LAS-176, ADSP-21061LKS-160, and
ADSP-21061LKS-176 models from Ordering Guide ........ 52
GENERAL NOTE
This data sheet represents production released specifications for
the ADSP-21061 (5 V) and ADSP-21061L (3.3 V) processors for
33 MHz, 40 MHz, 44 MHz, and 50 MHz speed grades. The
product name“ADSP-21061” is used throughout this data sheet
to represent all devices, except where expressly noted.
:5 31:4 w :iww E: , 3,: xx: xx: I 300M bps DMA Transfer Rate
ADSP-21061/ADSP-21061L
Rev. D | Page 3 of 52 | May 2013
GENERAL DESCRIPTION
The ADSP-21061 SHARC—Super Harvard Architecture Com-
puter—is a signal processing microcomputer that offers new
capabilities and levels of performance. The ADSP-21061
SHARC is a 32-bit processor optimized for high performance
DSP applications. The ADSP-21061 builds on the ADSP-21000
DSP core to form a complete system-on-a-chip, adding a dual-
ported on-chip SRAM and integrated I/O peripherals supported
by a dedicated I/O bus.
Fabricated in a high speed, low power CMOS process, the
ADSP-21061 has a 20 ns instruction cycle time and operates at
50 MIPS. With its on-chip instruction cache, the processor can
execute every instruction in a single cycle. Table 1 shows perfor-
mance benchmarks for the ADSP-21061/ADSP-21061L.
The ADSP-21061 SHARC represents a new standard of integra-
tion for signal computers, combining a high performance
floating-point DSP core with integrated, on-chip system fea-
tures including 1M bit SRAM memory, a host processor
interface, a DMA controller, serial ports, and parallel bus con-
nectivity for glueless DSP multiprocessing.
The ADSP-21061 continues SHARC’s industry-leading stan-
dards of integration for DSPs, combining a high performance
32-bit DSP core with integrated, on-chip system features.
The block diagram on Page 1, illustrates the following architec-
tural features:
Computation units (ALU, multiplier, and shifter) with a
shared data register file
Data address generators (DAG1, DAG2)
Program sequencer with instruction cache
PM and DM buses capable of supporting four 32-bit data
transfers between memory and the core at every core pro-
cessor cycle
•Interval timer
•On-chip SRAM
External port for interfacing to off-chip memory and
peripherals
Host port and multiprocessor interface
DMA controller
•Serial ports
JTAG test access port
SHARC FAMILY CORE ARCHITECTURE
The ADSP-21061 includes the following architectural features
of the ADSP-21000 family core. The ADSP-21061 processors
are code- and function-compatible with the ADSP-21020,
ADSP-21060, and ADSP-21062 SHARC processors.
Independent, Parallel Computation Units
The arithmetic/logic unit (ALU), multiplier, and shifter all per-
form single-cycle instructions. The three units are arranged in
parallel, maximizing computational throughput. Single multi-
function instructions execute parallel ALU and multiplier oper-
ations. These computation units support IEEE 32-bit single-
precision floating-point, extended-precision 40-bit floating-
point, and 32-bit fixed-point data formats.
Data Register File
A general-purpose data register file is used for transferring data
between the computation units and the data buses, and for stor-
ing intermediate results. This 10-port, 32-register (16 primary,
16 secondary) register file, combined with the ADSP-21000
Harvard architecture, allows unconstrained data flow between
computation units and internal memory.
Table 1. Benchmarks (at 50 MHz)
Benchmark Algorithm Speed Cycles
1024 Point Complex FFT (Radix 4,
with reversal)
.37 ms 18,221
FIR Filter (per tap) 20 ns 1
IIR Filter (per biquad) 80 ns 4
Divide (y/x) 120 ns 6
Inverse Square Root 180 ns 9
DMA Transfer Rate 300M bps
Figure 2. ADSP-21061/ADSP-21061L System Sample Configuration
3
4
RESET JTAG
7
ADSP-21061
BMS
1CLOCK CS BOOT
EPROM
(OPTIONAL)
MEMORY-
MAPPED
DEVICES
(OPTIONAL)
OE
DATA
DMA DEVICE
(OPTIONAL)
DATA
ADDR
DATA
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
CS
RD
PAGE
ADRCLK
ACK
BR1–6
DMAR1–2
CLKIN
IRQ2–0
TCLK0
RPBA
EBOOT
LBOOT
FLAG3–0
TIMEXP
DR0
DT0
RSF0
TFS0
RCLK0
TCLK1
DR1
DT1
RSF1
TFS1
RCLK1
ID2–0
SERIAL
DEVICE
(OPTIONAL)
SERIAL
DEVICE
(OPTIONAL)
CPA
REDY
HBG
HBR
DMAG1–2
SBTS
MS3–0
WR
DATA47–0
DATA
ADDR
CS
ACK
WE
ADDR31–0
DATA
CONTROL
ADDRESS
ADDR
TO GND
SW
Rev. D | Page 4 of 52 | May 2013
ADSP-21061/ADSP-21061L
Single-Cycle Fetch of Instruction and Two Operands
The ADSP-21061 features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data and the pro-
gram memory (PM) bus transfers both instructions and data
(Figure 1 on Page 1). With its separate program and data mem-
ory buses and on-chip instruction cache, the processor can
simultaneously fetch two operands and an instruction (from the
cache), all in a single cycle.
Instruction Cache
The ADSP-21061 includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and two
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This
allows full-speed execution of core, looped operations such as
digital filter multiply-accumulates and FFT butterfly processing.
Data Address Generators with Hardware Circular Buffers
The ADSP-21061’s two data address generators (DAGs) imple-
ment circular data buffers in hardware. Circular buffers allow
efficient programming of delay lines and other data structures
required in digital signal processing, and are commonly used in
digital filters and Fourier transforms. The two DAGs of the
ADSP-21061 contain sufficient registers to allow the creation of
up to 32 circular buffers (16 primary register sets, 16 secondary).
The DAGs automatically handle address pointer wraparound,
reducing overhead, increasing performance and simplifying
implementation. Circular buffers can start and end at any mem-
ory location.
Flexible Instruction Set
The 48-bit instruction word accommodates a variety of parallel
operations, for concise programming. For example, the
ADSP-21061 can conditionally execute a multiply, an add, a
subtract, and a branch, all in a single instruction.
MEMORY AND I/O INTERFACE FEATURES
The ADSP-21061 processors add the following architectural
features to the SHARC family core.
Dual-Ported On-Chip Memory
The ADSP-21061 contains one megabit of on-chip SRAM, orga-
nized as two blocks of 0.5M bits each. Each bank has eight 16-bit
columns with 4k 16-bit words per column. Each memory block
is dual-ported for single-cycle, independent accesses by the core
processor and I/O processor or DMA controller. The dual-
ported memory and separate on-chip buses allow two data
transfers from the core and one from I/O, all in a single cycle
(see Figure 4 for the ADSP-21061 memory map).
On the ADSP-21061, the memory can be configured as a maxi-
mum of 32k words of 32-bit data, 64k words for 16-bit data, 16k
words of 48-bit instructions (and 40-bit data) or combinations
of different word sizes up to 1 megabit. All the memory can be
accessed as 16-bit, 32-bit, or 48-bit.
A 16-bit floating-point storage format is supported, which effec-
tively doubles the amount of data that may be stored on-chip.
Conversion between the 32-bit floating-point and 16-bit float-
ing-point formats is done in a single instruction.
While each memory block can store combinations of code and
data, accesses are most efficient when one block stores data,
using the DM bus for transfers, and the other block stores
instructions and data, using the PM bus for transfers. Using the
DM bus and PM bus in this way, with one dedicated to each
memory block, assures single-cycle execution with two data
transfers. In this case, the instruction must be available in the
cache. Single-cycle execution is also maintained when one of the
data operands is transferred to or from off-chip, via the
ADSP-21061’s external port.
Off-Chip Memory and Peripherals Interface
The ADSP-21061’s external port provides the processor’s inter-
face to off-chip memory and peripherals. The 4-gigaword off-
chip address space is included in the ADSP-21061’s unified
address space. The separate on-chip buses—for program mem-
ory, data memory, and I/O—are multiplexed at the external port
to create an external system bus with a single 32-bit address bus
and a single 48-bit (or 32-bit) data bus. The on-chip Super Har-
vard Architecture provides three-bus performance, while the
off-chip unified address space gives flexibility to the designer.
Addressing of external memory devices is facilitated by on-chip
decoding of high order address lines to generate memory bank
select signals. Separate control lines are also generated for sim-
plified addressing of page-mode DRAM. The ADSP-21061
provides programmable memory wait states and external mem-
ory acknowledge controls to allow interfacing to DRAM and
peripherals with variable access, hold, and disable time
requirements.
Host Processor Interface
The ADSP-21061’s host interface allows easy connection to
standard microprocessor buses, both 16-bit and 32-bit, with lit-
tle additional hardware required. Asynchronous transfers at
speeds up to the full clock rate of the processor are supported.
The host interface is accessed through the ADSP-21061’s exter-
nal port and is memory-mapped into the unified address space.
Two channels of DMA are available for the host interface; code
and data transfers are accomplished with low software
overhead.
The host processor requests the ADSP-21061’s external bus
with the host bus request (HBR), host bus grant (HBG), and
ready (REDY) signals. The host can directly read and write the
internal memory of the ADSP-21061, and can access the DMA
channel setup and mailbox registers. Vector interrupt support is
provided for efficient execution of host commands.
DMA Controller
The ADSP-21061’s on-chip DMA controller allows zero-
overhead data transfers without processor intervention. The
DMA controller operates independently and invisibly to the
processor core, allowing DMA operations to occur while the
core is simultaneously executing its program instructions.
ADSP-21061/ADSP-21061L
Rev. D | Page 5 of 52 | May 2013
DMA transfers can occur between the ADSP-21061’s internal
memory and either external memory, external peripherals, or a
host processor. DMA transfers can also occur between the
ADSP-21061’s internal memory and its serial ports.
DMA transfers between external memory and external periph-
eral devices are another option. External bus packing to 16-,
32-, or 48-bit words is performed during DMA transfers.
Figure 3. Shared Memory Multiprocessing System
ADDR31–0
CPA
BMS
CONTROL
ADSP-21061 #1
5
CONTROL
ADSP-21061 #2
ADDR31–0
CONTROL
ADSP-21061 #3
5
ID2–0
RESET
RPBA
CLKIN
ID2–0
RESET
RPBA
ID2–0
RESET
RPBA
CLKIN
ADSP-21061 #6
ADSP-21061 #5
ADSP-21061 #4
CLOCK
RESET
ADDR
DATA
HOSTPROCESSOR
INTERFACE (OPTIONAL)
ACK
GLOBAL MEMORY
AND
PERIPHERAL (OPTIONAL)
OE
ADDR
DATA
CS
ADDR
DATA
BOOT EPROM (OPTIONAL)
RDx
MS3–0
SBTS
CS
ACK
ADDR31–0
CLKIN
3
001
PAGE
3
010
3
011
BR1
BR2–6
REDY
HBG
HBR
CS
WE
WRx
5
CONTROL
ADDRESS
DATA
CONTROL
ADDRESS
DATA
DATA47–0
BR1–2, BR4–6
BR3
DATA47–0
BR1, BR3–6
BR2
DATA47–0
BUS
PRIORITY
CPA
Rev. D | Page 6 of 52 | May 2013
ADSP-21061/ADSP-21061L
Six channels of DMA are available on the ADSP-21061—four
via the serial ports, and two via the processor’s external port (for
either host processor, other ADSP-21061s, memory or I/O
transfers). Programs can be downloaded to the ADSP-21061
using DMA transfers. Asynchronous off-chip peripherals can
control two DMA channels using DMA request/grant lines
(DMAR
1–2
, DMAG
1–2
). Other DMA features include interrupt
generation upon completion of DMA transfers and DMA
chaining for automatic linked DMA transfers.
Serial Ports
The ADSP-21061 features two synchronous serial ports that
provide an inexpensive interface to a wide variety of digital and
mixed-signal peripheral devices. The serial ports can operate at
the full clock rate of the processor, providing each with a maxi-
mum data rate of up to 50 Mbps. Independent transmit and
receive functions provide greater flexibility for serial communi-
cations. Serial port data can be automatically transferred to and
from on-chip memory via DMA. Each of the serial ports offers
TDM multichannel mode.
The serial ports can operate with little-endian or big-endian
transmission formats, with word lengths selectable from 3 bits
to 32 bits. They offer selectable synchronization and transmit
modes as well as optional μ-law or A-law companding. Serial
port clocks and frame syncs can be internally or externally gen-
erated. The serial ports also include keyword and key mask
features to enhance interprocessor communication.
Multiprocessing
The ADSP-21061 offers powerful features tailored to multipro-
cessor DSP systems. The unified address space (see Figure 4)
allows direct interprocessor accesses of each ADSP-21061’s
internal memory. Distributed bus arbitration logic is included
on-chip for simple, glueless connection of systems containing
up to six ADSP-21061s and a host processor. Master processor
changeover incurs only one cycle of overhead. Bus arbitration is
selectable as either fixed or rotating priority. Bus lock allows
indivisible read-modify-write sequences for semaphores. A vec-
tor interrupt is provided for interprocessor commands. Maxi-
mum throughput for interprocessor data transfer is 500 Mbps
over the external port. Broadcast writes allow simultaneous
transmission of data to all ADSP-21061s and can be used to
implement reflective semaphores.
Figure 4. Memory Map
0x0004 0000
0x0010 0000
0x00080000
0x00180000
0x0012 0000
0x00280000
0x0038 0000
0x0000 0000
0x0002 0000
0x0040 0000
BANK 1
MS0
BANK 2
MS1
BANK 3
MS2
MS3
IOP REGISTERS
SHORT WORD ADDRESSING
(16-BIT DATA WORDS)
NORMAL WORD ADDRESSING
(32-BIT DATA WORDS
48-BIT INSTRUCTION WORDS)
ADDRESS
BANK 0
SDRAM
(OPTIONAL)
0x0FFF FFFF
NONBANKED
NOTE: BANK SIZESARE SELECTED BY
MSIZE BITSOF THE SYSCON REGISTER
0x0030 0000
INTERNAL
MEMORY
SPACE
MULTIPROCESSOR
MEMORY
SPACE
ADDRESS
INTERNAL MEMORY SPACE
WITH ID = 001
0x003F FFFF
EXTERNAL
MEMORY
SPACE
INTERNAL MEMORY SPACE
WITH ID = 010
INTERNAL MEMORY SPACE
WITH ID = 011
INTERNAL MEMORY SPACE
WITH ID = 100
INTERNAL MEMORY SPACE
WITH ID = 101
INTERNAL MEMORY SPACE
WITH ID = 110
BROADCASTWRITE
TO ALL ADSP-21061s
ADSP-21061/ADSP-21061L
Rev. D | Page 7 of 52 | May 2013
Program Booting
The internal memory of the ADSP-21061 can be booted at sys-
tem power-up from either an 8-bit EPROM, or a host processor.
Selection of the boot source is controlled by the BMS (boot
memory select), EBOOT (EPROM boot), and LBOOT (host
boot) pins. 32-bit and 16-bit host processors can be used for
booting.
PORTING CODE FROM THE ADSP-21060 OR
ADSP-21062
The ADSP-21061 is pin compatible with the ADSP-21060/
ADSP-21061/ADSP-21062 processors. The ADSP-21061 pins
that correspond to the link port pins of the ADSP-21060/
ADSP-21062 are no-connects.
The ADSP-21061 is object code compatible with the
ADSP-21060/ADSP-21062 processors except for the following
functional elements:
The ADSP-21061 memory is organized into two blocks
with eight columns that are 4k deep per block. The
ADSP-21060/ADSP-21062 memory has 16 columns per
block.
Link port functions are not available.
Handshake external port DMA pins DMAR2 and DMAG2
are assigned to external port DMA Channel 6 instead of
Channel 8.
2-D DMA capability of the SPORT is not available.
The modify registers in SPORT DMA are not
programmable.
On the ADSP-21061, Block 0 starts at the beginning of internal
memory, normal word address 0x0002 0000. Block 1 starts at
the end of Block 0, with contiguous addresses. The remaining
addresses in internal memory are divided into blocks that alias
into Block 1. This allows any code or data stored in Block 1 on
the ADSP-21062 to retain the same addresses on the
ADSP- 21061—these addresses will alias into the actual Block 1
of each processor.
If you develop your application using the ADSP-21062, but will
migrate to the ADSP-21061, use only the first eight columns of
each memory bank. Limit your application to 8k of instructions
or up to 16k of data in each bank of the ADSP-21062, or any
combination of instructions or data that does not exceed the
memory bank.
DEVELOPMENT TOOLS
Analog Devices supports its processors with a complete line of
software and hardware development tools, including integrated
development environments (which include CrossCore
®
Embed-
ded Studio and/or VisualDSP++
®
), evaluation products,
emulators, and a wide variety of software add-ins.
Integrated Development Environments (IDEs)
For C/C++ software writing and editing, code generation, and
debug support, Analog Devices offers two IDEs.
The newest IDE, CrossCore Embedded Studio, is based on the
Eclipse
TM
framework. Supporting most Analog Devices proces-
sor families, it is the IDE of choice for future processors,
including multicore devices. CrossCore Embedded Studio
seamlessly integrates available software add-ins to support real
time operating systems, file systems, TCP/IP stacks, USB stacks,
algorithmic software modules, and evaluation hardware board
support packages. For more information visit
www.analog.com/cces.
The other Analog Devices IDE, VisualDSP++, supports proces-
sor families introduced prior to the release of CrossCore
Embedded Studio. This IDE includes the Analog Devices VDK
real time operating system and an open source TCP/IP stack.
For more information visit www.analog.com/visualdsp. Note
that VisualDSP++ will not support future Analog Devices
processors.
EZ-KIT Lite Evaluation Board
For processor evaluation, Analog Devices provides wide range
of EZ-KIT Lite
®
evaluation boards. Including the processor and
key peripherals, the evaluation board also supports on-chip
emulation capabilities and other evaluation and development
features. Also available are various EZ-Extenders
®
, which are
daughter cards delivering additional specialized functionality,
including audio and video processing. For more information
visit www.analog.com and search on “ezkit” or “ezextender”.
EZ-KIT Lite Evaluation Kits
For a cost-effective way to learn more about developing with
Analog Devices processors, Analog Devices offer a range of EZ-
KIT Lite evaluation kits. Each evaluation kit includes an EZ-KIT
Lite evaluation board, directions for downloading an evaluation
version of the available IDE(s), a USB cable, and a power supply.
The USB controller on the EZ-KIT Lite board connects to the
USB port of the user’s PC, enabling the chosen IDE evaluation
suite to emulate the on-board processor in-circuit. This permits
the customer to download, execute, and debug programs for the
EZ-KIT Lite system. It also supports in-circuit programming of
the on-board Flash device to store user-specific boot code,
enabling standalone operation. With the full version of Cross-
Core Embedded Studio or VisualDSP++ installed (sold
separately), engineers can develop software for supported EZ-
KITs or any custom system utilizing supported Analog Devices
processors.
Software Add-Ins for CrossCore Embedded Studio
Analog Devices offers software add-ins which seamlessly inte-
grate with CrossCore Embedded Studio to extend its capabilities
and reduce development time. Add-ins include board support
packages for evaluation hardware, various middleware pack-
ages, and algorithmic modules. Documentation, help,
configuration dialogs, and coding examples present in these
add-ins are viewable through the CrossCore Embedded Studio
IDE once the add-in is installed.
Rev. D | Page 8 of 52 | May 2013
ADSP-21061/ADSP-21061L
Board Support Packages for Evaluation Hardware
Software support for the EZ-KIT Lite evaluation boards and EZ-
Extender daughter cards is provided by software add-ins called
Board Support Packages (BSPs). The BSPs contain the required
drivers, pertinent release notes, and select example code for the
given evaluation hardware. A download link for a specific BSP is
located on the web page for the associated EZ-KIT or EZ-
Extender product. The link is found in the Product Download
area of the product web page.
Middleware Packages
Analog Devices separately offers middleware add-ins such as
real time operating systems, file systems, USB stacks, and
TCP/IP stacks. For more information see the following web
pages:
www.analog.com/ucos3
www.analog.com/ucfs
www.analog.com/ucusbd
www.analog.com/lwip
Algorithmic Modules
To speed development, Analog Devices offers add-ins that per-
form popular audio and video processing algorithms. These are
available for use with both CrossCore Embedded Studio and
VisualDSP++. For more information visit www.analog.com and
search on “Blackfin software modules” or “SHARC software
modules”.
Designing an Emulator-Compatible DSP Board (Target)
For embedded system test and debug, Analog Devices provides
a family of emulators. On each JTAG DSP, Analog Devices sup-
plies an IEEE 1149.1 JTAG Test Access Port (TAP). In-circuit
emulation is facilitated by use of this JTAG interface. The emu-
lator accesses the processor’s internal features via the
processor’s TAP, allowing the developer to load code, set break-
points, and view variables, memory, and registers. The
processor must be halted to send data and commands, but once
an operation is completed by the emulator, the DSP system is set
to run at full speed with no impact on system timing. The emu-
lators require the target board to include a header that supports
connection of the DSP’s JTAG port to the emulator.
For details on target board design issues including mechanical
layout, single processor connections, signal buffering, signal ter-
mination, and emulator pod logic, see the EE-68: Analog Devices
JTAG Emulation Technical Reference on the Analog Devices
website (www.analog.com)—use site search on “EE-68.” This
document is updated regularly to keep pace with improvements
to emulator support.
ADDITIONAL INFORMATION
This data sheet provides a general overview of the ADSP-21061
architecture and functionality. For detailed information on the
ADSP-21000 Family core architecture and instruction set, refer
to the ADSP- 2106x SHARC User’s Manual.
RELATED SIGNAL CHAINS
A signal chain is a series of signal conditioning electronic com-
ponents that receive input (data acquired from sampling either
real-time phenomena or from stored data) in tandem, with the
output of one portion of the chain supplying input to the next.
Signal chains are often used in signal processing applications to
gather and process data or to apply system controls based on
analysis of real-time phenomena. For more information about
this term and related topics, see the “signal chain” entry in the
Glossary of EE Terms on the Analog Devices website.
Analog Devices eases signal processing system development by
providing signal processing components that are designed to
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ADSP-21061/ADSP-21061L
Rev. D | Page 9 of 52 | May 2013
PIN FUNCTION DESCRIPTIONS
ADSP-21061 pin definitions are listed below. All pins are identi-
cal on the ADSP-21061 and ADSP-21061L. Inputs identified as
synchronous (S) must meet timing requirements with respect to
CLKIN (or with respect to TCK for TMS, TDI). Inputs identi-
fied as asynchronous (A) can be asserted asynchronously to
CLKIN (or to TCK for TRST).
Unused inputs should be tied or pulled to VDD or GND, except
for ADDR31-0, DATA47-0, FLAG3-0, SW, and inputs that have
internal pull-up or pull-down resistors (CPA, ACK, DTx, DRx,
TCLKx, RCLKx, TMS, and TDI)—these pins can be left float-
ing. These pins have a logic-level hold circuit that prevents the
input from floating internally.
Table 2. Pin Descriptions
Pin Type Function
ADDR
31–0
I/O/T External Bus Address. The ADSP-21061 outputs addresses for external memory and peripherals on these
pins. In a multiprocessor system the bus master outputs addresses for read/write of the internal memory or
IOP registers of other ADSP-21061s. The ADSP-21061 inputs addresses when a host processor or multipro-
cessing bus master is reading or writing its internal memory or IOP registers.
DATA
47–0
I/O/T External Bus Data. The ADSP-21061 inputs and outputs data and instructions on these pins. 32-bit single-
precision floating-point data and 32-bit fixed-point data is transferred over Bits 47 to 16 of the bus. 40-bit
extended-precision floating-point data is transferred over Bits 47 to 8 of the bus. 16-bit short word data is
transferred over Bits 31 to 16 of the bus. In PROM boot mode, 8-bit data is transferred over Bits 23 to 16. Pull-
up resistors on unused DATA pins are not necessary.
MS
3–0
O/T Memory Select Lines. These lines are asserted (low) as chip selects for the corresponding banks of external
memory. Memory bank size must be defined in the ADSP-21061’s system control register (SYSCON). The
MS
3–0
lines are decoded memory address lines that change at the same time as the other address lines.
When no external memory access is occurring the MS
3–0
lines are inactive; they are active however when a
conditional memory access instruction is executed, whether or not the condition is true. MS
0
can be used
with the PAGE signal to implement a bank of DRAM memory (Bank 0). In a multiprocessing system the MS
3–0
lines are output by the bus master.
RD I/O/T Memory Read Strobe. This pin is asserted (low) when the ADSP-21061 reads from external memory devices
or from the internal memory of other ADSP-21061s. External devices (including other ADSP-21061s) must
assert RD to read from the ADSP-21061’s internal memory. In a multiprocessing system RD is output by the
bus master and is input by all other ADSP-21061s.
WR I/O/T Memory Write Strobe. This pin is asserted (low) when the ADSP-21061 writes to external memory devices
or to the internal memory of other ADSP-21061s. External devices must assert WR to write to the
ADSP-21061’s internal memory. In a multiprocessing system WR is output by the bus master and is input by
all other ADSP-21061s.
PAGE O/T DRAM Page Boundary. The ADSP-21061 asserts this pin to signal that an external DRAM page boundary
has been crossed. DRAM page size must be defined in the ADSP-21061’s memory control register (WAIT).
DRAM can only be implemented in external memory Bank 0; the PAGE signal can only be activated for
Bank 0 accesses. In a multiprocessing system PAGE is output by the bus master.
ADRCLK O/T Clock Output Reference. In a multiprocessing system ADRCLK is output by the bus master.
SW I/O/T Synchronous Write Select. This signal is used to interface the ADSP-21061 to synchronous memory devices
(including other ADSP-21061s). The ADSP-21061 asserts SW (low) to provide an early indication of an
impending write cycle, which can be aborted if WR is not later asserted (e.g., in a conditional write
instruction). In a multiprocessing system, SW is output by the bus master and is input by all other
ADSP-21061s to determine if the multiprocessor memory access is a read or write. SW is asserted at the same
time as the address output. A host processor using synchronous writes must assert this pin when writing to
the ADSP-21061(s).
A = Asynchronous, G = Ground, I = Input, O = Output, P = Power Supply, S = Synchronous, (A/D) = Active Drive, (O/D) = Open-Drain,
T = Three-State (when SBTS is asserted, or when the ADSP-21061 is a bus slave)
i o I m :2 I m a 0‘ U E )> )2 gig ,, m RCLKX I/O Se \eu exter SETS exter H 56 fits in rogra E E SETS es in a high while SBTS SBTS This must b rled by W serted ull'ipro HBG qu'ish HBR A 5 H56 nai me ed in W Used b ipro rives fl ssor W eterm sing b W W Wpinaiowstha access the ext ysiem em W Ea(h RCLK pin has a 50 k ADSPrZi s masle 5, data W the h HBR itrai D27 W W W ssoro W internai puilrup resistor A : Asynchronous, G : Ground, i : input, 0 : Outpm, P : Power Supply, 5 : Syn T hreeVSlate (when SBTS is assened, or when the ADSP721061 is a bus Slave]
Rev. D | Page 10 of 52 | May 2013
ADSP-21061/ADSP-21061L
ACK I/O/S Memory Acknowledge. External devices can deassert ACK (low) to add wait states to an external memory
access. ACK is used by I/O devices, memory controllers, or other peripherals to hold off completion of an
external memory access. The ADSP-21061 deasserts ACK as an output to add wait states to a synchronous
access of its internal memory. In a multiprocessing system, a slave ADSP-21061 deasserts the bus masters
ACK input to add wait state(s) to an access of its internal memory. The bus master has a keeper latch on its
ACK pin that maintains the input at the level to which it was last driven.
SBTS I/S Suspend Bus Three-State. External devices can assert SBTS (low) to place the external bus address, data,
selects, and strobes in a high impedance state for the following cycle. If the ADSP-21061 attempts to access
external memory while SBTS is asserted, the processor halts and the memory access is not complete until
SBTS is deasserted. SBTS should only be used to recover from host processor/ADSP-21061 deadlock, or used
with a DRAM controller.
IRQ
2–0
I/A Interrupt Request Lines. May be either edge-triggered or level-sensitive.
FLAG
3–0
I/O/A Flag Pins. Each is configured via control bits as either an input or output. As an input, they can be tested as
a condition. As an output, they can be used to signal external peripherals.
TIMEXP O Timer Expired. Asserted for four cycles when the timer is enabled and TCOUNT decrements to zero.
HBR I/A Host Bus Request. This pin must be asserted by a host processor to request control of the ADSP-21061’s
external bus. When HBR is asserted in a multiprocessing system, the ADSP-21061 that is bus master will
relinquish the bus and assert HBG. To relinquish the bus, the ADSP-21061 places the address, data, select,
and strobe lines in a high impedance state. HBR has priority over all ADSP-21061 bus requests BR
6–1
in a
multiprocessing system.
HBG I/O Host Bus Grant. Acknowledges a bus request, indicating that the host processor may take control of the
external bus. HBG is asserted (held low) by the ADSP-21061 until HBR is released. In a multiprocessing system,
HBG is output by the ADSP-21061 bus master and is monitored by all others.
CS I/A Chip Select. Asserted by host processor to select the ADSP-21061.
REDY O (O/D) Host Bus Acknowledge. The ADSP-21061 deasserts REDY (low) to add wait states to an asynchronous access
of its internal memory or IOP registers by a host. This pin is an open-drain output (O/D) by default; it can be
programmed in the ADREDY bit of the SYSCON register to be active drive (A/D). REDY will only be output if
the CS and HBR inputs are asserted.
DMAR
2–1
I/A DMA Request 1 (DMA Channel 7) and DMA Request 2 (DMA Channel 6).
DMAG
2–1
O/T DMA Grant 1 (DMA Channel 7) and DMA Grant 2 (DMA Channel 6).
BR
6–1
I/O/S Multiprocessing Bus Requests. Used by multiprocessing ADSP-21061 processors to arbitrate for bus
mastership. An ADSP-21061 only drives its own BRx line (corresponding to the value of its ID2-0 inputs) and
monitors all others. In a multiprocessor system with less than six ADSP-21061s, the unused BRx pins should
be pulled high; the processor’s own BRx line must not be pulled high or low because it is an output.
ID2–0 O (O/D) Multiprocessing ID. Determines which multiprocessing bus request (BR1 BR6) is used by ADSP-21061.
ID = 001 corresponds to BR1, ID = 010 corresponds to BR2, etc., ID = 000 in single-processor systems. These
lines are a system configuration selection which should be hardwired or changed at reset only.
RPBA I/S Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for multiprocessor bus
arbitration is selected. When RPBA is low, fixed priority is selected. This signal is a system configuration
selection which must be set to the same value on every ADSP-21061. If the value of RPBA is changed during
system operation, it must be changed in the same CLKIN cycle on every ADSP-21061.
CPA I/O (O/D) Core Priority Access. Asserting its CPA pin allows the core processor of an ADSP-21061 bus slave to interrupt
background DMA transfers and gain access to the external bus. CPA is an open-drain output that is
connected to all ADSP-21061s in the system. The CPA pin has an internal 5 k pull-up resistor. If core access
priority is not required in a system, the CPA pin should be left unconnected.
DTx O Data Transmit (Serial Ports 0, 1). Each DT pin has a 50 k internal pull-up resistor.
DRx I Data Receive (Serial Ports 0, 1). Each DR pin has a 50 k internal pull-up resistor.
TCLKx I/O Transmit Clock (Serial Ports 0, 1). Each TCLK pin has a 50 k internal pull-up resistor.
RCLKx I/O Receive Clock (Serial Ports 0, 1). Each RCLK pin has a 50 k internal pull-up resistor.
Table 2. Pin Descriptions (Continued)
Pin Type Function
A = Asynchronous, G = Ground, I = Input, O = Output, P = Power Supply, S = Synchronous, (A/D) = Active Drive, (O/D) = Open-Drain,
T = Three-State (when SBTS is asserted, or when the ADSP-21061 is a bus slave)
w m NC \5 high bit E BMS BMS :u; (mos ocessors BMS halADS temco BMS BMS 'me TRST TRST E U Reserved pins which must be \eft open and unconnected. A : Asynchronous, G : Ground, \ : Input, 0 : Outpm, P : Power Supply, 5 : Syn T hreeVSlate (when SBTS is assened, or when the ADSP721061 is a bus Slave]
ADSP-21061/ADSP-21061L
Rev. D | Page 11 of 52 | May 2013
TFSx I/O Transmit Frame Sync (Serial Ports 0, 1).
RFSx I/O Receive Frame Sync (Serial Ports 0, 1).
EBOOT I EPROM Boot Select. When EBOOT is high, the ADSP-21061 is configured for booting from an 8-bit EPROM.
When EBOOT is low, the LBOOT and BMS inputs determine booting mode. See the table in the BMS pin
description below. This signal is a system configuration selection that should be hardwired.
LBOOT I Link Boot. Must be tied to GND.
BMS I/O/T* Boot Memory Select. Output: Used as chip select for boot EPROM devices (when EBOOT = 1,
LBOOT = 0). In a multiprocessor system, BMS is output by the bus master. Input: When low, indicates that no
booting will occur and that ADSP-21061 will begin executing instructions from external memory. See table
below. This input is a system configuration selection that should be hardwired. *Three-statable only in
EPROM boot mode (when BMS is an output).
EBOOT LBOOT BMS Booting Mode
1 0 Output EPROM (Connect BMS to EPROM chip select.)
0 0 1(Input) Host Processor.
0 0 0 (Input) No Booting. Processor executes from external memory.
CLKIN I Clock In. External clock input to the ADSP-21061. The instruction cycle rate is equal to CLKIN. CLKIN may
not be halted, changed, or operated below the minimum specified frequency.
RESET I/A Processor Reset. Resets the ADSP-21061 to a known state and begins program execution at the program
memory location specified by the hardware reset vector address. This input must be asserted (low) at
power-up.
TCK I Test Clock (JTAG). Provides an asynchronous clock for JTAG boundary scan.
TMS I/S Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20 k internal pull-up resistor.
TDI I/S Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 20 k internal pull-up
resistor.
TDO O Test Data Output (JTAG). Serial scan output of the boundary scan path.
TRST I/A Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-up or held
low for proper operation of the ADSP-21061. TRST has a 20 k internal pull-up resistor.
EMU OEmulation Status. Must be connected to the ADSP-21061 EZ-ICE target board connector only. EMU has a
50 k internal pull-up resistor.
ICSA O Reserved. Leave unconnected.
VDD P Power Supply. (30 pins). See Operating Conditions (5 V) and Operating Conditions (3.3 V).
GND G Power Supply Return. (30 pins)
NC Do Not Connect. Reserved pins which must be left open and unconnected.
Table 2. Pin Descriptions (Continued)
Pin Type Function
A = Asynchronous, G = Ground, I = Input, O = Output, P = Power Supply, S = Synchronous, (A/D) = Active Drive, (O/D) = Open-Drain,
T = Three-State (when SBTS is asserted, or when the ADSP-21061 is a bus slave)
m c Amve Low, 4.7 k PullrUp Resmor, 10penrDram Outpm from the DSP) cm: I I EU arm cm: I I mo
Rev. D | Page 12 of 52 | May 2013
ADSP-21061/ADSP-21061L
TARGET BOARD CONNECTOR FOR EZ-ICE PROBE
The ADSP-2106x EZ-ICE Emulator uses the IEEE 1149.1 JTAG
test access port of the ADSP-2106x to monitor and control the
target board processor during emulation. The EZ-ICE probe
requires the ADSP-2106x’s CLKIN, TMS, TCK, TDI, TDO, and
GND signals be made accessible on the target system via a
14-pin connector (a 2-row, 7-pin strip header) such as that
shown in Figure 5. The EZ-ICE probe plugs directly onto this
connector for chip-on-board emulation. You must add this con-
nector to your target board design if you intend to use the
ADSP-2106x EZ-ICE. The total trace length between the EZ-
ICE connector and the farthest device sharing the EZ-ICE JTAG
pin should be limited to 15 inches maximum for guaranteed
operation. This length restriction must include EZ-ICE JTAG
signals that are routed to one or more ADSP-2106x devices, or a
combination of ADSP-2106x devices and other JTAG devices
on the chain.
The 14-pin, 2-row pin strip header is keyed at the Pin 3 loca-
tion—Pin 3 must be removed from the header. The pins must be
0.025 inch square and at least 0.20 inches in length. Pin spacing
should be 0.1 0.1 inches. Pin strip headers are available from
vendors such as 3M, McKenzie, and Samtec. The BTMS, BTCK,
BTRST, and BTDI signals are provided so that the test access
port can also be used for board-level testing.
When the connector is not being used for emulation, place
jumpers between the Bxxx pins and the xxx pins as shown in
Figure 5. If you are not going to use the test access port for
board testing, tie BTRST to GND and tie or pull up BTCK to
V
DD
. The TRST pin must be asserted (pulsed low) after power-
up (through BTRST on the connector) or held low for proper
operation of the ADSP-2106x. None of the Bxxx pins (Pins 5, 7,
9, and 11) are connected on the EZ-ICE probe.
The JTAG signals are terminated on the EZ-ICE probe as shown
in Table 3.
Figure 6 shows JTAG scan path connections for systems that
contain multiple ADSP-2106x processors.
Connecting CLKIN to Pin 4 of the EZ-ICE header is optional.
The emulator only uses CLKIN when directed to perform oper-
ations such as starting, stopping, and single-stepping multiple
ADSP-2106xs in a synchronous manner. If you do not need
these operations to occur synchronously on the multiple proces-
sors, simply tie Pin 4 of the EZ-ICE header to ground.
If synchronous multiprocessor operations are needed and
CLKIN is connected, clock skew between the multiple
ADSP-21061 processors and the CLKIN pin on the EZ-ICE
header must be minimal. If the skew is too large, synchronous
operations may be off by one or more cycles between proces-
sors. For synchronous multiprocessor operation TCK, TMS,
CLKIN, and EMU should be treated as critical signals in terms
of skew, and should be laid out as short as possible on your
board. If TCK, TMS, and CLKIN are driving a large number of
ADSP-21061s (more than eight) in your system, then treat them
as a “clock tree” using multiple drivers to minimize skew. (See
Figure 7 below and “JTAG Clock Tree” and “Clock Distribu-
tion” in the “High Frequency Design Considerations” section of
the ADSP-2106x SHARC User’s Manual.)
If synchronous multiprocessor operations are not needed (i.e.,
CLKIN is not connected), just use appropriate parallel termina-
tion on TCK and TMS. TDI, TDO, EMU, and TRST are not
critical signals in terms of skew.
Figure 5. Target Board Connector For ADSP-2106x EZ-ICE Emulator
(Jumpers in Place)
TOP VIEW
1314
11 12
910
9
78
56
34
12
EMU
GND
TMS
TCK
TRST
TDI
TDO
GND
KEY (NO PIN)
BTMS
BTCK
BTRST
BTDI
GND
Table 3. Core Instruction Rate/CLKIN Ratio Selection
Signal Termination
TMS Driven Through 22 Resistor (16 mA Driver)
TCK Driven at 10 MHz Through 22 Resistor (16 mA
Driver)
TRST
1
1
TRST is driven low until the EZ-ICE probe is turned on by the emulator at software
startup. After software startup, is driven high.
Active Low Driven Through 22 Resistor (16 mA
Driver) (Pulled Up by On-Chip 20 k Resistor)
TDI Driven by 22 Resistor (16 mA Driver)
TDO One TTL Load, Split Termination (160/220)
CLKIN One TTL Load, Split Termination (160/220)
EMU Active Low, 4.7 k Pull-Up Resistor, One TTL Load
(Open-Drain Output from the DSP)
ADSP-21061/ADSP-21061L
Rev. D | Page 13 of 52 | May 2013
Figure 6. JTAG Scan Path Connections for Multiple ADSP-2106x Systems
Figure 7. JTAG Clock Tree for Multiple ADSP-2106x Systems
SYSTEM
CLKIN
EMU
5k
*
TDI TDO
5k
TDI
EMU
TMS
TCK
TDO
TRST
CLKIN
*OPEN-DRAIN DRIVER OR EQUIVALENT, i.e,
TDI TDO TDI TDO
TDI TDO TDI TDO TDI TDO
*
Rev. D | Page 14 of 52 | May 2013
ADSP-21061/ADSP-21061L
ADSP-21061 SPECIFICATIONS
OPERATING CONDITIONS (5 V)
ELECTRICAL CHARACTERISTICS (5 V)
K Grade
Parameter Description Min Nom Max Unit
V
DD
Supply Voltage 4.75 5.0 5.25 V
T
CASE
Case Operating Temperature 0 85 C
V
IH
1
1
1
Applies to input and bidirectional pins: DATA
47–0
, ADDR
31–0
, RD, WR, SW, ACK, SBTS, IRQ2–0, FLAG3–0, HGB, CS, DMAR1, DMAR2, BR
6–1
, ID
2–0
, RPBA, CPA, TFS0,
TFS1, RFS0, RFS1, EBOOT, BMS, TMS, TDI, TCK, HBR, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1.
High Level Input Voltage @ V
DD
= Max 2.0 V
DD
+ 0.5 V
V
IH
2
2
2
Applies to input pins: CLKIN, RESET, TRST.
High Level Input Voltage @ V
DD
= Max 2.2 V
DD
+ 0.5 V
V
IL
1,
2
Low Level Input Voltage @ V
DD
= Min –0.5 +0.8 V
Parameter Description Test Conditions Min Max Unit
V
OH
1, 2
High Level Output Voltage @ V
DD
= Min, I
OH
= –2.0 mA 4.1 V
V
OL
1,
2
Low Level Output Voltage @ V
DD
= Min, I
OL
= 4.0 mA 0.4 V
I
IH
3,
4
High Level Input Current @ V
DD
= Max, V
IN
= V
DD
Max 10 μA
I
IL
3
Low Level Input Current @ V
DD
= Max, V
IN
= 0 V 10 μA
I
ILP
4
Low Level Input Current @ V
DD
= Max, V
IN
= 0 V 150 μA
I
OZH
5,
6,
7,
8
Three-State Leakage Current @ V
DD
= Max, V
IN
= V
DD
Max 10 μA
I
OZL
5
Three-State Leakage Current @ V
DD
= Max, V
IN
= 0 V 10 μA
I
OZHP
Three-State Leakage Current @ V
DD
= Max, V
IN
= V
DD
Max 350 μA
I
OZLC
7
Three-State Leakage Current @ V
DD
= Max, V
IN
= 0 V 1.5 mA
I
OZLA
9
Three-State Leakage Current @ V
DD
= Max, V
IN
= 1.5 V 350 μA
I
OZLAR
8
Three-State Leakage Current @ V
DD
= Max, V
IN
= 0 V 4.2 mA
I
OZLS
6
Three-State Leakage Current @ V
DD
= Max, V
IN
= 0 V 150 μA
C
IN
10,
11
Input Capacitance f
IN
= 1 MHz, T
CASE
= 25°C, V
IN
= 2.5 V 4.7 pF
1
Applies to output and bidirectional pins: DATA
47-0
, ADDR
31-0
, 3-0, MS
3–0
, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG3-0, TIMEXP, HBG, REDY, DMAG1, DMAG2,
BR
6–1
, CPA, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, BMS, TDO, EMU, ICSA.
2
See “Output Drive Currents” on Page 44 for typical drive current capabilities.
3
Applies to input pins: ACK, SBTS, IRQ
2–0
, HBR, CS, DMAR1, DMAR2, ID
2–0
, RPBA, EBOOT, LBOOT, CLKIN, RESET, TCK.
4
Applies to input pins with internal pull-ups:DR0, DR1, TRST, TMS, TDI, EMU.
5
Applies to three-statable pins: DATA
47–0
, ADDR
31–0
, MS
3–0
, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG
3–0
, HBG, REDY, DMAG1, DMAG2, BMS, BR
6–1
, TFSx, RFSx,
TDO, EMU. (Note that ACK is pulled up internally with 2 k during reset in a multiprocessor system, when ID
2–0
= 001 and another ADSP-21061 is not requesting bus
mastership.)
6
Applies to three-statable pins with internal pull-ups: DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1.
7
Applies to CPA pin.
8
Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 k during reset in a multiprocessor system, when ID
2–0
= 001 and another ADSP-21061L
is not requesting bus mastership).
9
Applies to ACK pin when keeper latch enabled.
10
Applies to all signal pins.
11
Guaranteed but not tested.
Internal Memory DMA 1 perCyde 1 per 2 Cycles 1 per 2 Cycles | Supply Current (ldlel v : Max 20 mA 1mm Supply Current (ldle15) VDD : Max 55 mA
ADSP-21061/ADSP-21061L
Rev. D | Page 15 of 52 | May 2013
INTERNAL POWER DISSIPATION (5 V)
These specifications apply to the internal power portion of V
DD
only. See the Power Dissipation section of this data sheet for cal-
culation of external supply current and total supply current. For
a complete discussion of the code used to measure power dissi-
pation, see the technical note “SHARC Power Dissipation
Measurements.”
Specifications are based on the operating scenarios:
To estimate power consumption for a specific application, use
the following equation where % is the amount of time your pro-
gram spends in that state:
%PEAK I
DDINPEAK
+ %HIGH I
DDINHIGH
+ %LOW I
DDINLOW
+
%IDLE I
DDIDLE
= power consumption
Operation Peak Activity (I
DDINPEAK
) High Activity (I
DDINHIGH
) Low Activity (I
DDINLOW
)
Instruction Type Multifunction Multifunction Single Function
Instruction Fetch Cache Internal Memory Internal Memory
Core Memory Access 2 per Cycle (DM and PM) 1 per Cycle (DM) None
Internal Memory DMA 1 per Cycle 1 per 2 Cycles 1 per 2 Cycles
Parameter Test Conditions Max Unit
I
DDINPEAK
Supply Current (Internal)
1
t
CK
= 30 ns, V
DD
= Max
t
CK
= 25 ns, V
DD
= Max
t
CK
= 20 ns, V
DD
= Max
595
680
850
mA
mA
I
DDINHIGH
Supply Current (Internal)
2
t
CK
= 30 ns, V
DD
= Max
t
CK
= 25 ns, V
DD
= Max
t
CK
= 20 ns, V
DD
= Max
460
540
670
mA
mA
I
DDINLOW
Supply Current (Internal)
3
t
CK
= 30 ns, V
DD
= Max
t
CK
= 25 ns, V
DD
= Max
t
CK
= 20 ns, V
DD
= Max
270
320
390
mA
mA
I
DDIDLE
Supply Current (Idle)
4
I
DDIDLE
Supply Current (Idle16)
5
V
DD
= Max
V
DD
= Max
200
55
mA
mA
1
The test program used to measure I
DDINPEAK
represents worst-case processor operation and is not sustainable under normal application conditions. Actual internal power
measurements made using typical applications are less than specified.
2
I
DDINHIGH
is a composite average based on a range of high activity code. I
DDINLOW
is a composite average based on a range of low activity code.
3
I
DDINLOW
is a composite average based on a range of low activity code.
4
Idle denotes ADSP-21061L state during execution of IDLE instruction.
5
Idle16 denotes ADSP-2106x state during execution of IDLE16 instruction.
DD EXY E‘ m a E x ADDRCLK 4.7 pF 20 MHz 25V : 0.002 W
Rev. D | Page 16 of 52 | May 2013
ADSP-21061/ADSP-21061L
EXTERNAL POWER DISSIPATION (5 V)
Total power dissipation has two components, one due to inter-
nal circuitry and one due to the switching of external output
drivers. Internal power dissipation is dependent on the instruc-
tion execution sequence and the data operands involved.
Internal power dissipation is calculated in the following way:
P
INT
= I
DDIN

V
DD
The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on:
the number of output pins that switch during each cycle
(O)
—the maximum frequency at which they can switch (f)
—their load capacitance (C)
their voltage swing (V
DD
)
and is calculated by:
PEXT = O
C
V
DD
2
f
The load capacitance should include the processor’s package
capacitance (CIN). The switching frequency includes driving
the load high and then back low. Address and data pins can
drive high and low at a maximum rate of 1/(2t
CK
). The write
strobe can switch every cycle at a frequency of 1/t
CK
. Select pins
switch at 1/(2t
CK
), but selects can switch on each cycle.
Example: Estimate P
EXT
with the following assumptions:
A system with one bank of external data memory RAM
(32-bit)
Four 128k 8 RAM chips are used, each with a load of
10 pF
External data memory writes occur every other cycle, a rate
of 1/(4t
CK
), with 50% of the pins switching
The instruction cycle rate is 40 MHz (t
CK
= 25 ns)
The P
EXT
equation is calculated for each class of pins that can
drive:
A typical power consumption can now be calculated for these
conditions by adding a typical internal power dissipation:
P
TOTAL
= P
EXT
+ (I
DDIN2
5.0 V)
Note that the conditions causing a worst-case P
EXT
are different
from those causing a worst-case P
INT
. Maximum P
INT
cannot
occur while 100% of the output pins are switching from all ones
to all zeros. Note also that it is not common for an application to
have 100% or even 50% of the outputs switching
simultaneously.
Table 4. External Power Calculations
Pin Type No. of Pins % Switching C f V
DD
2
= P
EXT
Address 15 50 44.7 pF 10 MHz 25 V = 0.084 W
MS0 10 44.7 pF 10 MHz 25 V = 0.000 W
WR 1— 44.7 pF 20 MHz 25 V = 0.022 W
Data 32 50 14.7 pF 10 MHz 25 V = 0.059 W
ADDRCLK 1 4.7 pF 20 MHz 25 V = 0.002 W
P
EXT
= 0.167 W
ADSP-21061/ADSP-21061L
Rev. D | Page 17 of 52 | May 2013
ADSP-21061L SPECIFICATIONS
OPERATING CONDITIONS (3.3 V)
ELECTRICAL CHARACTERISTICS (3.3 V)
A Grade K Grade
Parameter Description Min Nom Max Min Nom Max Unit
V
DD
Supply Voltage 3.15 3.3 3.45 3.15 3.3 3.45 V
T
CASE
Case Operating Temperature –40 +85 0 +85 C
V
IH
1
1
1
Applies to input and bidirectional pins: DATA
47–0
, ADDR
31–0
, RD, WR, SW, ACK, SBTS, IRQ2–0, FLAG3–0, HGB, CS, DMAR1, DMAR2, BR
6–1
, ID
2–0
, RPBA, CPA, TFS0,
TFS1, RFS0, RFS1, EBOOT, BMS, TMS, TDI, TCK, HBR, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1
High Level Input Voltage @ V
DD
= Max 2.0 V
DD
+ 0.5 2.0 V
DD
+ 0.5 V
V
IH
2
2
2
Applies to input pins: CLKIN, RESET, TRST
High Level Input Voltage @ V
DD
= Max 2.2 V
DD
+ 0.5 2.2 V
DD
+ 0.5 V
V
IL
1,
2
Low Level Input Voltage @ V
DD
= Min –0.5 +0.8 –0.5 +0.8 V
Parameter Description Test Conditions Min Max Unit
V
OH
1,2
High Level Output Voltage @ V
DD
= Min, I
OH
= –2.0 mA 2.4 V
V
OL
1,
2
Low Level Output Voltage @ V
DD
= Min, I
OL
= 4.0 mA 0.4 V
I
IH
3,
4
High Level Input Current @ V
DD
= Max, V
IN
= V
DD
Max 10 μA
I
IL
3
Low Level Input Current @ V
DD
= Max, V
IN
= 0 V 10 μA
I
ILP
4
Low Level Input Current @ V
DD
= Max, V
IN
= 0 V 150 μA
I
OZH
5,
6,
7,
8
Three-State Leakage Current @ V
DD
= Max, V
IN
= V
DD
Max 10 μA
I
OZL
5
Three-State Leakage Current @ V
DD
= Max, V
IN
= 0 V 10 μA
I
OZHP
Three-State Leakage Current @ V
DD
= Max, V
IN
= V
DD
Max 350 μA
I
OZLC
7
Three-State Leakage Current @ V
DD
= Max, V
IN
= 0 V 1.5 mA
I
OZLA
9
Three-State Leakage Current @ V
DD
= Max, V
IN
= 1.5 V 350 μA
I
OZLAR
8
Three-State Leakage Current @ V
DD
= Max, V
IN
= 0 V 4.2 mA
I
OZLS
6
Three-State Leakage Current @ V
DD
= Max, V
IN
= 0 V 150 μA
C
IN
10,
11
Input Capacitance f
IN
= 1 MHz, T
CASE
= 25°C, V
IN
= 2.5 V 4.7 pF
1
Applies to output and bidirectional pins: DATA
47–0
, ADDR
31–0
, 3-0, MS
3–0
, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG3-0, TIMEXP, HBG, REDY, DMAG1, DMAG2,
BR
6–1
, CPA, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, BMS, TDO, EMU, ICSA.
2
See “Output Drive Currents” on Page 45 for typical drive current capabilities.
3
Applies to input pins: ACK, SBTS, IRQ
2–0
, HBR, CS, DMAR1, DMAR2, ID
2–0
, RPBA, EBOOT, LBOOT, CLKIN, RESET, TCK.
4
Applies to input pins with internal pull-ups: DR0, DR1, TRST, TMS, TDI, EMU.
5
Applies to three-statable pins: DATA
47–0
, ADDR
31–0
, MS
3–0
, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG
3–0
, HBG, REDY, DMAG1, DMAG2, BMS, BR
6–1
, TFSx, RFSx,
TDO, EMU. (Note that ACK is pulled up internally with 2 k during reset in a multiprocessor system, when ID
2–0
= 001 and another ADSP-21061 is not requesting bus
mastership.)
6
Applies to three-statable pins with internal pull-ups: DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1.
7
Applies to CPA pin.
8
Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 k during reset in a multiprocessor system, when ID
2–0
= 001 and another ADSP-21061L
is not requesting bus mastership).
9
Applies to ACK pin when keeper latch enabled.
10
Applies to all signal pins.
11
Guaranteed but not tested.
Interna1 Memory DMA 1 perCyde 1 per 2 Cydes 1 per 2 Cycles 1 Supply Current (Id‘e) v : Max 18 mA 1mm Supply Current (Id‘e) VDD : Max 50 mA
Rev. D | Page 18 of 52 | May 2013
ADSP-21061/ADSP-21061L
INTERNAL POWER DISSIPATION (3.3 V)
These specifications apply to the internal power portion of V
DD
only. See the Power Dissipation section of this data sheet for cal-
culation of external supply current and total supply current. For
a complete discussion of the code used to measure power dissi-
pation, see the technical note “SHARC Power Dissipation
Measurements.”
Specifications are based on the operating scenarios:
To estimate power consumption for a specific application, use
the following equation where % is the amount of time your pro-
gram spends in that state:
%PEAK I
DDINPEAK
+ %HIGH I
DDINHIGH
+ %LOW I
DDINLOW
+ %IDLE
I
DDIDLE
= power consumption
Operation Peak Activity (I
DDINPEAK
) High Activity (I
DDINHIGH
) Low Activity (I
DDINLOW
)
Instruction Type Multifunction Multifunction Single Function
Instruction Fetch Cache Internal Memory Internal Memory
Core memory Access 2 per Cycle (DM and PM) 1 per Cycle (DM) None
Internal Memory DMA 1 per Cycle 1 per 2 Cycles 1 per 2 Cycles
Parameter Test Conditions Max Unit
I
DDINPEAK
Supply Current (Internal)
1
t
CK
= 25 ns, V
DD
= Max
t
CK
= 22.5 ns, V
DD
= Max
480
535
mA
mA
I
DDINHIGH
Supply Current (Internal)
2
t
CK
= 25 ns, V
DD
= Max
t
CK
= 22.5 ns, V
DD
= Max
380
425
mA
mA
I
DDINLOW
Supply Current (Internal)
3
t
CK
= 25 ns, V
DD
= Max
t
CK
= 22.5 ns, V
DD
= Max
220
245
mA
mA
I
DDIDLE
Supply Current (Idle)
4
I
DDIDLE
Supply Current (Idle)
5
V
DD
= Max
V
DD
= Max
180
50
mA
mA
1
The test program used to measure I
DDINPEAK
represents worst-case processor operation and is not sustainable under normal application conditions. Actual internal power
measurements made using typical applications are less than specified.
2
I
DDINHIGH
is a composite average based on a range of high activity code. I
DDINLOW
is a composite average based on a range of low activity code.
3
IDDINLOW
is a composite average based on a range of low activity code.
4
Idle denotes ADSP-21061L state during execution of IDLE instruction.
5
Idle16 denotes ADSP-21061L state during execution of IDLE16 instruction.
DB in g‘ m a E x ADDRCLK 4.7 pF x ZDMHZ x10.9V :0.001 W
ADSP-21061/ADSP-21061L
Rev. D | Page 19 of 52 | May 2013
EXTERNAL POWER DISSIPATION (3.3 V)
Total power dissipation has two components, one due to inter-
nal circuitry and one due to the switching of external output
drivers. Internal power dissipation is dependent on the instruc-
tion execution sequence and the data operands involved.
Internal power dissipation is calculated in the following way:
P
INT
= I
DDIN

V
DD
The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on:
the number of output pins that switch during each cycle
(O)
the maximum frequency at which they can switch (f)
—their load capacitance (C)
their voltage swing (V
DD
)
and is calculated by:
PEXT = O
C
V
DD
2
f
The load capacitance should include the processor’s package
capacitance (CIN). The switching frequency includes driving
the load high and then back low. Address and data pins can
drive high and low at a maximum rate of 1/(2t
CK
). The write
strobe can switch every cycle at a frequency of 1/t
CK
. Select pins
switch at 1/(2t
CK
), but selects can switch on each cycle.
Example: Estimate P
EXT
with the following assumptions:
A system with one bank of external data memory RAM
(32-bit)
Four 128k 8 RAM chips are used, each with a load of
10 pF
External data memory writes occur every other cycle, a rate
of 1/(4t
CK
), with 50% of the pins switching
The instruction cycle rate is 40 MHz (t
CK
= 25 ns)
The P
EXT
equation is calculated for each class of pins that can
drive:
A typical power consumption can now be calculated for these
conditions by adding a typical internal power dissipation:
P
TOTAL
= P
EXT
+ (I
DDIN2
3.3 V)
Note that the conditions causing a worst-case P
EXT
are different
from those causing a worst-case P
INT
. Maximum P
INT
cannot
occur while 100% of the output pins are switching from all ones
to all zeros. Note also that it is not common for an application to
have 100% or even 50% of the outputs switching
simultaneously.
Table 5. External Power Calculations
Pin Type No. of Pins % Switching C f V
DD
2
= P
EXT
Address 15 50 44.7 pF 10 MHz 10.9 V = 0.037 W
MS0 10 44.7 pF 10 MHz 10.9 V = 0.000 W
WR 1— 44.7 pF 20 MHz 10.9 V = 0.010 W
Data 32 50 14.7 pF 10 MHz 10.9 V = 0.026 W
ADDRCLK 1 4.7 pF 20 MHz 10.9 V = 0.001 W
P
EXT
= 0.074 W
Junction Temperature Under Bias 130C 130°C A M yyww Date Code
Rev. D | Page 20 of 52 | May 2013
ADSP-21061/ADSP-21061L
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed below may cause permanent
damage to the device. These are stress ratings only; functional
operation of the device at these or any other conditions greater
than those indicated in the operational sections of this specifica-
tion is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ESD CAUTION
PACKAGE MARKING INFORMATION
The information presented in Figure 8 provides details about
the package branding for the ADSP-21061 processor. For a
complete listing of product availability, see Ordering Guide on
Page 52.
TIMING SPECIFICATIONS
The timing specifications shown are based on a CLKIN fre-
quency of 50 MHz (t
CK
= 20 ns). The DT derating enables the
calculation of timing specifications within the min to max range
of the t
CK
specification (see Table 7). DT is the difference
between the derated CLKIN period (t
CK
) and a CLKIN period of
25 ns:
DT = t
CK
– 20 ns
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently, you
cannot meaningfully add parameters to derive longer times.
For voltage reference levels, see Figure 29 under Test
Conditions.
Timing Requirements apply to signals that are controlled by cir-
cuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices. (O/D) = Open Drain,
(A/D) = Active Drive.
Switching Characteristics specify how the processor changes its
signals. You have no control over this timing—circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics tell you what the
processor will do in a given circumstance. You can also use
switching characteristics to ensure that any timing requirement
of a device connected to the processor (such as memory) is
satisfied.
Parameter 5 V 3.3 V
Supply Voltage (V
DD
) –0.3 V to +7.0 V –0.3 V to +4.6 V
Input Voltage –0.5 V to V
DD
+0.5 V –0.5 V to V
DD
+0.5 V
Output Voltage Swing –0.5 V to V
DD
+0.5 V –0.5 V to V
DD
+0.5 V
Load Capacitance 200 pF 200 pF
Storage Temperature Range –65C to +150C–65C to +150C
Lead Temperature (5 seconds) 280C280C
Junction Temperature Under Bias 130C130C
Figure 8. Typical Package Marking (Actual Marking Format May Vary)
Table 6. Package Brand Information
Brand Key Field Description
t Temperature Range
pp Package Type
Z Lead Free Option
ccc See Ordering Guide
vvvvvv.x Assembly Lot Code
n.n Silicon Revision
yyww Date Code
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid
performance degradation or loss of functionality.
vvvvvv.x n.n
tppZccc
S
ADSP-21061
a
yyww country_of_origin
tcm CLK‘N Rise/Fall (0.4 v to 2.0 V) ns RESET tsm RESET Semp Before CLK‘N ngh 14 + DT/Z ta ns
ADSP-21061/ADSP-21061L
Rev. D | Page 21 of 52 | May 2013
Clock Input
Reset
Table 7. Clock Input
Parameter
ADSP-21061
50 MHz, 5 V
ADSP-21061L
44 MHz, 3.3 V
ADSP-21061/
ADSP-21061L
40 MHz,
5 V and 3.3 V
ADSP-21061
33 MHz, 5 V
UnitMin Max Min Max Min Max Min Max
Timing Requirements
t
CK
CLKIN Period 20 100 22.5 100 25 100 30 100 ns
t
CKL
CLKIN Width Low 7777ns
t
CKH
CLKIN Width High 5555ns
t
CKRF
CLKIN Rise/Fall (0.4 V to 2.0 V) 3 3 3 3 ns
Figure 9. Clock Input
CLKIN
tCKH tCKL
tCK
Table 8. Reset
5 V and 3.3 V
Unit
Parameter Min Max
Timing Requirements
t
WRST
RESET Pulse Width Low
1
4t
CK
ns
t
SRST
RESET Setup Before CLKIN High
2
14 + DT/2 t
CK
ns
1
Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming stable
V
DD
and CLKIN (not including startup time of external clock oscillator).
2
Only required if multiple ADSP-21061s must come out of reset synchronous to CLKIN with program counters (PC) equal. Not required for multiple ADSP-21061s commu-
nicating over the shared bus (through the external port), because the bus arbitration logic automatically synchronizes itself after reset.
Figure 10. Reset
CLKIN
RESET
tWRST
tSRST
‘ww IRQZrO IRQZrO IRQZrO Pu‘sewidth Z+t0< ns="" tdtex="" clkin="" high="" m="" t‘mexp="" ns="" \="" j="">
Rev. D | Page 22 of 52 | May 2013
ADSP-21061/ADSP-21061L
Interrupts
Timer
Table 9. Interrupts
5 V and 3.3 V
Unit
Parameter Min Max
Timing Requirements
t
SIR
IRQ2–0 Setup Before CLKIN High
1
18 + 3DT/4 ns
t
HIR
IRQ2–0 Hold Before CLKIN High
1
12 + 3DT/4 ns
t
IPW
IRQ2–0 Pulsewidth
2
2+t
CK
ns
1
Only required for IRQx recognition in the following cycle.
2
Applies only if t
SIR
and t
HIR
requirements are not met.
Figure 11. Interrupts
CLKIN
IRQ2–0
tIPW
tSIR
tHIR
Table 10. Timer
5 V and 3.3 V
Unit
Parameter Min Max
Switching Characteristic
t
DTEX
CLKIN High to TIMEXP 15 ns
Figure 12. Timer
CLKIN
TIMEXP
tDTEX
tDTEX
‘DFOD CLK‘N High to FLAG370 OUT D‘sable 14 ns
ADSP-21061/ADSP-21061L
Rev. D | Page 23 of 52 | May 2013
Flags
Table 11. Flags
5 V and 3.3 V
Unit
Parameter Min Max
Timing Requirements
t
SFI
FLAG3–0 IN Setup Before CLKIN High
1
8 + 5DT/16 ns
t
HFI
FLAG3–0 IN Hold After CLKIN High
1
0 – 5DT/16 ns
t
DWRFI
FLAG3–0 IN Delay After RD/WR Low
1
5 + 7DT/16 ns
t
HFIWR
FLAG3–0 IN Hold After RD/WR Deasserted
1
0ns
Switching Characteristics
t
DFO
FLAG3–0 OUT Delay After CLKIN High 16 ns
t
HFO
FLAG3–0 OUT Hold After CLKIN High 4 ns
t
DFOE
CLKIN High to FLAG3–0 OUT Enable 3 ns
t
DFOD
CLKIN High to FLAG3–0 OUT Disable 14 ns
1
Flag inputs meeting these setup and hold times for Instruction Cycle N will affect conditional instructions in Instruction Cycle N+2.
Figure 13. Flags
CLKIN
FLAG3–0 OUT
FLAG OUTPUT
CLKIN
FLAG INPUT
FLAG3–0 IN
tDFO
tHFO
tDFO tDFOD
tDFOE
tSFI tHFI
tHFIWR
tDWRFI
RD WR
RD E RD RD E W fi,fi DMAGX Mum Address, Se‘ects Setup Belore ADRCLK High 0 + DT/A ns (K H :‘CK (ifan address herd cyde occurs as spedlied in wmr regisrer; otherwise H : 0)
Rev. D | Page 24 of 52 | May 2013
ADSP-21061/ADSP-21061L
Memory Read—Bus Master
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) without reference to
CLKIN. These specifications apply when the ADSP-21061 is the
bus master accessing external memory space in asynchronous
access mode. Note that timing for ACK, DATA, RD, WR, and
DMAGx strobe timing parameters only applies to asynchronous
access mode.
Table 12. Memory Read—Bus Master
5 V and 3.3 V
Unit
Parameter Min Max
Timing Requirements
t
DAD
Address, Selects Delay to Data Valid
1,
2
18 + DT+W ns
t
DRLD
RD Low to Data Valid
1
12 + 5DT/8 + W ns
t
HDA
Data Hold from Address, Selects
3
0.5 ns
t
HDRH
Data Hold from RD High
3
2.0 ns
t
DAAK
ACK Delay from Address, Selects
2,
4
15 + 7DT/8 + W ns
t
DSAK
ACK Delay from RD Low
4
8 + DT/2 + W ns
Switching Characteristics
t
DRHA
Address, Selects Hold After RD High 0+H ns
t
DARL
Address, Selects to RD Low
2
2 + 3DT/8 ns
t
RW
RD Pulse Width 12.5 + 5DT/8 + W ns
t
RWR
RD High to WR, RD, DMAGx Low 8 + 3DT/8 + HI ns
t
SADADC
Address, Selects Setup Before ADRCLK High
2
0 + DT/4 ns
W = (number of wait states specified in WAIT register) t
CK
.
HI = t
CK
(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
H = t
CK
(if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).
1
Data delay/setup: user must meet t
DAD
or t
DRLD
or synchronous spec t
SSDATI
.
2
The falling edge of MSx, SW, BMS is referenced.
3
Data hold: user must meet t
HDA
or t
HDRH
or synchronous spec t
HSDATI
. See Example System Hold Time Calculation on Page 43 for the calculation of hold times given capacitive
and dc loads.
4
ACK delay/setup: user must meet t
DAAK
or t
DSAK
or synchronous specification t
SACKC
(Table 13 on Page 25) for deassertion of ACK (Low), all three specifications must be met
for assertion of ACK (High).
Figure 14. Memory Read—Bus Master
WR, DMAG
ACK
DATA
RD
ADDRESS
MSX, SW
BMS
tDARL tRW
tDAD
tSADADC
tDAAK
tHDRH
tHDA
tRWR
tDRLD
ADDRCLK
(OUT)
tDRHA
tDSAK
W W W m r7 T m 7 IT, DMAGX 7 W W mum Address, Selects to ADRCLK High 0 + DT/A ns CK I: ta Ufa bus \dle (yde occurs, as spedlied m WA‘T regmer; otherwise I : 0).
ADSP-21061/ADSP-21061L
Rev. D | Page 25 of 52 | May 2013
Memory Write—Bus Master
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) without reference to
CLKIN. These specifications apply when the ADSP-21061 is the
bus master accessing external memory space in asynchronous
access mode. Note that timing for ACK, DATA, RD, WR, and
DMAGx strobe timing parameters only applies to asynchronous
access mode.
Table 13. Memory Write—Bus Master
5 V and 3.3 V
Unit
Parameter Min Max
Timing Requirements
t
DAAK
ACK Delay from Address, Selects
1, 2
15 + 7DT/8 + W ns
t
DSAK
ACK Delay from WR Low
1
8 + DT/2 + W ns
Switching Characteristics
t
DAWH
Address, Selects to WR Deasserted
2
17 + 15DT/16 + W ns
t
DAWL
Address, Selects to WR Low
2
3 + 3DT/8 ns
t
WW
WR Pulse Width 13 + 9DT/16 + W ns
t
DDWH
Data Setup Before WR High 7 + DT/2 + W ns
t
DWHA
Address Hold After WR Deasserted 1 + DT/16 + H ns
t
DATRWH
Data Disable After WR Deasserted
3
1 + DT/16 +H 6 + DT/16 +H ns
t
WWR
WR High to WR, RD, DMAGx Low 8 + 7DT/16 + H ns
t
DDWR
Data Disable Before WR or RD Low 5 + 3DT/8 + I ns
t
WDE
WR Low to Data Enabled –1 + DT/16 ns
t
SADADC
Address, Selects to ADRCLK High
2
0 + DT/4 ns
W = (number of wait states specified in WAIT register) × t
CK
.
H = t
CK
(if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).
I = t
CK
(if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).
1
ACK delay/setup: User must meet t
DAAK
or t
DSAK
or synchronous specification t
SAKC
for deassertion of ACK (low), all three specifications must be met for assertion of ACK
(high).
2
The falling edge of MSx, SW, BMS is referenced.
3
For more information, see Example System Hold Time Calculation on Page 43 for calculation of hold times given capacitive and dc loads.
Figure 15. Memory Write—Bus Master
RD, DMAG
ACK
DATA
WR
ADDRESS
MSX, SW
BMS
tWW
tSADADC
tDAAK
tWWR
ADRCLK
(OUT)
tDWHA
tDSAK
tDAWL
tWDE tDDWR
tDATRWH
tDDWH
tDAWH
W BMS, W MSX BMS, W W W W T ‘ADRCKL ADRCLK Width Low “(K/2 , 2] n5
Rev. D | Page 26 of 52 | May 2013
ADSP-21061/ADSP-21061L
Synchronous Read/Write—Bus Master
Use these specifications for interfacing to external memory sys-
tems that require CLKIN—relative timing or for accessing a
slave ADSP-21061 (in multiprocessor memory space). These
synchronous switching characteristics are also valid during
asynchronous memory reads and writes except where noted (see
Memory Read—Bus Master on Page 24 and Memory Write—
Bus Master on Page 25). When accessing a slave ADSP-21061,
these switching characteristics must meet the slave’s timing
requirements for synchronous read/writes (see Synchronous
Read/Write—Bus Slave on Page 28). The slave ADSP-21061
must also meet these (bus master) timing requirements for data
and acknowledge setup and hold times.
Table 14. Synchronous Read/Write—Bus Master
5 V and 3.3 V
Unit
Parameter Min Max
Timing Requirements
t
SSDATI
Data Setup Before CLKIN
(50 MHz, t
CK
= 20 ns)
1
2 + DT/8
1.5 + DT/8
ns
t
HSDATI
Data Hold After CLKIN 3.5 – DT/8 ns
t
DAAK
ACK Delay After Address, Selects
2, 3
15 + 7DT/8 + W ns
t
SACKC
ACK Setup Before CLKIN
3
6.5+DT/4 ns
t
HACK
ACK Hold After CLKIN –1 – DT/4 ns
Switching Characteristics
t
DADRO
Address, MSx, BMS, SW Delay After CLKIN
2
6.5 – DT/8 ns
t
HADRO
Address, MSx, BMS, SW Hold After CLKIN –1 – DT/8 ns
t
DPGC
PAGE Delay After CLKIN 9 + DT/8 16 + DT/8 ns
t
DRDO
RD High Delay After CLKIN –1.5 – DT/8 4 – DT/8 ns
t
DWRO
WR High Delay After CLKIN
(50 MHz, t
CK
= 20 ns)
–2.5 – 3DT/16
–1.5 – 3DT/16
4 – 3DT/16
4 – 3DT/16
ns
t
DRWL
RD/WR Low Delay After CLKIN 8 + DT/4 12 + DT/4 ns
t
SDDATO
Data Delay After CLKIN 19 + 5DT/16 ns
t
DATTR
Data Disable After CLKIN
4
0 – DT/8 7 – DT/8 ns
t
DADCCK
ADRCLK Delay After CLKIN 4 + DT/8 10 + DT/8 ns
t
ADRCK
ADRCLK Period t
CK
ns
t
ADRCKH
ADRCLK Width High (t
CK
/2 – 2) ns
t
ADRCKL
ADRCLK Width Low (t
CK
/2 – 2) ns
1
This specification applies to the ADSP-21061KS-200 (5 V, 50 MHz) operating at t
CK
< 25 ns. For all other devices, use the preceding timing specification of the same name.
2
The falling edge of MSx, SW, BMS is referenced.
3
ACK delay/setup: User must meet t
DAAK
or t
DSAK
or synchronous specification t
SAKC
for deassertion of ACK (low), all three specifications must be met for assertion of ACK
(high).
4
See Example System Hold Time Calculation on Page 43 for calculation of hold times given capacitive and dc loads.
| WV“!
ADSP-21061/ADSP-21061L
Rev. D | Page 27 of 52 | May 2013
Figure 16. Synchronous Read/Write—Bus Master
CLKIN
ADDRCLK
ADDRESS,BMS,
SW,MSx
ACK
(IN)
PAGE
RD
DATA
(OUT)
WR
DATA (IN)
WRITE CYCLE
READ CYCLE
tDRWL
tHSDATI
tSSDATI
tDRDO
tDWRO
tDATTR
tSDDATO
tDRWL
tDADCCK
tADRCK
tADRCKL
tHADRO
tDPGC
tSACKC tHACK
tDADRO
tADRCKH
tDAAK
‘ACKTR w E\ SW 3 3 §\ §\ a 5‘ x \ x W ACK Disab‘e Afier CLK‘N r1rDT/8 érDT/S ns
Rev. D | Page 28 of 52 | May 2013
ADSP-21061/ADSP-21061L
Synchronous Read/Write—Bus Slave
Use these specifications for ADSP-21061 bus master accesses of
a slave’s IOP registers or internal memory (in multiprocessor
memory space). The bus master must meet these (bus slave)
timing requirements.
Table 15. Synchronous Read/Write—Bus Slave
5 V and 3.3 V
Unit
Parameter Min Max
Timing Requirements
t
SADRI
Address, SW Setup Before CLKIN 14 + DT/2 ns
t
HADRI
Address, SW Hold After CLKIN 5 + DT/2 ns
t
SRWLI
RD/WR Low Setup Before CLKIN
1
8.5 + 5DT/16 ns
t
HRWLI
RD/WR Low Hold After CLKIN
44 MHz/50 MHz
2
–4 – 5DT/16
–3.5 – 5DT/16
8 + 7DT/16
8 + 7DT/16
ns
t
RWHPI
RD/WR Pulse High 3 ns
t
SDATWH
Data Setup Before WR High 3 ns
t
HDATWH
Data Hold After WR High 1 ns
Switching Characteristics
t
SDDATO
Data Delay After CLKIN 19 + 5DT/16 ns
t
DATTR
Data Disable After CLKIN
3
0 – DT/8 7 – DT/8 ns
t
DACKAD
ACK Delay After Address, SW
4
8ns
t
ACKTR
ACK Disable After CLKIN
2
–1 – DT/8 6 – DT/8 ns
1
t
SRWLI
(min) = 9.5 + 5DT/16 when multiprocessor memory space wait state (MMSWS bit in WAIT register) is disabled; when MMSWS is enabled, t
SRWLI
(min)= 4 + DT/8.
2
This specification applies to the ADSP-21061LKS-176 (3.3 V, 44 MHz) and the ADSP-21061KS-200 (5 V, 50 MHz), operating at t
CK
< 25 ns. For all other devices, use the
preceding timing specification of the same name.
3
See Example System Hold Time Calculation on Page 43 for calculation of hold times given capacitive and dc loads.
4
t
DACKAD
is true only if the address and SW inputs have setup times (before CLKIN) greater than 10 + DT/8 and less than 19 + 3DT/4. If the address and inputs have setup
times greater than 19 + 3DT/4, then ACK is valid 14 + DT/4 (max) after CLKIN. A slave that sees an address with an M field match will respond with ACK regardless of
the state of MMSWS or strobes. A slave will three-state ACK every cycle with t
ACKTR
.
ADSP-21061/ADSP-21061L
Rev. D | Page 29 of 52 | May 2013
Figure 17. Synchronous Read/Write—Bus Slave
CLKIN
ADDRESS,SW
ACK
RD
DATA
(OU T)
WR
WRITE ACCESS
DATA
(IN)
READ ACCESS
tSADRI
tHADRI
tDACKAD tACKTR
tHRWLI
tSRWLI
tSDDATO tDATTR
tSRWLI tHRWLI
tHDATWH
tSDATWH
tRWHPI
tRWHPI
I m o a 5‘ 3: 3‘ QWWII >xxgg Q > 3% ‘ARDVTR REDYUVD] D‘sable (VomfiorWHigh
Rev. D | Page 30 of 52 | May 2013
ADSP-21061/ADSP-21061L
Multiprocessor Bus Request and Host Bus Request
Use these specifications for passing of bus mastership between
multiprocessing ADSP-21061s (BRx) or a host processor, both
synchronous and asynchronous (HBR, HBG).
Table 16. Multiprocessor Bus Request and Host Bus Request
5 V and 3.3 V
Unit
Parameter Min Max
Timing Requirements
t
HBGRCSV
HBG Low to RD/WR/CS Valid
1
20 + 5DT/4 ns
t
SHBRI
HBR Setup Before CLKIN
2
20 + 3DT/4 ns
t
HHBRI
HBR Hold After CLKIN
2
14 + 3DT/4 ns
t
SHBGI
HBG Setup Before CLKIN 13 + DT/2 ns
t
HHBGI
HBG Hold After CLKIN High 6 + DT/2 ns
t
SBRI
BRx, CPA Setup Before CLKIN
3
13 + DT/2 ns
t
HBRI
BRx, CPA Hold After CLKIN High 6 + DT/2 ns
t
SRPBAI
RPBA Setup Before CLKIN 20 + 3DT/4 ns
t
HRPBAI
RPBA Hold After CLKIN 12 + 3DT/4 ns
Switching Characteristics
t
DHBGO
HBG Delay After CLKIN 7 – DT/8 ns
t
HHBGO
HBG Hold After CLKIN –2 – DT/8 ns
t
DBRO
BRx Delay After CLKIN 5.5 – DT/8 ns
t
HBRO
BRx Hold After CLKIN –2 – DT/8 ns
t
DCPAO
CPA Low Delay After CLKIN
4
6.5 – DT/8 ns
t
TRCPA
CPA Disable After CLKIN –2 – DT/8 4.5 – DT/8 ns
t
DRDYCS
REDY (O/D) or (A/D) Low from CS and HBR Low
5,
6
8ns
t
TRDYHG
REDY (O/D) Disable or REDY (A/D) High from HBG
5,
7
44 + 27DT/16 ns
t
ARDYTR
REDY (A/D) Disable from CS or HBR High
5
10 ns
1
For first asynchronous access after HBR and CS asserted, ADDR31-0 must be a non-MMS value 1/2 t
CK
before RD or WR goes low or by t
HBGRCSV
after HBG goes low. This is
easily accomplished by driving an upper address signal high when HBG is asserted. See the “Host Processor Control of the ADSP-21061” section in the ADSP-2106x SHARC
User’s Manual.
2
Only required for recognition in the current cycle.
3
CPA assertion must meet the setup to CLKIN; deassertion does not need to meet the setup to CLKIN.
4
For the ADSP-21061L (3.3 V), this specification is 8.5 – DT/8 ns max.
5
(O/D) = open drain, (A/D) = active drive.
6
For the ADSP-21061L (3.3 V), this specification is 12 ns max.
7
For the ADSP-21061L (3.3 V), this specification is 40 + 23DT/16 ns min.
ADSP-21061/ADSP-21061L
Rev. D | Page 31 of 52 | May 2013
Figure 18. Multiprocessor Bus Request and Host Bus Request
B
Rx,CPA (IN, O/D)
HBR
CS
RPBA
RE DY
(O/D)
REDY
(A/D)
HBG (OUT)
RD
WR
CS
O/D = OPEN-DRAIN, A/ D = ACTIVE DRIVE
tSRPBAI
HBG (I N)
CLKIN
HBR
HBG (OUT)
BRx (OUT)
CP A (OUT, O/D)
tHHBGO
tHBRO
tTRCPA
tHRPBAI
t
HBRI
tSBRI
tSHBGI
tHHBGI
tDCPAO
tDBRO
tDHBGO
tHHBRI
tSHBRI
tDRDYCStTRDYHG
tHBGRCSV
tARDYTR
E W G W W W W W W tHnARWH Data Disab‘e Aherfi High 2 8 M E W E W 7R W W W T W W rm rm 6 gm“ REDV (O/D) or (A/D) Disable m CLK‘N 1 + 7DT/16 8+ 7DT/16 ns
Rev. D | Page 32 of 52 | May 2013
ADSP-21061/ADSP-21061L
Asynchronous Read/Write—Host to ADSP-21061
Use these specifications for asynchronous host processor
accesses of an ADSP-21061, after the host has asserted CS and
HBR (low). After HBG is returned by the ADSP-21061, the host
can drive the RD and WR pins to access the ADSP-21061’s
internal memory or IOP registers. HBR and HBG are assumed
low for this timing.
Table 17. Read Cycle
5 V and 3.3 V
Unit
Parameter Min Max
Timing Requirements
t
SADRDL
Address Setup/CS Low Before RD Low
1
0ns
t
HADRDH
Address Hold/CS Hold Low After RD 0ns
t
WRWH
RD/WR High Width 6 ns
t
DRDHRDY
RD High Delay After REDY (O/D) Disable 0 ns
t
DRDHRDY
RD High Delay After REDY (A/D) Disable 0 ns
Switching Characteristics
t
SDATRDY
Data Valid Before REDY Disable from Low 2 ns
t
DRDYRDL
REDY (O/D) or (A/D) Low Delay After RD Low
2
10 ns
t
RDYPRD
REDY (O/D) or (A/D) Low Pulsewidth for Read 45 + DT ns
t
HDARWH
Data Disable After RD High 2 8 ns
1
Not required if RD and address are valid t
HBGRCSV
after HBG goes low. For first access after HBR asserted, ADDR31-0 must be a non-MMS value 1/2 t
CLK
before RD or WR goes
low or by t
HBGRCSV
after HBG goes low. This is easily accomplished by driving an upper address signal high when HBG is asserted. See the “Host Processor Control of the
ADSP-21061” section in the ADSP-2106x SHARC User’s Manual.
2
For the ADSP-21061L (3.3 V), this specification is 13.5 ns max.
Table 18. Write Cycle
5 V and 3.3 V
Unit
Parameter Min Max
Timing Requirements
t
SCSWRL
CS Low Setup Before WR Low 0 ns
t
HCSWRH
CS Low Hold After WR High 0 ns
t
SADWRH
Address Setup Before WR High 5 ns
t
HADWRH
Address Hold After WR High 2 ns
t
WWRL
WR Low Width 8 ns
t
WRWH
RD/WR High Width 6 ns
t
DWRHRDY
WR High Delay After REDY (O/D) or (A/D) Disable 0 ns
t
SDATWH
Data Setup Before WR High
50 MHz, t
CK
= 20 ns
1
3
2.5
ns
t
HDATWH
Data Hold After WR High 1 ns
Switching Characteristics
t
DRDYWRL
REDY (O/D) or (A/D) Low Delay After WR/CS Low
2
11 ns
t
RDYPWR
REDY (O/D) or (A/D) Low Pulsewidth for Write 15 ns
t
SRDYCK
REDY (O/D) or (A/D) Disable to CLKIN 1 + 7DT/16 8 + 7DT/16 ns
1
This specification applies to the ADSP-21061KS-200 (5 V, 50 MHz) operating at t
CK
< 25 ns. For all other devices, use the preceding timing specification of the same name.
2
For the ADSP-21061L (3.3 V), this specification is 13.5 ns max.
ADSP-21061/ADSP-21061L
Rev. D | Page 33 of 52 | May 2013
Figure 19. Synchronous REDY Timing
Figure 20. Asynchronous Read/Write—Host to ADSP-21061
CL K I N
REDY (O/D)
O/D = OPEN-DRAIN, A/D = ACTIVE DRIVE
tSRDYCK
REDY (A/D)
tSADRDL
REDY (O/D)
RD
tDRDYRDL
tWRWH
tHADRDH
tHDARWH
tRD YPRD
tDRDHRDY
tSDAT R D Y
READ CYCLE
ADDRESS/CS
DATA (OUT)
REDY (A/D)
O/D = OPEN-DRAIN, A/D = ACT IVE DRIVE
tSDATWH
tHDATWH
tWW RL
RE DY ( O/D )
WR
tDRDYWRL
tWRWH
tHADWRH
tRDYPW R tDWRHRDY
WRITE CYCLE
tSADW RH
DA T A ( I N )
ADDRESS
REDY (A/D)
tSCSWRL
CS
tHCSWRH
‘MENHBG mm mm mm 56 I re HBG Memory \nterface Enab‘e AheriHBG High 19+DT ns
Rev. D | Page 34 of 52 | May 2013
ADSP-21061/ADSP-21061L
Three-State Timing—Bus Master, Bus Slave, HBR, SBTS
These specifications show how the memory interface is disabled
(stops driving) or enabled (resumes driving) relative to CLKIN
and the SBTS pin. This timing is applicable to bus master transi-
tion cycles (BTC) and host transition cycles (HTC) as well as the
SBTS pin.
Table 19. Three-State Timing—Bus Master, Bus Slave
5 V and 3.3 V
Unit
Parameter Min Max
Timing Requirements
t
STSCK
SBTS Setup Before CLKIN 12 + DT/2 ns
t
HTSCK
SBTS Hold Before CLKIN 6 + DT/2 ns
Switching Characteristics
t
MIENA
Address/Select Enable After CLKIN –1 – DT/8 ns
t
MIENS
Strobes Enable After CLKIN
1
–1.5 – DT/8 ns
t
MIENHG
HBG Enable After CLKIN –1.5 – DT/8 ns
t
MITRA
Address/Select Disable After CLKIN 0 – DT/4 ns
t
MITRS
Strobes Disable After CLKIN
1
1.5 – DT/4 ns
t
MITRHG
HBG Disable After CLKIN 2.0 – DT/4 ns
t
DATEN
Data Enable After CLKIN
2
9 + 5DT/16 ns
t
DATTR
Data Disable After CLKIN
2
0 – DT/8 7 – DT/8 ns
t
ACKEN
ACK Enable After CLKIN
2
7.5 + DT/4 ns
t
ACKTR
ACK Disable After CLKIN
2
–1 – DT/8 6 – DT/8 ns
t
ADCEN
ADRCLK Enable After CLKIN –2 – DT/8 ns
t
ADCTR
ADRCLK Disable After CLKIN 8 – DT/4 ns
t
MTRHBG
Memory Interface Disable Before HBG Low
3
0 + DT/8 ns
t
MENHBG
Memory Interface Enable After HBG High
3
19 + DT ns
1
Strobes = RD, WR, PAGE, DMAGx, MSx, BMS, SW.
2
In addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write.
3
Memory Interface = Address, RD, WR, MSx, SW, PAGE, DMAGx, and BMS (in EPROM boot mode).
Figure 21. Three-State Timing (Bus Transition Cycle, SBTS Assertion)
CLKIN
SBTS
ACK
CLKOUT
DATA
MEMORY
INTERFACE
tMITRA, tMITRS,tMITRHG
tSTSCK
tHTSCK
tDATTR
tDATEN
tACKTR
tACKEN
tADCTR
tADCEN
tMIENA, tMIENS,tMIENHG
ADSP-21061/ADSP-21061L
Rev. D | Page 35 of 52 | May 2013
Figure 22. Three-State Timing (Bus Transition Cycle, SBTS Assertion)
MEMORY
INTERFACE
HBG
MEMORY INTERFACE = ADDRESS,RD,WR,MSx,SW,PAGE,DMAGx.BMS (IN EPROM BOOT MODE)
tMENHBG
tMTRHBG
DMARX W W m m m DMARX DMARX DMAGX DMAGX DMAGX DMAGX m rm T m W W W re m E m E m E rem W W W m m mum Address/Select Hold after DMAGX ngh 70.5 ns CK HI = 1(K «data bus idle cycle occurs, as specmed ‘m WAIT register; mherwise HI: 0).
Rev. D | Page 36 of 52 | May 2013
ADSP-21061/ADSP-21061L
DMA Handshake
These specifications describe the three DMA handshake modes.
In all three modes, DMARx is used to initiate transfers. For
Handshake mode, DMAGx controls the latching or enabling of
data externally. For External Handshake mode, the data transfer
is controlled by the ADDR31–0, RD, WR, SW, PAGE, MS3–0,
ACK, and DMAGx signals. For Paced Master mode, the data
transfer is controlled by ADDR31–0, RD, WR, MS3–0, and
ACK (not DMAG). For Paced Master mode, the Memory Read-
Bus Master, Memory Write-Bus Master, and Synchronous
Read/Write-Bus Master timing specifications for ADDR31–0,
RD, WR, MS3–0, SW, PAGE, DATA47–0, and ACK also apply.
Table 20. DMA Handshake
5 V and 3.3 V
Unit
Parameter Min Max
Timing Requirements
t
SDRLC
DMARx Low Setup Before CLKIN
1
5ns
t
SDRHC
DMARx High Setup Before CLKIN
1
5ns
t
WDR
DMARx Width Low (Nonsynchronous) 6 ns
t
SDATDGL
Data Setup After DMAGx Low
2
10 + 5DT/8 ns
t
HDATIDG
Data Hold After DMAGx High 2 ns
t
DATDRH
Data Valid After DMARx High
2
16 + 7DT/8 ns
t
DMARLL
DMARx Low Edge to Low Edge
3
23 + 7DT/8 ns
t
DMARH
DMARx Width High 6 ns
Switching Characteristics
t
DDGL
DMAGx Low Delay After CLKIN 9 + DT/4 15 + DT/4 ns
t
WDGH
DMAGx High Width 6 + 3DT/8 ns
t
WDGL
DMAGx Low Width 12 + 5DT/8 ns
t
HDGC
DMAGx High Delay After CLKIN –2 – DT/8 6 – DT/8 ns
t
VDATDGH
Data Valid Before DMAGx High
4
8 + 9DT/16 ns
t
DATRDGH
Data Disable After DMAGx High
5
07ns
t
DGWRL
WR Low Before DMAGx Low 0 2 ns
t
DGWRH
DMAGx Low Before WR High 10 + 5DT/8 +W ns
t
DGWRR
WR High Before DMAGx High 1 + DT/16 3 + DT/16 ns
t
DGRDL
RD Low Before DMAGx Low 0 2 ns
t
DRDGH
RD Low Before DMAGx High 11 + 9DT/16 + W ns
t
DGRDR
RD High Before DMAGx High 0 3 ns
t
DGWR
DMAGx High to WR, RD, DMAGx Low 5 + 3DT/8 + HI ns
t
DADGH
Address/Select Valid to DMAGx High 17 + DT ns
t
DDGHA
Address/Select Hold after DMAGx High
6
–0.5 ns
W = (number of wait states specified in WAIT register) t
CK
.
HI = t
CK
(if data bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
1
Only required for recognition in the current cycle.
2
t
SDATDGL
is the data setup requirement if DMARx is not being used to hold off completion of a write. Otherwise, if DMARx low holds off completion of the write, the data can
be driven t
DATDRH
after DMARx is brought high.
3
For the ADSP-21061L (3.3 V), this specification is 23.5 + 7DT/8 ns min.
4
t
VDATDGH
is valid if DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then t
VDATDGH
=t
CK
– .25t
CCLK
–8+(n×t
CK
) where n equals
the number of extra cycles that the access is prolonged.
5
See Example System Hold Time Calculation on Page 43 for calculation of hold times given capacitive and dc loads.
6
For the ADSP-21061L (3.3 V), this specification is –1.0 ns min.
ADSP-21061/ADSP-21061L
Rev. D | Page 37 of 52 | May 2013
Figure 23. DMA Handshake
CLKIN
tSDRLC
DMARx
DATA
DATA
RD
WR
tWDR
tSDRHC
tDMARH
tDMARLL
tHDGC
tWDGH
tDDGL
DMAGx
tVDATDGH
tDATDRH
tDATRDGH
tHDATIDG
tDGWRL tDGWRH tDGWRR
tDGRDL
tDRDGH
tDGRDR
tSDATDGL
*MEMORY READ BUSMASTER, MEMORY WRITE BUSMASTER, OR SYNCHRONOUSREAD/WRITE BUSMASTER
TIMING SPECIFICATIONSFOR ADDR31–0, RD,WR,SW MS3–0,ANDACKALSO APPLY HERE.
(EXTERNAL DEVICE TO EXTERNAL MEMORY)
(EXTERNAL MEMORY TO EXTERNAL DEVICE)
TRANSFERSBETWEEN ADSP-2106x
INTERNAL MEMORY AND EXTERNAL DEVICE
TRANSFERSBETWEEN EXTERNAL DEVICE AND
EXTERNAL MEMORY* (EXTERNAL HANDSHAKE MODE)
tDDGHA
ADDR
MSx, SW
tDADGH
tWDGL
(FROM EXTERNAL DEVICE TO ADSP-2106x)
(FROM ADSP-2106x TO EXTERNAL DEVICE)
tsm TCLK/RCLK Penod t“ n5 mum Re(ewe Data Hold After RCLK 3 n5 twsg RFS Hold After RCLK (Internauy Generated RFS] 3 n5 tHomE Transmit Data Hold AlterTCLK 5 n5
Rev. D | Page 38 of 52 | May 2013
ADSP-21061/ADSP-21061L
Serial Ports
To determine whether communication is possible between two
devices at clock speed n, the following specifications must be
confirmed: 1) frame sync delay and frame sync setup and hold,
2) data delay and data setup and hold, and 3) SCLK width.
Table 21. Serial Ports—External Clock
Parameter
5 V and 3.3 V
Unit
Min Max
Timing Requirements
t
SFSE
TFS/RFS Setup Before TCLK/RCLK
1
3.5 ns
t
HFSE
TFS/RFS Hold After TCLK/RCLK
1,
2
4ns
t
SDRE
Receive Data Setup Before RCLK
1
1.5 ns
t
HDRE
Receive Data Hold After RCLK
1
4ns
t
SCLKW
TCLK/RCLK Width 9 ns
t
SCLK
TCLK/RCLK Period t
CK
ns
1
Referenced to sample edge.
2
RFS hold after RCK when MCE = 1, MFD = 0 is 0 ns minimum from drive edge. TFS hold after TCK for late external TFS is 0 ns minimum from drive edge.
Table 22. Serial Ports—Internal Clock
Parameter
5 V and 3.3 V
Unit
Min Max
Timing Requirements
t
SFSI
TFS Setup Before TCLK
1
; RFS Setup Before RCLK
1
8ns
t
HFSI
TFS/RFS Hold After TCLK/RCLK
1,
2
1ns
t
SDRI
Receive Data Setup Before RCLK
1
3ns
t
HDRI
Receive Data Hold After RCLK
1
3ns
1
Referenced to sample edge.
2
RFS hold after RCK when MCE = 1, MFD = 0 is 0 ns minimum from drive edge. TFS hold after TCK for late external TFS is 0 ns minimum from drive edge.
Table 23. Serial Ports—External or Internal Clock
Parameter
5 V and 3.3 V
Unit
Min Max
Switching Characteristics
t
DFSE
RFS Delay After RCLK (Internally Generated RFS)
1
13 ns
t
HOFSE
RFS Hold After RCLK (Internally Generated RFS)
1
3ns
1
Referenced to drive edge.
Table 24. Serial Ports—External Clock
Parameter
5 V and 3.3 V
Unit
Min Max
Switching Characteristics
t
DFSE
TFS Delay After TCLK (Internally Generated TFS)
1
13 ns
t
HOFSE
TFS Hold After TCLK (Internally Generated TFS)
1
3ns
t
DDTE
Transmit Data Delay After TCLK
1
16 ns
t
HODTE
Transmit Data Hold After TCLK
1
5ns
1
Referenced to drive edge.
‘scww TCLK/RCLK Wwdth “(M/271.5 tm/zn 5 n5 tum SPORT Dwsable After CLK‘N 17 ns tDDTENg Dam Enable from Lam FSor MCE: 1,MFD:0 3.5 n;
ADSP-21061/ADSP-21061L
Rev. D | Page 39 of 52 | May 2013
Table 25. Serial Ports—Internal Clock
Parameter
5 V and 3.3 V
Unit
Min Max
Switching Characteristics
t
DFSI
TFS Delay After TCLK (Internally Generated TFS)
1
4.5 ns
t
HOFSI
TFS Hold After TCLK (Internally Generated TFS)
1
–1.5 ns
t
DDTI
Transmit Data Delay After TCLK
1
7.5 ns
t
HDTI
Transmit Data Hold After TCLK
1
0ns
t
SCLKIW
TCLK/RCLK Width t
SCLK
/2 –1.5 t
SCLK
/2+1.5 ns
1
Referenced to drive edge.
Table 26. Serial Ports—Enable and Three-State
Parameter
5 V and 3.3 V
Unit
Min Max
Switching Characteristics
t
DDTEN
Data Enable from External TCLK
1, 2
4.5 ns
t
DDTTE
Data Disable from External TCLK
1
10.5 ns
t
DDTIN
Data Enable from Internal TCLK
1
0ns
t
DDTTI
Data Disable from Internal TCLK
1
3ns
t
DCLK
TCLK/RCLK Delay from CLKIN 22 + 3DT/8 ns
t
DPTR
SPORT Disable After CLKIN 17 ns
1
Referenced to drive edge.
2
For the ADSP-21061L (3.3 V), this specification is 3.5 ns min.
Table 27. Serial Ports—External Late Frame Sync
Parameter
5 V and 3.3 V
Unit
Min Max
Switching Characteristics
t
DDTLFSE
Data Delay from Late External TFS or External RFS with MCE = 1, MFD = 0
1
12 ns
t
DDTENFS
Data Enable from Late FS or MCE = 1, MFD = 0
1
3.5 ns
1
MCE = 1, TFS enable and TFS valid follow t
DDTLFSE
and t
DDTENFS
.
Rev. D | Page 40 of 52 | May 2013
ADSP-21061/ADSP-21061L
Figure 24. Serial Ports
DT
DT
DRIVE EDGE DRIVE EDGE
DRIVE
EDGE
DRIVE
EDGE
TCLK/RCLK
TCLK
(INT)
TCLK/RCLK
TCLK
(EXT)
RCLK
RFS
DR
DRIVE
EDGE
SAMPLE
EDGE
DATA RECEIVE— INTERNAL CLOCK DATA RECEIVE— EXTERNAL CLOCK
RCLK
RFS
DR
DRIVE
EDGE
SAMPLE
EDGE
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED ASTHE ACTIVE SAMPLING EDGE.
TCLK
TFS
DT
DRIVE
EDGE
SAMPLE
EDGE
TCLK
TFS
DT
DRIVE
EDGE
SAMPLE
EDGE
DATA TRANSMIT— INTERNAL CLOCK DATA TRANSMIT— EXTERNAL CLOCK
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED ASTHE ACTIVE SAMPLING EDGE.
tDDTTE
tDDTEN
tDDTTI
tDDTIN
tSDRI tHDRI
tSFSItHFSI
tDFSE
tHOFSE
tSCLKIW
tSDRE tHDRE
tSFSEtHFSE
tDFSE
tSCLKW
tHOFSE
tDDTI
tHDTI
tSFSItHFSI
tSCLKIW
tDFSI
tHOFSI
tDDTE
tHDTE
tSFSEtHFSE
tDFSE
tSCLKW
tHOFSE
CLKIN
tDPTR
SPORT DISABLE DELAY
FROM INSTRUCTION
TCLK, RCLK
TFS,RFS,DT
TCLK (INT)
RCLK (INT)
SPORT ENABLE AND
THREE-STATE
LATENCY
ISTWO CYCLES
tDCLK
LOW TO HIGH ONLY
tSTFSCK
CLKIN tHTFSCK
NOTE: APPLIESONLY TO GATED SERIAL CLOCK MODE WITH
EXTERNAL TFS,ASUSED IN THE SERIAL PORT SYSTEM I/O
FOR MESHMULTIPROCESSING.
TFS(EXT)
k IHI U
ADSP-21061/ADSP-21061L
Rev. D | Page 41 of 52 | May 2013
Figure 25. Serial Ports—External Late Frame Sync
DRIVE SAMPLE DRIVE
TCLK
TFS
DT
DRIVE SAMPLE DRIVE
LATE EXTERNAL TFS
EXTERNAL RFS WITH MCE = 1, MFD = 0
1ST BIT 2ND BITDT
RCLK
RFS
1ST BIT 2ND BIT
t
HOFSE/I
t
SFSE/I
t
DDTE/I
t
DDTENFS
t
DDTLFSE
t
HDTE/I
t
HOFSE/I
t
SFSE/I
t
DDTE/I
t
DDTLFSE
t
HDTE/I
t
DDTENFS
TRST mm System Outputs Delay AfterTCK Low ns
Rev. D | Page 42 of 52 | May 2013
ADSP-21061/ADSP-21061L
JTAG Test Access Port and Emulation
For JTAG Test Access Port and Emulation, see Table 28 and
Figure 26.
Table 28. JTAG Test Access Port and Emulation
Parameter
5 V and 3.3 V
Unit
Min Max
Timing Requirements
t
TCK
TCK Period t
CK
ns
t
STAP
TDI, TMS Setup Before TCK High t
CK
ns
t
HTAP
TDI, TMS Hold After TCK High 6 ns
t
SSYS
System Inputs Setup Before TCK Low
1
7ns
t
HSYS
System Inputs Hold After TCK Low
1
18 ns
t
TRSTW
TRST Pulse Width 4t
CK
ns
Switching Characteristics
t
DTDO
TDO Delay from TCK Low 13 ns
t
DSYS
System Outputs Delay After TCK Low
2
18.5 ns
1
System Inputs = DATA47–0, ADDR31–0, RD, WR, ACK, SBTS, HBR, HBG, CS, DMAR1, DMAR2, BR6–1, ID2–0, RPBA, IRQ2–0, FLAG3–0, CPA, DR0, DR1, TCLK0,
TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, EBOOT, LBOOT, BMS, CLKIN, RESET.
2
System Outputs = DATA47–0, ADDR31–0, MS3–0, RD, WR, SW, ACK, ADRCLK, CLKOUT, HBG, REDY, DMAG1, DMAG2, BR6–1, CPA, FLAG3–0, TIMEXP, DT0, DT1,
TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, BMS.
Figure 26. JTAG Test Access Port and Emulation
TCK
TMS
TDI
TDO
SYSTEM
INPUTS
SYSTEM
OUTPUTS
tSTAP
tTCK
tHTAP
tDTDO
tSSYStHSYS
tDSYS
ADSP-21061/ADSP-21061L
Rev. D | Page 43 of 52 | May 2013
TEST CONDITIONS
Output Disable Time
Output pins are considered to be disabled when they stop driv-
ing, go into a high impedance state, and start to decay from their
output high or low voltage. The time for the voltage on the bus
to decay by V is dependent on the capacitive load, C
L
, and the
load current, I
L
. This decay time can be approximated by the
following equation:
The output disable time t
DIS
is the difference between
t
MEASURED
and t
DECAY
as shown in Figure 27. The time t
MEASURED
is
the interval from when the reference signal switches to when the
output voltage decays V from the measured output high or
output low voltage. t
DECAY
is calculated with test loads C
L
and I
L
,
and with V equal to 0.5 V.
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to when they start driv-
ing. The output enable time t
ENA
is the interval from when a
reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in the Output Enable/Disable diagram (Figure 27). If multiple
pins (such as the data bus) are enabled, the measurement value
is that of the first pin to start driving.
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate t
DECAY
using the equation given above. Choose V
to be the difference between the ADSP-21061’s output voltage
and the input threshold for the device requiring the hold time. A
typical V will be 0.4 V. C
L
is the total bus capacitance (per data
line), and I
L
is the total leakage or three-state current (per data
line). The hold time will be t
DECAY
plus the minimum disable
time (i.e., t
DATRWH
for the write cycle).
Output Drive Characteristics
Figure 30 through Figure 37 show typical characteristics for the
output drivers of the ADSP-21061 (5 V) and ADSP-21061L
(3 V). The curves represent the current drive capability and
switching behavior of the output drivers as a function of
resistive and capacitive loading.
Capacitive Loading
Output delays and holds are based on standard capacitive loads:
50 pF on all pins (see Figure 28). The delay and hold specifica-
tions given should be derated by a factor of 1.5 ns/50 pF for
loads other than the nominal value of 50 pF. Figure 31,
Figure 32, Figure 35, and Figure 36 show how output rise time
varies with capacitance. Figure 33 and Figure 37 show graphi-
cally how output delays and holds vary with load capacitance.
(Note that this graph or derating does not apply to output dis-
able delays; see the previous section Output Disable Time under
Test Conditions.) The graphs of Figure 31, Figure 32, Figure 35,
and Figure 36 may not be linear outside the ranges shown.
Figure 27. Output Enable/Disable
PEXT
CLV
IL
---------------
=
REFERENCE
SIGNAL
tDIS
OUTPUT STARTS
DRIVING
VOH (MEASURED) -V
VOL (MEASURED) +V
tMEASURED
VOH (MEASURED)
VOL (MEASURED)
2.0V
1.0V
VOH (MEASURED)
VOL (MEASURED)
HIGH IMPEDANCE STATE.
TESTCONDITIONSCAUSE
THISVOLTAGE TO BE
APPROXIMATELY 1.5V.
OUTPUT STOPS
DRIVING
tENA
tDECAY
Figure 28. Equivalent Device Loading for AC Measurements (Includes All
Fixtures)
Figure 29. Voltage Reference Levels for AC Measurements (Except Output
Enable/Disable)
1.5V
50pF
TO
OUTPUT
PIN
IOL
IOH
INPUT
OR
OUTPUT 1.5V 1.5V
Rev. D | Page 44 of 52 | May 2013
ADSP-21061/ADSP-21061L
Output Characteristics (5 V)
Figure 30. Typical Output Drive Currents (V
DD
= 5 V)
Figure 31. Typical Output Rise Time (10% to 90% V
DD
) vs. Load Capacitance
(V
DD
= 5 V)
SOURCE VOLTAGE (V)
-
75
-
15005.25
SOURCECURRENT(mA)
0.75 1.50 2.25 3.00 3.75 4.50
75
-
50
-
100
-
125
25
-
25
50
0
4.75V, +100°C
4.75V,+ 100°C
5.0V, +25°C
5.25V,
-
40°C
5.0V, +25°C
5.25V,
-
40°C
LOAD CAPACITANCE (pF)
16.0
8.0
0020020 40 60 80 100 120 140 160 180
14.0
12.0
4.0
2.0
10.0
6.0
FALL TIM E
RISETIME
RISEANDFALLTIMES(ns)
(0.5Vto4.5V
,10%to90%)
Y = 0.005x + 3.7
Y = 0.0031x + 1.1
Figure 32. Typical Output Rise Time (0.8 V to 2.0 V) vs. Load Capacitance
(V
DD
= 5 V)
Figure 33. Typical Output Delay or Hold vs. Load Capacitance (at Maximum
Case Temperature) (V
DD
= 5 V)
3.5
0
RISEANDFALLTIMES(ns)(0.8Vto2.0V)
3.0
2.5
2.0
1.5
1.0
0.5
LOAD CAPACITANCE (pF)
020020 40 60 80 100 120 140 160 180
FALL TIME
RISETIME
Y = 0.009x + 1.1
Y = 0.005x + 0.6
LOAD CAPACITANCE (pF)
OUTPUTDELAYORHOLD(ns)
5
-
1
25 20050 75 100 125 150 175
4
3
2
1
NOMINAL
Y=0.03X
-
1.45
ADSP-21061/ADSP-21061L
Rev. D | Page 45 of 52 | May 2013
Input/Output Characteristics (3.3 V)
Figure 34. Typical Drive Currents (V
DD
= 3.3 V)
Figure 35. Typical Output Rise Time (10% to 90% V
DD
) vs. Load Capacitance
(V
DD
= 3.3 V)
SOURCE VOLTAGE (V)
120
-
20
-
80
03.5
SOURCECURRENT(mA)
0.5 1.0 1.5 2.0 2.5 3.0
100
0
-
40
-
60
60
20
80
40
-
100
-
120
3.0V, +85°C
3.3V, + 2 5 ° C
3.6V,
-
40°C
3.6V,
-
40°C
3.3V, + 25 ° C
3.0V, +85°C VOH
VOL
LOAD CAPACITANCE (pF)
0
2
0
20 40 60 80100120
Y = 0.0796x + 1.17
Y = 0.0467x + 0.55
RISETIME
FALL TIME
140 160 180200
4
6
8
10
12
14
16
18
RISEANDFALLTIMES(ns)(10%to90%)
Figure 36. Typical Output Rise Time (0.8 V to 2.0 V) vs. Load Capacitance
(V
DD
= 3.3 V)
Figure 37. Typical Output Delay or Hold vs. Load Capacitance (at Maximum
Case Temperature) (V
DD
= 3.3 V)
LOAD CAPACITANCE (pF)
0
020 40 60 80 100 120
Y=0.0391x + 0.36
Y=0.0305x + 0.24
RISETIME
FALL TIME
140 160 180200
RISEANDFALLTIMES(ns)(0.8Vto2.0V)
1
2
3
4
5
6
7
8
9
LOAD CAPACITANCE (pF)
OUTPUTDELAYORHOLD(ns)
5
-
125 20050 75 100 125 150 175
4
3
2
1
NOMINAL
Y=0.0329x
-
1.65
AIrflow : 0 1 100 9 Airflow : 200 S Airflo 400 7 Airflow : 600 6 0 19 6 100 17 6 Airflow : 200 15 6 Airflo 400 13 9 Airflow:600 122 19 0 13 6 11 Z
Rev. D | Page 46 of 52 | May 2013
ADSP-21061/ADSP-21061L
ENVIRONMENTAL CONDITIONS
Thermal Characteristics
The ADSP-21061 is available in 240-lead thermally enhanced
MQFP package. The top surface of the thermally enhanced
MQFP contains a metal slug from which most of the die heat is
dissipated. The slug is flush with the top surface of the package.
Note that the metal slug is internally connected to GND
through the device substrate.
The ADSP-21061L is available in 240-lead MQFP and 225-ball
plastic BGA packages.
All packages are specified for a case temperature (T
CASE
). To
ensure that the T
CASE
is not exceeded, a heatsink and/or an air-
flow source may be used. A heat sink should be attached with a
thermal adhesive.
T
CASE
= T
AMB
+ (PD
CA
)
T
CASE
= Case temperature (measured on top surface of package)
T
AMB
= Ambient temperature C
PD =Power dissipation in W (this value depends upon the spe-
cific application; a method for calculating PD is shown under
Power Dissipation).
CA
=Value from tables below.
Table 29. ADSP-21061 (5 V Thermally Enhanced ED/MQFP
Package)
Parameter Condition (Linear Ft./Min.) Typical Unit
CA
Airflow = 0
Airflow = 100
Airflow = 200
Airflow = 400
Airflow = 600
10
9
8
7
6
°C/W
Table 30. ADSP-21061L (3.3 V MQFP Package)
Parameter Condition (Linear Ft./Min.) Typical Unit
CA
Airflow = 0
Airflow = 100
Airflow = 200
Airflow = 400
Airflow = 600
19.6
17.6
15.6
13.9
12.2
°C/W
Table 31. ADSP-21061L (3.3 V PBGA Package)
Parameter Condition (Linear Ft./Min.) Typical Unit
CA
Airflow = 0
Airflow = 200
Airflow = 400
19.0
13.6
11.2
°C/W
B S E U DMARZ M52 1R 0 1R 1 DMAR1 W H56 3 DMAGZ W W W DAT/M2 A15 DATA34 D15 DATA23 G15 DATA1 4 K15 DATAS N15 M50 TRST W W W W W DATA39 B15 DATA31 E15 DATAZO H15 DATA10 L15 DATAO P15 53 S1 1R 2 RESET SETS W DMAG1 W DATA46 C12 DATAZQ F12 DATA12 J12 NC M12 NC R12
ADSP-21061/ADSP-21061L
Rev. D | Page 47 of 52 | May 2013
225-BALL PBGA PIN CONFIGURATIONS
Table 32. ADSP-21061L 225-Lead Metric PBGA (B-225-2) Pin Assignments
Pin
Name
PBGA
Pin Number
Pin
Name
PBGA
Pin Number
Pin
Name
PBGA
Pin Number
Pin
Name
PBGA
Pin Number
Pin
Name
PBGA
Pin Number
BMS A01 ADDR25 D01 ADDR14 G01 ADDR6 K01 EMU N01
ADDR30 A02 ADDR26 D02 ADDR15 G02 ADDR5 K02 TDO N02
DMAR2 A03 MS2 D03 ADDR16 G03 ADDR3 K03 IRQ0 N03
DT1 A04 ADDR29 D04 ADDR19 G04 ADDR0 K04 IRQ1 N04
RCLK1 A05 DMAR1 D05 GND G05 ICSA K05 ID2 N05
TCLK0 A06 TFS1 D06 V
DD
G06 GND K06 NC N06
RCLK0 A07 CPA D07 V
DD
G07 V
DD
K07 NC N07
ADRCLK A08 HBG D08 V
DD
G08 V
DD
K08 NC N08
CS A09 DMAG2 D09 V
DD
G09 V
DD
K09 NC N09
CLKIN A10 BR5 D10 V
DD
G10 GND K10 NC N10
PAGE A11 BR1 D11 GND G11 GND K11 NC N11
BR3 A12 DATA40 D12 DATA22 G12 DATA8 K12 NC N12
DATA47 A13 DATA37 D13 DATA25 G13 DATA11 K13 NC N13
DATA44 A14 DATA35 D14 DATA24 G14 DATA13 K14 DATA1 N14
DATA42 A15 DATA34 D15 DATA23 G15 DATA14 K15 DATA3 N15
MS0 B01 ADDR21 E01 ADDR12 H01 ADDR2 L01 TRST P01
SW B02 ADDR22 E02 ADDR11 H02 ADDR1 L02 TMS P02
ADDR31 B03 ADDR24 E03 ADDR13 H03 FLAG0 L03 EBOOT P03
HBR B04 ADDR27 E04 ADDR10 H04 FLAG3 L04 ID0 P04
DR1 B05 GND E05 GND H05 RPBA L05 NC P05
DT0 B06 GND E06 V
DD
H06 GND L06 NC P06
DR0 B07 GND E07 V
DD
H07 GND L07 NC P07
REDY B08 GND E08 V
DD
H08 GND L08 NC P08
RD B09 GND E09 V
DD
H09 GND L09 NC P09
ACK B10 GND E10 V
DD
H10 GND L10 NC P10
BR6 B11 NC E11 GND H11 NC L11 NC P11
BR2 B12 DATA33 E12 DATA18 H12 DATA4 L12 NC P12
DATA45 B13 DATA30 E13 DATA19 H13 DATA7 L13 NC P13
DATA43 B14 DATA32 E14 DATA21 H14 DATA9 L14 NC P14
DATA39 B15 DATA31 E15 DATA20 H15 DATA10 L15 DATA0 P15
MS3 C01 ADDR17 F01 ADDR9 J01 FLAG1 M01 TCK R01
MS1 C02 ADDR18 F02 ADDR8 J02 FLAG2 M02 IRQ2 R02
ADDR28 C03 ADDR20 F03 ADDR7 J03 TIMEXP M03 RESET R03
SBTS C04 ADDR23 F04 ADDR4 J04 TDI M04 ID1 R04
TCLK1 C05 GND F05 GND J05 LBOOT (GND) M05 NC R05
RFS1 C06 GND F06 V
DD
J06 NC M06 NC R06
TFS0 C07 V
DD
F07 V
DD
J07 NC M07 NC R07
RFS0 C08 V
DD
F08 V
DD
J08 NC M08 NC R08
WR C09 V
DD
F09 V
DD
J09 NC M09 NC R09
DMAG1 C10 GND F10 V
DD
J10 NC M10 NC R10
BR4 C11 GND F11 GND J11 NC M11 NC R11
DATA46 C12 DATA29 F12 DATA12 J12 NC M12 NC R12
DATA36 C15 DATA27 F15 DATA1 7 J15 DATA6 M15 NC R15
Rev. D | Page 48 of 52 | May 2013
ADSP-21061/ADSP-21061L
DATA41 C13 DATA26 F13 DATA15 J13 DATA2 M13 NC R13
DATA38 C14 DATA28 F14 DATA16 J14 DATA5 M14 NC R14
DATA36 C15 DATA27 F15 DATA17 J15 DATA6 M15 NC R15
Figure 38. BGA Pin Assignments (Top View, Summary)
Table 32. ADSP-21061L 225-Lead Metric PBGA (B-225-2) Pin Assignments (Continued)
Pin
Name
PBGA
Pin Number
Pin
Name
PBGA
Pin Number
Pin
Name
PBGA
Pin Number
Pin
Name
PBGA
Pin Number
Pin
Name
PBGA
Pin Number
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
ADRCLK BMS
ADDR30
DMAR2
DT1RCLK1TCLK0RCLK0
CS
CLKINPAGE
BR3
DATA47DATA44DATA42
MS0SW
ADDR31
HBR
DR1DT0DR0REDY
RD
ACK
BR6BR2
DATA45DATA43DATA39
MS3MS1
ADDR28
SBTS
TCLK1RFS1TFS0RFS0
WRDMAG1BR4
DATA46DATA41DATA38DATA36
ADDR25ADDR26
MS2
ADDR29
DMAR1
TFS1
CPAHBGDMAG2BR5BR1
DATA40DATA37DATA35DATA34
ADDR21ADDR22ADDR24ADDR27GNDGNDGNDGNDGNDGNDNCDATA33DATA30DATA32DATA31
ADDR17ADDR18ADDR20ADDR23GNDGNDVDD
VDD
VDD
GNDGNDDATA29DATA26DATA28DATA27
ADDR14ADDR15ADDR16ADDR19GNDVDD
VDD
VDD
VDD
VDD
GNDDATA22DATA25DATA24DATA23
ADDR12ADDR11ADDR13ADDR10GNDVDD
VDD
VDD
VDD
VDD
GNDDATA18DATA19DATA21DATA20
ADDR9ADDR8ADDR7ADDR4GNDVDD
VDD
VDD
VDD
VDD
GNDDATA12DATA15DATA16DATA17
ADDR6ADDR5ADDR3ADDR0ICSAGNDVDD
VDD
VDD
GNDGNDDATA8DATA11DATA13DATA14
ADDR2ADDR1FLAG0FLAG3RPBAGNDGNDGNDGNDGNDNCDATA4DATA7DATA9DATA10
FLAG1FLAG2TIMEXPTDI
LBOOT
(GND)
NCNC
NCNCNCNCNCDATA2DATA5
DATA6
EMU
TDO
IRQ1
ID2NCNCNCNCNCNCNCNCDATA1DATA3
TRST
TMSEBOOTID0NCNCNCNCNCNCNCNCNCNCDATA0
TCK
IRQ2RESET
ID1NCNCNCNCNC NC NC NC NC NC NC
NC = NO CONNECT
IRQ0
m c ADDR19 40 m z D g‘g‘g‘ mmm 4N“: a”; é‘é‘a vv w m U E )> ‘ U i I w :2 DTO 80 I w a a a w wwwww xxxxx wau‘a‘ w 3: GND 120 VDD 160 NC 200 240
ADSP-21061/ADSP-21061L
Rev. D | Page 49 of 52 | May 2013
240-LEAD MQFP PIN CONFIGURATIONS
Table 33. ADSP-21061 MQFP/ED (SP-240); ADSP-21061L MQFP (S-240) Pin Assignments
Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No.
TDI 1 ADDR20 41 TCLK0 81 DATA41 121 DATA14 161 NC 201
TRST 2 ADDR21 42 TFS0 82 DATA40 122 DATA13 162 NC 202
V
DD
3GND43 DR0 83 DATA39 123 DATA12 163 NC 203
TDO 4 ADDR22 44 RCLK0 84 V
DD
124 GND 164 NC 204
TIMEXP 5 ADDR23 45 RFS0 85 DATA38 125 DATA11 165 V
DD
205
EMU 6ADDR2446V
DD
86 DATA37 126 DATA10 166 NC 206
ICSA 7 V
DD
47 V
DD
87 DATA36 127 DATA9 167 NC 207
FLAG3 8 GND 48 GND 88 GND 128 V
DD
168 NC 208
FLAG2 9 V
DD
49 ADRCLK 89 NC 129 DATA8 169 NC 209
FLAG110ADDR2550REDY90DATA35130DATA7170NC 210
FLAG011ADDR2651HBG 91 DATA34 131 DATA6 171 NC 211
GND12ADDR2752CS 92 DATA33 132 GND 172 GND 212
ADDR0 13 GND 53 RD 93 V
DD
133 DATA5 173 NC 213
ADDR1 14 MS3 54 WR 94 V
DD
134 DATA4 174 NC 214
V
DD
15 MS2 55 GND 95 GND 135 DATA3 175 NC 215
ADDR2 16 MS1 56 V
DD
96 DATA32 136 V
DD
176 NC 216
ADDR3 17 MS0 57 GND 97 DATA31 137 DATA2 177 NC 217
ADDR4 18 SW 58 CLKIN 98 DATA30 138 DATA1 178 NC 218
GND 19 BMS 59 ACK 99 GND 139 DATA0 179 V
DD
219
ADDR520ADDR2860DMAG2
100 DATA29 140 GND 180 GND 220
ADDR6 21 GND 61 DMAG1 101 DATA28 141 GND 181 V
DD
221
ADDR7 22 V
DD
62 PAGE 102 DATA27 142 NC 182 NC 222
V
DD
23 V
DD
63 V
DD
103 V
DD
143 NC 183 NC 223
ADDR824ADDR2964BR6 104 V
DD
144 NC 184 NC 224
ADDR925ADDR3065BR5 105 DATA26 145 NC 185 NC 225
ADDR10 26 ADDR31 66 BR4 106 DATA25 146 NC 186 NC 226
GND 27 GND 67 BR3 107 DATA24 147 NC 187 NC 227
ADDR11 28 SBTS 68 BR2 108 GND 148 V
DD
188 GND 228
ADDR12 29 DMAR2 69 BR1 109 DATA23 149 NC 189 ID2 229
ADDR13 30 DMAR1 70 GND 110 DATA22 150 NC 190 ID1 230
V
DD
31 HBR 71 V
DD
111 DATA21 151 NC 191 ID0 231
ADDR14 32 DT1 72 GND 112 V
DD
152 NC 192 LBOOT (GND) 232
ADDR15 33 TCLK1 73 DATA47 113 DATA20 153 NC 193 RPBA 233
GND 34 TFS1 74 DATA46 114 DATA19 154 NC 194 RESET 234
ADDR16 35 DR1 75 DATA45 115 DATA18 155 GND 195 EBOOT 235
ADDR17 36 RCLK1 76 V
DD
116 GND 156 GND 196 IRQ2 236
ADDR18 37 RFS1 77 DATA44 117 DATA17 157 V
DD
197 IRQ1 237
V
DD
38 GND 78 DATA43 118 DATA16 158 NC 198 IRQ0 238
V
DD
39 CPA 79 DATA42 119 DATA15 159 NC 199 TCK 239
ADDR19 40 DT0 80 GND 120 V
DD
160 NC 200 TMS 240
: 50 :79 no: i wig 0' 25 I} ”SJ camnmw
Rev. D | Page 50 of 52 | May 2013
ADSP-21061/ADSP-21061L
OUTLINE DIMENSIONS
Figure 39. 240-Lead Metric Quad Flat Package, Thermally Enhanced [MQFP/ED] (SP-240-2)
0.66
0.56
0.46
4.10
3.78
3.55
SEATING
PLANE
VIEW A
0.38
0.25
0.20
0.09
0.076
COPLANARITY
3.50
3.40
3.30
VIEW A
ROTATED 90° CCW
1
240 181
180
121
120
61
60
PIN 1
HEAT SLUG
TOP VIEW
(PINS DOWN)
34.60 BSC
SQ
29.50 REF
SQ
32.00 BSC
SQ
3.92 × 45°
(4 PLACES)
24.00 REF
SQ
0.27 MAX
0.17 MIN
0.50
BSC
LEAD PITCH
250030003 0000025003 30000333 3333233 2333033 71
ADSP-21061/ADSP-21061L
Rev. D | Page 51 of 52 | May 2013
Figure 40. 240-Lead Metric Quad Flat Package, [MQFP] (S-240)
Figure 41. 225-Ball Plastic Ball Grid Array [PBGA] (B-225-2)
1
181042
180
121
12061
60
34.85
34.60 SQ
34.35
32.00 BSC
SQ
29.50
REF
SQ
SEATING
PLANE
4.10
MAX
0.75
0.60
0.45
0.50
0.25
3.50
3.40
3.20
0.27
0.17
0.50
BSC
0.08 MAX
COPLANARITY
PIN 1
2.70 MAX
1.27
BSC
18.00
BSC SQ
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
1514131211 10 9876542
31
TOP VIEW
1.30
1.20
1.10
0.15 MAX
COPLANARITY
0.70
0.60
0.50
DETAIL A
0.90
0.75
0.60
BALL DIAMETER
BOTTOM VIEW
DETAIL A
A1 CORNER
INDEX AREA
20.10
20.00 SQ
19.90
23.20
23.00 SQ
22.80
BALL A1
INDICATOR
0.50 R
3 PLACES
SEATING
PLANE
2253a“ Grid Array (PBGA) Solder Mask Defined 0 63 mm diame‘er 0.73 mm dwame‘er ADSP721061LKSZV176 0°C to 85 C 44MHZ 1M 81‘ 3.3 V 2407Lead MQFP 57240 ANALOG DEVICES www.ana|og.cnm
Rev. D | Page 52 of 52 | May 2013
ADSP-21061/ADSP-21061L
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00170-0-5/13(D)
SURFACE-MOUNT DESIGN
Table 34 is provided as an aide to PCB design. For industry-standard design recommendations, refer to IPC-7351, Generic Requirements
for Surface-Mount Design and Land Pattern Standard.
ORDERING GUIDE
Table 34. BGA Data for Use with Surface-Mount Design
Package Ball Attach Type Solder Mask Opening Ball Pad Size
225-Ball Grid Array (PBGA) Solder Mask Defined 0.63 mm diameter 0.73 mm diameter
Model Notes
Temperature
Range
Instruction
Rate
On-Chip
SRAM
Operating
Voltage Package Description
Package
Option
ADSP-21061KS-133 0C to 85C 33 MHz 1M Bit 5 V 240-Lead MQFP_ED SP-240-2
ADSP-21061KSZ-133
1
1
Z = RoHS Compliant Part.
0C to 85C 33 MHz 1M Bit 5 V 240-Lead MQFP_ED SP-240-2
ADSP-21061KS-160 0C to 85C 40 MHz 1M Bit 5 V 240-Lead MQFP_ED SP-240-2
ADSP-21061KSZ-160
1
0C to 85C 40 MHz 1M Bit 5 V 240-Lead MQFP_ED SP-240-2
ADSP-21061KS-200 0C to 85C 50 MHz 1M Bit 5 V 240-Lead MQFP_ED SP-240-2
ADSP-21061KSZ-200
1
0C to 85C 50 MHz 1M Bit 5 V 240-Lead MQFP_ED SP-240-2
ADSP-21061LKB-160 0C to 85C 40 MHz 1M Bit 3.3 V 225-Ball PBGA B-225-2
ADSP-21061LKBZ-160
1
0C to 85C 40 MHz 1M Bit 3.3 V 225-Ball PBGA B-225-2
ADSP-21061LKSZ-160
1
0C to 85C 40 MHz 1M Bit 3.3 V 240-Lead MQFP S-240
ADSP-21061LASZ-176
1
–40C to +85C 44 MHz 1M Bit 3.3 V 240-Lead MQFP S-240
ADSP-21061LKSZ-176
1
0C to 85C 44 MHz 1M Bit 3.3 V 240-Lead MQFP S-240

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