AD712 Datasheet by Analog Devices Inc.

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ANALOG DEVICES :“55 '9'.
Precision, Low Cost,
High Speed BiFET Dual Op Amp
Data Sheet AD712
Rev. I Document Feedback
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Tel: 781.329.4700 ©1986–2018 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
Enhanced replacement for LF412 and TL082
AC performance
Settles to ±0.01% in 1.0 μs
16 V/μs minimum slew rate (AD712J)
3 MHz minimum unity-gain bandwidth (AD712J)
DC performance
200 V/mV minimum open-loop gain (AD712K)
Surface mount available in tape and reel in
accordance with the EIA-481A standard
MIL-STD-883B parts available
Single version available: AD711
Quad version: AD713
Available in PDIP, SOIC_N, and CERDIP packages
CONNECTION DIAGRAM
8
7
6
5
1
2
3
4
OUTPUT V+
OUTPUT
V–
AD712
AMPLIFIER NO. 2
A
MPLIFIER NO. 1
INVERTING
INPUT
NONINVERTING
INPUT
INVERTING
INPUT
NONINVERTING
INPUT
00823-001
Figure 1. 8-Lead PDIP (N-Suffix),
SOIC_N (R-Suffix), and CERDIP (Q-Suffix)
GENERAL DESCRIPTION
The AD712 is a high speed, precision, monolithic operational
amplifier offering high performance at very modest prices. The
very low offset voltage and offset voltage drift are the results of
advanced laser wafer trimming technology. These performance
benefits allow the user to easily upgrade existing designs that
use older precision BiFETs and, in many cases, bipolar op amps.
The superior ac and dc performance of this op amp makes it
suitable for active filter applications. With a slew rate of 16 V/μs
and a settling time of 1 μs to ±0.01%, the AD712 is ideal as a
buffer for 12-bit digital-to-analog converters (DACs) and analog-
to-digital converters (ADCs) and as a high speed integrator.
The settling time is unmatched by any similar IC amplifier.
The combination of excellent noise performance and low input
current also make the AD712 useful for photo diode preamps.
Common-mode rejection of 88 dB and open-loop gain of
400 V/mV ensure 12-bit performance even in high speed
unity-gain buffer circuits.
The AD712 is pinned out in a standard op amp configuration
and is available in seven performance grades. The AD712J and
AD712K are rated over the commercial temperature range of
0°C to 70°C. The AD712A is rated over the industrial tempera-
ture range of −40°C to +85°C. The AD712S is rated over the
military temperature range of −55°C to +125°C and is available
processed to MIL-STD-883B, Rev. C.
Extended reliability PLUS screening is available, specified
over the commercial and industrial temperature ranges. PLUS
screening includes 168-hour burn-in, in addition to other
environmental and physical tests.
The AD712 is available in 8-lead PDIP, SOIC_N, and CERDIP
packages.
PRODUCT HIGHLIGHTS
1. The AD712 offers excellent overall performance at very
competitive prices.
2. The Analog Devices, Inc., advanced processing technology
and 100% testing guarantee a low input offset voltage (3 mV
maximum, J grade). Input offset voltage is specified in the
warmed-up condition.
3. Together with precision dc performance, the AD712 offers
excellent dynamic response. It settles to ±0.01% in 1 μs and
has a minimum slew rate of 16 V/μs. Thus, this device is
ideal for applications such as DAC and ADC buffers that
require a combination of superior ac and dc performance.
AD712 Data Sheet
Rev. I | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Connection Diagram ....................................................................... 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution .................................................................................. 5
Typical Performance Characteristics ............................................. 6
Settling Time ................................................................................... 11
Optimizing Settling Time .......................................................... 11
Op Amp Settling TimeA Mathematical Model .................. 12
Applications Information .............................................................. 14
Guarding ...................................................................................... 14
DAC Converter Applications .................................................... 14
Noise Characteristics ................................................................. 15
Driving the Analog Input of an ADC ...................................... 15
Driving a Large Capacitive Load .............................................. 16
Filters ................................................................................................ 17
Active Filter Applications .......................................................... 17
Second-Order Low-Pass Filter.................................................. 17
9-Pole Chebychev Filter ............................................................. 18
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 20
REVISION HISTORY
11/2018—Re v. H to Rev. I
Added Thermal Resistance Section and Table 3 .......................... 5
Changes to Table 2 ............................................................................ 5
Changes to Ordering Guide .......................................................... 20
7/2010—Rev. G to Rev. H
Changes to Product Title ................................................................. 1
Added Input Voltage Noise Parameter, Input Current Noise
Parameter, and Open-Loop Gain Parameter, Table 1 .................. 4
Moved Figure 29 and Figure 30 .................................................... 11
Moved Figure 34 ............................................................................. 12
Moved Figure 44 and Figure 45 .................................................... 15
Changes to Ordering Guide .......................................................... 20
8/2006—Rev. F to Rev. G
Edits to Figure 1 ................................................................................ 1
Change to 9-Pole Chebychev Filter Section ................................ 18
6/2006—Rev. E to Rev. F
Updated Format .................................................................. Universal
Deleted B, C, and T Models............................................... Universal
Changes to General Description .................................................... 1
Changes to Product Highlights ....................................................... 1
Changes to Specifications Section .................................................. 3
Changes to Figure 43 ...................................................................... 15
7/2002—Re v. D to Re v. E
Edits to Features ................................................................................. 1
9/2001—Rev. C to Rev. D
Edits to Features ................................................................................. 1
Edits to General Description ........................................................... 1
Edits to Connection Diagram .......................................................... 1
Edits to Ordering Guide ................................................................... 3
Deleted Metallization Photograph .................................................. 3
Edits to Absolute Maximum Ratings ............................................. 3
Edits to Figure 7 ................................................................................. 9
Edits to Outline Dimensions ......................................................... 15
Data Sheet AD712
Rev. I | Page 3 of 20
SPECIFICATIONS
VS = ±15 V at TA = 25°C, unless otherwise noted. Specifications in boldface are tested on all production units at final electrical test.
Results from those tests are used to calculate outgoing quality levels. All minimum and maximum specifications are guaranteed, although
only those shown in boldface are tested on all production units.
Table 1.
AD712J/AD712A/AD712S AD712K
Parameter Min Typ Max Min Typ Max Unit
INPUT OFFSET VOLTAGE1
Initial Offset 0.3 3/1/1 0.2 1.0 mV
T
MIN
to T
MAX
4/2/
2
2.0
vs. Temperature 7 20/20/20 7 10 μV/°C
vs. Supply 76 95 80 100 dB
TMIN to TMAX 76/76/76 80 dB
Long-Term Offset Stability 15 15 µV/month
INPUT BIAS CURRENT2
VCM = 0 V 25 75 20 75 pA
VCM = 0 V at TMAX 0.6/1.6/26 1.7/4.8/77 0.5 1.7 nA
VCM = ±10 V 100 100 pA
INPUT OFFSET CURRENT
VCM = 0 V 10 25 5 25 pA
VCM = 0 V at TMAX 0.3/0.7/11 0.6/1.6/26 0.1 0.6 nA
MATCHING CHARACTERISTICS
Input Offset Voltage 3/1/1 1.0 mV
TMIN to TMAX 4/2/2 2.0 mV
Input Offset Voltage Drift 20/20/20 10 µV/°C
Input Bias Current 25 25 pA
Crosstalk
At f = 1 kHz 120 120 dB
At f = 100 kHz 90 90 dB
FREQUENCY RESPONSE
Small Signal Bandwidth 3.0 4.0 3.4 4.0 MHz
Full Power Response 200 200 kHz
Slew Rate 16 20 18 20 V/µs
Settling Time to 0.01%
1.0
1.2
1.0
1.2
Total Harmonic Distortion 0.0003 0.0003 %
INPUT IMPEDANCE
Differential
3×10
12
||5.5
3×10
12
||5.5
Common Mode 3×1012||5.5 3×1012||5.5 Ω||pF
INPUT VOLTAGE RANGE
Differential
3
±20
±20
Common-Mode Voltage4 +14.5, −11.5 +14.5, −11.5 V
TMIN to TMAX −VS + 4 +VS 2 −VS + 4 +VS 2 V
Common-Mode Rejection Ratio
VCM = ±10 V 76 88 80 88 dB
TMIN to TMAX 76/76/76 84 80 84 dB
VCM = ±11 V 70 84 76 84 dB
TMIN to TMAX 70/70/70 80 74 80 dB
AD712 Data Sheet
Rev. I | Page 4 of 20
AD712J/AD712A/AD712S AD712K
Parameter Min Typ Max Min Typ Max Unit
INPUT VOLTAGE NOISE
f = 0.1 Hz to 10 Hz 2 2 µV p-p
f = 10 Hz 45 45 nV/√Hz
f = 100 Hz 22 22 nV/√Hz
f = 1 kHz 18 18 nV/√Hz
f = 10 kHz 16 16 nV/√Hz
INPUT CURRENT NOISE
f = 1 kHz 0.01 0.01 pA/√Hz
OPEN-LOOP GAIN
VOUT = −10 V to +10 V 150 400 200 400 V/mV
TMIN to TMAX 100/100/100 100 V/mV
OUTPUT CHARACTERISTICS
Voltage +13, −12.5 +13.9, −13.3 +13, −12.5 +13.9, −13.3 V
±12/±12/±12 +13.8, −13.1 ±12 +13.8, −13.1 V
Current +25 +25 mA
POWER SUPPLY
Rated Performance
±15
±15
Operating Range ±4.5 ±18 ±4.5 ±18 V
Quiescent Current +5.0 +6.8 +5.0 +6.0 mA
1 Input offset voltage specifications are guaranteed after 5 minutes of operation at TA = 25°C.
2 Bias current specifications are guaranteed maximum at either input after 5 minutes of operation at TA = 25°C. For higher temperatures, the current doubles every 10°C.
3 Defined as voltage between inputs, such that neither exceeds ±10 V from ground.
4 Typically exceeding 14.1 V negative common-mode voltage on either input results in an output phase reversal.
Am ESD [electrosmiz charge] sensitive deviu. Charged devlces and crrcurr boavds can drscharge wrmour aerecrrcn Mmough rm; pvoduu lemme; paremed or propnerary prorecrron cwwmy, damage may occur on dawns; xumened m high energy ESD Therefore, proper {so precamions mama be raken m avmd perfmmarKe degvadanun or loss of luncrronamy
Data Sheet AD712
Rev. I | Page 5 of 20
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage ±18 V
Internal Power Dissipation1
Input Voltage2 ±18 V
Output Short-Circuit Duration Indefinite
Differential Input Voltage
+V
S
and −V
S
Storage Temperature Range
Q-Suffix −65°C to +150°C
N-Suffix and R-Suffix 65°C to +125°C
Operating Temperature Range
AD712J/K C to 70°C
AD712A
−40°C to +85°C
AD712S −55°C to +125°C
Lead Temperature Range (Soldering 60 sec) 300°C
1 See Table 3.
2 For supply voltages less than ±18 V, the absolute maximum voltage is equal
to the supply voltage.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Table 3.
Package Type
θ
JA
θ
JC
Unit
8-Lead PDIP 165 °C/W
8-Lead CERDIP
110
22
°C/W
8-Lead SOIC 120 °C/W
ESD CAUTION
/ is taxman Euumusa .353 a u >Csz=u gm 5%. 1m: .9 3232:. SEE 2n E 9:25 “3:9 5...: 2n S qufi 35:; SEE. 3n A 2 was: “9.59 :53
AD712 Data Sheet
Rev. I | Page 6 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
SUPPLY VOLTAGE ± V
INPUT VOLTAGE SWING (V)
20
15
0
10
5
0 5 10 15 20
R
L
= 2kΩ
25°C
00823-002
Figure 2. Input Voltage Swing vs. Supply Voltage
SUPPLY VOLTAGE ± V
OUTPUT VOLTAGE SWING (V)
20
15
0
05
10
5
10 15 20
+V
OUT
–V
OUT
R
L
= 2kΩ
25°C
00823-003
Figure 3. Output Voltage Swing vs. Supply Voltage
LOAD RESISTANCE (Ω)
OUTPUT VOLTAGE SWING (V p-p)
30
25
0
15
10
5
20
10 100 1k 10k
±15V SUPPLIES
00823-004
Figure 4. Output Voltage Swing vs. Load Resistance
QUIESCENT CURRENT (mA)
SUPPLY VOLTAGE ± V
6
5
2
4
3
0 5 10 15 20
00823-005
Figure 5. Quiescent Current vs. Supply Voltage
TEMPERATURE (°C)
–60
INPUT BIAS CURRENT (V
CM
= 0) (Amps)
10
10
10
11
10
12
10
6
10
7
10
8
10
9
–40 –20
020 40 60 80 100 120 140
00823-006
Figure 6. Input Bias Current vs. Temperature
FREQUENCY (Hz)
OUTPUT IMPEDANCE ()
0.011k
1.0
0.1
10
100
10k 100k 1M 10M
00823-007
Figure 7. Output Impedance vs. Frequency
uh
Data Sheet AD712
Rev. I | Page 7 of 20
COMMON MODE VOLTAGE (V)
INPUT BIAS CURRENT (pA)
100
75
0
50
25
–10
MAX J GRADE LIMIT
–5 0 5 10
V
S
= 15V
25°C
00823-008
Figure 8. Input Bias Current vs. Common-Mode Voltage
AMBIENT TEMPERATURE (°C)
SHORT-CIRCUIT CURRENT LIMIT (mA)
10
–60
12
14
16
18
20
22
24
26
–40 –20 0 20 40 60 80 100 120 140
+ OUTPUT CURRENT
– OUTPUT CURRENT
00823-009
Figure 9. Short-Circuit Current Limit vs. Temperature
UNITY-GAIN BANDWIDTH (MHz)
3.0
3.5
4.0
4.5
5.0
TEMPERATURE (°C)
–60 –40 –20 0 20 40 60 80 100 120 140
00823-010
Figure 10. Unity-Gain Bandwidth vs. Temperature
OPEN-LOOP GAIN (dB)
–20
0
20
40
60
80
100
–20
0
20
40
60
80
100
PHASE MARGIN (Degrees)
FREQUENCY (Hz)
10 100 1k 10k 100k 1M 10M
GAIN
PHASE
2k
100pF
LOAD
0
0823-011
Figure 11. Open-Loop Gain and Phase Margin vs. Frequency
OPEN-LOOP GAIN (dB)
125
120
115
110
105
100
95
SUPPLY VOLTAGE ± V
0 5 10 15 20
R
L
= 2k
25°C
00823-012
Figure 12. Open-Loop Gain vs. Supply Voltage
POWER SUPPLY REJECTION (dB)
110
0
100
80
60
40
20
VS = ±15V SUPPLIES
WITH 1V p-p SINEWAVE 25°C
– SUPPLY
+ SUPPLY
SUPPLY MODULATION FREQUENCY (Hz)
10 100 1k 10k 100k 1M
00823-013
Figure 13. Power Supply Rejection vs. Frequency
AD712 Data Sheet
Rev. I | Page 8 of 20
CMR (dB)
0
100
80
60
40
20
V
S
= ±15V
V
CM
= 1V p-p
25°C
FREQUENCY (Hz)
10 100 1k 10k 100k 1M
00823-014
Figure 14. Common-Mode Rejection vs. Frequency
OUTPUT VOLTAGE SWING (V p-p)
30
25
0
15
10
5
20
FREQUENCY (Hz)
100k 1M 10M
R
L
= 2k
25°C
V
S
= ±15V
00823-015
Figure 15. Large Signal Frequency Response
–8
0.5
–6
–4
–2
0
4
6
8
10
2
–10 0.6 0.7
0.01%0.1%1%
0.01%
0.1%1%ERROR
OUTPUT SWING FROM 0V TO ±VOLTS
0.8 0.9 1.0
SETTLING TIME (µs)
00823-016
Figure 16. Output Swing and Error vs. Settling Time
FREQUENCY (Hz)
THD (dB)
70
–80
–90
–100
–110
–120
–130
100 1k 10k 100k
3V rms
R
L
= 2k
C
L
= 100pF
00823-017
Figure 17. Total Harmonic Distortion vs. Frequency
FREQUENCY (Hz)
1
10
100
1k
INPUT NOISE VOLTAGE (nV/
Hz)
10 100 1k 10k 100k1
0
0823-018
Figure 18. Input Noise Voltage Spectral Density
INPUT ERROR SIGNAL (mV)
(AT SUMMING JUNCTION)
5
10
15
20
25
0
SLEW RATE (V/µs)
0100
200 300 400 500 600 700 800 900
00823-019
Figure 19. Slew Rate vs. Input Error Signal
stw run: my
Data Sheet AD712
Rev. I | Page 9 of 20
25
15
20
SLEW RATE (V/µs)
TEMPERATURE (°C)
–60 –40 –20
020 40 60 80 100 120 140
00823-020
Figure 20. Slew Rate vs. Temperature
OUTPUT
100pF
2kΩ
INPUT
+VS
0.1µF
0.F
–VS
8
4
1/2
AD712
+
00823-021
Figure 21. THD Test Circuit
V
OUT
20kΩ 2.2kΩ
20V p-p
5kΩ 5kΩ
1
2
3
4
5
6
7
8
1/2
AD712
+V
S
V
IN
CROSSTALK = 20 log
V
OUT
10V
IN
1/2
AD712
–V
S
+
+
00823-022
Figure 22. Crosstalk Test Circuit
V
OUT
C
L
100pF
R
L
2kΩ
+V
S
0.1µF
0.F
–V
S
8
4
1/2
AD712
V
IN
SQUARE
WAVE
INPUT
+
00823-023
Figure 23. Unity-Gain Follower
100
90
10
0%
1µs
5V
00823-024
Figure 24. Unity-Gain Follower Pulse Response (Large Signal)
100ns
50mV
100
10
0%
90
00823-025
Figure 25. Unity-Gain Follower Pulse Response (Small Signal)
AD712 Data Sheet
Rev. I | Page 10 of 20
V
OUT
C
L
100pF
R
L
2kΩ
+V
S
0.1µF
0.F
–V
S
8
4
1/2
AD712
V
IN
SQUARE
WAVE
INPUT
5kΩ
5kΩ
+
00823-026
Figure 26. Unity-Gain Inverter
100
90
10
0%
1µs
5V
00823-027
Figure 27. Unity-Gain Inverter Pulse Response (Large Signal)
50mV 200ns
100
10
0%
90
00823-028
Figure 28. Unity-Gain Inverter Pulse Response (Small Signal)
Data Sheet AD712
Rev. I | Page 11 of 20
SETTLING TIME
OPTIMIZING SETTLING TIME
Most bipolar high speed DACs have current outputs; therefore,
for most applications, an external op amp is required for a current-
to-voltage conversion. The settling time of the converter/op amp
combination depends on the settling time of the DAC and output
amplifier. A good approximation is
( ) ( )
22
AMPtDACtTotalt
SSS
+=
The settling time of an op amp DAC buffer varies with the noise
gain of the circuit, the DAC output capacitance, and the amount
of external compensation capacitance across the DAC output
scaling resistor.
Settling time for a bipolar DAC is typically 100 ns to 500 ns.
Previously, conventional op amps have required much longer
settling times than have typical state-of-the-art DACs; therefore,
the amplifier settling time has been the major limitation to a high
speed, voltage output, digital-to-analog function. The introduction
of the AD71x family of op amps with their 1 μs (to ±0.01% of
final value) settling time permits the full high speed capabilities
of most modern DACs to be realized.
In addition to a significant improvement in settling time, the
low offset voltage, low offset voltage drift, and high open-loop
gain of the AD71x family assure 12-bit accuracy over the full
operating temperature range.
The excellent high speed performance of the AD712 is shown in
the oscilloscope photos in Figure 29 and Figure 30. Measurements
were taken using a low input capacitance amplifier connected
directly to the summing junction of the AD712, and both figures
show a worst-case situation: full-scale input transition. The 4 kΩ
[10 k||8 k= 4.4 k] output impedance of the DAC, together
with a 10 kfeedback resistor, produce an op amp noise gain of
3.25. The current output from the DAC produces a 10 V step at
the op amp output (0 to 10 V shown in Figure 29, and −10 V to
0 V shown in Figure 30).
Therefore, with an ideal op amp, settling to ±1/2 LSB (±0.01%)
requires that 375 µV or less appears at the summing junction.
This means that the error between the input and output (that
voltage which appears at the AD712 summing junction) must
be less than 375 µV. As shown in Figure 29, the total settling
time for the AD712/AD565A combination is 1.2 microseconds.
0V
–10V
OUTPUT
5V1mV
SUMMING
JUNCTION
100
10
0%
90
500ns
00823-030
Figure 29. Settling Characteristics for AD712 with AD565A,
Full-Scale Negative Transition
0V
10V
OUTPUT
5V
1mV
SUMMING
JUNCTION
100
10
0%
90
500ns
00823-031
Figure 30. Settling Characteristics for AD712 with AD565A,
Full-Scale Positive Transition
+15V
0.1µF
0.F
10pF
OUTPUT
–10V TO +10V
AD565A
–15V
I
REF
BIPOLAR
OFFSET ADJUST
I
O
0.F
R1
100Ω
R2
100Ω
GAIN
ADJUST
REF
IN
REF
GND
–V
EE
0.1µF
POWER
GND MSB LSB
8kΩ
5kΩ
5kΩ
10V
19.95kΩ 0.5mA
DAC
OUT
10V
SPAN
20V
SPAN
V
CC
REF
OUT
BIPOLAR
OFF
9.95kΩ
+
8
4
1/2
AD712
DAC
I
OUT
= 4 ×
I
REF
× CODE
20kΩ
+
00823-029
Figure 31. ±10 V Voltage Output Bipolar DAC
<+—u—‘>
AD712 Data Sheet
Rev. I | Page 12 of 20
OP AMP SETTLING TIME—A MATHEMATICAL
MODEL
The design of the AD712 gives careful attention to optimizing
individual circuit components; in addition, a careful trade-off
was made: the gain bandwidth product (4 MHz) and slew rate
(20 V/µs) were chosen to be high enough to provide very fast
settling time but not too high to cause a significant reduction
in phase margin (and therefore, stability). Thus designed, the
AD712 settles to ±0.01%, with a 10 V output step, in under 1 µs,
while retaining the ability to drive a 250 pF load capacitance
when operating as a unity-gain follower.
If an op amp is modeled as an ideal integrator with a unity-gain
crossover frequency of ωO/2π, then Equation 1 accurately
describes the small signal behavior of the circuit of Figure 32,
consisting of an op amp connected as an I-to-V converter at the
output of a bipolar or CMOS DAC. This equation would com-
pletely describe the output of the system if not for the finite slew
rate and other nonlinear effects of the op amp.
1
)
(
2
+
+
ω
+
ω
=
s
RC
G
s
C
R
R
I
V
f
O
N
O
X
IN
O
(1)
Where
π
ω
2
O
= unity-gain frequency of the op amp.
GN = noise gain of circuit
+
O
R
R
1
.
This equation can then be solved for Cf
( )
2
1
2
O
N
O
X
O
N
X
R
GRC
R
G
Cω
+ω
+
ω
=
(2)
In these equations, Capacitance CX is the total capacitance
appearing at the inverting terminal of the op amp. When
modeling a DAC buffer application, the Norton equivalent
circuit shown in Figure 32 can be used directly; Capacitance CX
is the total capacitance of the output of the DAC plus the input
capacitance of the op amp (because the two are in parallel).
V
OUT
R
L
C
L
C
F
R
I
O
R
O
C
X
1/2
AD712
+
00823-032
Figure 32. Simplified Model of the AD712 Used as a Current-Out DAC Buffer
When RO and IO are replaced with their Thevenin VIN and RIN
equivalents, the general-purpose inverting amplifier shown in
Figure 33 is created. Note that when using this general model,
Capacitance CX is either the input capacitance of the op amp, if
a simple inverting op amp is being simulated or the combined
capacitance of the DAC output and the op amp input if the
DAC buffer is being modeled.
V
OUT
R
L
C
L
C
F
R
V
IN
R
IN
C
X
1/2
AD712
+
00823-033
Figure 33. Simplified Model of the AD712 Used as an Inverter
In either case, Capacitance CX causes the system to go from a
one-pole to a two-pole response; this additional pole increases
settling time by introducing peaking or ringing in the op amp
output. Because the value of CX can be estimated with reasonable
accuracy, Equation 2 can be used to choose a small capacitor
(CF) to cancel the input pole and optimize amplifier response.
Figure 34 is a graphical solution of Equation 2 for the AD712
with R = 4 kΩ.
C
F
C
X
40
30
0
100
20
10
50
60
G
N
= 4.0
G
N
= 3.0
20 30 40 50 60
G
N
= 2.0
G
N
= 1.5
G
N
= 1.0
00823-034
Figure 34. Value of Capacitor CF vs. Value of CX
Data Sheet AD712
Rev. I | Page 13 of 20
The photos of Figure 35 and Figure 36 show the dynamic
response of the AD712 in the settling test circuit of Figure 37.
5V
5mV 500ns
100
10
0%
90
00823-035
Figure 35. Settling Characteristics 0 V to +10 V Step
Upper Trace: Output of AD712 Under Test (5 V/Div)
Lower Trace: Amplified Error Voltage (0.01%/Div)
5V
5mV 500ns
100
10
0%
90
00823-036
Figure 36. Settling Characteristics 0 V to −10 V Step
Upper Trace: Output of AD712 Under Test (5 V/Div)
Lower Trace: Amplified Error Voltage (0.01%/Div)
The input of the settling time fixture is driven by a flat top pulse
generator. The error signal output from the false summing node
of A1 is clamped, amplified by A2, and then clamped again. The
error signal is thus clamped twice: once to prevent overloading
Amplifier A2 and then a second time to avoid overloading the
oscilloscope preamp. The Tektronix oscilloscope preamp type
7A26 was carefully chosen because it does not overload with
these input levels. Amplifier A2 needs to be a very high speed
FET-input op amp; it provides a gain of 10, amplifying the error
signal output of A1.
+15V
0.1µF
1/2
AD712
10pF
–15V
5k
4.99k
0.47µF
1/2
AD712
0.47µF
200
4.99k
5 TO 18pF
0.1µF
10k
10k
V
IN
HP2835
HP2835
20pF
1M
10k
0.2 TO 0.6pF
1.1k
5p
F
205
–15V +15V
V
OUT
TEKTRONIX 7A26
OSCILLOSCOPE
PREAMP
INPUT SECTION
V
ERROR ×
5
DATA
DYNAMICS
5109
(OR EQUIVALENT
FLAT TOP PULSE
GENERATION)
+
+
0
0823-037
Figure 37. Settling Time Test Circuit
AD712 Data Sheet
Rev. I | Page 14 of 20
APPLICATIONS INFORMATION
GUARDING
The low input bias current (15 pA) and low noise characteristics
of the AD712 BiFET op amp make it suitable for electrometer
applications such as photo diode preamplifiers and picoampere
current-to-voltage converters. The use of a guarding technique,
such as that shown in Figure 38, in printed circuit board (PCB)
layout and construction is critical to minimize leakage currents.
The guard ring is connected to a low impedance potential at the
same level as the inputs. High impedance signal lines should
not be extended for any unnecessary length on the PCB.
8
7
6
5
4
3
2
1
PDIP (N), CERDIP (Q),
AND SOIC (R) PACKAGES.
00823-038
Figure 38. Board Layout for Guarding Inputs
DAC CONVERTER APPLICATIONS
The AD712 is an excellent output amplifier for CMOS DACs. It can
be used to perform both 2-quadrant and 4-quadrant operations.
The output impedance of a DAC using an inverted R-2R ladder
approaches R for codes containing many 1s, and 3R for codes
containing a single 1. For codes containing all 0s, the output
impedance is infinite.
For example, the output resistance of the AD7545 modulates
between 11 kΩ and 33 kΩ. Therefore, with an 11 kΩ DAC
internal feedback resistance, the noise gain varies from 2 to 4/3.
This changing noise gain modulates the effect of the input offset
voltage of the amplifier, resulting in nonlinear DAC amplifier
performance.
The AD712K with guaranteed 700 μV offset voltage minimizes
this effect to achieve 12-bit performance.
Figure 39 and Figure 40 show the AD712 and AD7545 (12-bit
CMOS DAC) configured for unipolar binary (2-quadrant multi-
plication) or bipolar (4-quadrant multiplication) operation.
Capacitor C1 provides phase compensation to reduce overshoot
and ringing.
+15V
1/2
AD712
V
IN
V
REF
V
DD
R
FB
OUT1
AGND
AD7545
DGND
V
OUTA
R2A*
DB11 TO DB0
0.1µF
V
DD
R1A*
1/2
AD712
V
IN
V
REF
V
DD
R
FB
OUT1
AGND
AD7545
DGND
V
OUTB
R2B*
DB11 TO DB0
0.1µF
–15V
R1B*
V
DD
C1A
33pF
ANALOG
COMMON
*REFER TO
TABLE 3
GAIN
ADJUST
C1B
33pF
ANALOG
COMMON
GAIN
ADJUST
*REFER TO
TABLE 3
+
+
00823-039
Figure 39. Unipolar Binary Operation
R1 and R2 calibrate the zero offset and gain error of the DAC.
Specific values for these resistors depend upon the grade of
AD7545 and are listed in Table 4.
Table 4. Recommended Trim Resistor Values vs. Grades of
the AD7545 for VDD = 5 V
Trim
Resistor JN/AQ KN/BQ LN GLN
R1 500 Ω 200 Ω 100 Ω 20 Ω
R2 150 Ω 68 Ω 33 Ω 6.8 Ω
+15V
1/2
AD712
V
IN
V
REF
R
FB
OUT1
AGND
AD7545
DGND
R2*
DATA INPUT
0.1µF
V
DD
R1* 1/2
AD712
V
OUT
0.1µF
–15V
12
DB11 TO DB0
R4
20k1%
R5
20k1%
R3
10k1%
C1
33pF
ANALOG
COMMON
V
DD
GAIN
ADJUST
*FOR VALUES OF
R1 AND R2 SEE TABLE 3
+
+
00823-040
Figure 40. Bipolar Operation
Data Sheet AD712
Rev. I | Page 15 of 20
Figure 41 and Figure 42 show the settling time characteristics of
the AD712 when used as a DAC output buffer for the AD7545.
1mV
5V
500ns
100
10
0%
90
00823-041
Figure 41. Positive Settling Characteristics for AD712 with AD7545
1mV
5V
500ns
100
10
0%
90
00823-042
Figure 42. Negative Settling Characteristics for AD712 with AD7545
NOISE CHARACTERISTICS
The random nature of noise, particularly in the flicker noise
region, makes it difficult to specify in practical terms. At the
same time, designers of precision instrumentation require
certain guaranteed maximum noise levels to realize the full
accuracy of their equipment. All grades of the AD712 are sample
tested on an AQL basis to a limit of 6 μV p-p, 0.1 Hz to 10 Hz.
DRIVING THE ANALOG INPUT OF AN ADC
An op amp driving the analog input of an ADC, such as that
shown in Figure 43, must be capable of maintaining a constant
output voltage under dynamically changing load conditions. In
successive approximation converters, the input current is compared
to a series of switched trial currents. The comparison point is
diode clamped, but can deviate several hundred millivolts resulting
in high frequency modulation of analog-to-digital input current.
The output impedance of a feedback amplifier is made artificially
low by the loop gain. At high frequencies, where the loop gain is
low, the amplifier output impedance can approach its open-loop
value. Most IC amplifiers exhibit a minimum open-loop output
impedance of 25 Ω due to current-limiting resistors.
+15V
1/2
AD712
0.1µF
0.1µF
–15V ANALOG COM
AD574A
12/8
CS
AO
R/C
CE
REF IN
REF OUT
BIP OFF
10VIN
20VIN
STS
+5V
+15V
–15V
±10V
A
NALOG
INPUT
OFFSET
ADJUST
R2
100
R1
100
GAIN
ADJUST
HIGH
BITS
MIDDLE
BITS
LOW
BITS
AC DC
+
00823-043
Figure 43. AD712 as an ADC Unity-Gain Buffer
A few hundred microamps reflected from the change in converter
loading can introduce errors in instantaneous input voltage. If
the analog-to-digital conversion speed is not excessive and the
bandwidth of the amplifier is sufficient, the amplifier output
returns to the nominal value before the converter makes its
comparison. However, many amplifiers have relatively narrow
bandwidth yielding slow recovery from output transients. The
AD712 is ideally suited to drive high speed ADCs because it
offers both wide bandwidth and high open-loop gain.
200ns
500mV
PD711 BUFF
–10V ADC IN
1mV
100
10
0%
90
00823-044
Figure 44. ADC Input Unity Gain Buffer Recovery Times, −10 V ADC IN
200ns
500mV
PD711 BUFF
–5V ADC IN
1mV
100
10
0%
90
00823-045
Figure 45. ADC Input Unity Gain Buffer Recovery Times, −5 V ADC IN
AD712 Data Sheet
Rev. I | Page 16 of 20
DRIVING A LARGE CAPACITIVE LOAD
The circuit in Figure 46 uses a 100 isolation resistor that enables
the amplifier to drive capacitive loads exceeding 1500 pF; the
resistor effectively isolates the high frequency feedback from
the load and stabilizes the circuit. Low frequency feedback is
returned to the amplifier summing junction via the low-pass filter
formed by the 100 series resistor and the Load Capacitance CL.
Figure 47 shows a typical transient response for this connection.
1/2
AD712
0.1µF
0.1µF
–V
IN
+V
IN
INPUT
R
1
2kΩ 1500pF
10kΩ 1500pF
20Ω 1000pF
C1 R1
4.99kΩ
4.99kΩ
30pF
OUTPUT
100Ω
+
+
TYPICAL CAPACITANCE
LIMIT FOR VARIOUS
LOAD RESISTORS
C
1
UP TO
+
00823-046
Figure 46. Circuit for Driving a Large Capacitive Load
5V
1µs
100
10
0%
90
00823-047
Figure 47. Transient Response RL = 2 kΩ, CL = 500 pF
REF 2m dBm arrsn ,o m mamw
Data Sheet AD712
Rev. I | Page 17 of 20
FILTERS
ACTIVE FILTER APPLICATIONS
In active filter applications using op amps, the dc accuracy of
the amplifier is critical to optimal filter performance. The
amplifier offset voltage and bias current contribute to output
error. Offset voltage is passed by the filter and can be amplified
to produce excessive output offset. For low frequency applications
requiring large value input resistors, bias currents flowing
through these resistors also generate an offset voltage.
In addition, at higher frequencies, the op amp dynamics must
be carefully considered. Here, slew rate, bandwidth, and open-
loop gain play a major role in op amp selection. The slew rate
must be fast as well as symmetrical to minimize distortion. The
amplifier bandwidth in conjunction with the filter gain dictates
the frequency response of the filter.
The use of a high performance amplifier such as the AD712
minimizes both dc and ac errors in all active filter applications.
SECOND-ORDER LOW-PASS FILTER
Figure 48 depicts the AD712 configured as a second-order,
Butterworth low-pass filter. With the values as shown, the
corner frequency is 20 kHz; however, the wide bandwidth of the
AD712 permits a corner frequency as high as several hundred
kilohertz. Equations for component selection are as follows:
R1 = R2 = A user selected value (10 kΩ to 100 kΩ, typical)
C1 (in farads) =
()
()
()
1
2
414.
1
R
f
cutoff
π
( )
( )
( )
12
707.
0
2Rf
C
cutoff
π
=
+15V
1/2
AD712
0.1µF
0.1µF
–15V
V
OUT
V
IN
C1
560pF
R2
20kΩ
R1
20kΩ
C2
280pF
+
00823-048
Figure 48. Second-Order Low-Pass Filter
An important property of filters is their out-of-band rejection.
The simple 20 kHz low-pass filter shown in Figure 48 can be
used to condition a signal contaminated with clock pulses or
sampling glitches that have considerable energy content at high
frequencies.
The low output impedance and high bandwidth of the AD712
minimize high frequency feedthrough as shown in Figure 49.
The upper trace is that of another low cost BiFET op amp
showing 17 dB more feedthrough at 5 MHz.
REF 20.0 dBm
10dB/DIV RANGE 15.0dBm
OFFSET .0 Hz
0dB
CENTER 5 000 000.0Hz
RBW 30kHz
SPAN 10 000 000.0Hz
ST .8 SEC
VBW 30kHz
TYPICAL BIFET
AD712
00823-049
Figure 49. High Frequency Feedthrough
AD712 Data Sheet
Rev. I | Page 18 of 20
+15V
0.001µF
100k
0.1µF
0.1µF
–15V
+15
V
0.1µF
0.1µF
–15V
*
D
*
C
*
B
*
A
28006190649061902800
V
IN
0.001µF 124k
4.99k
4.99k
V
OUT
4.9395E
–15
5.9276E
–15
5.9276E
–15
4.9395E
–15
*
SEE TEXT
A1
AD711
A2
AD711
++++
+
+
00823-050
Figure 50. 9-Pole Chebychev Filter
9-POLE CHEBYCHEV FILTER
Figure 50 and Figure 51 show the AD712 and its dual counterpart,
the AD711, as a 9-pole Chebychev filter using active frequency
dependent negative resistors (FDNRs). With a cutoff frequency
of 50 kHz and better than 90 dB rejection, it can be used as an
antialiasing filter for a 12-bit data acquisition system with
100 kHz throughput.
As shown in Figure 50, the filter is comprised of four FDNRs
(A, B, C, D) having values of 4.9395 × 10−15 and 5.9276 × 10–15
farad-seconds. Each FDNR active network provides a two-pole
response for eight poles. The ninth pole consists of a 0.001F
capacitor and a 124 kΩ resistor at Pin 3 of Amplifier A2. Figure 51
depicts the circuits for each FDNR with the proper selection of
R. To achieve optimal performance, the 0.001 µF capacitors
must be selected for 1% or better matching and all resistors
should have 1% or better tolerance.
+15V
0.001µF
4.99k
0.1µF
0.1µF
–15V
1.0k
0.001µF
R
+
1/2
AD712
+
1/2
AD712
R: 24.9k FOR 4.9395E
–15
29.4k FOR 5.9276E
–15
+
0
0823-051
Figure 51. FDNR for 9-Pole Chebychev Filter
REF 5.0dBm
10dB/DIV RANGE –5.0dBm
MARKER 96 800.0Hz
–90dBm
START.0Hz
RBW 300Hz
STOP 200 000.0Hz
ST 69.6 SECVBW 30Hz
00823-052
Figure 52. High Frequency Response for 9-Pole Chebychev Filter
mo 110.15) 1 0.230 (7.11I 0.250 (6.39 0.140(6.1D| I} 32513 16) 1 w I} 3m: 11 $2) I} 195 (A 95) I} 130 (3 l L in 11511921 j , 1 1m. 1m. 11—1 3 I} 430 110.91) 0.055 (1.15) 17.005 0.13 M31 ’ 512 ‘11 To 18.31013) .m 17. 1111* I} 060 11 51) I} 015 m 38) I: 20915 as 1112513181 991519.111 00231058) 00081. ) 0014 m 3111 L" 7“ (1 L7” 0 an (n 1111
Data Sheet AD712
Rev. I | Page 19 of 20
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLYAND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
070606-A
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
SEATING
PLANE
0.015
(0.38)
MIN
0.210 (5.33)
MAX
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
8
14
5
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.100 (2.54)
BSC
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
0.060 (1.52)
MAX
0.430 (10.92)
MAX
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
PLANE
0.005 (0.13)
MIN
Figure 53. 8-Lead Plastic Dual In-Line Package [PDIP]
(N-8)
Dimensions shown in inches and (millimeters)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
0.310 (7.87)
0.220 (5.59)
0.005 (0.13)
MIN 0.055 (1.40)
MAX
0.100 (2.54) BSC
15°
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
0.200 (5.08)
MAX
0.405 (10.29) MAX
0.150 (3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36) 0.070 (1.78)
0.030 (0.76)
0.060 (1.52)
0.015 (0.38)
14
5
8
Figure 54. 8-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-8)
Dimensions shown in inches and (millimeters)
1 *m‘ ‘ HHHH T v o 7 HH u H4 ,4 1‘ 7 3"}I‘W' n.1nmnnwlLfifij 4L7 ““ NE W BEGIéOECS; www.ana|ng.cnm
AD712 Data Sheet
Rev. I | Page 20 of 20
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AA
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
85
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 55. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD712AQ −40°C to +85°C 8-Lead CERDIP Q-8
AD712JNZ 0°C to 70°C 8-Lead PDIP N-8
AD712JRZ 0°C to 70°C 8-Lead SOIC_N R-8
AD712JRZ-REEL 0°C to 70°C 8-Lead SOIC_N R-8
AD712JRZ-REEL7 0°C to 70°C 8-Lead SOIC_N R-8
AD712KNZ 0°C to 70°C 8-Lead PDIP N-8
AD712KRZ 0°C to 70°C 8-Lead SOIC_N R-8
AD712KRZ-REEL 0°C to 70°C 8-Lead SOIC_N R-8
AD712KRZ-REEL7 0°C to 70°C 8-Lead SOIC_N R-8
AD712SQ/883B −55°C to +125°C 8-Lead CERDIP Q-8
1 Z = RoHS Compliant Part.
©1986–2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00823-0-11/18(I)

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