STLC7550 Datasheet by STMicroelectronics

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February 2006 Rev 9 1/24
24
STLC7550
Low Power Low Voltage Analog Front End
Features
General purpose signal processing Analog
Front End (AFE)
Targeted for V.34bis Modem and 56Kbps
Modem applications
16-BIT oversampling Σ∆ A/D and D/A
converters
83dB signal to noise ratio for sampling
frequency up to 9.6kHz @ 3V
87dB dynamic range @ 3V
Filter bandwidths:
0.425 x the sampling frequency
On-chip reference voltage
Single power supply range: 2.7 to 5.5V
Low power consumption less than 30mW
operating power 3V
Stand-by mode power consumption less than
3mW at 3V
Programming sampling frequency
Max. sampling frequency : 45kHz
Synchronous serial interface for processor
datas exchange Master or Slave operations
0.50µm CMOS process
TQFP48 package
STLC7546 mode of operation compatible
Description
The STLC7550 is a single chip Analog Front-end
(AFE) designed to implement modems up to
56Kbps.
It has been especially designed for host
processing application in which the modulation
software (V.34bis, 56Kbps) is performed by the
main application processor : Pentium, Risc or
DSP processors.
The main target of this device is stand alone
appliances as Hand Held PC (HPC), Personnal
Digital Assistants (PDA), Webphones, Network
Computers, Set Top Boxes for Digital Television
(Satellite and Cable).
To comply with such applications STLC7550 is
powered nominally at 3V only.
Maximum Power Dissipation 30mW is well suited
for Battery operations. In case of battery low,
STLC7550 will continue to work even at a 2.7V
level.
STLC7550 also provides clock generator for all
sampling frequencies requested for V.34bis and
56Kbps applications.
This new AFE can also be used for PC mother
boards or add-on cards or stand alone MODEMs.
It can be used in a master mode or slave mode.
The slave mode eases multi AFE architecture
design in saving external logical glue.
Order codes
(*) ECOPACK® (see Section 6)
TQFP48 (7 x 7 x 1.4mm)
(Full Plastic Quad Flat Pack)
Part number Temp range, °CPackage Packing
STLC7550TQF7 0 to 70 TQFP48 Tube
STLC7550TQF7TR 0 to 70 TQFP48 Tape & Reel
E-STLC7550TQF7 (*) 0 to 70 TQFP48 Tube
www.st.com
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
Content STLC7550
2/24 Rev 9
Content
1 Pins description & Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1.1 Power Supply (5 pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1.2 Host interface (10 pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1.3 Clock signals (2 pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1.4 Analog interface (9 pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Transmit D/A section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.1 Transmit Low Pass Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.2 D/A Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Receive A/D section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2.1 A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2.2 Receive Low Pass Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.5 Host interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.6 Control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2 Nominal DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3 Nominal AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4 Transmit Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4.1 Performance of the Tx channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4.2 Smoothing filter transfer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.5 Receive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.5.1 Performance of the Rx channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4 Typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5 Definition and Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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STLC7550 Pins description & Block diagram
Rev 9 3/24
1 Pins description & Block diagram
Figure 1. Pin connection (top view)
Table 1. Pin list
Pin # Pin Name Type Description
1 - 2, 10 to 14,
22 to 26, 34 to
38, 46 to 48
NC - Not connected
3 SCLK O Shift Clock Output
4 FS I/O Frame Synchronization Input (slave)/Output (master)
5 DVDD I Positive Digital Power Supply (2.7V TO 5.5V)
6 DGND I Digital Ground
7 MCM I Master Clock Mode
8 XTALOUT O Crystal Output
9 XTALIN/MCLK I Crystal Input (MCM = 1) / External Clock (MCM = 0)
15 HC1 I Hardware Control Input
16 HC0 I Hardware Control Input
17 PWRDWN I Power down Input
18 M/S I Master/Slave Mode Control Pin Input
19 VREFP O 16-bit D/A and A/D Positive Reference Voltage
20 VREFN O 16-bit D/A and A/D Negative Reference Voltage
1234567891011
25 26 27 28 29 30 31 32 33
12
34 35 36
13
14
15
16
17
18
19
20
21
22
23
24
44
43
42
41
40
39
38
37
45
46
47
48
AGND2
V
CM
AV
DD
IN-
IN+
AUXIN+
AUXIN- XTALIN/MCLK
XTALOUT
MCM
DGND
DV
DD
FS
SCLK
DOUT
DIN
TSTD1
TS
RESET
OUT-
OUT+
AGND1
V
REFN
M/S
V
REFP
PWRDWN
HC0
HC1
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Pins description & Block diagram STLC7550
4/24 Rev 9
Note: 1 To obtain published performance, the analog VDD and Digital VDD should be decoupled with
respect to Analog Ground and Digital Ground, respectively. The decoupling is intended to
isolate digital noise from the analog section ; decoupling capacitors should be as close as
possible to the respective analog and digital supply pins.
2 All the ground pins must be tied together. In the following section, the ground and supply
pins are referred to as GND and VDD, respectively.
1.1 Pin description
1.1.1 Power Supply (5 pins)
Analog VDD Supply (AVDD)
This pin is the positive analog power supply voltage for the DAC and the ADC section.
It is not internally connected to digital VDD supply (DVDD).
In any case the voltage on this pin must be higher or equal to the voltage of the Digital power
supply (DVDD).
Digital VDD Supply (DVDD)
This pin is the positive digital power supply for DAC and ADC digital internal circuitry.
Analog Ground (AGND1, AGND2)
These pins are the ground return of the analog DAC (ADC) section.
21 AGND1 I Analog Ground
27 AUXIN+ I Non-inverting Input to Auxiliary Analog Input
28 AUXIN- I Inverting Input to Auxiliary Analog Input
29 IN+ I Non-inverting Input to Analog Input Amplifier
30 IN- I Inverting Input to Analog Input Amplifier
31 AVDD I Positive Analog Power Supply (2.7V to 5.5V)
32 VCM O Common Mode Voltage Output (AVDD/2)
33 AGND2 I Analog Ground
39 OUT+ O Non-inverting Smoothing Filter Output
40 OUT- O Inverting Smoothing Filter Output
41 RESET I Reset Function to initialize the internal counters
42 TS I Timeslot Control Input
43 TSTD1 I/O Digital Input/Output reserved for test
44 DIN I Serial Data Input
45 DOUT O Serial Data Output
Table 1. Pin list (continued)
Pin # Pin Name Type Description
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STLC7550 Pins description & Block diagram
Rev 9 5/24
Digital Ground (DGND)
This pin is the ground for DAC and ADC internal digital circuitry.
1.1.2 Host interface (10 pins)
Data In (DIN)
In Data Mode, the data word is the input of the DAC channel. In software, the data word is
followed by the control register word.
Data Out (DOUT)
In Data Mode, the data word is the ADC conversion result. In software, the data word is
followed by the register read.
Frame Synchronization (FS)
In master mode, the frame synchronization signal is used to indicate that the device is ready
to send and receive data. The data transfer begins on the falling edge of the frame-sync
signal. The framesync is generated internally and goes low on the rising edge of SCLK in
master mode. In slave mode the frame is generated externally.
Serial Bit Clock (SCLK)
SCLK clocks the digital data into DIN and out of DOUT during the frame synchronization
interval. The Serial bit clock is generated internally.
Reset Function (RESET)
The reset function is to initialize the internal counters and control register. A minimum low
pulse of 100ns is required to reset the chip. This reset function initiates the serial data
communications. The reset function will initialize all the registers to their default value and
will put the device in a pre-programmed state. After a low-going pulse on RESET
, the device
registers will be initialized to provide an over-sampling ratio equal to 160, the serial interface
will be in data mode, the DAC attenuation will be set to infinite, the ADC gain will be set to
0dB, the Differential input mode on the ADC converter will be selected, and the multiplexor
will be set on the main inputs IN+ and IN-. After a reset condition, the first frame
synchronization corresponds to the primary channel.
Power Down (PWRDWN)
The Power-Down input powers down the entire chip (< 50mW). When PWRDWN Pin is
taken low, the device powers down such that the existing internally programmed state is
maintained. When PWRDWN is driven high, full operation resumes after 1ms. If the
PWRDWN input is not used, it should be tied to VDD.
Hardware Control (HC0, HC1)
These two pins are used for Hardware/Software Control of the device. The data on HC0 and
HC1 will be latched on to the device on the rising edge of the Frame Synchronization Pulse.
If these two pins are low, Software Control Mode is selected. When in Software Control
Mode, the LSB of the 16-bit word will select the Data Mode (LSB = 0) or the Control Mode
(LSB = 1). Other combinations of HC0/HC1 are for Hardware Control. These inputs should
be tied low if not used.
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Pins description & Block diagram STLC7550
6/24 Rev 9
Master/Slave Control (M/S)
When M/S is high, the device is in master mode and Fs is generated internally. When M/S is
low, the device is in slave mode and Fs must be generated externally.
Master Clock Mode (MCM)
When MCM is high, XTALIN is provided externally and must be equal to 36.864MHz. When
MCM is low, XTALIN is provided externally and must be equal to oversampling frequency :
Fs x Over (see Figure 3 and Section 2.4).
Timeslot Control (TS)
When TS = 0 the data are assigned to the first 16 bits after falling edge of FS (7546 mode)
otherwise the data are bits 17 to 32. The case M/S = 1 with TS = 1 is reserved for life-test
(transmit gain fixed to 0dB).
1.1.3 Clock signals (2 pins)
Depending on MCM value, these pins have different function.
MCM = 1 (XTALIN, XTALOUT)
These pins must be tied to external crystal. For the value of crystal see Section 2.3.
MCM = 0 (MCLK, XTALOUT)
MCLK Pin must be connected to an external clock. XTALOUT is not used.
1.1.4 Analog interface (9 pins)
DAC and ADC Positive Reference Voltage Output (VREFP)
This pin provides the Positive Reference Voltage used by the 16-bit converters. The
reference voltage, VREF
, is the voltage difference between the VREFP and VREFN outputs,
and its nominal value is 1.25V. VREFP should be externally decoupled with respect to VCM.
DAC and ADC Negative Reference Voltage Output (VREFN)
This pin provides the Negative Reference Voltage used by the 16-bit converters, and should
be externally decoupled with respect to VCM.
Common Mode Voltage Output (VCM)
This output pin is the common mode voltage (AVDD - AGND)/2. This output must be
decoupled with respect to GND.
Non-inverting Smoothing Filter Output(OUT+)
This pin is the non-inverting output of the fully differential analog smoothing filter.
Inverting Smoothing Filter Output (OUT-)
This pin is the inverting output of the fully differential analog smoothing filter. Outputs OUT+
and OUTprovide analog signals with maximum peak-topeak amplitude 2 x VREF, and must
be followed by an external two pole smoothing filter. The external filter follows the internal
single pole switch capacitor filter. The cutoff frequency of the external filter must be greater
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STLC7550 Pins description & Block diagram
Rev 9 7/24
than two times the sampling frequency (FS), so that the combined frequency response of
both the internal and external filters is flat in the passband. The attenuator of the last output
stage can be programmed to 0dB, 6dB or infinite.
Non-inverting Analog Input (IN+)
This pin is the differential non-inverting ADC input.
Inverting Analog Input (IN-)
This pin is the differential inverting ADC input. These analog inputs (IN+, IN-) are presented
to the Sigma-Delta modulator. The analog input peak-topeak differential signal range must
be less than 2 x VREF
, and must be preceded by an external single pole anti-aliasing filter.
The cut-off frequency of the filter must be lower than one half the oversampling frequency.
These filters should be set as close as possible to the IN+ and IN- pins. The gain of the first
stage is programmable (see Ta bl e 4 ).
Non-inverting Auxiliary Analog Input (AUX IN+)
This pin is the differential non-inverting auxiliary ADC input. The characteristics are same as
the IN+ input.
Inverting Auxiliary Analog Input (AUX IN-)
This pin is the differential inverting auxiliary ADC input. The characteristics are same as the
IN- input. The input pair (IN+/IN- or AUX IN+/AUX IN-) are software selectable.
Figure 2. Block diagram
ANALOG
MODULATOR
2nd ORDER
MODULATOR
LOW-PASS
(0.425 x sampling
frequency)
HC0
OUT+
OUT-
V
CM
V
REFN
V
REFP
IN+
IN-
(0 + 6dB in
diff. input)
DAC 1 BIT
First order
differential
switched
capacitor
filter
LOW-PASS
(0.425 x sampling
frequency)
SERIAL PORTS
AND CONTROL REGISTER
ATTEN.
0dB/+6dB/
INFINITE
M/S
FS
SCLK
DOUT
DIN
CLOCK
GENERATOR
XTALINXTALOUTAGND2AGND1AV
DD
DV
DD
DGND
STLC7550
RESET PWRDWN
41 176598332131
40
39
32
20
19
30
29
16
TS
7MCM
42
HC1
15
18
4
3
45
44
TSTD1
43
AUXIN+
AUXIN- 28
27
MUX
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Functional description STLC7550
8/24 Rev 9
2 Functional description
2.1 Transmit D/A section
The functions included in the Tx D/A section are detailed hereafter. 16-bit 2’s complement
data format is used in the DAC channel.
2.1.1 Transmit Low Pass Filters
The transmit low pass filter is basically an interpolating filter including a sinx/x correction. It
is a combination of Finite Impulse Response filter (FIR) and an Infinite Impulse Response
filter (IIR). The digital signal from the serial interface gets interpolated by 2, 3, 4, 5 or 6 x
Sampling Frequency (FS) through the IIR filter. The signal is further interpolated by 32 x FS
x n (with n equal to 2, 3, 4, 5, 6) through the IIR and FIR filter. The low pass filter is followed
by the DAC. The DAC is oversampled at 64, 96, 128, 160, 192 x FS. The oversampling ratio
is user selectable.
2.1.2 D/A Converter
The oversampled D/A converter includes a second order digital noise shaper, a one bit D/A
converter and a single pole analog low-pass filter. The attenuation of the last output stage
can be programmed to 0dB, +6dB or infinite. The cut-off frequency of the single pole switch-
capacitor lowpass is:
with OCLK = Oversampling Clock frequency.
Continuous-time filtering of the analog differential output is necessary using an off-chip
amplifier and a few external passive components. At least 79dB signal to noise plus
distortion ratio can obtained in the frequency band of 0.425 x 9.6kHz (with an oversampling
ratio equal to 160).
2.2 Receive A/D section
The different functions included in the ADC channel section are described below. 16-bit 2’s
complement data format is used in the ADC.
2.2.1 A/D Converter
The oversampled A/D converter is based on a second order sigma-delta modulator. To
produce excellent common-mode rejection of unwanted signals, the analog signal is
processed differentially until it is converted to digital data. Single-ended mode can also be
used. The ADC is oversampled at 64, 96, 128, 160 or 192 x FS. The oversampling ratio is
user selectable. At least -85dB SNDR can be expected in the 0.425 x 9.6kHz bandwidth with
a -6dBr differential input signal and an oversampling ratio equal to 160.
2.2.2 Receive Low Pass Filter
It is a decimation filter. The decimation is performed by two decimation digital filters : one
decimation FIR filter and one decimation IIR filter. The purpose of the FIR filter is to
decimate 32 times the digital signal coming from the ADC modulator.
fc 3dB
OCLK
2π10⋅⋅
----------------------=
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STLC7550 Functional description
Rev 9 9/24
The IIR is a cascade of 5 biquads. It provides the low-pass filtering needed to remove the
noise remaining above half the sampling frequency. The output of the IIR will be processed
by the DSP.
2.3 Clock generator
The master clock, MCLK is provided by the user thanks to a crystal or external clock
generator (see Figure 3).
The MCLK could be equal to 36.864MHz (MCM = 1). In that case thanks to the divider M x
Q, the STLC7550 is able to generate all V.34bis and 56 Kbps sampling frequencies (see
Ta bl e 2 ).
When MCM = 0, the MCLK must be equal to the oversampling frequency : Fs x OVER (7546
mode). The ADC and DAC are oversampled at the OCLK frequency. OCLK is equal to the
shift clock used in the serial interface.
The MCLK frequency should be :
MCLK = K x Sampling frequency
Combination of M, Q and oversampling ratios allows to generate several sampling
frequencies.
Recommended values for classical modem applications are as follow :
Note: 1 Recommended value.
Table 2. Sampling Frequencies Generation
F (kHz)
FQ = 36.864MHz (1) FQ = 18.432MHz FQ = 9.216MHz
M Q over M Q over M Q over
16.00 3 6 128 2 4.5 128 1 6 96
13.96 3 5.5 160 ------
13.71 3 7 128 1 7 192 1 7 96
12.80 3 6 160 2 4.5 160 1 4.5 160
12.00 3 8 128 2 6 128 1 6 128
11.82 3 6.5 160 ------
10.97 3 7 160 ------
10.47 4 5.5 160 2 5.5 160 1 5.5 160
10.29 4 7 128 2 7 128 1 7 128
9.60 4 6 160 2 6 160 1 6 160
9.00 4 8 128 2 8 128 1 8 128
8.86 4 6.5 160 2 6.5 160 1 6.5 160
8.23 4 7 160 2 7 160 1 7 160
8.00 4 6 192 2 6 192 1 6 192
7.20 4 8 160 2 8 160 1 8 160
H1
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Functional description STLC7550
10/24 Rev 9
Figure 3. Clock Block Diagram
2.4 Modes of operation
Thanks to MCM and M/S programmation pins we can get the following configuration.
Configuration 1 : MCM = 1, M/S = 1
The STLC7550 is in master mode and we have :
Fs = XTAL IN / (M x Q x OVER)
Fs and SCLK are output pins.
Figure 4. Configuration 1
Configuration 2 : MCM = 1, M/S = 0
The STLC7550 is in slave mode. SCLK is provided by the STLC7550, the processor
generates the Fs and controls the phase of the sampling frequency.
Fs must be the result of a division of a number of cycles of SLCK (Fs = SCLK % OVER).
Configuration 3 : MCM = 0, M/S = 1
The STLC7550 is in master mode and the processor provides the XTAL IN = MCLK =
OCLK. The STLC7550 generates the Fs from OCLK. In this mode the configuration 3 is
equivalent to the STLC7546 mode.
Configuration 4 : MCM = 0, M/S = 0
The STLC7550 is in slave mode. The configuration 4 is equivalent to configuration 3 but the
Fs is generated and phase controlled by the processor.
Bit 3-4-5 Internal
Sampling
M/S
Sync
FS
SCLK
(OCLK)
% OVER
XTALIN
(MCLK) XTALOUT
÷ M ÷ Q
MCM
Cont. Reg. : Bit 8-9-10-11-12-13
V
DD
SCLK
FS
DIN
DOUT
BCLK
FS
DO
DI
XTALIN
M/S
MCM
STLC7550
PROCESSOR
V
DD
f
Q
= 36.864MHz
V
DD
TS GND
H? H“: H?
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STLC7550 Functional description
Rev 9 11/24
Figure 5. Configuration 2
Figure 6. Configuration 3 (7546 mode)
Configuration 5 : MCM = 1, M/S = 1 (master codec) MCM = 0, M/S = 0 (slave codec) This
is dual codec application. The master codec has his data in timeslot 0 and the slave codec
has his data in timeslot 1 thanks to the programmation of TS.
Figure 7. Configuration 4
SCLK
FS
DIN
DOUT
BCLK
FS
DO
DI
XTALIN
M/S
MCM
STLC7550
PROCESSOR
GND
V
DD
f
Q
= 36.864MHz
TS GND
SCLK
FS
DIN
DOUT
XTALIN
M/S
MCM
STLC7550
V
DD
GND
f
Q
= K x Fs
BCLK
FS
DO
DI
PROCESSOR
TS GND
SCLK
FS
DIN
DOUT
XTALIN
M/S
MCM
STLC7550
GND
f
Q
= K x Fs
BCLK
FS
DO
DI
PROCESSOR
GND
TS GND
, m
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Functional description STLC7550
12/24 Rev 9
Figure 8. Configuration 5
2.5 Host interface
The Host interface consist of the shift clock, the frame synchronization signal, the
ADCchannel data output, and the DAC-channel data input.
Two modes of serial transfer are available :
First : Software mode for 15-bit transmit data transfer and 16-bit receive data
transfer
Second : hardware mode for 16-bit data transfer.
Both modes are selected by the Hardware Control pins (HC0, HC1).
The data to the device, input/output are MSB-first in 2’s complement format (see Ta b l e 3 ).
When Control Mode is selected, the device will internally generate an additional Frame
Synchronization Pulse (Secondary Frame Synchronization Pulse) at the midpoint of the
original Frame Period. If the device is in slave mode the additional frame sync (secondary
frame sync pulse) must be generated by the processor. The Original Frame Synchronization
Pulse will also be referred to as the Primary Frame Synchronization Pulse.
SCLK
FS
DIN
DOUT
BCLK
FS
DO
DI
XTALIN
M/S
MCM
STLC7550
PROCESSOR
V
DD
f
Q
= 36.864MHz
TS
FS
DIN
DOUT
HC0
M/S
MCM
STLC7550
GND
HC0
XTAKIN
V
DD
GND
V
DD
TS GND
HC1
HC1
Table 3. Mode selection
HC1 HC0 LSB Useful Data Secondary
FSYNC Description
0 0 0 15bits No Software Mode for Data Transfer only.
0 0 1 15bits (+16bits reg.) Yes Software Mode for Data Transfer + Control
Register Transfer.
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STLC7550 Functional description
Rev 9 13/24
Figure 9. Data Mode
Figure 10. Mixed Mode
2.6 Control register
This section defines the control and device status information. The register programming
occurs only during Secondary Frame Synchronization. After a reset condition, the device is
always in data mode.
0 1 X 16bits No Hardware Mode for Data Transfer only.
1 X X 16bits (+16bits reg.) Yes Hardware Mode for Data Transfer +
Control Register Transfer.
Table 3. Mode selection (continued)
HC1 HC0 LSB Useful Data Secondary
FSYNC Description
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 - D15 D14--
--
FS
SCLK
TxDI
HC1, HC0
Sampling period
00 or 01
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 - D15 D14--
--
TxDO
Sampling Period
1/2 Sampling Period (see Note)
FS
TxDI
HC1, HC0
1X
Data Word Input Control Word
01
SCLK
TxDO
Data Word Output Register Word
Note :
In slave mode, this 1/2 Sampling Period is not mandatory. If 1/2 Sampling Period is not provided, one sample is lost.
Table 4. Bits Assignment
Bits Name Function Reset Value
0 - - 0
1 D1 Aux/Main Input 0
2 D2 Receive Gain 0
Obsolete Product(s) - Obsolete Product(s)
Functional description STLC7550
14/24 Rev 9
Note: 1 Not recommended case. Performances could be reduced.
3 D3 Oversampling bit 0 0
4 D4 Oversampling bit 1 0
5 D5 Oversampling bit 2 0
6 D6 Attenuator transmit bit 0 0
7 D7 Attenuator transmit bit1 0
8 M M Divider 1
9 Q0 Q0 Divider 1
10 Q1 Q1 Divider 0
11 Q2 Q2 Divider 0
12 T0 M Divider and Test mode bit 0 0
13 T1 M Divider and Test mode bit 1 0
14 TEST2 Test mode bit 2 0
15 TEST3 Test mode bit 3 0
Table 5. Aux/Main Input
D1 Function
0 Main Receive Input
1 Auxiliary Receive Input
Table 6. Receive Gain
D2 Function
DIFFERENTIAL INPUT
0 0dB gain (commun mode fixed)
1 +6dB gain (commun mode non-fixed)
SINGLE ENDED (one input used, other at VCM)
0 -6dB gain (see Note 1)
1 0dB gain
Table 4. Bits Assignment (continued)
Bits Name Function Reset Value
Table 7. Oversampling Ratio
D5 D4 D3 Function
0 0 0 160
0 0 1 192
0 1 0 Reserved
0 1 1 Reserved
Obsolete Product(s) - Obsolete Product(s)
STLC7550 Functional description
Rev 9 15/24
This two bits must be set to 0 for normal operation.
1 0 0 Reserved
1 0 1 64
1 1 0 96
1 1 1 128
Table 8. Transmit Attenuation
D7 D6 Function
0 0 Infinite
0 1 Reserved
1 0 -6dB
1 1 0dB
Table 9. Q Divider Clock Generator
D11 D10 D9 Function
0 0 0 Q divider = 5
0 0 1 Q divider = 6
0 1 0 Q divider = 7
0 1 1 Q divider = 8
1 0 0 Q divider = 4.5
1 0 1 Q divider = 5.5
1 1 0 Q divider = 6.5
1 1 1 Q divider = 7.5
Table 10. M Divider Clock Generator
D13 D12 D8 Function
0 0 0 M divider = 3
0 0 1 M divider = 4
0 1 X Reserved
1 0 X Reserved
1 1 0 M divider = 1
1 1 1 M divider = 2
Table 11. Reserved Mode
D15 D14 Function
X X Reserved for test
Table 7. Oversampling Ratio (continued)
D5 D4 D3 Function
nu TA
Obsolete Product(s) - Obsolete Product(s)
Electrical Specifications STLC7550
16/24 Rev 9
3 Electrical Specifications
Unless otherwise noted, Electrical Characteristics are specified over the operating range.
Typical values are given for VDD = 3V, Tamb = 25°C and for nominal Master clock frequency
MCLK = 1.536MHz and oversampling ratio = 160.
3.1 Absolute maximum ratings
3.2 Nominal DC Characteristics
Table 12. Absolute Maximum Ratings (referenced to GND)
Symbol Parameter Value Unit
VDD DC Supply Voltage -0.3, 7.0 V
VI,VIN Digital or Analog Input Voltage -0.3, VDD+0.3 V
II,IIN Digital or Analog Input Current ±1 mA
IO Digital Output Current ±20 mA
IOUT Analog Output Current ±10 mA
Toper Operating Temperature 0, 70 °C
Tstg Storage Temperature -40, 125 °C
PDMAX Maximum Power Dissipation 200 mW
ESD Electrostatic Discharge 2000 V
Table 13. Nominal DC Characteristics
(VDD = 3V ± 5%, GND = 0V, TA = 0 to 70°C unless otherwise specified)
Symbol Parameter Min. Typ. Max. Unit
VDD Supply Voltage Range 2.70 3 5.5 V
POWER SUPPLY AND COMMON MODE VOLTAGE
SINGLE POWER SUPPLY (DVDD= AVDD)
IDDA Analog Supply Current 6 mA
IDDD Digital Supply Current 4 mA
IDD-LP
Supply Current in Low Power Mode
MCLK Stopped
MCLK Running
1
200
10 µA
VCM
Output Common Mode Voltage VCM Output
Voltage Load Current (see Note 1) VDD/2-5% VDD/2 VDD/2+5% V
DIGITAL INTERFACE
VIL Low Level Input Voltage -0.3 0.5 V
VIH High Level Input Voltage DVDD-0.5 V
DD
Obsolete Product(s) - Obsolete Product(s)
STLC7550 Electrical Specifications
Rev 9 17/24
Note: 1 Device is very sensitive to noise on VCM Pin. VCM output voltage load current must be DC
(<10µA). in order to drive dynamic load, VCM must be buffered. AC variation in VCM current
magnitude decrease A/D and D/A performance.
3.3 Nominal AC Electrical Characteristics
II Input Current VI = VDD or VI = GND -10 ±1 10 µA
VOH High Level Output Voltage (ILOAD= -600µA) DVDD-0.5 V
VOL Low Level Output Voltage (ILOAD= 800µA) 0.3 V
ANALOG INTERFACE
VREF Differential Reference Voltage Output
VREF = (VREFP- VREFN) 1.15 1.25 1.35 V
Tcoeff (VREF)V
REF Temperature Coefficient 200 ppm/°C
VCMO IN Input Common Mode Offset Voltage
VCMO IN = [(IN+)+(IN-)]/2 -VCM -100 100 mV
VDIF IN Differential Input Voltage : [(IN+)-(IN-)] 2 x VREF 2 x VREF Vpp
VOFF IN Differential Input DC Offset Voltage -100 100 mV
VCMO OUT
Output Common Mode Voltage Offset :
(OUT+ + OUT-)/2 - VCM (see Note 1) -20 20 mV
VDIF OUT
Differential Output Voltage :
OUT+ - OUT- 2 x VREF 2 x VREF V
VOFF OUT
Differential Output DC Offset Voltage :
(OUT+ -OUT-) (0000x) -100 100 mV
RIN Input Resistance IN+, IN- (id. AUX IN) 100 k
ROUT Output Resistance (OUT+, OUT-) 50 W
RL Load Resistance (OUT+, OUT-) 10 k
CL Load Capacitance (OUT+, OUT-) 20 pF
VADO OUT Output A/D Modulator Voltage Offset:
IN+ = IN- = VCM -1000 +1000 LSB
Table 13. Nominal DC Characteristics (continued)
(VDD = 3V ± 5%, GND = 0V, TA = 0 to 70°C unless otherwise specified)
Symbol Parameter Min. Typ. Max. Unit
Table 14. Nominal AC Electrical Characteristics
(Reference level VIL = 0.5V, VIH = DVDD - 0.5V, VOL = 0.3V, VOH = DVDD - 0.5V, DVDD = 3V,
Output load = 50pF unless otherwise)
Symbol N° Parameter Min. Typ. Max. Unit
SERIAL CHANNEL TIMING (see Figure 11 for Parameter numbers)
1 SCLK Period 300 ns
2 SCLK Width Low 150 ns
Obsolete Product(s) - Obsolete Product(s)
Electrical Specifications STLC7550
18/24 Rev 9
Figure 11. Serial Interface Timing Diagram
3 SCLK Width High 150 ns
4 SCLK Rise Time 10 ns
5 SCLK Fall Time 10 ns
6 FS Setup 100 ns
7 FS Hold 100 ns
8 DIN Setup 50 ns
9 DIN Hold 0 ns
10 DOUT Valid 20 ns
11 HC0,HC1 Set-up 20 ns
12 0 50 ns
MASTER CLOCK INTERFACE (MCLK) (MCM = 0)
MCLK Master Clock Input 0.92 1.54 2.8 MHz
Master Clock Duty Cycle 45 55 %
Table 14. Nominal AC Electrical Characteristics (continued)
(Reference level VIL = 0.5V, VIH = DVDD - 0.5V, VOL = 0.3V, VOH = DVDD - 0.5V, DVDD = 3V,
Output load = 50pF unless otherwise)
Symbol N° Parameter Min. Typ. Max. Unit
SCLK
FS
DIN
1
67
10
89
2.4 35
MSB
MSB
DOUT
HC0
11
12
Obsolete Product(s) - Obsolete Product(s)
STLC7550 Electrical Specifications
Rev 9 19/24
3.4 Transmit Characteristics
3.4.1 Performance of the Tx channel
Note: 1 The dynamic range can be measured in bit with : Nbit = with DR in dB.
3.4.2 Smoothing filter transfer characteristics
The cut-off frequency of the single pole switch-capacitor low-pass filter following the DAC is :
with n = 2, 3, 4, 5, 6 (see Section 2.1.1).
3.5 Receive Characteristics
3.5.1 Performance of the Rx channel
Table 15. Performance of the Tx channel
Typical values are given for AVDD = 3V, Tamb = 25°C and for nominal master
clock MCLK = 1.536MHz, differential mode and oversampling ratio = 160.
Measurement band = 100Hz to 0.425 x Sampling frequency.
Symbol Parameter Min. Typ. Max. Unit
Gabs Absolute Gain at 1kHz -0.5 0 0.5 dB
Ripple Ripple in Band : 0 to 0.425 x FS ±0.2 dB
THD Total Harmonic Distortion (differential Tx signal :
VOUT = 1.25VPP
, f = 1kHz) -85 -92 dB
DR
Dynamic Range (f = 1kHz) (measured over the
full 0 to FS/2 with a -20dBr output signal and
extrapolated to full scale) (see Note 1)
87 dB
CRxTx Crosstalk (transmit channel to receive channel) 85 dB
DR 1.76
6.02
--------------------------
fc 3dB
n32FS⋅⋅
2π10⋅⋅
---------------------------=
Table 16. Performance of the Rx channel
Typical values are given for AVDD = 3V, Tamb = 25°C and for nominal master
clock MCLK = 1.536MHz, differential mode and oversampling ratio = 160.
Measurement band = 100Hz to 0.425 x Sampling frequency.
Symbol Parameter Min. Typ. Max. Unit
Gabs Absolute Gain at 1kHz -0.5 0 0.5 dB
Ripple Ripple in Band : 0 to 0.425 x FS ±0.2 dB
THD Total Harmonic Distortion (differential Tx signal :
VOUT = 1.25VPP
, f = 1kHz) -85 -92 dB
DR
Dynamic Range (f = 1kHz) (measured over the
full 0 to FS/2 with a -20dBr output signal and
extrapolated to full scale) (see Note 2)
87 dB
CRxTx Crosstalk (transmit channel to receive channel) 85 dB
TEL ‘E E I
Obsolete Product(s) - Obsolete Product(s)
Typical application STLC7550
20/24 Rev 9
4 Typical application
Figure 12. Line Interface - Differential Duplexor
All capacitor, resistor and impedance values are provided for indication only. These values
must be readjusted according to line transformer characteristics and also
telecommunication regulations in force in individual countries.
Refer to Application Note AN930 for more detailed information. Contact your local
representative.
22k
22k
100pF
VCM
22k
22k
100pF
680pF
13.2k
13.2k
OUT-
OUT+
C'
1.2k
1.2k
2.2nF
VCM
2.2nF
C
2R
Z0/2
C
2R
Z0/2
R
R
Phone
Line
C : Improve the low frequency response.
Its value depends on the transformer inductance.
C' : Reduces the DC offset gain.
Z0 : Nominal line impedance
IN+
IN-
R'
r
R'
Obsolete Product(s) - Obsolete Product(s)
STLC7550 Definition and Terminology
Rev 9 21/24
5 Definition and Terminology
Data Transfer Interval The time during which data is transfered from DOUTand to
DIN. This interval is 16 shift clocks provides by the chip.
Signal Data This refers to the input signal and all the converted
representations through the ADC channel and the DAC
channel.
Data Mode This refers to the data transfer. Since the device is
synchronous, the signal data words from the ADC channel
and to the DAC channel occur simultaneously.
Control Mode This refers to the digital control data transfer into DIN and
the register read data from DOUT. The control mode interval
occurs when requested by hardware or software.
Frame Sync. Frame sync refers only to the falling edge of the signal which
initiates the data transfer interval. The primary frame sync
starts the Data Mode and the secondary frame sync starts
the Control Mode.
Frame Sync and Sampling
Period
The time between falling edges of successive primary frame
sync signals.
ADC Channel This term refers to all signal processing circuits between the
analog input and the digital conversion result at DOUT.
DAC Channel This term refers to all signal processing circuits between the
digital data word applied to DINand the differential output
analog signal available at OUT+ and OUT-pins.
OverSampling Ratio This term refer to the ratio between the master clock MCLK
corresponding to the oversampling frequency and the
sampling frequency FS.
Resolution The number of bits in the input words to the DAC, and the
output words in the ADC.
Dynamic Range The S/(N+D) with a 1kHz, -20dBr input signal and
extrapolated to full scale. Use of a small input signal reduces
the harmonic distortion components of the noise to
insignificance. Units in dB or in Nbitas explained before.
Signal-to-
(Noise+Distortion)
S/(THD+N) is the ratio of the rms of the input signal to the
rms of all other spectral components within the
measurement bandwidth (0.425 x Sampling Frequency).
Units in dB.
Crosstalk The amount of 1kHz signal present on the output of the
grounded input channel with 1kHz 0dB signal present on the
other channel. Units in dB.
Power Supply Rejection
Ratio
PSRR. The amount of 1kHz signal present on the output of
the grounded input channel with 1kHz 200mVPPsignal
present on the power supply.
ma mm Q 0C3 mch saws “MNE
Obsolete Product(s) - Obsolete Product(s)
Package information STLC7550
22/24 Rev 9
6 Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
Figure 13. TQFP48 (7 x 7 x 1.4mm) Mechanical Data & Package Dimensions
Body: 7 x 7 x 1.40mm
DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 1.60 0.063
A1 0.05 0.15 0.002 0.006
A2 1.35 1.40 1.45 0.053 0.055 0.057
B 0.17 0.22 0.27 0.006 0.008 0.010
C 0.09 0.20 0.004 0.008
D 9.00 0.354
D1 7.00 0.276
D3 5.50 0.217
e 0.50 0.020
E 9.00 0.354
E1 7.00 0.276
E3 5.50 0.217
L 0.45 0.60 0.75 0.018 0.024 0.030
L1 1.00 0.039
K(min.), 3.5˚(typ.), 7°(max.)
TQFP48
OUTLINE AND
MECHANICAL DATA
Obsolete Product(s) - Obsolete Product(s)
STLC7550 Revision history
Rev 9 23/24
7 Revision history
Table 17. Document revision history
Date Revision Changes
14-Jan-2004 8Initial release.
06-Feb-2006 9
Removed the TQFP44 package and the respective ordering
part number.
Inserted the new part number E-STLC7550TQF7 (ECOPACK).
Obsolete Product(s) - Obsolete Product(s)
STLC7550
24/24 Rev 9
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