MCP1406,07 Datasheet by Microchip Technology

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MICRQICHIP MCP1406/07
2006-2016 Microchip Technology Inc. DS20002019C-page 1
MCP1406/07
Features
High Peak Output Current: 6.0A (typical)
Low Shoot-Through/Cross-Conduction Current in
Output Stage
Wide Input Supply Voltage Operating Range:
-4.5Vto18V
High Capacitive Load Drive Capability:
- 2500 pF in 20 ns
- 6800 pF in 40 ns
Short Delay Times: 40 ns (typical)
Matched Rise/Fall Times
Low Supply Current:
- With Logic ‘1’ Input – 130 µA (typical)
- With Logic ‘0’ Input – 35 µA (typical)
Latch-Up Protected: Will Withstand 1.5A Reverse
Current
Logic Input Will Withstand Negative Swing up to 5V
Pin compatible with the TC4420/TC4429 devices
Space-saving 8-Pin SOIC, PDIP and
8-Pin 6 x 5 mm DFN Packages
Applications
Switch Mode Power Supplies
Pulse Transformer Drive
Line Drivers
Motor and Solenoid Drive
General Description
The MCP1406/07 devices are a family of
buffers/MOSFET drivers that feature a single-output
with 6A peak drive current capability, low shoot-through
current, matched rise/fall times and propagation delay
times. These devices are pin-compatible and are
improved versions of the TC4420/TC4429 MOSFET
drivers.
The MCP1406/07 MOSFET drivers can easily charge
and discharge 2500 pF gate capacitance in under
20 ns, provide low enough impedances (in both the ON
and OFF states) to ensure that intended state of the
MOSFETs will not be affected, even by large transients.
The input to the MCP1406/07 may be driven directly
from either TTL or CMOS (3V to 18V).
These devices are highly latch-up resistant under any
conditions that fall within their power and voltage
ratings. They are not subject to damage when up to 5V
of noise spiking (of either polarity) occurs on the ground
pin. All terminals are fully protected against
electrostatic discharge (ESD), up to 2.0 kV (HBM) and
400V (MM).
The MCP1406/07 single-output 6A MOSFET driver
family is offered in both surface-mount and
pin-through-hole packages with a -40°C to +125°C
temperature rating, making it useful in any wide
temperature range application.
6A High-Speed Power MOSFET Drivers
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MCP1406/07
DS20002019C-page 2 2006-2016 Microchip Technology Inc.
Package Types
1
2
3
45
6
7
8
VDD VDD
OUT
OUT
GND GND
INPUT
NC
8-Pin PDIP/SOIC
MCP1407MCP1406
VDD
OUT
OUT
GND
VDD
GND
INPUT
NC
5-Pin TO-220
MCP1407
MCP1406
VDD
OUT
OUT
GND
Tab is common to VDD
Note 1: Duplicate pins must both be connected for proper operation.
2: Exposed pad of the DFN package is electrically isolated; see Table 3-1.
1
2
3
45
6
7
8
VDD
GND
INPUT
NC
VDD
GND
INPUT
OUT
GND
12345
MCP1406
VDD
GND
INPUT
OUT
GND
12345
MCP1407
1
2
3
4
8
7
6
5
EP
9
VDD
GND
INPUT
NC
VDD
OUT
OUT
GND
1
2
3
4
8
7
6
5
EP
9
8-Pin 6x5 DFN-S(2)
2006-2016 Microchip Technology Inc. DS20002019C-page 3
MCP1406/07
Functional Block Diagram(1)
Effective
Input C = 25 pF
MCP1406 Inverting
MCP1407 Non-Inverting
Input
GND
VDD
300 mV
4.7V
Inverting
Non-Inverting
Note 1: Unused inputs should be grounded.
130 µA
Output
Output
MCP1406/07
DS20002019C-page 4 2006-2016 Microchip Technology Inc.
1.0 ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
Supply Voltage ................................................................+20V
Input Voltage ..................................(VDD +0.3V) to (GND -5V)
Input Current (VIN > VDD) ..............................................50 mA
Package Power Dissipation (TA <= +70°C)
DFN-S .......................................................................2.5W
PDIP..........................................................................1.2W
SOIC .......................................................................0.83W
TO-220 ......................................................................3.9W
ESD Protection on all Pins ................2 kV (HBM), 400V (MM)
Notice: Stresses above those listed under “Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational sections of this
specification is not intended. Exposure to maximum
rating conditions for extended periods may affect
device reliability.
DC CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, TA = +25°C, with 4.5VVDD18V.
Parameters Sym. Min. Typ. Max. Units Conditions
Input
Logic ‘1’, High Input Voltage VIH 2.4 1.8 V
Logic ‘0’, Low Input Voltage VIL —1.30.8 V
Input Current IIN –10 10 µA 0VVINVDD
Input Voltage VIN -5 — VDD +0.3 V
Output
High Output Voltage VOH VDD – 0.025 V DC Test
Low Output Voltage VOL 0.025 V DC Test
Output Resistance, High ROH —2.12.8 IOUT = 10 mA, VDD = 18V
Output Resistance, Low ROL —1.52.5 IOUT = 10 mA, VDD = 18V
Peak Output Current IPK —6 —AV
DD 18V (Note 1)
Continuous Output Current IDC 1.3 A Note 1, Note 2
Latch-Up Protection Withstand
Reverse Current
IREV 1.5 A Duty cycle2%, t 300 µs
Switching Time (Note 3)
Rise Time tR—20 30nsFigure 4-1, Figure 4-2
CL = 2500 pF
Fall Time tF—20 30nsFigure 4-1, Figure 4-2
CL = 2500 pF
Delay Time tD1 —40 55nsFigure 4-1, Figure 4-2
Delay Time tD2 —40 55nsFigure 4-1, Figure 4-2
Power Supply
Supply Voltage VDD 4.5 — 18.0 V
Power Supply Current IS 130 250 µA VIN = 3V
IS 35 100 µA VIN = 0V
Note 1: Tested during characterization, not production tested.
2: Valid for AT (TO-220) and MF (DFN-S) packages only. TA = +25°C
3: Switching times ensured by design.
2006-2016 Microchip Technology Inc. DS20002019C-page 5
MCP1406/07
DC CHARACTERISTICS (OVER OPERATING TEMPERATURE RANGE)
Electrical Specifications: Unless otherwise indicated, operating temperature range with 4.5V VDD18V.
Parameters Sym. Min. Typ. Max. Units Conditions
Input
Logic ‘1’, High Input Voltage VIH 2.4 — — V
Logic ‘0’, Low Input Voltage VIL ——0.8V
Input Current IIN -10 +10 µA 0VVINVDD
Input Voltage VIN -5 — VDD+0.3 V
Output
High Output Voltage VOH VDD – 0.025 V DC TEST
Low Output Voltage VOL 0.025 V DC TEST
Output Resistance, High ROH —3.05.0IOUT = 10 mA, VDD = 18V
Output Resistance, Low ROL —2.35.0IOUT = 10 mA, VDD = 18V
Switching Time (Note 1)
Rise Time tR—2540nsFigure 4-1, Figure 4-2
CL = 2500 pF
Fall Time tF—2540nsFigure 4-1, Figure 4-2
CL = 2500 pF
Delay Time tD1 —5065nsFigure 4-1, Figure 4-2
Delay Time tD2 —5065nsFigure 4-1, Figure 4-2
Power Supply
Supply Voltage VDD 4.5 — 18.0 V
Power Supply Current IS—200500µAV
IN = 3V
—50150 V
IN = 0V
Note 1: Switching times ensured by design.
“JA
MCP1406/07
DS20002019C-page 6 2006-2016 Microchip Technology Inc.
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise noted, all parameters apply with 4.5V VDD 18V.
Parameters Sym. Min. Typ. Max. Units Conditions
Temperature Ranges
Specified Temperature Range TA-40 +125 °C
Maximum Junction Temperature TJ +150 °C
Storage Temperature Range TA-65 +150 °C
Package Thermal Resistances
Junction-to-Ambient Thermal Resistance,
8-L 6x5 DFN
JA —31.8 —°C/WNote 1
Junction-to-Ambient Thermal Resistance, 8-L PDIP JA —65.2 —°C/WNote 1
Junction-to-Ambient Thermal Resistance, 8-L SOIC JA —96.3 —°C/WNote 1
Junction-to-Ambient Thermal Resistance,
5-L TO-220
JA —20.1 —°C/WNote 1
Junction-to-Case (Bottom) Thermal Resistance,
5-L TO-220
JC(BOT) 3.2 °C/W Note 2
Junction-to-Top Characterization Parameter,
8-L 6x5 DFN
JT 0.2 °C/W Note 1
Junction-to-Top Characterization Parameter,
8-L PDIP
JT 8.8 °C/W Note 1
Junction-to-Top Characterization Parameter,
8-L SOIC
JT 3.2 °C/W Note 1
Junction-to-Top Characterization Parameter,
5-L TO-220
JT 3.6 °C/W Note 1
Junction-to-Board Characterization Parameter,
8-L 6x5 DFN
JB 15.5 °C/W Note 1
Junction-to-Board Characterization Parameter,
8-L PDIP
JB 36.1 °C/W Note 1
Junction-to-Board Characterization Parameter,
8-L SOIC
JB 60.7 °C/W Note 1
Junction-to-Board Characterization Parameter,
5-L TO-220
JB 4.0 °C/W Note 1
Note 1: Parameter is determined using a High 2S2P 4-layer board, as described in JESD 51-7, as well as in JESD
51-5, for packages with exposed pads.
2: Parameter is determined using a 1S0P 2-layer board with a cold plate attached to indicated location.
man or FIGURE 2-1: Rise Time vs. Supp/y FIGURE 2-4: Fall Time vs. Supply / FIGURE 2-2: Rise Time vs. Capacitive FIGURE 2-5: Fall Time vs. Capacitive FIGURE 2-3: Rise and Fall Times vs. FIGURE 2-6: Propagation Delay vs.
2006-2016 Microchip Technology Inc. DS20002019C-page 7
MCP1406/07
2.0 TYPICAL PERFORMANCE CURVES
Note: Unless otherwise indicated, TA= +25°C with 4.5V VDD 18V.
FIGURE 2-1: Rise Time vs. Supply
Voltage.
FIGURE 2-2: Rise Time vs. Capacitive
Load.
FIGURE 2-3: Rise and Fall Times vs.
Temperature.
FIGURE 2-4: Fall Time vs. Supply
Voltage.
FIGURE 2-5: Fall Time vs. Capacitive
Load.
FIGURE 2-6: Propagation Delay vs.
Supply Voltage.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
0
20
40
60
80
100
120
4 6 8 1012141618
Supply Voltage (V)
Rise Time (ns)
100 pF
4,700 pF
1,000 pF
6,800 pF
2,500 pF
10,000 pF
8,200 pF
0
10
20
30
40
50
60
70
80
100 1000 10000
Capacitive Load (pF)
Rise Time (ns)
5V
15V
10V
0
5
10
15
20
25
30
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (oC)
Rise and Fall Time (ns)
VDD = 18V
tRISE
tFALL
0
10
20
30
40
50
60
70
80
4 6 8 1012141618
Supply Voltage (V)
Fall Time (ns)
100 pF
4,700 pF
1,000 pF
6,800 pF
2,500 pF
10,000 pF 8,200 pF
0
10
20
30
40
50
60
70
100 1000 10000
Capacitive Load (pF)
Fall Time (ns)
5V
15V
10V
35
45
55
65
75
85
4 6 8 10 12 14 16 18
Supply Voltage (V)
Propagation Delay (ns)
VIN = 5V
tD1
tD2
FIGURE 2-7: Propagation Delay Time vs. FIGURE 2-10: Quiescent Current vs. FIGURE 2-8: Propagation Delay Time vs. FIGURE 2-11: Input Threshold vs. Supply FIGURE 2-9: Quiescent Current vs. FIGURE 2-12: Input Threshold vs.
MCP1406/07
DS20002019C-page 8 2006-2016 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C with 4.5V VDD 18V.
FIGURE 2-7: Propagation Delay Time vs.
Input Amplitude.
FIGURE 2-8: Propagation Delay Time vs.
Temperature.
FIGURE 2-9: Quiescent Current vs.
Supply Voltage.
FIGURE 2-10: Quiescent Current vs.
Temperature.
FIGURE 2-11: Input Threshold vs. Supply
Voltage.
FIGURE 2-12: Input Threshold vs.
Temperature.
25
50
75
100
125
150
175
200
2345678910
Input Amplitude (V)
Propagation Delay (ns)
VDD = 12V
tD1
tD2
30
35
40
45
50
55
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (oC)
Propagation Delay (ns)
VDD = 18V
VIN = 5V
tD1
tD2
0
20
40
60
80
100
120
140
160
180
4 6 8 10 12 14 16 18
Supply Voltage (V)
Quiescent Current (µA)
INPUT = 1
INPUT = 0
0
50
100
150
200
250
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (oC)
Quiescent Current (µA)
Input = Low
VDD = 18V
Input = High
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2
4 6 8 1012141618
Supply Voltage (V)
Input Threshold (V)
VHI
VLO
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (oC)
Input Threshold (V)
VDD = 12V VHI
VLO
J FIGURE 2-13: Supply Current vs. FIGURE 2-16: Supply Current vs. / f :fi/ A FIGURE 2-14: Supply Current vs. FIGURE 2-17: Supply Current vs. / 4 FIGURE 2-15: Supply Current vs. FIGURE 2-18: Supply Current vs.
2006-2016 Microchip Technology Inc. DS20002019C-page 9
MCP1406/07
Note: Unless otherwise indicated, TA = +25°C with 4.5VVDD 18V.
FIGURE 2-13: Supply Current vs.
Capacitive Load.
FIGURE 2-14: Supply Current vs.
Capacitive Load.
FIGURE 2-15: Supply Current vs.
Capacitive Load.
FIGURE 2-16: Supply Current vs.
Frequency.
FIGURE 2-17: Supply Current vs.
Frequency.
FIGURE 2-18: Supply Current vs.
Frequency.
0
25
50
75
100
125
150
100 1000 10000
Capacitive Load (pF)
Supply Current (mA)
500 kHz
1 MHz
200 kHz
100 kHz
VDD = 18V
50 kHz
0
25
50
75
100
125
150
100 1000 10000
Capacitive Load (pF)
Supply Current (mA)
500 kHz
1 MHz
200 kHz
100 kHz
VDD = 12V
50 kHz
2 MHz
0
10
20
30
40
50
60
70
80
90
100
100 1000 10000
Capacitive Load (pF)
Supply Current (mA)
500 kHz
1 MHz
200 kHz
100 kHz
VDD = 6V
50 kHz
2 MHz
0
20
40
60
80
100
120
10 100 1000
Frequency (kHz)
Supply Current (mA)
100 pF
4,700 pF
1,000 pF
6,800 pF
VDD = 18V
2,500 pF
10,000 pF
0
10
20
30
40
50
60
70
80
10 100 1000
Frequency (kHz)
Supply Current (mA)
100 pF
4,700 pF
1,000 pF
6,800 pF
VDD = 12V
2,500 pF
10,000 pF
0
5
10
15
20
25
30
35
40
10 100 1000
Frequency (kHz)
Supply Current (mA)
100 pF
4,700 pF
1,000 pF
6,800 pF
VDD = 6V
2,500 pF
10,000 pF
FIGURE 2-19: Output Resistance FIGURE 2-20: Output Resistance FIGURE 2-21: Crossover Energy vs.
MCP1406/07
DS20002019C-page 10 2006-2016 Microchip Technology Inc.
Note: Unless otherwise indicated, TA= +25°C with 4.5V VDD 18V.
FIGURE 2-19: Output Resistance
(Output High) vs. Supply Voltage.
FIGURE 2-20: Output Resistance
(Output Low) vs. Supply Voltage.
FIGURE 2-21: Crossover Energy vs.
Supply Voltage.
1
2
3
4
5
6
7
4 6 8 10 12 14 16 18
Supply Voltage (V)
R
OUT-HI
(:)
VIN = 2.5V (MCP1407)
VIN = 0V (MCP1406)
TJ= +125oC
TJ= +25oC
1
2
3
4
5
6
7
4 6 8 10 12 14 16 18
Supply Voltage (V)
R
OUT-LO
(:)
VIN = 0V (MCP1407)
VIN = 2.5V (MCP1406)
TJ= +125oC
TJ= +25oC
1.00
10.00
100.00
4 6 8 10 12 14 16 18
Crossover Energy (nA sec)
Supply Voltage (V)
2006-2016 Microchip Technology Inc. DS20002019C-page 11
MCP1406/07
3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
3.1 Supply Input (VDD)
VDD is the bias supply input for the MOSFET driver and
has a voltage range of 4.5V to 18V. This input must be
decoupled to ground with local capacitors. The bypass
capacitors provide a localized low-impedance path for
the peak currents that are to be provided to the load.
3.2 Control Input (INPUT)
The MOSFET driver input is a high-impedance,
TTL/CMOS-compatible input. The input also has hys-
teresis between the high and low input levels, allowing
them to be driven from slow rising and falling signals,
and to provide noise immunity.
3.3 Ground (GND)
Ground is the device return pin. The ground pin should
have a low impedance connection to the bias supply
source return. High peak currents will flow out the
ground pin when the capacitive load is being
discharged.
3.4 CMOS Push-Pull Output
(OUTPUT)
The output is a CMOS push-pull output that is capable
of sourcing peak currents of 6A (VDD = 18V). The low
output impedance ensures the gate of the external
MOSFET will stay in the intended state even during
large transients. The output pins also have reverse
current latch-up ratings of 1.5A.
3.5 Exposed Metal Pad (6x5 DFN only)
The exposed metal pad of the DFN package is not
internally connected to any potential. Therefore, this
pad can be connected to a ground plane or other
copper plane on a printed circuit board to aid in heat
removal from the package.
3.6 TO-220 Metal Tab
The metal tab on the TO-220 package is at VDD
potential. This metal tab is not intended to be the VDD
connection to MCP1406/07. VDD should be supplied
using the Supply Input pin of the TO-220.
TABLE 3-1: PIN FUNCTION TABLE(1)
5-Pin
TO-220
8-Pin
6x5 DFN
8-Pin
PDIP, SOIC Symbol Description
—1 1 V
DD Supply Input
1 2 2 INPUT Control Input
3 3 NC No Connection
2 4 4 GND Ground
4 5 5 GND Ground
5 6 6 OUTPUT CMOS Push-Pull Output
7 7 OUTPUT CMOS Push-Pull Output
388V
DD Supply Input
9 EP Exposed Metal Pad
TAB — VDD Metal Tab at VDD Potential
Note 1: Duplicate pins must be connected for proper operation.
Q i W%%T° ; f 10°/ Non-Invemng Driver Timing FIGURE 4-2: Inverting Driver Timing FIGURE 4-1:
MCP1406/07
DS20002019C-page 12 2006-2016 Microchip Technology Inc.
4.0 APPLICATION INFORMATION
4.1 General Information
MOSFET drivers are high-speed, high current devices
which are intended to provide high peak currents to
charge the gate capacitance of external MOSFETs or
IGBTs. In high frequency switching power supplies, the
PWM controller may not have the drive capability to
directly drive the power MOSFET. A MOSFET driver
like the MCP1406/07 family can be used to provide
additional drive current capability.
4.2 MOSFET Driver Timing
The ability of a MOSFET driver to transition from a
fully-OFF state to a fully-ON state are characterized by
the drivers’ rise time (tR), fall time (tF) and propagation
delays (tD1 and tD2). The MCP1406/07 family of
devices is able to make this transition very quickly.
Figure 4-1 and Figure 4-2 show the test circuits and
timing waveforms used to verify the MCP1406/07
timing.
FIGURE 4-1: Inverting Driver Timing
Waveform.
FIGURE 4-2: Non-Inverting Driver Timing
Waveform.
4.3 Decoupling Capacitors
Careful layout and decoupling capacitors are highly
recommended when using MOSFET drivers. Large
currents are required to charge and discharge
capacitive loads quickly. For example, 2.25A are
needed to charge a 2500 pF load with 18V in 20 ns.
To operate the MOSFET driver over a wide frequency
range with low supply impedance, a ceramic and a
low ESR film capacitor are recommended to be placed
in parallel between the driver VDD and the GND. A
1.0 µF low ESR film capacitor and a 0.1 µF
ceramic capacitor placed between pins 1, 8 and 4, 5
should be used. These capacitors should be placed
close to the driver to minimize circuit board parasitics
and provide a local source for the required current.
0.1 µF
+5V
10%
90%
10%
90%
10%
90%
18V
F
0V
0V
MCP1406
CL = 2500 pF
Input
Input
Output
tD1 tF
tD2
Output
tR
VDD = 18V
Ceramic
Input Signal: tRISE = tFALL = 10ns,
100 Hz, 0-5V Square Wave
90%
Input
tD1 tF
tD2
Output tR
10%
10% 10%
+5V
18V
0V
0V
90%
90%
0.1 µF
F
MCP1407
CL = 2500 pF
Input Output
VDD = 18V
Ceramic
Input Signal: tRISE = tFALL = 10ns,
100 Hz, 0-5V Square Wave
NH
2006-2016 Microchip Technology Inc. DS20002019C-page 13
MCP1406/07
4.4 PCB Layout Considerations
Proper PCB layout is important in a high current,
fast switching circuit to provide proper device operation
and robustness of design. PCB trace loop area and
inductance should be minimized by the use of a ground
plane or ground trace located under the MOSFET gate
drive signals, separate analog and power grounds, and
local driver decoupling.
The MCP1406/07 devices have two pins each for VDD,
OUTPUT and GND. Both pins must be used for proper
operation. This also lowers path inductance which will,
along with proper decoupling, help minimize ringing in
the circuit.
Placing a ground plane beneath the MCP1406/07 will
help as a radiated noise shield as well as providing
some heat sinking for power dissipated within the
device.
4.5 Power Dissipation
The total internal power dissipation in a MOSFET driver
is the summation of three separate power dissipation
elements, which can be calculated by using the
following equation:
EQUATION 4-1:
4.5.1 CAPACITIVE LOAD DISSIPATION
The power dissipation caused by a capacitive load is a
direct function of frequency, total capacitive load and
supply voltage. The power lost in the MOSFET driver
for a complete charging and discharging cycle of a
MOSFET can be determined by means of this
equation:
EQUATION 4-2:
4.5.2 QUIESCENT POWER DISSIPATION
The power dissipation associated with the quiescent
current draw depends on the state of the input pin. The
MCP1406/07 devices have a quiescent current draw
when the input is high of 0.13 mA (typ) and 0.035 mA
(typ) when the input is low. The quiescent power dissi-
pation can be determined by using this equation:
EQUATION 4-3:
4.5.3 OPERATING POWER DISSIPATION
The operating power dissipation occurs each time the
MOSFET driver output transitions; this is because, for
a very short period of time, both MOSFETs in the output
stage are ON simultaneously. This cross-conduction
current leads to a power dissipation, as described by
the following equation:
EQUATION 4-4:
PTPLPQPCC
++=
Where:
PT= Total power dissipation
PL= Load power dissipation
PQ= Quiescent power dissipation
PCC = Operating power dissipation
PLfC
TVDD
2
=
Where:
f = Switching frequency
CT = Total load capacitance
VDD = MOSFET driver supply voltage
PQIQH DI
QL 1D+VDD
=
Where:
IQH = Quiescent current in the high state
D = Duty cycle
IQL = Quiescent current in the low state
VDD = MOSFET driver supply voltage
PCC CC fVDD
=
Where:
CC = Cross-conduction constant (A sec.)
f = Switching frequency
VDD = MOSFET driver supply voltage
MEL XXXXXXXX XXXXYYWW 0% O 6‘0 HHHH 0% XXXXXXX XXXXXXX XXYYWW ‘3‘ UUUU 6‘0 \ NNN
MCP1406/07
DS20002019C-page 14 2006-2016 Microchip Technology Inc.
5.0 PACKAGING INFORMATION
5.1 Package Marking Information (Not to Scale)
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
8-Lead SOIC (3.90 mm) Example
MCP1406E
SN ^^1510
256
3
e
YYWWNNN
XXXXXXXXX
XXXXXXXXX
MCP1406
EAT ^^
15102562
5-Lead TO-220 Example
3
e
PIN 1
NNN
PIN 1
8-Lead DFN-S (6x5x0.9 mm) Example
MCP1406
E/MF ^^
1510
256
3
e
Wflflfl Wflflfl 0% 09 LJLALALJ LJLALALJ NNN alor( ‘)
2006-2016 Microchip Technology Inc. DS20002019C-page 15
MCP1406/07
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
XXXXXXXX
XXXXXNNN
YYWW
8-Lead PDIP (300 mil) Example
MCP1407
E/P ^^256
1510
3
e
MCP1406/07
DS20002019C-page 16 2006-2016 Microchip Technology Inc.

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 
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  
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   
   
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   
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   
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E
Q
D
D1
H1
A
A1
A2
c
N
e
e1
b
123
L
CHAMFER
OPTIONAL
Pφ
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\\ \\\ N} \ 4% @,
2006-2016 Microchip Technology Inc. DS20002019C-page 17
MCP1406/07
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 
   
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    
  
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  
    
    
    
    
  
NOTE 2
A1
A
A3
NOTE 1 12
E
N
D
EXPOSED PAD
NOTE 1
21
E2
L
N
e
b
K
BOTTOM VIEW
TOP VIEW
D2
   
8-Lead PIasfic Dual Flat, No Lead Package (MF) - 6x5 mm Body [DFN-S] <—t2——><— )(1="" ejuuv'="" w2="" silk="" screen="" recommended="" land="" pattern="" r="" 1="" i="" i="" i="" i="" l="" l="" note="" this="" package="" may="" also="" be="" i="" i="" used="" with="" the="" 8l="" 301::="" (3.90="" mm)="" :="" :="" land="" pattern="" .="" .="" |="" i="" i="" i="" |="" i="" i,="" 4="" units="" millimeters="" d1mensian="" l1mils="" min="" |="" nom="" i="" max="" comm="" pitch="" e="" 1.27="" bsc="" opuonal="" center="" pad="" width="" w2="" 2.40="" ophonal="" center="" pad="" lenglh="" 12="" 4.10="" comm="" pad="" spacing="" c="" 5.50="" contact="" pad="" width="" (x5)="" x1="" 0.45="" contact="" pad="" length="" (x3)="" v1="" 1.10="" notes:="" 1.="" dimensmmng="" and="" iolerancmg="" perasme="" y14.5m="" asc-="" 8551c="" dimensmn="" theoreucany="" exact="" vaiue="" shown="" wnhom="" loierances="" m1cmchip="" technqugy="" drawmg="" nu="" goa-2122a="">
MCP1406/07
DS20002019C-page 18 2006-2016 Microchip Technology Inc.
 

2006-2016 Microchip Technology Inc. DS20002019C-page 19
MCP1406/07
B
A
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Microchip Technology Drawing No. C04-018D Sheet 1 of 2
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
eB
E
A
A1
A2
L
8X b
8X b1
D
E1
c
C
PLANE
.010 C
12
N
NOTE 1
TOP VIEW
END VIEWSIDE VIEW
e
MCP1406/07
DS20002019C-page 20 2006-2016 Microchip Technology Inc.
Microchip Technology Drawing No. C04-018D Sheet 2 of 2
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
Units INCHES
Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e.100 BSC
Top to Seating Plane A - - .210
Molded Package Thickness A2 .115 .130 .195
Base to Seating Plane A1 .015
Shoulder to Shoulder Width E .290 .310 .325
Molded Package Width E1 .240 .250 .280
Overall Length D .348 .365 .400
Tip to Seating Plane L .115 .130 .150
Lead Thickness c.008 .010 .015
Upper Lead Width b1 .040 .060 .070
Lower Lead Width b.014 .018 .022
Overall Row Spacing eB - - .430
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
3.
1.
protrusions shall not exceed .010" per side.
2.
4.
Notes:
§
--
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
Pin 1 visual index feature may vary, but must be located within the hatched area.
§ Significant Characteristic
Dimensioning and tolerancing per ASME Y14.5M
e
DATUM A DATUM A
e
b
e
2
b
e
2
ALTERNATE LEAD DESIGN
(VENDOR DEPENDENT)
B-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC] //7 / / ’Mx’é/ I l C. 0.10 c D ‘ ' W 2x 2 3 ED 20 NOT“ 2x N/z TIPS <— an="" eie="" -_="" _5®-="" top="" view="" a=""><— am-="" a="" a2="" nx="" seating="" plane="" i="" m="" _="" side="" view=""><— _—=""><_ h="" ll="" qf="" view="" a-a="" microchip="" technology="" drawing="" no.="" comm:="" sheet="" 1="" 012="">
2006-2016 Microchip Technology Inc. DS20002019C-page 21
MCP1406/07
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
B-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC] Unlls MILLlMETERS Dimenslon Limits MIN l NOM l MAX Numberol Plns N a Pitch e 1 27 BSC Overall Heigni A . . 1.75 Molded Package Thickness A2 1.25 . . Slandofl § A1 0.10 . 0.25 Overall Wldm E 6.00 BSC Molded Package Wldm E1 3.90 BSC Overall Length D 4.90 BSC Chamier (Optional) h 0.25 . 0.50 Foot Length L 0.40 . 1.27 Foolpilnl L1 1.04 REF Foot Angle ¢ 0“ . a“ Lead Thickness c 0.17 . 0.25 Lead Wldlh o 0.31 . 0.51 Mold Drafl Angle Top a 5“ . 15° Mold Drafl Angle aotiom fl 5“ . 15° Notes: 1. Pin 1 vlsual lndex reatore may vary, but must be located wilhln the hatched area 2. § Slgniflcanl Characterlstic a Dlmensions D and E1 do not lnclude mold flash or prmmsmns Mold flash or protrusions shall not exceed c.15mrn per side 4. Dlmensronlng ano Iolerancmg per ASME Y‘lA 5M ESC' Easlc DImEnslon Theorellcally Exact Value shown wllhuul IDlErances REF' Re'erence Dlmenslon, usually wllhoul tolerance. for lnlormallon purposes only Mlcrochip Technology Drawing No co4057z: Sheet 2 at 2
MCP1406/07
DS20002019C-page 22 2006-2016 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Nules' UDE \JLJ / S‘LK SCREEN L4 HUB: <—x1 recommended="" land="" pattern="" umts="" mlll‘meters="" dwmension="" lvmts="" min="" \="" nom="" \="" max="" contad="" fitch="" e="" 1.27="" bsc="" contad="" pad="" spacmg="" c="" 5.40="" contact="" pad="" wmh="" (x8)="" x1="" 0.50="" contad="" pad="" length="" (xx)="" y1="" 1.55="" 1="" dimenswonlng="" and="" lo‘eranclng="" per="" asme="" v14="" sm="" 380="" easlc="" dimensmn="" theoreucauy="" exact="" value="" shown="" wmhout="" ta‘erances="" microcmp="" technology="" drawmg="" no.="" 004—20st="">
2006-2016 Microchip Technology Inc. DS20002019C-page 23
MCP1406/07
+(+%,!-./(()*+01
 

MCP1406/07
DS20002019C-page 24 2006-2016 Microchip Technology Inc.
NOTES:
2006-2016 Microchip Technology Inc. DS20002019C-page 25
MCP1406/07
APPENDIX A: REVISION HISTORY
Revision C (April 2016)
The following is the list of modifications:
Updated the Package Thermal Resistances sec-
tion of Temperature Characteristics table with the
latest information.
Updated Figure 2-21 in Section 2.0 “Typical
Performance Curves”.
Revision B (May 2012)
The following is the list of modifications:
Removed the information referring to the
Electrostatic Discharge from the General
Description section.
Revision A (December 2006)
Original release of this document.
MCP1406/07
DS20002019C-page 26 2006-2016 Microchip Technology Inc.
NOTES:
PART NO. v
2006-2016 Microchip Technology Inc. DS20002019C-page 27
MCP1406/07
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Device: MCP1406: 6A High-Speed MOSFET Driver,
Inverting
MCP1406T: 6A High-Speed MOSFET Driver,
Inverting, Tape and Reel
MCP1407: 6A High-Speed MOSFET Driver,
Non-Inverting
MCP1407T: 6A High-Speed MOSFET Driver,
Non-Inverting, Tape and Reel
Temperature Range: E = -40°C to +125°C
Package: * AT = Plastic Transistor Outline, 5-Lead (TO-220)
MF = Plastic Dual Flat - 6x5 mm Body,
8-Lead (DFN-S)
P = Plastic Dual In-Line - 300 mil Body,
8-Lead (PDIP)
SN = Plastic Small Outline - Narrow, 3.90 mm Body,
8-Lead (SOIC)
* All package offerings are Pb Free (Lead Free)
Examples:
a) MCP1406-E/MF: 6A High-Speed MOSFET
Driver, Inverting,
8LD DFN Package
b) MCP1406-E/AT: 6A High-Speed MOSFET
Driver, Inverting,
5LD TO-220 Package
c) MCP1406-E/SN: 6A High-Speed MOSFET
Driver, Inverting,
8LD SOIC Package
d) MCP1406-E/P: 6A High-Speed MOSFET
Driver, Inverting,
8LD PDIP Package
e) MCP1406T-E/MF: Tape and Reel,
6A High-Speed MOSFET
Driver, Inverting,
8LD DFN Package
f) MCP1406T-E/SN: Tape and Reel,
6A High-Speed MOSFET
Driver, Inverting,
8LD SOIC Package
a) MCP1407-E/MF: 6A High-Speed MOSFET
Driver, Non-Inverting,
8LD DFN Package
b) MCP1407-E/AT: 6A High-Speed MOSFET
Driver, Non-Inverting,
5LD TO-220 Package
c) MCP1407-E/SN: 6A High-Speed MOSFET
Driver, Non-Inverting,
8LD SOIC Package
d) MCP1407-E/P: 6A High-Speed MOSFET
Driver, Non-Inverting,
8LD PDIP Package
e) MCP1407T-E/MF: Tape and Reel,
6A High-Speed MOSFET
Driver, Non-Inverting,
8LD DFN Package
f) MCP1407T-E/SN: Tape and Reel,
6A High-Speed MOSFET
Driver, Non-Inverting,
8LD SOIC Package
PART NO. XXX
PackageTemperature
Range
Device
XXX
Tape & Reel
MCP1406/07
DS20002019C-page 28 2006-2016 Microchip Technology Inc.
NOTES:
YSTEM
2006-2016 Microchip Technology Inc. DS20002019C-page 29
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate,
dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ,
KEELOQ logo, Kleer, LANCheck, LINK MD, MediaLB, MOST,
MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo,
RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O
are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
ClockWorks, The Embedded Control Solutions Company,
ETHERSYNCH, Hyper Speed Control, HyperLight Load,
IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut,
BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, Dynamic Average Matching, DAM, ECAN,
EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip
Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker,
Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2006-2016, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-0450-7
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITYMANAGEMENTS
YSTEM
CERTIFIEDBYDNV
== ISO/TS16949==
6‘ ‘MICROCHIP AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE
DS20002019C-page 30 2006-2016 Microchip Technology Inc.
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Worldwide Sales and Service
07/14/15

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