TC530, 534 Datasheet by Microchip Technology

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Q ‘MICROCHIP TC530/TC534
© 2007 Microchip Technology Inc. DS21433C-page 1
TC530/TC534
Features
Precision (up to 17-Bits) A/D Converter
3-Wire Serial Port
Flexible: User Can Trade Off Conversion Speed
For Resolution
Single Supply Operation
-5V Output Pin
4 Input, Differential Analog MUX (TC530)
Automatic Input Polarity and Overrange Detection
Low Operating Current: 5mA Max
Wide Analog Input Range: ±4.2V Max
Cost Effective
Applications
Precision Analog Signal Processor
Precision Sensor Interface
High Accuracy DC Measurements
General Description
The TC530/TC534 are serial analog data acquisition
subsystems ideal for high precision measurements (up
to 17-bits plus sign). The TC534 consists of a dual
slope integrating A/D converter, negative power
supply generator and 3 wire serial interface port. The
TC530 is identical to the TC534, but adds a four
channel differential input multiplexer. Key A/D
converter operating parameters (Auto Zero and Inte-
gration time) are programmable, allowing the user to
trade conversion time for resolution.
Data conversion is initiated when the RESET input is
brought low. After conversion, data is loaded into the
output shift register and EOC is asserted, indicating
new data is available. The converted data (plus Over-
range and polarity bits) is held in the output shift
register until read by the processor or until the next
conversion is completed, allowing the user to access
data at any time.
The TC530/TC534 timebase can be derived from an
external crystal of 2MHz (max) or from an external fre-
quency source. The TC530/TC534 requires a single 5V
power supply and features a -5V, 10mA output which
can be used to supply negative bias to other
components in the system.
Typical Application
A0 A1 OSCIN
R/W
DIN
DOUT
DCLK
OSCOUT
OSC
RESET
CAP+ CAP–
CAZ
TC530
TC534
CREF
RINT
CINT
TC534
(Only)
(TC530 Only)
DC-TO-DC
Converter
State
Machine
Serial Port
Negative
Supply Output
Oscillator
(÷ 4)
Dual Slope A/D Converter
.01 µF
0.01 µF
Optional
Power-On
Reset Cap
100 kΩ
+5V
DIF.
MUX
(TC534
Only)
AB
CMPTR
BUF INT
CAZ ACOM
VDD
VDD
VDD
VDD
VSS
MCP1525
VREF-
VREF+
VIN-
VIN+
EOC
CH2+
CH3+
CH1+
CH4+
CH4-
CH3-
CH2-
CH1- IN+
IN-
CREF-
CREF+
5V Precision Data Acquisition Subsystems
Obsolete Device
EEEjjjjjjjjjjjjjjjjj 0534CF EEECCCCCCCCCCCCCCCCC
TC530/TC534
DS21433C-page 2 © 2007 Microchip Technology Inc.
Package Types
1
2
3
4
20
19
18
5
6
7
8
17
23
22
21
9
10
11
12
24
25
26
27
28
TC530CPI
TC530COI
16
15
13
14
VSS
CREF-
CREF+
VREF-
VREF+
CINT
CAZ
BUF
ACOM
OSCOUT
VIN-
VIN+
DGND
N/C
VCCD
VDD
DOUT
DCLK
CAP-
AGND
RESET
N/C
OSC
CAP+
OSCIN
DIN
R/W
EOC
28-Pin SOIC
28-Pin PDIP
TC534CPL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
40-Pin PDIP
VCDD
VDD
OSCOUT CAP-
CAP+
OSCIN
DOUT
DCLK
DIN
CH2+
CH3+
CH1+
DGND
AGND
A1
A0
27
26
25
24
23
7
8
9
10
11
N/C
N/C
12 13 14 15 16 17 18 19 20 21 22
38 37 36 35 34
N/C
394041424344
28
29
30
31
32
33
6
5
4
3
2
1
BUF
CAZ
VSS
CINT
N/C
N/C
N/C
OSC
RESET
N/C
N/C
N/C
EOC
N/C
R/W
TC534CKW
44-Pin MQFP
CH4+
CH4-
CH3-
CH2-
CH1-
CREF-
CREF+
VREF-
VREF+
ACOM
VSS
CREF-
CREF+
VREF-
VREF+
CINT
CAZ
BUF
ACOM
A0
CH4-
CH3-
DGND
A1
CH2-
CH1-
CH4+
CH3+
CH2+
CH1+
VCCD
VDD
DOUT
DCLK
CAP-
AGND
RESET
N/C
OSC
CAP+
OSCIN
DIN
R/W
EOC
OSCOUT
N/C
N/C
N/C
N/C
N/C
© 2007 Microchip Technology Inc. DS21433C-page 3
TC530/TC534
1.0 ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
Supply Voltage ......................................................+6V
Analog Input Voltage (VIN+ or VIN-).............VDD to VSS
Logic Input Voltage.........(VDD + 0.3V) to (GND - 0.3V)
Ambient Operating Temperature Range:
PDIP Package (C) ............................... 0°C to +70°C
SOIC Package (C)............................... 0°C to +70°C
MQFP Package (C) ............................. 0°C to +70°C
Storage Temperature Range .............. -65°C to +150°C
† Stresses above those listed under "Absolute Maximum Rat-
ings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at
these or any other conditions above those indicated in the
operation sections of the specifications is not implied. Expo-
sure to Absolute Maximum Rating conditions for extended
periods may affect device reliability.
ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise specifier, VDD = VCCD, CAZ = CREF = 0.47 µF
Parameter Symbol
TA = +25°C TA = 0°C to +70°C
Unit Conditions
Min Typ Max Min Typ Max
Analog Power Supply
Voltage
VDD 4.5 5.0 5.5 4.5 5.5 V
Digital Power Supply Voltage VCCD 4.5 5.0 5.5 4.5 — 5.5 V
Total Power Dissipation PD— —25 — — mWV
DD = VCCD = 5V
Supply Current (VS + PIN)I
S—1.82.5 3.0 mA
Supply Current (VCCD PIN)I
CCD ——1.5 1.7 mAF
OSC = 1 MHz
Analog
Resolution R ±17 ±17 Bits Note 1
Zero Scale Error with Auto
Zero Phase
ZSE 0.5 0.005 0.012 % F.S.
End Point Linearity ENL 0.015 0.030 0.015 0.045 % F.S. Note 1 and
Note 2
Max. Deviation from Best
Straight Line Fit
NL 0.008 0.015 — — % F.S. Note 1 and
Note 2
Zero Scale Temperature
Coefficient
ZSTC —— 1 2µV/°C
Rollover Error SYE .012 .03 % F.S. Note 3
Full Scale Temperature
Coefficient
FSTC — — 10
ppm/°
C
Ext. VREF
T.C. = 0 ppm/°C
Input Current IIN —6 — pAV
IN = 0V
Common-Mode Voltage
Range
VCMR VSS + 1.5 VDD - 1.5 VSS + 1.5 VDD - 1.5 V
Integrator Output Swing VINT VSS + 0.9 VDD - 0.9 VSS + 0.9 VDD - 0.9 V
Analog Input Signal Range VIN VSS + 1.5 VDD -1.5 VSS + 1.5 VDD - 1.5 V
Voltage Reference Range VREF VSS + 1 VDD - 1 VDD + 1 VDD - 1 V
Zero Crossing Comparator
Delay
TD 2.0 3.0 μs
Note 1: Integrate time 66 ms. Auto Zero time 66 ms. VINT (pk) = 4V.
2: End point linearity at ±1/4, ±1/2, and ±3/4. F.S. after full scale adjustment.
3: Rollover error is related to capacitor used for CINT. See Table 6-2, Recommended Capacitor for CINT
.
4: TC534 Only.
TC530/TC534
DS21433C-page 4 © 2007 Microchip Technology Inc.
Serial Port Interface
Input Logic HIGH Level VIH 2.5 2.5 V
Input Logic LOW Level VIL 0.8 0.8 V
Input Current (DI, DO, DCLK)I
IN ——10 — — µA
Logic LOW Output Voltage
(EOC)
VOL 0.2 0.3 0.35 V IOUT = 250 µA
Rise and Fall Times
(EOC, DI, DO)
TR, TF 250 250 ns CL = 10 pF
Crystal Frequency FXTL ——2.0 — 2.0MHz
External Frequency on
OSCIN
FEXT ——4.0 — 4.0MHz
Read Setup Time TRS 1— 1— µs
Read Delay Time TRD 250 250 ns
DCLK to DOUT Delay TDRS 450 — 450 ns
DCLK LOW Pulse Width TPWL 150 150 ns
DCLK HIGH Pulse Width TPWH 150 — 150 ns
Data Ready Delay TDR 200 — 200 ns
Output Resistance ROUT 65 85 100 ΩIOUT = 10 mA
Oscillator Frequency FCLK 100 kHz COSC = 0
VSS Output Current IOUT 10 10 mA
Multiplexer
Maximum Input Voltage VIMMAX -2.5 2.5 -2.5 2.5 V
Drain/Source ON
Resistance
RDSON —610 — — kΩ
ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise specifier, VDD = VCCD, CAZ = CREF = 0.47 µF
Parameter Symbol
TA = +25°C TA = 0°C to +70°C
Unit Conditions
Min Typ Max Min Typ Max
Note 1: Integrate time 66 ms. Auto Zero time 66 ms. VINT (pk) = 4V.
2: End point linearity at ±1/4, ±1/2, and ±3/4. F.S. after full scale adjustment.
3: Rollover error is related to capacitor used for CINT. See Table 6-2, Recommended Capacitor for CINT
.
4: TC534 Only.
VA 05:. F121 flflkHz CAP : wk v._ 5v (CD
© 2007 Microchip Technology Inc. DS21433C-page 5
TC530/TC534
2.0 TYPICAL PERFORMANCE CURVES
FIGURE 2-1: Output Voltage vs. Load
Current.
FIGURE 2-2: Output Ripple vs. Load
Current.
FIGURE 2-3: Oscillator Frequency vs.
Capacitance.
FIGURE 2-4: Output Voltage vs. Output
Current.
FIGURE 2-5: Output Source Resistance
vs. Temperature.
FIGURE 2-6: Oscillator Frequency vs.
Temperature.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range), and therefore outside the warranted range.
LOAD CURRENT (mA)
-5
-4
-3
-2
-1
0
1
2
3
4
5
010203040
50 60 70 80
OUTPUT VOLTAGE (V)
Output Voltage vs. Load Current
T
A
= 25
˚
C
V+ = 5V
Slope 60Ω
LOAD CURRENT (mA)
0 3 45612 78 910
0
25
50
75
100
125
150
175
200
OUTPUT RIPPLE (mV PK-PK)
Output Ripple vs. Load Current
V+ = 5V, T
A
= 25˚C
Osc. Freq. = 100kHz
CAP = 1μF
CAP = 10μF
OSCILLATOR CAPACITANCE (pF)
100
10
1
110 100 1000
OSCILLATOR FREQUENCY (kHz)
Oscillator Frequency vs. Capacitance
TA = +25˚C
V+ = 5V
OUTPUT CURRENT (mA)
068104214161812 20
-0
-1
-3
-2
-4
-5
-7
-6
-8
Output Voltage vs. Output Current
T
A
= 25˚C
OUTPUT VOLTAGE (V)
TEMPERATURE (˚C)
70
80
90
100
60
50
40
-50 025
-25 50 75 100
OUTPUT SOURCE RESISTANCE (Ω)
Output Source Resistance vs. Temperature
V+ = 5V
I
OUT
= 10mA
TEMPERATURE
(
˚C
)
125
150
100
75
50
-50 025-25 50 75 125100
OSCILLATOR FREQUENCY (kHz)
Oscillator Frequency vs. Temperature
V+ = 5V
TC530/TC534
DS21433C-page 6 © 2007 Microchip Technology Inc.
3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE
Pin Number
(TC530)
28-Pin PDIP
Pin Number
(TC530)
28-Pin SOIC
Pin Number
(TC534)
40-Pin PDIP
Pin
Number
(TC534)
44-Pin
MQFP
Sym Description
11140V
SS Analog output. Negative power supply converter output and
reservoir capacitor connection. This output can be used to
provide negative bias to other devices in the system.
22241C
INT Analog output. Integrator capacitor connection and
integrator output.
33342C
AZ Analog input. Auto Zero capacitor connection.
4 4 4 43 BUF Analog output. Integrator capacitor connection and voltage
buffer output.
5 5 5 2 ACOM Analog input. This pin is ground for all of the analog
switches in the A/D converter. It is grounded for most
applications. ACOM and the input common pin (VIN- or
CHX-) should be within the common mode range, CMR.
6663C
REF- Analog Input. Reference cap negative connection.
7774C
REF+ Analog Input. Reference cap positive connection.
8885V
REF- Analog Input. External voltage reference negative
connection.
9996V
REF+ Analog Input. External voltage reference positive
connection.
10 7 CH4- Analog Input. Multiplexer channel 4 negative differential
11 8 CH3- Analog Input. Multiplexer channel 3 negative differential
12 9 CH2- Analog Input. Multiplexer channel 2 negative differential
13 10 CH1- Analog Input. Multiplexer channel 1 negative differential
14 11 CH4+ Analog Input. Multiplexer channel 4 positive differential
15 12 CH3+ Analog Input. Multiplexer channel 3 positive differential
16 13 CH2+ Analog Input. Multiplexer channel 2 positive differential
17 14 CH1+ Analog Input. Multiplexer channel 1 positive differential
10 10 — VN- Analog Input. Negative differential analog voltage input.
11 11 — VIN+ Analog Input. Positive differential analog voltage input.
12 12 18 15 DGND Analog Input. Ground connection for serial port circuit.
19 16 A1 Logic Level Input. Multiplexer address MSB.
20 17 A0 Logic Level Input. Multiplexer address LSB.
14 14 21 18 OSCOUT Analog Input. Timebase for state machine. This pin
connects to one side of an AT-cut crystal having an effective
series resistance of 100Ω (typ) and a parallel capacitance
of 20 pF. If an external frequency source is used to clock
the TC530/TC534 this pin must be left floating.
15 15 22 19 OSCIN Analog Input. This pin connects to the other side of the
crystal described in OSCOUT above. The TC530/TC534
may also be clocked from an external frequency source
connected to this pin. The external frequency source must
be a pulse waveform with a minimum 30% duty cycle and
rise and fall times 15nsec (Max). If an external frequency
source is used, OSCOUT ) must be left floating. A maximum
operating frequency of 2 MHz (crystal) or 4 MHz (external
clock source) is permitted.
© 2007 Microchip Technology Inc. DS21433C-page 7
TC530/TC534
16 16 23 20 DOUT Logic Level Output. Serial port data output pin. This pin is
enabled only when R/W is high.
17 17 24 21 DCLK Logic Input, Positive and Negative Edge Triggered. Serial
port clock. When R/W is high, serial data is clocked out of
the TC530/TC534A (on DOUT) at each high-to-low transition
of DCLK. A/D initialization data (LOAD VALUE) is clocked
into the TC530/TC534 (on DIN) at each low-to-high
transition of DCLK. A maximum serial port DCLK frequency
of 3 MHz is permitted.
18 18 25 22 DIN Logic Level Input. Serial port input pin. The A/D converter
integration time (TINT) and Auto Zero time (TAZ) values are
determined by the LOAD VALUE byte clocked into this pin.
This initialization must take place at power up, and can be
rewritten (or modified and rewritten) at any time. The LOAD
VALUE is clocked into DIN MSB first.
19 19 26 23 R/W Logic Level Input. This pin must be brought low to perform a
write to the serial port (e.g. initialize the A/D converter). The
DOUT pin of the serial port is enabled only when this pin is
high.
20 20 27 24 EOC Open Drain Output. End-of-Conversion (EOC) is asserted
any time the TC530/TC534 is in the AZ phase of
conversion. This occurs when either the TC530/TC534
initiates a normal AZ phase or when RESET is pulled high.
EOC is returned high when the TC530/TC534 exits AZ.
Since EOC is driven low immediately following completion
of a conversion cycle, it can be used as a DATA READY
processor interrupt.
21 21 30 28 RESET Logic Level Input. It is necessary to force the TC530/TC534
into the Auto Zero phase when power is initially applied.
This is accomplished by momentarily taking RESET high.
Using an I/O port line from the microprocessor or by
applying an external system reset signal or by connecting a
0.01 µF capacitor from the RESET input to VDD. Conver-
sions are performed continuously as long as RESET is low
and conversion is halted when RESET is high. RESET may
therefore be used in a complex system to momentarily
suspend conversion (for example, while the address lines
of an input multiplexer are changing state). In this case,
RESET should be pulled high only when the EOC is LOW
to avoid excessively long integrator discharge times which
could result in erroneous conversion. (See Applications
Section).
22 22 32 30 VCCD Analog Input. Power supply connection for digital logic and
serial port. Proper power-up sequencing is critical, see the
Applications section.
23 23 34 32 OSC Input. The negative power supply converter normally runs
at a frequency of 100 kHz. This frequency can be slowed
down to reduce quiescent current by connecting an external
capacitor between this pin and V+DD.
See Section 2.0 “Typical Performance Curves”, Typical
Characteristics.
25 25 37 35 VDD Analog Input. Power supply connection for the A/D analog
section and DC-DC converter. Proper power-up sequencing
is critical, (See the Applications section).
TABLE 3-1: PIN FUNCTION TABLE (CONTINUED)
Pin Number
(TC530)
28-Pin PDIP
Pin Number
(TC530)
28-Pin SOIC
Pin Number
(TC534)
40-Pin PDIP
Pin
Number
(TC534)
44-Pin
MQFP
Sym Description
TC530/TC534
DS21433C-page 8 © 2007 Microchip Technology Inc.
26 26 38 36 CAP+ Analog Input. Storage capacitor positive connection for the
DC/DC converter.
27 27 39 37 AGND Analog Input. Ground connection for DC/DC converter.
28 28 40 38 CAP- Analog Input. Storage capacitor negative connection for the
DC/DC converter.
13, 24 13, 24 28, 29, 31,
33, 35, 36
1, 25, 26,
27, 29, 31,
33, 34, 39,
44
N/C No connect. Do not connect any signal to these pins.
TABLE 3-1: PIN FUNCTION TABLE (CONTINUED)
Pin Number
(TC530)
28-Pin PDIP
Pin Number
(TC530)
28-Pin SOIC
Pin Number
(TC534)
40-Pin PDIP
Pin
Number
(TC534)
44-Pin
MQFP
Sym Description
© 2007 Microchip Technology Inc. DS21433C-page 9
TC530/TC534
4.0 DETAILED DESCRIPTION
4.1 Dual Slope Integrating Converter
The TC530/TC534 dual slope converter operates by
integrating the input signal for a fixed time period, then
applying an opposite polarity reference voltage while
timing the period (counting clocks pulses) for the
integrator output to cross 0V (deintegrating). The
resulting count is read as conversion data.
A simple mathematical expression that describes dual
slope conversion is:
EQUATION 4-1:
EQUATION 4-2:
from which:
EQUATION 4-3:
And therefore:
EQUATION 4-4:
Inspection of Equation 4-4 shows dual slope converter
accuracy is unrelated to integrating resistor and
capacitor values, as long as they are stable throughout
the measurement cycle. This measurement technique
is inherently ratiometric (i.e., the ratio between the TINT
and TDEINT times is equal to the ratio between VIN and
VREF).
Another inherent benefit is noise immunity. Input noise
spikes are integrated, or averaged to zero, during the
integration period. The integrating converter has a noise
immunity with an attenuation rate of at least -20 dB per
decade. Interference signals with frequencies at integral
multiples of the integration period are, for the most part,
completely removed. For this reason, the integration
period of the converter is often established to reject
50/60 Hz line noise. The ability to reject such noise is
shown by the plot of Figure 4-1.
In addition to the two phases required for dual slope
measurement (Integrate and De-integrate), the
TC530/TC534 performs two additional adjustments to
minimize measurement error due to system offset volt-
ages. The resulting four internal operations (conver-
sion phases) performed each measurement cycle are:
Auto Zero (AZ), Integrator Output Zero (IZ), Input
Integrate (INT) and Reference De-integrate (DINT).
The AZ and IZ phases compensate for system offset
errors and the INT and DINT phases perform the actual
A/D conversion.
FIGURE 4-1: Integrating Converter
Normal Mode Rejection.
4.2 Auto Zero Phase (AZ)
This phase compensates for errors due to buffer,
integrator and comparator offset voltages. During this
phase, an internal feedback loop forces a
compensating error voltage on auto zero capacitor
(CAZ). The duration of the AZ phase is programmable
via the serial port (see Section 5.1.1 “AZ and INT
Phase Duration”, AZ and INT Phase Duration).
Integrate Voltage = De-integrate Voltage
1
RINTCINT
------------------------TINT
0
VIN T()dT 1
RINTCINT
------------------------TDEINT
0
VREF
=
(VIN) (RINT)(CINT)
[
(TINT) = (VREF)
]
(RINT)(CINT)
[
(TDEINT)
]
VIN = VREF
[]
TINT
TDEINT
Where:
VREF = Reference Voltage
TINT = Integrate Time
TDEINT = Reference Voltage De-integrate
Time
30
20
10
0
0.1/T 1/T 10/T
Input Frequenc
Normal Mode Rejection (dB)
T = Measurement
Period
TC530/TC534
DS21433C-page 10 © 2007 Microchip Technology Inc.
FIGURE 4-2: Serial Port Timing.
FIGURE 4-3: A/D Converter Timing.
TRD
TRS
TDRS TPWL
R/W
Read Timing
Read Format
Write Format
Write Timing Write Default Timing
EOC
DOUT
DCLK
R/W
EOC
DOUT
DCLK
EOC SGN MSB LSB
OVR
TLS
TDLSTPWL
R/W
DIN
DCLK
TLDL
TLDS
DIN
R/W
DOUT
DCLK
MSB LSB
For Polled vs. Interrupt Operation and Write Value Modified Cycle Use TC520A Data Sheet (DS21431).
R/W
EOC
TDR
AZ
Updated Data
Ready
Updated Data
Ready
INT DINT IZ AZ
Conversion
Phase
Data to Serial
Port Transmit
Register
© 2007 Microchip Technology Inc. DS21433C-page 11
TC530/TC534
4.3 Input Integrate Phase (INT)
In this phase, a current directly proportional to differen-
tial input voltage is sourced into integrating capacitor
CINT
. The amount of voltage stored on CINT at the end
of the INT phase is directly proportional to the applied
differential input voltage. Input signal polarity (sign bit)
is determined at the end of this phase. Converter
resolution and speed is a function of the duration of the
INT phase, which is programmable by the user via the
serial port (see Section 5.1.1 “AZ and INT Phase
Duration”, AZ and INT Phase Duration). The shorter
the integration time, the faster the speed of conversion
(but the lower the resolution). Conversely, the longer
the integration time, the greater the resolution (but at
slower the speed of conversion).
4.4 Reference De-integrate Phase
(DINT)
This phase consists of measuring the time for the
integrator output to return (at a rate determined by the
external reference voltage) from its initial voltage to 0V.
The resulting timer data is stored in the output shift
register as converted analog data.
4.5 Integrator Output Zero Phase (IZ)
This phase ensures the integrator output is at zero volts
when the AZ phase is entered so that only true system
offset voltages will be compensated for.
All internal converter timing is derived from the
frequency source at OSCIN and OSCOUT
. This
frequency source must be either an externally provided
clock signal or an external crystal. If an external clock
is used, it must be connected to the OSCIN pin and the
OSCOUT pin must remain floating. If a crystal is used, it
must be connected between OSCIN and OSCOUT and
be physically located as close to the OSCIN and
OSCOUT pins as possible. In either case, the incoming
clock frequency is divided by four, with the resulting
clock serving as the internal TC530/TC534 timebase.
TC530/TC534
DS21433C-page 12 © 2007 Microchip Technology Inc.
5.0 TYPICAL APPLICATIONS
5.1 Programming the TC530/TC534
5.1.1 AZ AND INT PHASE DURATION
These two phases have equal duration determined by
the crystal (or external) frequency and the timer initial-
ization byte (LOAD VALUE). Timing is selected as
follows:
1. Select Integration Time
Integration time must be picked as a multiple of
the period of the line frequency. For example,
TINT times of 33 ms, 66 ms and 132 ms
maximize 60 Hz line rejection.
2. Estimate Crystal Frequency
Crystal frequencies as high as 2 MHz are
allowed. Crystal frequency is estimated using:
EQUATION 5-1:
3. Calculate LOAD VALUE
EQUATION 5-2:
FIN can be adjusted to a standard value during this
step. The resulting base, -10 LOAD VALUE, must be
converted to a hexadecimal number and then loaded
into the serial port prior to initiating A/D conversion.
5.2 DINT and IZ Phase Timing
The duration of the DINT phase is a function of the
amount of voltage stored on the integrator capacitor
during INT and the value of VREF
. The DINT phase is
initiated immediately following INT and terminated
when an integrator output zero crossing is detected. In
general, the maximum number of counts chosen for
DINT is twice that of INT (with VREF chosen at
VIN(MAX)/2).
5.3 System RESET
The TC530/TC534 must be forced into the AZ state
when power is first applied. A .01 µF capacitor
connected from RESET to VDD (or external system
reset logic signal) can be used to momentarily drive
RESET high for a minimum of 100 ms.
5.4 Design Example
Figure 5-1 shows a typical TC530 interrupt-driven
application. Timing and component values are
calculated from equations and recommendations made
in Section 4.1 “Dual Slope Integrating Converter”
and Section 5.1 “Programming the TC530/TC534”
of this document. The EOC connection to the
processor INT input is for interrupt-driven applications
only. (In polled systems, the EOC output is available on
DOUT).
Given:
1. Pick Integration time (TINT): 66 ms.
2. Estimate crystal frequency.
EXAMPLE 5-1:
3. Calculate LOAD VALUE
EXAMPLE 5-2:
4. Calculate RINT
.
EXAMPLE 5-3:
5. Calculate CINT for maximum (4V) integrator out-
put swing:
2(RES)/TINT
Where:
RES = Desired Converter Resolution (in
counts)
FIN = Input Frequency (in MHz)
INT = Integration Time (in seconds)
[LOAD VALUE]10 256 TINT
()FIN
()
1024
------------------------------
=
Required Resolution
(RES):
16-bits (65,536 counts.)
Maximum: VIN ±2V
Power Supply Voltage: +5V
60Hz System
FIN
2RES
TINT
------------ 2 65536
66ms
----------------------- 2MHz==
LOAD VALUE 256 TINT
()FIN
()
1024
------------------------------
128[]
10
==
128[]
10 80 hex=
RINT
VINMAX
20
------------------- 2
20
------ 100k
Ω
===
WW
© 2007 Microchip Technology Inc. DS21433C-page 13
TC530/TC534
EXAMPLE 5-4:
6. Choose CREF and CAZ based on conversion
rate:
EXAMPLE 5-5:
7. Calculate VREF.
EXAMPLE 5-1:
5.5 Power Supply Sequencing
Improper sequencing of the power supply inputs (VDD
vs. VCCD) can potentially cause an improper power-up
sequence to occur. See Section 5.6 “Circuit
Design/Layout Considerations”, Circuit Design/Lay-
out Considerations. Failing to insure a proper power-up
sequence can cause spurious operation.
5.6 Circuit Design/Layout
Considerations
1. Separate ground return paths should be used
for the analog and digital circuitry. Use of ground
planes and trace fill on analog circuit sections is
highly recommended EXCEPT for in and around
the integrator section and CREF
, CAZ (CINT
,
CREF
, CAZ, RINT). Stray capacitance between
these nodes and ground appears in parallel with
the components themselves and can affect
measurement accuracy.
2. Improper sequencing of the power supply inputs
(VDD vs. VCCD) can potentially cause an
improper power-up sequence to occur in the
internal state machines. It is recommended that
the digital supply, VCCD, be powered up first.
One method of insuring the correct power-up
sequence is to delay the analog supply using a
series resistor and a capacitor. See Figure 5-1,
TC530/TC534 Typical Application.
3. Decoupling capacitors, preferably a higher
value electrolytic or tantulum in parallel with a
small ceramic or tantalum, should be used
liberally. This includes bypassing the supply
connections of all active components and the
voltage reference.
4. Critical components should be chosen for
stability and low noise. The use of a metal-film
resistor for RINT and Polypropylene or
Polyphenelyne Sulfide (PPS) capacitors for
CINT
, CAZ and CREF is highly recommended.
5. The inputs and integrator section are very high
impedance nodes. Leakage to or from these
critical nodes can contribute measurement
error. A guard-ring should be used to protect the
integrator section from stray leakage.
6. Circuit assemblies should be exceptionally
clean to prevent the presence of contamination
from assembly, handling or the cleaning itself.
Minute conductive trace contaminates, easily
ignored in most applications, can adversely
affect the performance of high impedance
circuits. The input and integrator sections should
be made as compact and close to the TC53X as
possible.
7. Digital and other dynamic signal conductors
should be kept as far from the TC53X’s analog
section as possible. The microcontroller or other
host logic should be kept quiet during a
measurement cycle. Background activities such
as keypad scanning, display refreshing and
power switching can introduce noise.
Note: Microchip recommended capacitor:
Evox-Rifa p/n: SMR5 334K50J03L
Note: Microchip recommended capacitor:
Evox-Rifa p/n: SMR5 224K50J02L4.
CINT
TINT
()20 106
×
()
Vs0.9()
------------------------------------------=
.066()20 10 6
×
()=
4.1
---------------------------------------------------
.32
μ
F(use closest value: 0.33
μ
F)=
Conversions/sec = 1/(TAZ + TINT + 2TINT + 2ms)
= 1/(66ms + 66ms + 132ms + 2ms)
= 3.7 conversions/sec
from which CAZ = CREF = 0.22µF (Table 6 -1)
VREF
VS0.9()CINT
()RINT
()
2T
INT
()
-----------------------------------------------------------=
4.1()0.33 1 6
×
()105
()
2 .066
···
()
--------------------------------------------------------=
1.025V=
TC530/TC534
DS21433C-page 14 © 2007 Microchip Technology Inc.
FIGURE 5-1: Typical Application.
A0
A1
RESET
VCCD
VCCD
VDD
VDD
DOUT
DCLK
X1: 2 MHz
R2
100
R1
100 kΩ
100Ω
F
(1.03V)
DIN
R/W
ACOM
OSCIN
OSCOUT
VSS
DGND
CAZ
CAZ
0.22 µF
CIN
0.33 µF
RINT
100 kΩ
TC534
CINT
Analog
Inputs
Channel
Control
C1
.01 µF 10 µF
MUX
IN1+
IN1-
IN2+
IN2-
IN3+
IN3-
IN4+
IN4-
+5V
+5V
–5V
(Optional)
BUF
CREF
0.22 µF
F
+5V
EOC INT
MCU
I/O
I/O
I/O
I/O
.01 µF
.01 µF F
CAP-
CAP+
CREF-
CREF+
VREF-
VREF+ kΩ
cINT REF AZ
© 2007 Microchip Technology Inc. DS21433C-page 15
TC530/TC534
6.0 SELECTING COMPONENT
VALUES FOR THE
TC530/TC534
1. Calculate Integrating Resistor (RINT)
The desired full scale input voltage and amplifier
output current capability determine the value of
RINT
. The buffer and integrator amplifiers each
have a full scale current of 20 µA. The value of
RINT is therefore directly calculated as follows:
EQUATION 6-1:
2. Select Reference (CREF) and Auto Zero (CAZ)
Capacitors.
CREF and CAZ must be low leakage capacitors
(such as polypropylene). The slower the conver-
sion rate, the larger the value CREF must be.
Recommended capacitors for CREF and CAZ are
shown in Tab l e 6- 1 . Larger values for CAZ and
CREF may also be used to limit rollover errors.
TABLE 6-1: CREF AND CAZ SELECTION
6.1 Calculate Integrating Capacitor
(CINT)
The integrating capacitor must be selected to maximize
integrator output voltage swing. The integrator output
voltage swing is defined as the absolute value of VDD
(or VSS) less 0.9V (i.e.,IVDD – 0.9VI or IVSS +0.9VI).
Using the 20 µA buffer maximum output current, the
value of the integrating capacitor is calculated using
Equation 6-2.
EQUATION 6-2:
It is critical that the integrating capacitor have a very
low dielectric absorption. PPS capacitors are an exam-
ple of one such dielectric. Table 6-2 summarizes
various capacitors suitable for CINT
.
TABLE 6-2: RECOMMENDED CAPACITOR
FOR CINT
6.2 Calculate VREF
The reference de-integration voltage is calculated
using the following equaton:
EQUATION 6-3:
6.3 Serial Port
Communication with the TC530/TC534 is
accomplished over a 3-wire serial port. Data is clocked
into DIN on the rising edge of DCLK and clocked out of
DOUT on the falling edge of DCLK. R/W must be HIGH
to read converted data from the serial port and LOW to
write the LOAD VALUE to the TC530/TC534.
Conversion
Per Second
Typical Value
of CREF
, CAZ
(µF)
Suggested (1) Part
Number
>7 0.1 SMR5 104K50J0IL
2 to 7 0.22 SMR5 224K50J2L
2 or less 0.47 SMR5 474K50J04L
Note 1: Manufactured by Evox-Rifa, Inc.
Where:
VIN(MAX) = Maximum Input Voltage (full
count voltage)
RINT = Integrating Resistor (in MΩ)
For loop stability, RINT should be 50 kΩ.
RINT MΩ()
VINMAX
20
-------------------=
Value (µF) Suggested Part Number(1)
0.1 SMR5 104K50J0IL
0.22 SMR5 224K50J2L
0.33 SMR5 334K50J03L4
0.47 SMR5 474K50J04L
Note 1: Manufactured by Evox-Rifa, Inc.
Where:
TINT = Integration Period
VS=IV
DDI
CINT = Integrated Capacitor Value (µF)
CINT
μ
F() TINT
()20 10 6
×
()
VS0.9()
---------------------------------------------=
VREF
VS0.9()CINT
()RINT
()
2R
INT
()
-----------------------------------------------------------V=
TC530/TC534
DS21433C-page 16 © 2007 Microchip Technology Inc.
6.4 Data Read Cycle
Data is shifted out of the serial port in the following
order: End of Conversion (EOC), Overrange (OVR),
Polarity (POL), conversion data (MSB first). When R/W
is high, the state of the EOC bit can be polled by simply
reading the state of DOUT
. This allows the processor to
determine if new data is available without connecting
an additional wire to the EOC output pin (this is
especially useful in a polled environment). Refer to
Figure 6-1.
FIGURE 6-1: Serial Port Data Read
Cycle.
6.5 Load Value Write Cycle
Following the power-up reset pulse, the LOAD VALUE
(which sets the duration of AZ and INT) must next be
transmitted to the serial port. To accomplish this, the
processor monitors the state of EOC (which is available
as a hardware output or at DOUT). R/W is taken low to
initiate the write cycle only when EOC is low (during the
AZ phase). (Failure to observe EOC low may cause an
offset voltage to be developed across CINT
, resulting in
erroneous readings). The 8-bit LOAD VALUE data on
DIN is clocked in by DCLK. The processor then
terminates the write cycle by taking R/W high. (Data is
transferred from the serial input shift register to the time
base counter on the rising edge of R/W and data
conversion is initiated). See Figure 6-2.
6.6 Input Multiplexer (TC534 Only)
A 4-input, differential multiplexer is included in the
TC534. The states of channel address lines A0 and A1
determine which differential VIN pair is routed to the
converter input. A0 is the least significant address bit
(i.e., channel 1 is selected when A0 = 0 and A1 = 0).
The multiplexer is designed to be operated in a differ-
ential mode. For single-ended inputs, the CHx- input for
the channel under selection must be connected to the
ground reference associated with the input signal.
6.7 DC/DC Converter
An on-board, TC7660H-type charge pump supplies
negative bias to the converter circuitry, as well as to
external devices. The charge pump develops a
negative output voltage by moving charge from the
power supply to the reservoir capacitor at VSS by way
of the commutating capacitor connected to the CAP+
and CAP- inputs.
The charge pump clock operates at a typical frequency
of 100 kHz. If lower quiescent current is desired, the
charge pump clock can be slowed by connecting an
external capacitor from the OSC pin to VDD. Reference
typical characteristics curves.
FIGURE 6-2: TC530/TC534 Initialization and Load Value Write Cycle.
EOC OVR POL MSB LSB
R/W
DCLK
DOUT
EOC
R/W
RESET
DCLK
DIN
11001111
AZAZ
LOAD VALUE
MSB LSB
INT DINT IZ AZ...
Conversion
Phase
Timing
Status
Converter held in AZ
state due to RESET = 1
Write LOAD VALUE to Serial PortPower-up RESET Undefined Converter in Normal Service
R/W brought LOW during AZ
for serial port write cycle
R/W = HIGH strobes
LOAD VALUE into
timebase and starts
conversion
Continuous Conversions
winch 09 3:530:01 O Q Mcnocrw Q MIEHOCHIF anocmp NNN alor( )
© 2007 Microchip Technology Inc. DS21433C-page 17
TC530/TC534
7.0 PACKAGING INFORMATION
7.1 Package Marking Information
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
28-Lead SPDIP
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
Example
TC530CPJ ^^
0732256
28-Lead SOIC (.300”)
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
YYWWNNN
Example
TC530COI ^^
0732256
40-Lead PDIP
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
YYWWNNN
Example
TC534CPL ^^
0732256
44-Lead MQFP
XXXXXXXXXX
YYWWNNN
XXXXXXXXXX
XXXXXXXXXX
Example
TC534CKW
^^ 0732256
3
e
3
e
3
e
3
e
TC530/TC534
DS21433C-page 18 © 2007 Microchip Technology Inc.
28-Lead Skinny Plastic Dual In-Line (PJ) – 300 mil Body [SPDIP]
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units INCHES
Dimension Limits MIN NOM MAX
Number of Pins N 28
Pitch e .100 BSC
Top to Seating Plane A .200
Molded Package Thickness A2 .120 .135 .150
Base to Seating Plane A1 .015
Shoulder to Shoulder Width E .290 .310 .335
Molded Package Width E1 .240 .285 .295
Overall Length D 1.345 1.365 1.400
Tip to Seating Plane L .110 .130 .150
Lead Thickness c .008 .010 .015
Upper Lead Width b1 .040 .050 .070
Lower Lead Width b .014 .018 .022
Overall Row Spacing § eB .430
NOTE 1
N
12
D
E1
eB
c
E
L
A2
eb
b1
A1
A
3
Microchip Technology Drawing C04-070B
HHHHHHMHHHHHH \
© 2007 Microchip Technology Inc. DS21433C-page 19
TC530/TC534
28-Lead Plastic Small Outline (OI) – Wide, 7.50 mm Body [SOIC]
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 28
Pitch e 1.27 BSC
Overall Height A 2.65
Molded Package Thickness A2 2.05
Standoff § A1 0.10 0.30
Overall Width E 10.30 BSC
Molded Package Width E1 7.50 BSC
Overall Length D 17.90 BSC
Chamfer (optional) h 0.25 0.75
Foot Length L 0.40 1.27
Footprint L1 1.40 REF
Foot Angle Top φ0° – 8°
Lead Thickness c 0.18 0.33
Lead Width b 0.31 0.51
Mold Draft Angle Top α – 15°
Mold Draft Angle Bottom β – 15°
c
h
h
L
L1
A2
A1
A
NOTE 1
123
b
e
E
E1
D
φ
β
α
N
Microchip Technology Drawing C04-052B
TC530/TC534
DS21433C-page 20 © 2007 Microchip Technology Inc.
40-Lead Plastic Dual In-Line (PL) – 600 mil Body [PDIP]
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units INCHES
Dimension Limits MIN NOM MAX
Number of Pins N 40
Pitch e .100 BSC
Top to Seating Plane A .250
Molded Package Thickness A2 .125 .195
Base to Seating Plane A1 .015
Shoulder to Shoulder Width E .590 .625
Molded Package Width E1 .485 .580
Overall Length D 1.980 2.095
Tip to Seating Plane L .115 .200
Lead Thickness c .008 .015
Upper Lead Width b1 .030 .070
Lower Lead Width b .014 .023
Overall Row Spacing § eB .700
N
NOTE 1
E1
D
123
A
A1 b1
be
c
eB
E
L
A2
Microchip Technology Drawing C04-016B
é HHHHHHHHHHH UUUUUUUUUUU g? g? H H / u \
© 2007 Microchip Technology Inc. DS21433C-page 21
TC530/TC534
44-Lead Plastic Metric Quad Flatpack (KW) – 10x10x2 mm Body, 3.20 mm Footprint [MQFP]
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Chamfers at corners are optional; size may vary.
3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
5. § Significant Characteristic.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Leads N 44
Lead Pitch e 0.80 BSC
Overall Height A 2.45
Molded Package Thickness A2 1.80 2.00 2.20
Standoff § A1 0.00 0.25
Foot Length L 0.73 0.88 1.03
Footprint L1 1.60 REF
Foot Angle φ0° – 7°
Overall Width E 13.20 BSC
Overall Length D 13.20 BSC
Molded Package Width E1 10.00 BSC
Molded Package Length D1 10.00 BSC
Lead Thickness c 0.11 0.23
Lead Width b 0.29 0.45
Mold Draft Angle Top α – 16°
Mold Draft Angle Bottom β – 16°
E
E1
D
D1
e
N
b
NOTE 1
123NOTE 2 α
c
βL
φAA1
L1 A2
Microchip Technology Drawing C04-071B
TC530/TC534
DS21433C-page 22 © 2007 Microchip Technology Inc.
NOTES:
© 2007 Microchip Technology Inc. DS21433C-page 23
TC530/TC534
APPENDIX A: REVISION HISTORY
Revision C (September 2007)
Change status from active to end-of-life (EOL).
Revision B (May 2002)
Changes not documented.
Revision A (April 2002)
Original Release of this Document.
TC530/TC534
DS21433C-page 24 © 2007 Microchip Technology Inc.
NOTES:
PART No. v
© 2007 Microchip Technology Inc. DS21433C-page 25
TC530/TC534
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X/XX
PackageTemperature
Range
Device
Device TC530: Precision Data Acquisition Subsystem
TC534: Precision Data Acquisition Subsystem
Temperature Range C = 0°C to +70°C (Commercial)
Package KW = Plastic Metric Quad Flatpack (10x10x2 mm), 44-lead
PJ = Skinny Plastic Dual In-Line (300 mil), 28-lead
PL = Plastic Dual In-Line (600 mil), 40-lead
OI = Plastic Small Outline (wide, 7.50 mm), 28-lead
Examples:
a) TC530CPJ: 0°C to +70°C, 28LD SPDIP pkg
b) TC530COI: 0°C to +70°C, 28LD SOIC pkg
a) TC534CPL: 0°C to +70°C, 40LD PDIP pkg
b) TC534CKW: 0°C to +70°C, 44LD MQFP pkg
TC530/TC534
DS21433C-page 26 © 2007 Microchip Technology Inc.
NOTES:
QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV = ISO/TS 16949:2002 =
© 2007 Microchip Technology Inc. DS21433C-page 27
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
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OTHERWISE, RELATED TO THE INFORMATION,
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conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
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The Microchip name and logo, the Microchip logo, Accuron,
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ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
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All other trademarks mentioned herein are property of their
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© 2007, Microchip Technology Incorporated, Printed in the
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Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
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Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 certification for its worldwide
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are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
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Q ‘MICROCHIP AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE
DS21433C-page 28 © 2007 Microchip Technology Inc.
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Fax: 86-28-8665-7889
China - Fuzhou
Tel: 86-591-8750-3506
Fax: 86-591-8750-3521
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
China - Shunde
Tel: 86-757-2839-5507
Fax: 86-757-2839-5571
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
ASIA/PACIFIC
India - Bangalore
Tel: 91-80-4182-8400
Fax: 91-80-4182-8422
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Malaysia - Penang
Tel: 60-4-646-8870
Fax: 60-4-646-5086
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Taiwan - Hsin Chu
Tel: 886-3-572-9526
Fax: 886-3-572-6459
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
EUROPE
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
WORLDWIDE SALES AND SERVICE
06/25/07

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