Si7220DN Datasheet by Vishay Siliconix

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Vishay Siliconix
Si7220DN
Document Number: 73117
S-83052-Rev. C, 29-Dec-08
www.vishay.com
1
Dual N-Channel 60-V (D-S) MOSFET
FEATURES
Halogen-free According to IEC 61249-2-21
Available
TrenchFET® Power MOSFET
New Low Thermal Resistance PowerPAK®
Package, 1/3 the Space of An SO-8 While
Thermally Comparable
APPLICATIONS
Synchronous Rectification
Primary Side Switch
PRODUCT SUMMARY
VDS (V) RDS(on) (Ω)I
D (A) Qg (Typ.)
60 0.060 at VGS = 10 V 4.8 13
0.075 at VGS = 4.5 V 4.3
PowerPAK 1212-8
Bottom View
1
2
3
4
5
6
7
8
S1
G1
S2
G2
D1
D1
D2
D2
3.30 mm 3.30 mm
Ordering Information: Si7220DN-T1-E3 (Lead (Pb)-free)
Si7220DN-T1-GE3 (Lead (Pb)-free and Halogen-free) N-Channel MOSFET
G1
D1
S1
N-Channel MOSFET
G2
D2
S2
Notes:
a. Surface Mounted on 1" x 1" FR4 board.
b. See Solder Profile (www.vishay.com/ppg?73257). The PowerPAK 1212-8 is a leadless package. The end of the lead terminal is exposed
copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and
is not required to ensure adequate bottom side solder interconnection.
c. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components.
ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted
Parameter Symbol 10 s Steady State Unit
Drain-Source Voltage VDS 60 V
Gate-Source Voltage VGS ± 20
Continuous Drain Current (TJ = 150 °C)aTA = 25 °C ID
4.8 3.4
A
TA = 70 °C 3.8 2.7
Pulsed Drain Current IDM 20
Avalanche Current L = 0 1 mH IAS 11
Single Avalanche Energy EAS 6.1 mJ
Continuous Source Current (Diode Conduction)aIS2.2 1.1 A
Maximum Power DissipationaTA = 25 °C PD
2.6 1.3 W
TA = 70 °C 1.4 0.69
Operating Junction and Storage Temperature Range TJ, Tstg - 55 to 150 °C
Soldering Recommendations (Peak Temperature)b, c 260
THERMAL RESISTANCE RATINGS
Parameter Symbol Typical Maximum Unit
Maximum Junction-to-Ambientat 10 s RthJA
38 48
°C/W
Steady State 77 94
Maximum Junction-to-Case (Drain) Steady State RthJC 4.3 5.4
— VISHAK V
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Document Number: 73117
S-83052-Rev. C, 29-Dec-08
Vishay Siliconix
Si7220DN
Notes:
a. Pulse test; pulse width 300 µs, duty cycle 2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
Parameter Symbol Test Conditions Min. Typ. Max. Unit
Static
Gate Threshold Voltage VGS(th) VDS = VGS, ID = 250 µA 13V
Gate-Body Leakage IGSS VDS = 0 V, VGS = ± 20 V ± 100 nA
Zero Gate Voltage Drain Current IDSS
VDS = 60 V, VGS = 0 V 1µA
VDS = 60 V, VGS = 0 V, TJ = 85 °C 5
On-State Drain CurrentaID(on) V
DS 5 V, VGS = 10 V 20 A
Drain-Source On-State ResistanceaRDS(on)
VGS = 10 V, ID = 4.8 A 0.048 0.060 Ω
VGS = 4.5 V, ID = 4.3 A 0.061 0.075
Forward Transconductanceagfs VDS = 10 V, ID = 4.8 A 15 S
Diode Forward VoltageaVSD IS = 2.2 A, VGS = 0 V 0.8 1.2 V
Dynamicb
Total Gate Charge Qg
VDS = 30 V, VGS = 10 V, ID = 4.8 A
13 20
nCGate-Source Charge Qgs 2.3
Gate-Drain Charge Qgd 2.6
Gate Resistance Rgf = 1 MHz 2 Ω
Tur n - O n D e l ay Time td(on)
VDD = 30 V, RL = 30 Ω
ID 1 A, VGEN = 10 V, Rg = 6 Ω
10 15
ns
Rise Time tr10 15
Turn-Off Delay Time td(off) 20 30
Fall Time tf10 15
Source-Drain Reverse Recovery Time trr IF = 2.2 A, dI/dt = 100 A/µs 30 60
Output Characteristics
0
4
8
12
16
20
012345
VGS = 10 thru 5 V
VDS
- Drain-to-Source Voltage (V)
- Drain Current (A)ID
4 V
3 V
Transfer Characteristics
0
4
8
12
16
20
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
TC = 125 °C
- 55 °C
25 °C
VGS
- Gate-to-Source Voltage (V)
- Drain Current (A)ID
— VISHAYE V
Document Number: 73117
S-83052-Rev. C, 29-Dec-08
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3
Vishay Siliconix
Si7220DN
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
On-Resistance vs. Drain Current
Gate Charge
Source-Drain Diode Forward Voltage
- On-Resistance (Ω)R
DS(on)
0.00
0.02
0.04
0.06
0.08
0.10
0 4 8 12 16 20
ID - Drain Current (A)
VGS = 10 V
VGS = 4.5 V
0
2
4
6
8
10
03691215
VDS = 30 V
ID = 4.8 A
- Gate-to-Source Voltage (V)
Qg
- Total Gate Charge (nC)
V
GS
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
TJ = 150 °C
TJ = 25 °C
20
1
VSD
- Source-to-Drain Voltage (V)
- Source Current (A)IS
10
Capacitance
On-Resistance vs. Junction Temperature
On-Resistance vs. Gate-to-Source Voltage
0
200
400
600
800
1000
0 102030405060
VDS
- Drain-to-Source Voltage (V)
Coss
Ciss
C - Capacitance (pF)
Crss
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
- 50 - 25 0 25 50 75 100 125 150
VGS = 10 V
ID = 4.8 A
TJ - Junction Temperature (°C)
RDS(on) - On-Resistance
(Normalized)
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0246810
ID = 4.8 A
- On-Resistance (Ω)R
DS(on)
VGS - Gate-to-Source Voltage (V)
VISHAK
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Document Number: 73117
S-83052-Rev. C, 29-Dec-08
Vishay Siliconix
Si7220DN
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Threshold Voltage
- 1.0
- 0.8
- 0.6
- 0.4
- 0.2
0.0
0.2
0.4
0.6
- 50 - 25 0 25 50 75 100 125 150
ID = 250 µA
Variance (V)VGS(th)
TJ - Temperature (°C)
Single Pulse Power
0
30
50
10
20
Power (W)
Time (s)
40
100 6000.10.001 1100.01
Safe Operating Area, Junction-to-Ambient
100
1
0.1 1 10 100
0.01
10
TA = 25 °C
Single Pulse
- Drain Current (A)ID
0.1
IDM
Limited
ID(on)
Limited
RDS(on)
Limited by
BVDSS Limited
P(t) = 10
P(t) = 1
P(t) = 0.1
DC
P(t) = 0.01
P(t) = 0.001
P(t) = 0.0001
VDS - Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
*
Normalized Thermal Transient Impedance, Junction-to-Ambient
10-3 10-2 1 10 60010-1
10-4 100
2
1
0.1
0.01
0.2
0.1
0.05
0.02
Single Pulse
Duty Cycle = 0.5
Square Wave Pulse Duration (s)
Normalized Effective Transient
Thermal Impedance
1. Duty Cycle, D =
2. Per Unit Base = R
thJA
= 77 °C/W
3. T
JM
-
T
A
= P
DM
Z
thJA(t)
t
1
t
2
t
1
t
2
Notes:
4. Surface Mounted
P
DM
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Document Number: 73117
S-83052-Rev. C, 29-Dec-08
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Vishay Siliconix
Si7220DN
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Notes:
The minimum creepage between D1 and D2 for this 100 V device is 0.2 mm. Please see PowerPAK 1212-8 outline drawing, document # 71656,
for more information.
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?73117.
Normalized Thermal Transient Impedance, Junction-to-Case
1
0.2
0.1
10-3 10-2 10-1
10-4
2
1
0.1
0.01
0.05
Single Pulse
Duty Cycle = 0.5
Square Wave Pulse Duration (s)
Normalized Effective Transient
Thermal Impedance
0.02
— VISHAY. V www.msha .com/d05791000
Package Information
www.vishay.com Vishay Siliconix
Revison: 09-Jan-17 1Document Number: 71656
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
PowerPAK® 1212-8, (Single / Dual)
DIM. MILLIMETERS INCHES
MIN. NOM. MAX. MIN. NOM. MAX.
A 0.97 1.04 1.12 0.038 0.041 0.044
A1 0.00 - 0.05 0.000 - 0.002
b 0.23 0.30 0.41 0.009 0.012 0.016
c 0.23 0.28 0.33 0.009 0.011 0.013
D 3.20 3.30 3.40 0.126 0.130 0.134
D1 2.95 3.05 3.15 0.116 0.120 0.124
D2 1.98 2.11 2.24 0.078 0.083 0.088
D3 0.48 - 0.89 0.019 - 0.035
D4 0.47 typ. 0.0185 typ
D5 2.3 typ. 0.090 typ
E 3.20 3.30 3.40 0.126 0.130 0.134
E1 2.95 3.05 3.15 0.116 0.120 0.124
E2 1.47 1.60 1.73 0.058 0.063 0.068
E3 1.75 1.85 1.98 0.069 0.073 0.078
E4 0.034 typ. 0.013 typ.
e 0.65 BSC 0.026 BSC
K 0.86 typ. 0.034 typ.
K1 0.35 - - 0.014 - -
H 0.30 0.41 0.51 0.012 0.016 0.020
L 0.30 0.43 0.56 0.012 0.017 0.022
L1 0.06 0.13 0.20 0.002 0.005 0.008
- 12° - 12°
W 0.15 0.25 0.36 0.006 0.010 0.014
M 0.125 typ. 0.005 typ.
ECN: S16-2667-Rev. M, 09-Jan-17
DWG: 5882
Notes
1. Inch will govern
2 Dimensions exclusive of mold gate burrs
3. Dimensions exclusive of mold flash and cutting burrs
Backside view of single pad
Backside view of dual pad
Detail Z D1
D2
D1
E1
c
A
54
18
D2
4
3
H
2
1
θ
θ
e
b
θ
θ
E2 L
b
D3(2x)
4
3
2
1
A1
Z
K
K1
W
M
D4
E3
E4
D5
KH
E4
E2 L
D2 D4
E3
D5
L1
2
2
D
E
H
VISHAY. Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay S MOSFE Ts.
Vishay Siliconix
AN822
Document Number 71681
03-Mar-06
www.vishay.com
1
PowerPAK® 1212 Mounting and Thermal Considerations
Johnson Zhao
MOSFETs for switching applications are now available
with die on resistances around 1 mΩ and with the
capability to handle 85 A. While these die capabilities
represent a major advance over what was available
just a few years ago, it is important for power MOSFET
packaging technology to keep pace. It should be obvi-
ous that degradation of a high performance die by the
package is undesirable.
PowerPAK is a new package
technology that addresses these issues. The PowerPAK
1212-8 provides ultra-low thermal impedance in a
small package that is ideal for space-constrained
applications. In this application note, the PowerPAK
1212-8’s construction is described. Following this,
mounting information is presented. Finally, thermal
and electrical performance is discussed.
THE PowerPAK PACKAGE
The PowerPAK 1212-8 package (Figure 1) is a deriva-
tive of PowerPAK SO-8. It utilizes the same packaging
technology, maximizing the die area. The bottom of the
die attach pad is exposed to provide a direct, low resis-
tance thermal path to the substrate the device is
mounted on. The PowerPAK 1212-8 thus translates
the benefits of the PowerPAK SO-8 into a smaller
package, with the same level of thermal performance.
(Please refer to application note “PowerPAK SO-8
Mounting and Thermal Considerations.”)
The PowerPAK 1212-8 has a footprint area compara-
ble to TSOP-6. It is over 40 % smaller than standard
TSSOP-8. Its die capacity is more than twice the size
of the standard TSOP-6’s. It has thermal performance
an order of magnitude better than the SO-8, and 20
times better than TSSOP-8. Its thermal performance is
better than all current SMT packages in the market. It
will take the advantage of any PC board heat sink
capability. Bringing the junction temperature down also
increases the die efficiency by around 20 % compared
with TSSOP-8. For applications where bigger pack-
ages are typically required solely for thermal consider-
ation, the PowerPAK 1212-8 is a good option.
Both the single and dual PowerPAK 1212-8 utilize the
same pin-outs as the single and dual PowerPAK SO-8.
The low 1.05 mm PowerPAK height profile makes both
versions an excellent choice for applications with
space constraints.
PowerPAK 1212 SINGLE MOUNTING
To take the advantage of the single PowerPAK 1212-8’s
thermal performance see Application Note 826,
Recommended Minimum Pad Patterns With Outline
Drawing Access for Vishay Siliconix MOSFETs. Click
on the PowerPAK 1212-8 single in the index of this
document.
In this figure, the drain land pattern is given to make full
contact to the drain pad on the PowerPAK package.
This land pattern can be extended to the left, right, and
top of the drawn pattern. This extension will serve to
increase the heat dissipation by decreasing the ther-
mal resistance from the foot of the PowerPAK to the
PC board and therefore to the ambient. Note that
increasing the drain land area beyond a certain point
will yield little decrease in foot-to-board and foot-to-
ambient thermal resistance. Under specific conditions
of board configuration, copper weight, and layer stack,
experiments have found that adding copper beyond an
area of about 0.3 to 0.5 in2 of will yield little improve-
ment in thermal performance.
Figure 1. PowerPAK 1212 Devices
th Outline mgmi VISHAY» 267 pnzuw 2m: 2 mu: 3 REFLOW com 2m / \ 2n \ / \ fl, m \ 19 25 szco 33 55 an m use my 232 255 we
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Document Number 71681
03-Mar-06
Vishay Siliconix
AN822
PowerPAK 1212 DUAL
To take the advantage of the dual PowerPAK 1212-8’s
thermal performance, the minimum recommended
land pattern can be found in Application Note 826,
Recommended Minimum Pad Patterns With Outline
Drawing Access for Vishay Siliconix MOSFETs. Click
on the PowerPAK 1212-8 dual in the index of this doc-
ument.
The gap between the two drain pads is 10 mils. This
matches the spacing of the two drain pads on the Pow-
erPAK 1212-8 dual package.
This land pattern can be extended to the left, right, and
top of the drawn pattern. This extension will serve to
increase the heat dissipation by decreasing the ther-
mal resistance from the foot of the PowerPAK to the
PC board and therefore to the ambient. Note that
increasing the drain land area beyond a certain point
will yield little decrease in foot-to-board and foot-to-
ambient thermal resistance. Under specific conditions
of board configuration, copper weight, and layer stack,
experiments have found that adding copper beyond an
area of about 0.3 to 0.5 in2 of will yield little improve-
ment in thermal performance.
REFLOW SOLDERING
Vishay Siliconix surface-mount packages meet solder
reflow reliability requirements. Devices are subjected
to solder reflow as a preconditioning test and are then
reliability-tested using temperature cycle, bias humid-
ity, HAST, or pressure pot. The solder reflow tempera-
ture profile used, and the temperatures and time
duration, are shown in Figures 2 and 3. For the lead
(Pb)-free solder profile, see http://www.vishay.com/
doc?73257.
Ramp-Up Rate + 6 °C /Second Maximum
Temperature at 155 ± 15 °C 120 Seconds Maximum
Temperature Above 180 °C 70 - 180 Seconds
Maximum Temperature 240 + 5/- 0 °C
Time at Maximum Temperature
20 - 40 Seconds
Ramp-Down Rate
+ 6 °C/Second Maximum
Figure 2. Solder Reflow Temperature Profile
Figure 3. Solder Reflow Temperatures and Time Durations
210 - 220 °C
3 °C/s (max) 4 °C/s (max)
10 s (max)
183 °C
50 s (max)
Reflow Zone
60 s (min)
Pre-Heating Zone
3° C/s (max)
140 - 170 °C
Maximum peak temperature at 240 °C is allowed.
Vishay Siliconix
AN822
Document Number 71681
03-Mar-06
www.vishay.com
3
THERMAL PERFORMANCE
Introduction
A basic measure of a device’s thermal performance is
the junction-to-case thermal resistance, Rθjc, or the
junction to- foot thermal resistance, Rθjf. This parameter
is measured for the device mounted to an infinite heat
sink and is therefore a characterization of the device
only, in other words, independent of the properties of the
object to which the device is mounted. Table 1 shows a
comparison of the PowerPAK 1212-8, PowerPAK SO-8,
standard TSSOP-8 and SO-8 equivalent steady state
performance.
By minimizing the junction-to-foot thermal resistance, the
MOSFET die temperature is very close to the tempera-
ture of the PC board. Consider four devices mounted on
a PC board with a board temperature of 45 °C (Figure 4)
.
Suppose each device is dissipating 2 W. Using the junc-
tion-to-foot thermal resistance characteristics of the
PowerPAK 1212-8 and the other SMT packages, die
temperatures are determined to be 49.8 °C for the Pow-
erPAK 1212-8, 85 °C for the standard SO-8, 149 °C for
standard TSSOP-8, and 125 °C for TSOP-6. This is a
4.8 °C rise above the board temperature for the Power-
PAK 1212-8, and over 40 °C for other SMT packages. A
4.8 °C rise has minimal effect on rDS(ON) whereas a rise
of over 40 °C will cause an increase in rDS(ON) as high
as 20 %.
Spreading Copper
Designers add additional copper, spreading copper, to
the drain pad to aid in conducting heat from a device. It
is helpful to have some information about the thermal
performance for a given area of spreading copper.
Figure 5 and Figure 6 show the thermal resistance of a
PowerPAK 1212-8 single and dual devices mounted on
a 2-in. x 2-in., four-layer FR-4 PC boards. The two inter-
nal layers and the backside layer are solid copper. The
internal layers were chosen as solid copper to model the
large power and ground planes common in many appli-
cations. The top layer was cut back to a smaller area and
at each step junction-to-ambient thermal resistance
measurements were taken. The results indicate that an
area above 0.2 to 0.3 square inches of spreading copper
gives no additional thermal performance improvement.
A subsequent experiment was run where the copper on
the back-side was reduced, first to 50 % in stripes to
mimic circuit traces, and then totally removed. No signif-
icant effect was observed.
TABLE 1: EQIVALENT STEADY STATE PERFORMANCE
Package SO-8 TSSOP-8 TSOP-8 PPAK 1212 PPAK SO-8
Configuration Single Dual Single Dual Single Dual Single Dual Single Dual
Thermal Resiatance RthJC(C/W) 20 40 52 83 40 90 2.4 5.5 1.8 5.5
Figure 4. Temperature of Devices on a PC Board
2.4 °C/W
49.8 °C
PowerPAK 1212
20 °C/W
85 °C
Standard SO-8
PC Board at 45 °C
52 °C/W
149 °C
Standard TSSOP-8
40 °C/W
125 °C
TSOP-6
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Document Number 71681
03-Mar-06
Vishay Siliconix
AN822
CONCLUSIONS
As a derivative of the PowerPAK SO-8, the PowerPAK
1212-8 uses the same packaging technology and has
been shown to have the same level of thermal perfor-
mance while having a footprint that is more than 40 %
smaller than the standard TSSOP-8.
Recommended PowerPAK 1212-8 land patterns are
provided to aid in PC board layout for designs using this
new package.
The PowerPAK 1212-8 combines small size with attrac-
tive thermal characteristics. By minimizing the thermal
rise above the board temperature, PowerPAK simplifies
thermal design considerations, allows the device to run
cooler, keeps rDS(ON) low, and permits the device to
handle more current than a same- or larger-size MOS-
FET die in the standard TSSOP-8 or SO-8 packages.
Figure 5. Spreading Copper - Si7401DN
45
55
65
75
85
95
105
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
R
AJht
(°C/W)
Spreading Copper (sq. in.)
100 %
50 %
0 %
Figure 6. Spreading Copper - Junction-to-Ambient Performance
R
AJ
(°C/W)
ht
50
60
70
80
90
100
110
120
130
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
Spreading Copper (sq. in.)
100 %
0 %
50 %
VISHAY»
Application Note 826
Vishay Siliconix
www.vishay.com Document Number: 72598
1Revision: 14-Apr-08
APPLICATION NOTE
RECOMMENDED MINIMUM PADS FOR PowerPAK® 1212-8 Dual
0.088
(2.235)
Recommended Minimum Pads
Dimensions in Inches/(mm)
0.152
(3.860)
0.094
(2.390)
0.039
(0.990)
0.068
(1.725)
0.010
(0.255)
0.016
(0.405)
0.026
(0.660)
0.025
(0.635)
0.030
(0.760)
Return to Index
Return to Index
0.152
(3.860)
0.039
(0.990)
0.016
(0.405)
0.026
(0.660)
0.025
(0.635)
0.030
(0.760)
0.039
(0.990)
0.039
(0.990)
0.068
(1.725)
0.010
(0.225)
0.094
(2.390)
Recommended Minimum PADs for PowerPAK 1212-8 Dual
Dimensions in Inches/(mm)
— VISHAY. V
Legal Disclaimer Notice
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Revision: 08-Feb-17 1Document Number: 91000
Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,
“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
disclosure relating to any product.
Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or
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liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special,
consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular
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Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of
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statements about the suitability of products for a particular application. It is the customer’s responsibility to validate that a
particular product with the properties described in the product specification is suitable for use in a particular application.
Parameters provided in datasheets and / or specifications may vary in different applications and performance may vary over
time. All operating parameters, including typical parameters, must be validated for each customer application by the customer’s
technical experts. Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase,
including but not limited to the warranty expressed therein.
Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining
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