STM32F102x(4,6) Datasheet by STMicroelectronics

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This is information on a product in full production.
August 2019 DS5934 Rev 6 1/79
STM32F102x4
STM32F102x6
Low-density USB access line, Arm®-based 32-bit MCU with
16/32 KB Flash, USB FS, 5 timers, ADC and 5 com. interfaces
Datasheet - production data
Features
Core: Arm® 32-bit Cortex®-M3 CPU
48 MHz maximum frequency,
1.25 DMIPS/MHz (Dhrystone 2.1)
performance at 0 WS memory access
Single-cycle multiplication and hardware
division
Memories
16 or 32 Kbytes of Flash memory
4 or 6 Kbytes of SRAM
Clock, reset and supply management
2.0 to 3.6 V application supply and I/Os
POR, PDR and programmable voltage
detector (PVD)
4 to 16 MHz crystal oscillator
Internal 8 MHz factory-trimmed RC
Internal 40 kHz RC
PLL for CPU clock
32 kHz oscillator for RTC with calibration
Low power
Sleep, Stop and Standby modes
–V
BAT supply for RTC and backup registers
Debug mode
Serial wire debug (SWD) and JTAG
interfaces
DMA
7-channel DMA controller
Peripherals supported: timers, ADC, SPIs,
I2Cs and USARTs
1 × 12-bit, 1.2 µs A/D converter (up to 16
channels)
Conversion range: 0 to 3.6 V
Temperature sensor
Up to 51 fast I/O ports
37/51 I/Os all mappable on 16 external
interrupt vectors and almost all 5 V-tolerant
Up to five timers
Two 16-bit timers, each with up to 4
IC/OC/PWM or pulse counter
2 watchdog timers (Independent and
Window)
SysTick timer: 24-bit downcounter
Up to five communication interfaces
–One I
2C interface (SMBus/PMBus)
Two USARTs (ISO 7816 interface, LIN,
IrDA capability, modem control)
One SPI (12 Mbit/s)
One USB 2.0 full speed interface
CRC calculation unit, 96-bit unique ID
ECOPACK packages
Table 1. Device summary
Reference Part number
STM32F102x4 STM32F102C4, STM32F102R4
STM32F102x6 STM32F102C6, STM32F102R6
LQFP48
7 × 7 mm
LQFP64
10 × 10 mm
www.st.com
Contents STM32F102x4, STM32F102x6
2/79 DS5934 Rev 6
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3.1 Arm® Cortex®-M3 core with embedded Flash memory and SRAM . . . . 13
2.3.2 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.3 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 14
2.3.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.5 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 14
2.3.6 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.7 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.8 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.9 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.10 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.11 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.12 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.13 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.14 RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 16
2.3.15 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.16 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.17 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.18 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.19 I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.20 Universal synchronous/asynchronous receiver transmitter (USART) . . 18
2.3.21 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.22 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.23 GPIOs (general-purpose inputs / outputs) . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.24 ADC (analog to digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.25 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.26 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 19
3 Pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
DS5934 Rev 6 3/79
STM32F102x4, STM32F102x6 Contents
4
4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 29
5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 30
5.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.3.11 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 48
5.3.12 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.3.13 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.3.14 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.3.15 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.3.16 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.3.17 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.3.18 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.1 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.2 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.3 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Contents STM32F102x4, STM32F102x6
4/79 DS5934 Rev 6
6.4 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.4.1 Evaluating the maximum junction temperature for an application . . . . . 75
7 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
DS5934 Rev 6 5/79
STM32F102x4, STM32F102x6 List of tables
6
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. STM32F102x4 and STM32F102x6 low-density USB access line features
and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3. STM32F102xx USB access line family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 4. Low-density STM32F102xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 5. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 6. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 7. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 8. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 9. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 10. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 11. Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 12. Maximum current consumption in Run mode, code with data processing
running from Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 13. Maximum current consumption in Run mode, code with data processing
running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 14. Max. current consumption in Sleep mode, code running from Flash memory or RAM. . . . 34
Table 15. Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 34
Table 16. Typical current consumption in Run mode, code with data processing
running from Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 17. Typical current consumption in Sleep mode, code running from Flash memory or RAM. . 38
Table 18. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 19. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 20. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 21. HSE 4-16 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 22. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 23. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 24. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 25. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 26. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 27. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 28. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 29. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 30. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 31. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 32. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 33. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 34. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 35. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 36. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 37. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 38. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 39. I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 40. SCL frequency (fPCLK1= 36 MHz, VDD_I2C = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 41. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 42. USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 43. USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 44. USB: Full speed electrical characteristics of the driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
List of tables STM32F102x4, STM32F102x6
6/79 DS5934 Rev 6
Table 45. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 46. RAIN max for fADC = 12 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 47. ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 48. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 49. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 50. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 51. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 52. Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 53. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
DS5934 Rev 6 7/79
STM32F102x4, STM32F102x6 List of figures
7
List of figures
Figure 1. STM32F102T8 medium-density USB access line block diagram . . . . . . . . . . . . . . . . . . . . 11
Figure 2. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 3. STM32F102xx medium-density USB access line LQFP48 pinout . . . . . . . . . . . . . . . . . . . 20
Figure 4. STM32F102xx medium-density USB access line LQFP64 pinout . . . . . . . . . . . . . . . . . . . 20
Figure 5. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 6. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 7. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 8. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 9. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 10. Typical current consumption in Run mode versus temperature (at 3.6 V),
code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . . 33
Figure 11. Typical current consumption in Run mode versus temperature (at 3.6 V),
code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . . 33
Figure 12. Typical current consumption on VBAT with RTC on versus temperature
for different VBAT values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 13. Typical current consumption in Stop mode with regulator in Run mode
versus temperature, VDD = 3.3 / 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 14. Typical current consumption in Stop mode with regulator in Low-power mode
versus temperature, VDD = 3.3 / 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 15. Typical current consumption in Standby mode versus temperature, VDD = 3.3 / 3.6 V . . . 36
Figure 16. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 17. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 18. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 19. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 20. Standard I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 21. Standard I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 22. 5 V tolerant I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 23. 5 V tolerant I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 24. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 25. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 26. I2C bus AC waveforms and measurement circuit(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 27. SPI timing diagram - slave mode and CPHA=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 28. SPI timing diagram - slave mode and CPHA=1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 29. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 30. USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 31. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 32. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 33. Power supply and reference decoupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 34. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 68
Figure 35. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 36. LQFP48 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 37. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . 71
Figure 38. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 39. LQFP64 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 40. LQFP64 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
EEK "FIE” UsB ,, arm
Introduction STM32F102x4, STM32F102x6
8/79 DS5934 Rev 6
1 Introduction
This datasheet provides the ordering information and mechanical device characteristics of
STM32F102x4 and STM32F102x6 low-density USB access line microcontrollers. For more
details on the whole STMicroelectronics STM32F102xx family refer to Section 2.2: Full
compatibility throughout the family.
The medium-density STM32F102xx datasheet must be read in conjunction with the low-,
medium- and high-density STM32F10xxx reference manual.
For information on programming, erasing and protection of the internal Flash memory refer
to STM32F10xxx Flash memory microcontrollers (PM0075).
The reference and Flash programming manuals are both available from the
STMicroelectronics website www.st.com.
For information on the Arm® Cortex®-M3 core(a) refer to the Cortex®-M3 Technical
Reference Manual, available from the Arm® website.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
DS5934 Rev 6 9/79
STM32F102x4, STM32F102x6 Description
67
2 Description
The STM32F102xx medium-density USB access line incorporates the high-performance
Arm® Cortex®-M3 32-bit RISC core operating at a 48 MHz frequency, high-speed
embedded memories (Flash memory of 16 or 32 Kbytes and SRAM of 4 or 6 Kbytes), and
an extensive range of enhanced peripherals and I/Os connected to two APB buses. All
devices offer standard communication interfaces (one I2C, one SPI, one USB and two
USARTs), one 12-bit ADC and two general-purpose 16-bit timers.
The STM32F102xx family operates in the –40 to +85 °C temperature range, from a 2.0 to
3.6 V power supply. A comprehensive set of power-saving mode allows the design of
low-power applications.
The STM32F102xx medium-density USB access line is delivered in the LQFP48 7 × 7 mm
and LQFP64 10 × 10 mm packages.
The STM32F102xx medium-density USB access line microcontrollers are suitable for a
wide range of applications.
Application control and user interface
Medical and handheld equipment
PC peripherals, gaming and GPS platforms
Industrial applications: PLC, inverters, printers, and scanners
Alarm systems, Video intercom, and HVAC
Figure 1 shows the general block diagram of the device family.
Description STM32F102x4, STM32F102x6
10/79 DS5934 Rev 6
2.1 Device overview
Table 2. STM32F102x4 and STM32F102x6 low-density USB access line features
and peripheral counts
Peripheral STM32F102Cx STM32F102Rx
Flash memory - Kbytes 16 32 16 32
SRAM - Kbytes 46 4 6
Timers General purpose 22 2 2
Communication
interfaces
SPI 11 1 1
I2C11 1 1
USART 22 2 2
USB 11 1 1
12-bit synchronized ADC
number of channels
1
10 channels
1
16 channels
GPIOs 37 51
CPU frequency 48 MHz
Operating voltage 2.0 to 3.6 V
Operating temperature Ambient temperature: –40 to +85 °C (see Table 8)
Junction temperature: –40 to +105 °C (see Table 8)
Packages LQFP48 LQFP64
ms
DS5934 Rev 6 11/79
STM32F102x4, STM32F102x6 Description
67
Figure 1. STM32F102T8 medium-density USB access line block diagram
1. AF = alternate function on I/O port pin.
2. TA = –40 °C to +85 °C (junction temperature up to 105 °C).
Temp sensor
PA[15:1]
EXTI
W W D G
NVIC
12bit ADC1
SWD
16AF
JTDI
JTCK/SWCLK
JTMS/SWDIO
JNTRST
JTDO
NRST
V
DD
= 2 to 3.6 V
51AF
PB[15:0]
PC[15:0]
AHB2
SRAM
WAKEUP
GPIOA
GPIOB
GPIOC
F
max
: 48 MHz
V
SS
GP DMA
TIM2
TIM3
XTAL OSC
4-16 MHz
XTAL 32 kHz
OSC_IN
OSC_OUT
OSC32_OUT
OSC32_IN
PLL &
APB1: F
max
= 24 MHz
PCLK1
HCLK CLOCK
MANAGT
PCLK2
VOLT. REG.
3.3 V to 1.8 V
POWER
Backup interface
as AF
6 KB
RTC
RC 8 MHz
Cortex M3 CPU
USART1
USART2
7 channels
Backup
reg
SCL,SDA,SMBA L
I2C as AF
PD[2:0] GPIOD
AHB:F
max
=48 MHz
4 Channels
4 Channels
FCLK
RC 40 kHz
Stand by
IWDG
@VDD
@VBAT
POR / PDR
SUPPLY
@VDDA
VDDA
VSSA
@VDDA
V
BAT
RX,TX, CTS, RTS,
Smart Card as AF
RX,TX, CTS, RTS,
APB2 : F
max
= 48 MHz
NVIC
SPI
MOSI,MISO,
SCK,NSS as AF
IF
interface
@VDDA
SUPERVISION
PVD
Rst
Int
@VDD
AHB2
APB2 APB1 AWU TAMPER-RTC
Flash 32 KB
BusM atrix
64 bit
Interface
Ibus
Dbus
pbus
obl
Flash
Trace
Controlleront
System
ai15452b
TRACECLK
TRACED[0:3]
as AS
SW/JTAG
TPIU Trace/trig
CK, SmartCard as AF
USB 2.0 FS
USBDP, USBDM as AF
frD—LP
Description STM32F102x4, STM32F102x6
12/79 DS5934 Rev 6
Figure 2. Clock tree
1. For the USB function to be available, both HSE and PLL must be enabled, with the USB clock output
(USBCLK) at 48 MHz.
2. To have an ADC conversion time of 1.2 µs, APB2 must be at 12 MHz, 24 MHz or 48 MHz.
3. The Flash memory programming interface clock (FLITFCLK) is always the HSI clock.
HSE OSC
4-16 MHz
OSC_IN
OSC_OUT
OSC32_IN
OSC32_OUT
LSE OSC
32.768 kHz
HSI RC
8 MHz
LSI RC
40 kHz
to Independent Watchdog (IWDG)
PLL
x2, x3, x4
PLLMUL
Legend:
MCO
Clock Output
Main
PLLXTPRE
/2
..., x16 AHB
Prescaler
/1, 2..512
/2 PLLCLK
HSI
HSE
APB1
Prescaler
/1, 2, 4, 8, 16
ADC
Prescaler
/2, 4, 6, 8 ADCCLK
PCLK1
HCLK
PLLCLK
to AHB bus, core,
memory and DMA
USBCLK
to USB interface
to TIM2, TIM3
USB
Prescaler
/1, 1.5
to ADC
LSE
LSI
HSI
/128
/2
HSI
HSE
peripherals
to APB1
Peripheral Clock
Enable (13 bits)
Enable (2 bits)
Peripheral Clock
APB2
Prescaler
/1, 2, 4, 8, 16
PCLK2
peripherals
to APB2
Peripheral Clock
Enable (11 bits)
48 MHz
48 MHz max
48 MHz
48 MHz max
24 MHz max
to RTC
PLLSRC SW
MCO
CSS
to Cortex System timer
/8
Clock
Enable (3 bits)
SYSCLK
max
RTCCLK
RTCSEL[1:0]
TIMXCLK
IWDGCLK
SYSCLK
FCLK Cortex
free running clock
TIM2, TIM3
If (APB1 prescaler =1) x1
else x2
HSE = high-speed external clock signal
HSI = high-speed internal clock signal
LSI = low-speed internal clock signal
LSE = low-speed external clock signal
ai15455b
To Flash prog. if FLITFCLK
DS5934 Rev 6 13/79
STM32F102x4, STM32F102x6 Description
67
2.2 Full compatibility throughout the family
The STM32F102xx is a complete family whose members are fully pin-to-pin, software and
feature compatible. In the reference manual, the STM32F102x4 and STM32F102x6 are
referred to as low-density devices and the STM32F102x8 and STM32F102xB are referred
to as medium-density devices.
Low-density devices are an extension of the STM32F102x8/B devices, they are specified in
the STM32F102x4/6 datasheet. Low-density devices feature lower Flash memory and RAM
capacities, a timer and a few communication interfaces less.
The STM32F102x4 and STM32F102x6 are a drop-in replacement for the STM32F102x8/B
medium-density devices, allowing the user to try different memory densities and providing a
greater degree of freedom during the development cycle.
Moreover the STM32F102xx family is fully compatible with all existing STM32F101xx
access line and STM32F103xx performance line devices.
2.3 Overview
2.3.1 Arm® Cortex®-M3 core with embedded Flash memory and SRAM
The Arm® Cortex®-M3 processor is the latest generation of Arm® processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The Arm® Cortex®-M3 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an Arm® core in the memory size usually
associated with 8- and 16-bit devices.
The STM32F102xx medium-density USB access line having an embedded Arm® core is
therefore compatible with all Arm® tools and software.
Table 3. STM32F102xx USB access line family
Pins
Low-density STM32F102xx devices Medium-density STM32F102xx devices
16 KB
Flash memory
32 KB
Flash memory(1)
1. For orderable part numbers that do not show the A internal code after the temperature range code (6), the
reference datasheet for electrical characteristics is the one of the STM32F102x8/B medium-density
devices.
64 KB
Flash memory
128 KB
Flash memory
4 KB RAM 6 KB RAM 10 KB RAM 16 KB RAM
64 2 × USARTs, 2 × 16-bit timers
1 × SPI, 1 × I2C, 1 × ADC, 1 × USB
3 × USARTs, 3 × 16-bit timers
2 × SPIs, 2 × I2Cs, 1 × ADC, 1 × USB
48
36 - -
2 × USARTs,
3 × 16-bit timers
1 × SPI, 1 × I2C,
1 × ADC, 1 × USB
-
Description STM32F102x4, STM32F102x6
14/79 DS5934 Rev 6
2.3.2 Embedded Flash memory
16 or 32 Kbytes of embedded Flash is available for storing programs and data.
2.3.3 CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity, In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
2.3.4 Embedded SRAM
4 or 6 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait
states.
2.3.5 Nested vectored interrupt controller (NVIC)
The STM32F102xx medium-density USB access line embeds a nested vectored interrupt
controller able to handle up to 36 maskable interrupt channels (not including the 16 interrupt
lines of Cortex®-M3) and 16 priority levels.
Closely coupled NVIC gives low latency interrupt processing
Interrupt entry vector table address passed directly to the core
Closely coupled NVIC core interface
Makes possible early processing of interrupts
Processing of late arriving higher priority interrupts
Support for tail-chaining
Processor state automatically saved
Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
2.3.6 External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 19 edge detectors lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect external line with pulse
width lower than the Internal APB2 clock period. Up to 51 GPIOs are connected to the 16
external interrupt lines.
2.3.7 Clocks and startup
System clock selection is performed on startup. however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
DS5934 Rev 6 15/79
STM32F102x4, STM32F102x6 Description
67
interrupt management of the PLL clock entry is available when necessary (for example on
failure of an indirectly used external crystal, resonator or oscillator).
Several prescalers allow the configuration of the AHB frequency, the High Speed APB
(APB2) and the low Speed APB (APB1) domains. The maximum frequency of the AHB and
the APB domains is 48 MHz. See Figure 2 for details on the clock tree.
2.3.8 Boot modes
At startup, boot pins are used to select one of five boot options:
Boot from User Flash
Boot from System Memory
Boot from embedded SRAM
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using USART1. For further details refer to AN2606, available on www.st.com.
2.3.9 Power supply schemes
VDD = 2.0 to 3.6 V: External power supply for I/Os and the internal regulator.
Provided externally through VDD pins.
VSSA, VDDA = 2.0 to 3.6 V: External analog power supplies for ADC. Reset blocks, RCs
and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC is used).
VDDA and VSSA must be connected to VDD and VSS, respectively.
VBAT = 1.8 to 3.6 V: Power supply for RTC, external clock 32 kHz oscillator and backup
registers (through power switch) when VDD is not present.
For more details on how to connect power pins, refer to Figure 8: Power supply scheme.
2.3.10 Power supply supervisor
The device has an integrated power-on reset (POR) / power-down reset (PDR) circuitry. It is
always active, and ensures proper operation starting from/down to 2 V. The device remains
in Reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for an
external reset circuit.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD / VDDA power supply and compares it to the VPVD threshold. An interrupt can be
generated when VDD/VDDA drops below the VPVD threshold and/or when VDD / VDDA is
higher than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
Refer to Table 10: Embedded reset and power control block characteristics for the values of
VPOR/PDR and VPVD.
2.3.11 Voltage regulator
The regulator has three operation modes: main (MR), low power (LPR) and power down.
MR is used in the nominal regulation mode (Run)
LPR is used in the Stop mode
Power down is used in Standby mode: the regulator output is in high impedance: the
kernel circuitry is powered down, inducing zero consumption (but the contents of the
registers and SRAM are lost)
Description STM32F102x4, STM32F102x6
16/79 DS5934 Rev 6
This regulator is always enabled after reset. It is disabled in Standby mode, providing high
impedance output.
2.3.12 Low-power modes
The STM32F102xx medium-density USB access line supports three low-power modes to
achieve the best compromise between low power consumption, short startup time and
available wakeup sources:
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
Stop mode
The Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled. The voltage regulator can also be put
either in normal or in Low-power mode.
The device can be woken up from Stop mode by any of the EXTI line. The EXTI line
source can be one of the 16 external lines, the PVD output or the RTC alarm.
Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and registers content are lost except for registers in the Backup
domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a
rising edge on the WKUP pin, or an RTC alarm occurs.
Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop
or Standby mode.
2.3.13 DMA
The flexible 7-channel general-purpose DMA is able to manage memory-to-memory,
peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports
circular buffer management avoiding the generation of interrupts when the controller
reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with support for software
trigger on each channel. Configuration is made by software and transfer sizes between
source and destination are independent.
The DMA can be used with the main peripherals: SPI, I2C, USART, general purpose timers
TIMx and ADC.
2.3.14 RTC (real-time clock) and backup registers
The RTC and the backup registers are supplied through a switch that takes power either on
VDD supply when present or through the VBAT pin. The backup registers are ten 16-bit
registers used to store 20 bytes of user application data when VDD power is not present.
The real-time clock provides a set of continuously running counters which can be used with
suitable software to provide a clock calendar function, and provides an alarm interrupt and a
DS5934 Rev 6 17/79
STM32F102x4, STM32F102x6 Description
67
periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the
internal low power RC oscillator or the high-speed external clock divided by 128. The
internal low power RC has a typical frequency of 40 kHz. The RTC can be calibrated using
an external 512 Hz output to compensate for any natural crystal deviation. The RTC
features a 32-bit programmable counter for long term measurement using the Compare
register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by
default configured to generate a time base of 1 second from a clock at 32.768 kHz.
2.3.15 Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 40 kHz internal RC and as it operates independently from the
main clock. it can operate in Stop and Standby modes. It can be used as a watchdog to
reset the device when a problem occurs, or as a free running timer for application timeout
management. It is hardware or software configurable through the option bytes. The counter
can be frozen in debug mode.
2.3.16 Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
2.3.17 SysTick timer
This timer is dedicated for OS, but could also be used as a standard down counter. It
features:
A 24-bit down counter
Autoreload capability
Maskable system interrupt generation when the counter reaches 0.
Programmable clock source
2.3.18 General-purpose timers (TIMx)
There are two synchronizable general-purpose timers embedded in the STM32F102xx
medium-density USB access line devices. These timers are based on a 16-bit auto-reload
up/down counter, a 16-bit prescaler and feature four independent channels each for input
capture, output compare, PWM or one-pulse mode output. This gives up to twelve input
captures / output compares / PWMs on the LQFP48 and LQFP64 packages.
The general-purpose timers can work together via the Timer Link feature for synchronization
or event chaining. Their counter can be frozen in debug mode.
Any of the general-purpose timers can be used to generate PWM outputs. They both have
independent DMA request generation.
These timers are capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.
Description STM32F102x4, STM32F102x6
18/79 DS5934 Rev 6
2.3.19 I²C bus
One I²C bus interface can operate in multi-master and slave modes. It can support standard
and fast modes. It supports dual slave addressing (7-bit only) and both 7/10-bit addressing
in master mode. A hardware CRC generation/verification is embedded.
The I2C interface can be served by DMA and they support SM Bus 2.0/PM Bus.
2.3.20 Universal synchronous/asynchronous receiver transmitter (USART)
The available USART interfaces communicate at up to 2.25 Mbit/s. They provide hardware
management of the CTS and RTS signals, support IrDA SIR ENDEC, are ISO 7816
compliant and have LIN Master/Slave capability.
The USART interfaces can be served by the DMA controller.
2.3.21 Serial peripheral interface (SPI)
The SPI is able to communicate up to 12 Mbit/s in slave and master modes in full-duplex
and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies
and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification
supports basic SD Card/MMC modes.
The SPI can be served by the DMA controller.
2.3.22 Universal serial bus (USB)
The STM32F102xx medium-density USB access line embeds an USB device peripheral
compatible with the USB full-speed 12 Mbit/s. The USB interface implements a full-speed
(12 Mbit/s) function interface. It has software configurable endpoint setting and
suspend/resume support. The dedicated 48 MHz clock is generated from the internal main
PLL (the clock source must use a HSE crystal oscillator).
2.3.23 GPIOs (general-purpose inputs / outputs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current
capable.
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.
2.3.24 ADC (analog to digital converter)
The 12-bit analog to digital converter has up to 16 external channels and performs
conversions in single-shot or scan modes. In scan mode, automatic conversion is performed
on a selected group of analog inputs.
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
DS5934 Rev 6 19/79
STM32F102x4, STM32F102x6 Description
67
2.3.25 Temperature sensor
The temperature sensor has to generate a a voltage that varies linearly with temperature.
The conversion range is between 2 V < VDDA < 3.6 V. The temperature sensor is internally
connected to the ADC_IN16 input channel, which is used to convert the sensor output
voltage into a digital value.
2.3.26 Serial wire JTAG debug port (SWJ-DP)
The Arm® SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a
specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.
Pinout and pin description STM32F102x4, STM32F102x6
20/79 DS5934 Rev 6
3 Pinout and pin description
Figure 3. STM32F102xx medium-density USB access line LQFP48 pinout
Figure 4. STM32F102xx medium-density USB access line LQFP64 pinout
44 43 42 41 40 39 38 37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
12
13 14 15 16 17 18 19 20 21 22
1
2
3
4
5
6
7
8
9
10
11
48 47 46 45
LQFP48
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB10
PB11
VSS_1
VDD_1
VDD_2
VSS_2
PA13
PA12
PA11
PA10
PA9
PA8
PB15
PB14
PB13
PB12
VBAT
PC14-OSC32_IN
PC15-OSC32_OUT
PD0-OSC_IN
PD1-OSC_OUT
NRST
VSSA
VDDA
PA0-WKUP
PA1
PA2
VDD_3
VSS_3
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PA15
PA14
ai14378d
PC13-TAMPER-RTC
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17 18 19 20 21 22 23 24 29 30 31 3225 26 27 28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VBAT
PC14-OSC32_IN
PC15-OSC32_OUT
PD0-OSC_IN
PD1-OSC_OUT
NRST
PC0
PC1
PC2
PC3
VSSA
VDDA
PA 0 - W K U P
PA1
PA2
VDD_3
VSS_3
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PD2
PC12
PC11
PC10
PA 1 5
PA 1 4
VDD_2
VSS_2
PA 13
PA 12
PA 11
PA 10
PA 9
PA 8
PC9
PC8
PC7
PC6
PB15
PB14
PB13
PB12
PA3
VSS_4
VDD_4
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PB10
PB11
VSS_1
VDD_1
LQFP64
ai14387c
PC13-TAMPER-RTC
DS5934 Rev 6 21/79
STM32F102x4, STM32F102x6 Pinout and pin description
67
Table 4. Low-density STM32F102xx pin definitions
Pins
Pin name
Type(1)
I / O level(2)
Main
function(3)
(after reset)
Alternate functions(3) (4)
LQFP48
LQFP64
Default Remap
11 V
BAT S- V
BAT --
2 2 PC13-TAMPER-RTC(5) I/O - PC13(6) TAMPER-RTC -
3 3 PC14-OSC32_IN(5) I/O - PC14(6) OSC32_IN -
4 4 PC15-OSC32_OUT(5) I/O - PC15(6) OSC32_OUT -
5 5 OSC_IN I/O FT OSC_IN - PD0(7)
6 6 OSC_OUT I/O FT OSC_OUT - PD1(7)
7 7 NRST I/O - NRST - -
- 8 PC0 I/O - PC0 ADC_IN10 -
- 9 PC1 I/O - PC1 ADC_IN11 -
- 10 PC2 I/O - PC2 ADC_IN12 -
- 11 PC3 I/O - PC3 ADC_IN13 -
812 V
SSA S- V
SSA --
913 V
DDA S- V
DDA --
10 14 PA0-WKUP I/O - PA0
WKUP/USART2_CTS/
ADC_IN0/
TIM2_CH1_ETR(8)
-
11 15 PA1 I/O - PA1 USART2_RTS/
ADC_IN1/TIM2_CH2(8) -
12 16 PA2 I/O - PA2 USART2_TX/
ADC_IN2/TIM2_CH3(8) -
13 17 PA3 I/O - PA3 USART2_RX/
ADC_IN3/TIM2_CH4(8) -
-18 V
SS_4 S- V
SS_4 --
-19 V
DD_4 S- V
DD_4 --
14 20 PA4 I/O - PA4 SPI_NSS(8)/ADC_IN4
USART2_CK/ -
15 21 PA5 I/O - PA5 SPI_SCK(8)/ADC_IN5 -
16 22 PA6 I/O - PA6 SPI_MISO(8)/ADC_IN6/
TIM3_CH1(8) -
17 23 PA7 I/O - PA7 SPI_MOSI(8)/ADC_IN7/
TIM3_CH2(8) -
- 24 PC4 I/O - PC4 ADC_IN14 -
- 25 PC5 I/O - PC5 ADC_IN15 -
18 26 PB0 I/O - PB0 ADC_IN8/TIM3_CH3(8) -
19 27 PB1 I/O - PB1 ADC_IN9/TIM3_CH4(8) -
Pinout and pin description STM32F102x4, STM32F102x6
22/79 DS5934 Rev 6
20 28 PB2 I/O FT PB2/BOOT1 - -
21 29 PB10 I/O FT PB10 (8) TIM2_CH3
22 30 PB11 I/O FT PB11 (8) TIM2_CH4
23 31 VSS_1 S- V
SS_1 --
24 32 VDD_1 S- V
DD_1 --
25 33 PB12 I/O FT PB12 (8) -
26 34 PB13 I/O FT PB13 - -
27 35 PB14 I/O FT PB14 - -
28 36 PB15 I/O FT PB15 - -
- 37 PC6 I/O FT PC6 - TIM3_CH1
- 38 PC7 I/O FT PC7 - TIM3_CH2
- 39 PC8 I/O FT PC8 - TIM3_CH3
- 40 PC9 I/O FT PC9 - TIM3_CH4
29 41 PA8 I/O FT PA8 USART1_CK/MCO -
30 42 PA9 I/O FT PA9 USART1_TX(8) -
31 43 PA10 I/O FT PA10 USART1_RX(8) -
32 44 PA11 I/O FT PA11 USART1_CTS/USB_DM -
33 45 PA12 I/O FT PA12 USART1_RTS/USB_DP -
34 46 PA13 I/O FT JTMS-
SWDIO -PA13
35 47 VSS_2 S- V
SS_2 --
36 48 VDD_2 S- V
DD_2 --
37 49 PA14 I/O FT JTCK/
SWCLK -PA14
38 50 PA15 I/O FT JTDI -
TIM2_CH1_ETR
/ PA15
/SPI_NSS
-51 PC10 I/OFT PC10 - -
-52 PC11 I/OFT PC11 - -
-53 PC12 I/OFT PC12 - -
- 54 PD2 I/O FT PD2 - -
39 55 PB3 I/O FT JTDO -
TIM2_CH2/ PB3/
TRACESWO/
SPI_SCK
Table 4. Low-density STM32F102xx pin definitions (continued)
Pins
Pin name
Type(1)
I / O level(2)
Main
function(3)
(after reset)
Alternate functions(3) (4)
LQFP48
LQFP64
Default Remap
DS5934 Rev 6 23/79
STM32F102x4, STM32F102x6 Pinout and pin description
67
40 56 PB4 I/O FT JNTRST - TIM3_CH1 / PB4
SPI_MISO
41 57 PB5 I/O - PB5 I2C_SMBA TIM3_CH2 /
SPI_MOSI
42 58 PB6 I/O FT PB6 I2C_SCL(8) USART1_TX
43 59 PB7 I/O FT PB7 I2C_SDA(8) USART1_RX
44 60 BOOT0 I - BOOT0 - -
45 61 PB8 I/O FT PB8 - I2C_SCL
46 62 PB9 I/O FT PB9 - I2C_SDA
47 63 VSS_3 S- V
SS_3 --
48 64 VDD_3 S- V
DD_3 --
1. I = input, O = output, S = supply.
2. FT= 5 V-tolerant.
3. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower
number of peripherals that is included. For example, if a device has only one SPI, two USARTs and two timers, they will be
called SPI1, USART1 & USART2 and TIM2 & TIM 3, respectively. Refer to Table 3.
4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should
be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).
5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3
mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum load
of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED).
6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even
after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the
Battery backup domain and BKP register description sections in the STM32F102xx reference manual, available from
www.st.com.
7. The pins number 5 and 6 in the LQFP48 package are configured as OSC_IN/OSC_OUT after reset, however the
functionality of PD0 and PD1 can be remapped by software on these pins. For more details, refer to the Alternate function
I/O and debug configuration section in the STM32F10xxx reference manual.
The use of PD0 and PD1 in output mode is limited as they can only be used at 50 MHz in output mode.
8. This alternate function can be remapped by software to some other port pins (if available on the used package). For more
details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual,
available from www.st.com.
Table 4. Low-density STM32F102xx pin definitions (continued)
Pins
Pin name
Type(1)
I / O level(2)
Main
function(3)
(after reset)
Alternate functions(3) (4)
LQFP48
LQFP64
Default Remap
Memory mapping STM32F102x4, STM32F102x6
24/79 DS5934 Rev 6
4 Memory mapping
The memory map is shown in Figure 5.
Figure 5. Memory map
APB memory space
DMA
RTC
WWDG
IWDG
USART2
ADC1
USART1
SPI
EXTI
RCC
0
1
2
3
4
5
6
7
Peripherals
SRAM
reserved
reserved
Option Bytes
Reserved
0x4000 0000
0x4000 0400
0x4000 0800
0x4000 2800
0x4000 2C00
0x4000 3000
0x4000 3400
0x4000 4400
0x4000 4800
0x4000 5400
0x4000 5800
0x4000 5C00
0x4000 6000
0x4000 6400
0x4000 6C00
0x4000 7000
0x4000 7400
0x4001 0000
0x4001 0400
0x4001 0800
0x4001 0C00
0x4001 1000
0x4001 1400
0x4001 1800
0x4001 2400
0x4001 2800
0x4001 2C00
0x4001 3000
0x4001 3400
0x4001 3800
0x4001 3C00
0x4002 0000
0x4002 0400
0x4002 1000
0x4002 1400
0x4002 2000
0x4002 2400
0x4002 3000
0x4002 3400
0xE010 0000
0xFFFF FFFF
reserved
reserved
CRC
reserved
reserved
Flash interface
reserved
reserved
reserved
reserved
reserved
reserved
Port D
Port C
Port B
Port A
AFIO
PWR
BKP
reserved
512 byte USB SRAM
USB registers
I2C
reserved
reserved
reserved
TIM3
TIM2
0xFFFF FFFF
0xE010 0000
0xE000 0000
0xC000 0000
0xA000 0000
0x8000 0000
0x6000 0000
0x4000 0000
0x2000 0000
0x0000 0000
0x1FFF FFFF
0x1FFF F80F
0x1FFF F800
0x1FFF F000
0x0800 FFFF
0x0800 0000
System memory
Flash memory
Cortex-M3 internal
peripherals
ai15454b
0x2000 17FF
0xE000 0000
Cortex-M3 internal
peripherals
0x0000 0000
Aliased to Flash or
system memory
depending on
BOOT pins
reserved
reserved
DS5934 Rev 6 25/79
STM32F102x4, STM32F102x6 Electrical characteristics
67
5 Electrical characteristics
5.1 Parameter conditions
Unless otherwise specified, all voltages are referred to VSS.
5.1.1 Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3σ).
5.1.2 Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the
2V VDD 3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2σ).
5.1.3 Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
5.1.4 Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 6.
5.1.5 Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 7.
Figure 6. Pin loading conditions I Figure 7. Pin input voltage VBAT r1 LJ
Electrical characteristics STM32F102x4, STM32F102x6
26/79 DS5934 Rev 6
5.1.6 Power supply scheme
Figure 8. Power supply scheme
Caution: In Figure 8, the 4.7 µF capacitor must be connected to VDD3.
Figure 6. Pin loading conditions Figure 7. Pin input voltage
ai14972
C = 50 pF
STM32F102 pi
n
ai14973
STM32F102 pi
n
VIN
DS5934 Rev 6 27/79
STM32F102x4, STM32F102x6 Electrical characteristics
67
5.1.7 Current consumption measurement
Figure 9. Current consumption measurement scheme
5.2 Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 5, Table 6, and Table 7 may
cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these conditions is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability. Device mission profile
(application conditions) is compliant with JEDEC JESD47 Qualification Standard, extended
mission profiles are available on demand.
ai14126
VBAT
VDD
VDDA
IDD_VBAT
IDD
Table 5. Voltage characteristics
Symbol Ratings Min Max Unit
VDD VSS
External main supply voltage (including
VDDA and VDD)(1)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
–0.3 4.0
V
VIN(2)
2. VIN maximum must always be respected. Refer to Table 6 for the maximum allowed injected current
values.
Input voltage on 5 V-tolerant pin VSS 0.3 VDD + 4.0
Input voltage on any other pin VSS 0.3 4.0
|ΔVDDx| Variations between different VDD power pins - 50
mV
|VSSX VSS|Variations between all the different ground
pins -50
VESD(HBM)
Electrostatic discharge voltage
(human body model)
See Section 5.3.11: Absolute
maximum ratings (electrical sensitivity)
Electrical characteristics STM32F102x4, STM32F102x6
28/79 DS5934 Rev 6
Table 6. Current characteristics
Symbol Ratings Max. Unit
IVDD Total current into VDD/VDDA power lines (source)(1)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
150
mA
IVSS Total current out of VSS ground lines (sink)(1) 150
IIO
Output current sunk by any I/O and control pin 25
Output current source by any I/Os and control pin -25
IINJ(PIN) (2)
2. Negative injection disturbs the analog performance of the device.
Injected current five volt tolerant pins(3)
3. Positive injection is not possible on these I/Os. A negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer to Table 5 for maximum allowed input voltage values.
-5/+0
Injected current on any other pin(4)
4. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer to Table 5 for maximum allowed input voltage values.
± 5
ΣIINJ(PIN) Total injected current (sum of all I/O and control pins)(5)
5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values).
± 25
Table 7. Thermal characteristics
Symbol Ratings Value Unit
TSTG Storage temperature range –65 to +150 °C
TJMaximum junction temperature 150 °C
DS5934 Rev 6 29/79
STM32F102x4, STM32F102x6 Electrical characteristics
67
5.3 Operating conditions
5.3.1 General operating conditions
5.3.2 Operating conditions at power-up / power-down
Subject to general operating conditions for TA.
Table 8. General operating conditions
Symbol Parameter Conditions Min Max Unit
fHCLK Internal AHB clock frequency - 0 48
MHzfPCLK1 Internal APB1 clock frequency - 0 24
fPCLK2 Internal APB2 clock frequency - 0 48
VDD Standard operating voltage - 2 3.6 V
VDDA(1)
1. When the ADC is used, refer to Table 45: ADC characteristics.
Analog operating voltage
(ADC not used) Must be the same potential
as VDD(2)
2. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV
between VDD and VDDA can be tolerated during power-up and operation.
23.6
V
Analog operating voltage
(ADC used) 2.4 3.6
VIN I/O input voltage
Standard IO –0.3 VDD+
0.3
FTIO(3)
3. To sustain a voltage higher than VDD+0.3 V, the internal pull-up/pull-down resistors must be disabled.
2 V < VDD 3.6 V –0.3 5.5
VDD = 2 V –0.3 5.2
BOOT0 0 5.5
PDPower dissipation at TA = 85 °C(4)
4. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Section 6.3:
Thermal characteristics).
LQFP48 - 363
mW
LQFP64 - 444
TA Ambient temperature
Maximum power dissipation –40 85 °C
Low power dissipation(5)
5. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see
Section 6.3: Thermal characteristics).
–40 105 °C
TJ Junction temperature range - –40 105 °C
Table 9. Operating conditions at power-up / power-down
Symbol Parameter Conditions Min Max Unit
tVDD
VDD rise time rate
-
0
µs/V
VDD fall time rate 20
Electrical characteristics STM32F102x4, STM32F102x6
30/79 DS5934 Rev 6
5.3.3 Embedded reset and power control block characteristics
The parameters given in Table 10 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 8.
.
5.3.4 Embedded reference voltage
The parameters given in Table 11 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 8.
Table 10. Embedded reset and power control block characteristics
Symbol Parameter Conditions Min Typ Max Unit
VPVD
Programmable voltage
detector level selection
PLS[2:0]=000 (rising edge) 2.1 2.18 2.26 V
PLS[2:0]=000 (falling edge) 2.0 2.08 2.16 V
PLS[2:0]=001 (rising edge) 2.19 2.28 2.37 V
PLS[2:0]=001 (falling edge) 2.09 2.18 2.27 V
PLS[2:0]=010 (rising edge) 2.28 2.38 2.48 V
PLS[2:0]=010 (falling edge) 2.18 2.28 2.38 V
PLS[2:0]=011 (rising edge) 2.38 2.48 2.58 V
PLS[2:0]=011 (falling edge) 2.28 2.38 2.48 V
PLS[2:0]=100 (rising edge) 2.47 2.58 2.69 V
PLS[2:0]=100 (falling edge) 2.37 2.48 2.59 V
PLS[2:0]=101 (rising edge) 2.57 2.68 2.79 V
PLS[2:0]=101 (falling edge) 2.47 2.58 2.69 V
PLS[2:0]=110 (rising edge) 2.66 2.78 2.9 V
PLS[2:0]=110 (falling edge) 2.56 2.68 2.8 V
PLS[2:0]=111 (rising edge) 2.76 2.88 3 V
PLS[2:0]=111 (falling edge) 2.66 2.78 2.9 V
VPVDhyst(2) PVD hysteresis - - 100 - mV
VPOR/PDR
Power on/power down
reset threshold
Falling edge 1.8(1)
1. The product behavior is guaranteed by design down to the minimum VPOR/PDR value.
1.88 1.96 V
Rising edge 1.84 1.92 2.0 V
VPDRhyst PDR hysteresis - - 40 - mV
tRSTTEMPO(2)
2. Guaranteed by design, not tested in production.
Reset temporization - 1.5 2.5 4.5 ms
DS5934 Rev 6 31/79
STM32F102x4, STM32F102x6 Electrical characteristics
67
5.3.5 Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as shown in Figure 9.
All Run mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to Dhrystone 2.1 code.
Maximum current consumption
The MCU is placed under the following conditions:
All I/O pins are in input mode with a static value at VDD or VSS (no load)
All peripherals are disabled except if it is explicitly mentioned
The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1
wait state from 24 to 48 MHz)
Prefetch in on (reminder: this bit must be set before clock setting and bus prescaling)
When the peripherals are enabled fPCLK1 = fHCLK/2, fPCLK2 = fHCLK
The parameters given in Table 12 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 8.
Table 11. Embedded internal reference voltage
Symbol Parameter Conditions Min Typ Max Unit
VREFINT Internal reference voltage –40 °C < TA < +85 °C 1.16 1.20 1.24 V
TS_vrefint(1)
1. Shortest sampling time can be determined in the application by multiple iterations.
ADC sampling time when reading
the internal reference voltage - - 5.1 17.1(2)
2. Guaranteed by design, not tested in production.
µs
VRERINT(2) Internal reference voltage spread
over the temperature range VDD = 3 V ±10 mV - - 10 mV
TCoeff(2) Temperature coefficient - - - 100 ppm/
°C
Electrical characteristics STM32F102x4, STM32F102x6
32/79 DS5934 Rev 6
Table 12. Maximum current consumption in Run mode, code with data processing
running from Flash memory
Symbol Parameter Conditions fHCLK
Max(1)
1. Based on characterization results, not tested in production.
Unit
TA = 85 °C
IDD
Supply current
in Run mode
External clock (2), all
peripherals enabled
2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
48 MHz 32
mA
36 MHz 26
24 MHz 18
16 MHz 13
8 MHz 7
External clock (2), all
peripherals Disabled
48 MHz 23
36 MHz 19
24 MHz 13
16 MHz 10
8 MHz 6
Table 13. Maximum current consumption in Run mode, code with data processing
running from RAM
Symbol Parameter Conditions fHCLK
Max
Unit
TA = 85 °C(1)
1. Based on characterization, tested in production at VDD max, fHCLK max.
IDD
Supply current in
Run mode
External clock (2), all
peripherals enabled
2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
48 MHz 27
mA
36 MHz 20
24 MHz 14
16 MHz 10
8 MHz 6
External clock(2) all
peripherals disabled
48 MHz 19
36 MHz 15
24 MHz 10
16 MHz 7
8 MHz 5
+ Jr + Jr
DS5934 Rev 6 33/79
STM32F102x4, STM32F102x6 Electrical characteristics
67
Figure 10. Typical current consumption in Run mode versus temperature (at 3.6 V),
code with data processing running from RAM, peripherals enabled
Figure 11. Typical current consumption in Run mode versus temperature (at 3.6 V),
code with data processing running from RAM, peripherals disabled
0
5
10
15
20
25
30
–40 °C 25 °C 0 °C 70 °C 85 °C
Temperature (°C)
Consumption (mA)
48 MHz
36MHz
16 MHz
8 MHz
0
2
4
6
8
10
12
14
16
18
20
–40 °C 25 °C 0 °C 70 °C 85 °C
Temperature (°C)
Consumption (mA)
48 MHz
36 MHz
16 MHz
8 MHz
Electrical characteristics STM32F102x4, STM32F102x6
34/79 DS5934 Rev 6
Table 14. Max. current consumption in Sleep mode, code running from Flash memory or RAM
Symbol Parameter Conditions fHCLK
Max(1)
Unit
TA = 85 °C
IDD
Supply current in
Sleep mode
External clock(2), all
peripherals enabled
48 MHz 17
mA
36 MHz 14
24 MHz 10
16 MHz 7
8 MHz 4
External clock(2), all
peripherals disabled
48 MHz 6
36 MHz 5
24 MHz 4.5
16 MHz 4
8 MHz 3
1. Based on characterization, tested in production at VDD max and fHCLK max with peripherals enabled.
2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
Table 15. Typical and maximum current consumptions in Stop and Standby modes
Symbol Parameter Conditions
Typ(1) Max
Unit
VDD/
VBAT =
2.4 V
VDD/VBAT
= 3.3 V
VDD/VBAT
= 2.0 V
TA =
85 °C
IDD
Supply current
in Stop mode
Regulator in Run mode.
Low-speed and high-speed internal
RC oscillators and high-speed
oscillator OFF (no independent
watchdog)
21.3 21.7 - 160
µA
Regulator in Low Power mode.
Low-speed and high-speed internal
RC oscillators and high-speed
oscillator OFF (no independent
watchdog)
11.3 11.7 - 145
Supply current
in Standby
mode(2)
Low-speed internal RC oscillator and
independent watchdog ON 2.75 3.4 - -
Low-speed internal RC oscillator ON,
independent watchdog OFF 2.55 3.2 - -
Low-speed internal RC oscillator and
independent watchdog OFF, low-
speed oscillator and RTC OFF
1.55 1.9 - 3.2
IDD_VBAT
Backup
domain supply
current
Low-speed oscillator and RTC ON 1.1 1.4 0.9 1.9(3)
1. Typical values are measured at TA = 25 °C.
BAT DD
DS5934 Rev 6 35/79
STM32F102x4, STM32F102x6 Electrical characteristics
67
Figure 12. Typical current consumption on VBAT with RTC on versus temperature
for different VBAT values
Figure 13. Typical current consumption in Stop mode with regulator in Run mode
versus temperature, VDD = 3.3 / 3.6 V
2. To have the Standby consumption with RTC ON, add IDD_VBAT (Low-speed oscillator and RTC ON) to IDD Standby (when
VDD is present the Backup Domain is powered by VDD supply).
3. Based on characterization, not tested in production.
0
0.5
1
1.5
2
2.5
–40 °C 25 °C 70 °C 85 °C 105 °C
Temperature (°C)
Consumption ( µA )
2 V
2.4 V
3 V
3.6 V
ai17351
0
5
10
15
20
25
30
35
40
45
–45 °C 25 °C 85 °C
Temperature (°C)
Consumption (µA)
3.3 V
3.6 V
DD DD
Electrical characteristics STM32F102x4, STM32F102x6
36/79 DS5934 Rev 6
Figure 14. Typical current consumption in Stop mode with regulator in Low-power mode
versus temperature, VDD = 3.3 / 3.6 V
Figure 15. Typical current consumption in Standby mode versus temperature, VDD = 3.3 / 3.6 V
0
5
10
15
20
25
30
–45 °C 25 °C 85 °C
Temperature (°C)
Consumption (µA)
3.3 V
3.6 V
0
0.5
1
1.5
2
2.5
3
3.5
–45 °C 25 °C 85 °C
Temperature (°C)
Consumption (µA)
3.3 V
3.6 V
DS5934 Rev 6 37/79
STM32F102x4, STM32F102x6 Electrical characteristics
67
Typical current consumption
The MCU is placed under the following conditions:
All I/O pins are in input mode with a static value at VDD or VSS (no load)
All peripherals are disabled except if it is explicitly mentioned
The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1
wait state from 24 to 48 MHz)
Prefetch is on (reminder: this bit must be set before clock setting and bus prescaling)
When the peripherals are enabled fPCLK1 = fHCLK/4, fPCLK2 = fHCLK/2,
fADCCLK = fPCLK2 / 4
The parameters given in Table 16 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 8.
Table 16. Typical current consumption in Run mode, code with data processing
running from Flash memory
Symbol Parameter Conditions fHCLK
Typ(1)
1. Typical values are measures at TA = 25 °C, VDD = 3.3 V.
Typ(1)
Unit
All peripherals
enabled(2)
2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this
consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).
All peripherals
disabled
IDD
Supply
current in
Run mode
External
clock(3)
48 MHz 21.9 17.4
mA
36 MHz 17.2 13.8
24 MHz 11.2 8.9
16 MHz 8.1 6.6
8 MHz 5 4.2
4 MHz 3 2.6
2 MHz 2 1.8
1 MHz 1.5 1.4
500 kHz 1.2 1.2
125 kHz 1.05 1
Running on
high speed
internal RC
(HSI), AHB
prescaler
used to
reduce the
frequency
48 MHz 21.2 16.7
36 MHz 16.5 13.1
24 MHz 10.5 8.2
16 MHz 7.4 5.9
8 MHz 4.3 3.6
4 MHz 2.4 2
2 MHz 1.5 1.3
1 MHz 1.0 0.9
500 kHz 0.7 0.65
125 kHz 0.5 0.45
Electrical characteristics STM32F102x4, STM32F102x6
38/79 DS5934 Rev 6
3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
Table 17. Typical current consumption in Sleep mode, code running from Flash
memory or RAM
Symbol Parameter Conditions fHCLK
Typ(1)
1. Typical values are measures at TA = 25 °C, VDD = 3.3 V.
Typ(1)
Unit
All peripherals
enabled(2)
2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this
consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).
All peripherals
disabled
IDD
Supply
current in
Sleep mode
External clock(3)
3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
48 MHz 8.7 3.8
mA
36 MHz 6.7 3.1
24 MHz 4.8 2.3
16 MHz 3.4 1.8
8 MHz 2 1.2
4 MHz 1.5 1.1
2 MHz 1.25 1
1 MHz 1.1 0.98
500 kHz 1.05 0.96
125 kHz 1 0.95
Running on High
Speed Internal
RC (HSI), AHB
prescaler used to
reduce the
frequency
48 MHz 8.1 3.2
36 MHz 6.1 2.5
24 MHz 4.2 1.7
16 MHz 2.8 1.2
8 MHz 1.4 0.55
4 MHz 0.9 0.5
2 MHz 0.7 0.45
1 MHz 0.55 0.42
500 kHz 0.48 0.4
125 kHz 0.4 0.38
DS5934 Rev 6 39/79
STM32F102x4, STM32F102x6 Electrical characteristics
67
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in Table 18. The MCU is placed
under the following conditions:
all I/O pins are in input mode with a static value at VDD or VSS (no load)
all peripherals are disabled unless otherwise mentioned
the given value is calculated by measuring the current consumption
with all peripherals clocked off
with only one peripheral clocked on
ambient operating temperature and VDD supply voltage conditions as summarized in
Table 5.
Table 18. Peripheral current consumption(1)
1. fHCLK = 48 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, default prescaler value for each peripheral.
Peripheral µA/MHz
AHB (up to 48 MHz)
DMA1 15.97
CRC 1.67
BusMatrix(2)
2. The BusMatrix is automatically active when at least one master is ON.
8.33
APB1 (up to 24 MHz)
APB1-Bridge 7.22
TIM2 33.33
TIM3 33.61
USART2 12.78
I2C1 10.83
USB 16.94
WWDG 3.33
PWR 1.94
BKP 2.78
IWDG 1.39
APB2 (up to 48 MHz)
APB2-Bridge 3.33
GPIOA 7.50
GPIOB 6.81
GPIOC 7.22
GPIOD 6.94
SPI1 4.86
USART1 12.78
ADC1(3) (4)
3. Specific conditions for ADC: fHCLK = 48 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, fADCCLK = fAPB2/4.
4. When ADON bit in the ADC_CR2 register is set to 1, there is an additional current consumption of 0.68 mA.
When the ADC is enabled there is an additional current consumption of 0.06 mA.
15.54
Electrical characteristics STM32F102x4, STM32F102x6
40/79 DS5934 Rev 6
5.3.6 External clock source characteristics
High-speed external user clock generated from an external source
The characteristics given in Table 19 result from tests performed using an high-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 8.
Low-speed external user clock generated from an external source
The characteristics given in Table 20 result from tests performed using an low-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 8.
Table 19. High-speed external user clock characteristics
Symbol Parameter Conditions Min Typ Max Unit
fHSE_ext User external clock source frequency(1)
-
1825MHz
VHSEH OSC_IN input pin high level voltage 0.7VDD -V
DD V
VHSEL OSC_IN input pin low level voltage VSS -0.3V
DD
tw(HSE)
tw(HSE)
OSC_IN high or low time(1) 5- -
ns
tr(HSE)
tf(HSE)
OSC_IN rise or fall time(1) --20
Cin(HSE) OSC_IN input capacitance(1) -5 -pF
DuCy(HSE) Duty cycle 45 - 55 %
ILOSC_IN Input leakage current VSS VIN VDD 1µA
1. Guaranteed by design, not tested in production.
Table 20. Low-speed external user clock characteristics
Symbol Parameter Conditions Min Typ Max Unit
fLSE_ext User external clock source frequency(1)
-
- 32.768 1000 kHz
VLSEH OSC32_IN input pin high level voltage 0.7VDD -V
DD V
VLSEL OSC32_IN input pin low level voltage VSS -0.3V
DD
tw(LSE)
tw(LSE)
OSC32_IN high or low time(1) 450 - -
ns
tr(LSE)
tf(LSE)
OSC32_IN rise or fall time(1) --50
Cin(LSE) OSC32_IN input capacitance(1) -5-pF
DuCy(LSE) Duty cycle 30 - 70 %
ILOSC32_IN Input leakage current VSS VIN VDD --±1µA
1. Guaranteed by design, not tested in production.
DS5934 Rev 6 41/79
STM32F102x4, STM32F102x6 Electrical characteristics
67
Figure 16. High-speed external clock source AC timing diagram
Figure 17. Low-speed external clock source AC timing diagram
ai14975b
OSC _I N
STM32F102xx
VHSEH
tf(HSE) tW(HSE)
IL
90%
10%
THSE
t
tr(HSE) tW(HSE)
fHSE_ext
VHSEL
External
clock source
ai14976
b
OSC32_IN
STM32F102xx
VLSEH
tf(LSE) tW(LSE)
IL
90%
10%
TLSE
t
tr(LSE) tW(LSE)
fLSE_ext
VLSEL
External
clock source
Electrical characteristics STM32F102x4, STM32F102x6
42/79 DS5934 Rev 6
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 21. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
For CL1 and CL2 it is recommended to use high-quality external ceramic capacitors in the
5 pF to 25 pF range (typical), designed for high-frequency applications, and selected to
match the requirements of the crystal or resonator (see Figure 18). CL1 and CL2 are usually
the same size. The crystal manufacturer typically specifies a load capacitance that is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2. Refer to Oscillator design guide for ST microcontrollers (AN2867) available on
www.st.com.
Table 21. HSE 4-16 MHz oscillator characteristics(1)(2)
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. Based on characterization results, not tested in production.
Symbol Parameter Conditions Min Typ Max Unit
fOSC_IN Oscillator frequency - 4 8 16 MHz
RFFeedback resistor - - 200 - kΩ
C
Recommended load capacitance
versus equivalent serial
resistance of the crystal (RS)(3)
3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a
humid environment, due to the induced leakage and the bias condition change. However, it is
recommended to take this point into account if the MCU is used in tough humidity conditions.
RS = 30 Ω -30- pF
i2HSE driving current VDD = 3.3 V
VIN = VSS with 30 pF load --1mA
gmOscillator transconductance Startup 25 - - mA/V
tSU(HSE)(4)
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer
Startup time VDD is stabilized - 2 - ms
DS5934 Rev 6 43/79
STM32F102x4, STM32F102x6 Electrical characteristics
67
Figure 18. Typical application with an 8 MHz crystal
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 22. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
ai14977b
OSC_OUT
OSC_IN fHSE
CL1
RF
STM32F102xx
8 MHz
resonator
Bias
controlled
gain
REXT(1)
CL2
Resonator with
integrated capacitors
Table 22. LSE oscillator characteristics (fLSE = 32.768 kHz)
Symbol Parameter Conditions Min Typ Max Unit
RFFeedback resistor - - 5 - MΩ
C(1)
Recommended load capacitance
versus equivalent serial
resistance of the crystal (RS)
RS = 30 kΩ--15pF
I2LSE driving current VDD = 3.3 V
VIN = VSS
--1.4µA
gmOscillator transconductance - 5 - - µA/V
tSU(LSE)(2) Startup time VDD is stabilized
TA = 50 °C - 1.5 -
s
TA = 25 °C - 2.5 -
TA = 10 °C - 4.0 -
TA = 0 °C - 6.0 -
TA = -10 °C - 10.0 -
TA = -20 °C - 17.0 -
TA = -30 °C - 32.0 -
TA = -40 °C - 60.0 -
1. Refer to the note and caution paragraphs below the table, and to Oscillator design guide for ST microcontrollers (AN2867).
2. tSU(LSE) is the startup time measured from the moment it is enabled by software to a stabilized 32.768 kHz oscillation is
reached. This value is measured for a standard crystal and can vary significantly with the crystal manufacturer, PCB layout
and humidity.
Electrical characteristics STM32F102x4, STM32F102x6
44/79 DS5934 Rev 6
Note: For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5 pF to
15 pF range selected to match the requirements of the crystal or resonator. CL1 and CL2
are usually the same size. The crystal manufacturer typically specifies a load capacitance
which is the series combination of CL1 and CL2.
Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray
where Cstray is the pin capacitance and board or trace PCB-related capacitance. Typically, it
is between 2 pF and 7 pF.
Caution: To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended
to use a resonator with a load capacitance CL 7 pF. Never use a resonator with a load
capacitance of 12.5 pF.
Example: For a resonator with a load capacitance of CL = 6 pF, and Cstray = 2 pF, then
CL1 = CL2 = 8 pF.
Figure 19. Typical application with a 32.768 kHz crystal
5.3.7 Internal clock source characteristics
The parameters given in Table 23 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 8.
High-speed internal (HSI) RC oscillator
ai17531c
STM32
OSC32_OUT
fHSE
CL1
RF
32.768 kHz
resonator
Bias
controlled
gain
OSC32_IN
CL2
Resonator with
integrated capacitors
Table 23. HSI oscillator characteristics(1)
1. VDD = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
fHSI Frequency - - 8 - MHz
DuCy(HSI) Duty cycle - 45 - 55 %
ACCHSI
Accuracy of the HSI
oscillator
User-trimmed with the RCC_CR
register(2)
2. Refer to STM32F10xxx internal RC oscillator (HSI) calibration (AN2868) “” available from www.st.com.
--1
(3) %
Factory-
calibrated(4)(5)
TA = –40 to 105 °C –2.0 - 2.5 %
TA = –10 to 85 °C –1.5 - 2.2 %
TA = 0 to 70 °C –1.3 - 2 %
TA = 25 °C –1.1 - 1.8 %
tsu(HSI)(4) HSI oscillator
startup time -1-2µs
IDD(HSI)(4) HSI oscillator power
consumption --80100µA
DS5934 Rev 6 45/79
STM32F102x4, STM32F102x6 Electrical characteristics
67
Low-speed internal (LSI) RC oscillator
Wakeup time from Low-power mode
The wakeup times given in Table 25 is measured on a wakeup phase with a 8-MHz HSI RC
oscillator. The clock source used to wake up the device depends from the current operating
mode:
Stop or Standby mode: the clock source is the RC oscillator
Sleep mode: the clock source is the clock that was set before entering Sleep mode.
All timings are derived from tests performed under ambient temperature and VDD supply
voltage conditions summarized in Table 8.
5.3.8 PLL characteristics
The parameters given in Table 26 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 8.
3. Guaranteed by design, not tested in production.
4. Based on characterization, not tested in production.
5. The actual frequency of HSI oscillator may be impacted by a reflow, but does not drift out of the specified
range.
Table 24. LSI oscillator characteristics (1)
1. VDD = 3 V, TA = 40 to 85 °C unless otherwise specified.
Symbol Parameter Min(2)
2. Based on characterization, not tested in production.
Typ Max Unit
fLSI Frequency 30 40 60 kHz
tsu(LSI)(3)
3. Guaranteed by design, not tested in production.
LSI oscillator startup time - - 85 µs
IDD(LSI)(3) LSI oscillator power consumption - 0.65 1.2 µA
Table 25. Low-power mode wakeup timings
Symbol Parameter Typ Unit
tWUSLEEP(1)
1. The wakeup times are measured from the wakeup event to the point at which the user application code
reads the first instruction.
Wakeup from Sleep mode 1.8
µstWUSTOP(1) Wakeup from Stop mode (regulator in run mode) 3.6
Wakeup from Stop mode (regulator in low-power mode) 5.4
tWUSTDBY(1) Wakeup from Standby mode 50
Electrical characteristics STM32F102x4, STM32F102x6
46/79 DS5934 Rev 6
5.3.9 Memory characteristics
Flash memory
The characteristics are given at TA = –40 to 85 °C unless otherwise specified.
Table 26. PLL characteristics
Symbol Parameter
Value
Unit
Min(1) Typ Max(1)
fPLL_IN
PLL input clock(2) 18.025MHz
PLL input clock duty cycle 40 - 60 %
fPLL_OUT PLL multiplier output clock 16 - 48 MHz
tLOCK PLL lock time - - 200 µs
Jitter Cycle-to-cycle jitter - - 300 ps
1. Based on characterization, not tested in production.
2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by fPLL_OUT.
Table 27. Flash memory characteristics
Symbol Parameter Conditions Min(1)
1. Guaranteed by design, not tested in production.
Typ Max(1) Unit
tprog 16-bit programming time TA = –40 to +85 °C 40 52.5 70 µs
tERASE Page (1 KB) erase time TA = –40 to +85 °C 20 - 40 ms
tME Mass erase time TA = –40 to +85 °C 20 - 40 ms
IDD Supply current
Read mode
fHCLK = 48 MHz with 2
wait states, VDD = 3.3 V
--20mA
Write / Erase modes
fHCLK = 48 MHz, VDD =
3.3 V
--5mA
Power-down mode / Halt,
VDD = 3.0 to 3.6 V --50µA
Vprog Programming voltage - 2 - 3.6 V
Table 28. Flash memory endurance and data retention
Symbol Parameter Conditions
Value
Unit
Min(1) Typ Max
NEND Endurance 10 - - kcycles
tRET Data retention TA = 85 °C, 1000 cycles 30 - - Years
1. Based on characterization not tested in production.
DS5934 Rev 6 47/79
STM32F102x4, STM32F102x6 Electrical characteristics
67
5.3.10 EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling two LEDs through I/O ports),
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS
through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant
with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 29. They are based on the EMS levels and classes
defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and pre
qualification tests in relation with the EMC level requested for his application.
Software recommendations: the software flowchart must include the management of
runaway conditions such as:
Corrupted program counter
Unexpected reset
Critical data corruption (control registers, etc.)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the oscillator pins for one
second. To complete these trials, ESD stress can be applied directly on the device, over the
range of specification values. When unexpected behavior is detected, the software can be
hardened to prevent unrecoverable errors occurring (see application note AN1015).
Table 29. EMS characteristics
Symbol Parameter Conditions Level/Class
VFESD
Voltage limits to be applied on any I/O pin to
induce a functional disturbance
VDD = 3.3 V, TA = +25 °C,
fHCLK= 48 MHz
conforms to IEC 61000-4-2
2B
VEFTB
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS pins
to induce a functional disturbance
VDD = 3.3 V, TA = +25 °C,
fHCLK = 48 MHz
conforms to IEC 61000-4-4
4A
Electrical characteristics STM32F102x4, STM32F102x6
48/79 DS5934 Rev 6
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device is monitored while a simple application is
executed (toggling two LEDs through the I/O ports), This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
5.3.11 Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
A supply overvoltage is applied to each power supply pin
A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78 IC latch-up standard.
Table 30. EMI characteristics
Symbol Parameter Conditions Monitored
frequency band
Max vs. [fHSE/fHCLK]
Unit
8/48 MHz
SEMI Peak level VDD = 3.3 V, TA = 25 °C.
0.1 MHz to 30 MHz 7
dBµV30 MHz to 130 MHz 8
130 MHz to 1GHz 13
SAE EMI Level 3.5 -
Table 31. ESD absolute maximum ratings
Symbol Ratings Conditions Class Maximum
value(1)
1. Based on characterization results, not tested in production.
Unit
VESD(HBM)
Electrostatic discharge voltage
(human body model)
TA = +25 °C, conforming
to JESD22-A114 2 2000
V
VESD(CDM)
Electrostatic discharge voltage
(charge device model)
TA = +25 °C, conforming
to ANSI/ESD STM5.3.1 II 500
Table 32. Electrical sensitivities
Symbol Parameter Conditions Class
LU Static latch-up class TA = +105 °C conforming to JESD78A II level A
DS5934 Rev 6 49/79
STM32F102x4, STM32F102x6 Electrical characteristics
67
5.3.12 I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product
operation. However, in order to give an indication of the robustness of the microcontroller in
cases when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibilty to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (>5
LSB TUE), out of spec current injection on adjacent pins or other functional failure (for
example reset, oscillator frequency deviation).
The test results are given in Table 33.
5.3.13 I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 34 are derived from tests
performed under the conditions summarized in Table 8. All I/Os are CMOS and TTL
compliant.
Table 33. I/O current injection susceptibility
Symbol Description
Functional susceptibility
Unit
Negative
injection
Positive
injection
IINJ
Injected current on OSC_IN32,
OSC_OUT32, PA4, PA5, PC13 -0 +0
mA
Injected current on all FT pins -5 +0
Injected current on any other pin -5 +5
Electrical characteristics STM32F102x4, STM32F102x6
50/79 DS5934 Rev 6
Table 34. I/O static characteristics
Symbol Parameter Conditions Min Typ Max Unit
VIL Low level input voltage
Standard IO
input low level
voltage
- - 0.28*(VDD-2 V)+0.8 V(1)
V
IO FT(3) input
low level voltage - - 0.32*(VDD-2V)+0.75 V(1)
All I/Os except
BOOT0 - - 0.35VDD(2)
VIH
High level input
voltage
Standard IO
input high level
voltage
0.41*(VDD-2 V)+1.3 V(1) --
IO FT(3) input
high level
voltage
0.42*(VDD-2 V)+1 V(1) --
All I/Os except
BOOT0 0.65VDD(2) --
Vhys
Standard IO Schmitt
trigger voltage
hysteresis(4)
-200--
mV
IO FT Schmitt trigger
voltage hysteresis(4) -5% V
DD(5) --
Ilkg
Input leakage current
(6)
VSS VIN VDD
Standard I/Os --±1
µA
VIN = 5 V
I/O FT --3
RPU
Weak pull-up
equivalent resistor(7) VIN = VSS 30 40 50
kΩ
RPD
Weak pull-down
equivalent resistor(7) VIN = VDD 30 40 50
CIO I/O pin capacitance - - 5 - pF
1. Data based on design simulation.
2. Tested in production.
3. FT = 5-Volt tolerant, In order to sustain a voltage higher than VDD+0.3 the internal pull-up/pull-down resistors must be
disabled.
4. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.
5. With a minimum of 100 mV.
6. Leakage can be higher than max if negative current is injected on adjacent pins.
7. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. The
PMOS/NMOS contribution to the series resistance is small (~10%).
DS5934 Rev 6 51/79
STM32F102x4, STM32F102x6 Electrical characteristics
67
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 20 and Figure 21 for standard I/Os, and
in Figure 22 and Figure 23 for 5 V tolerant I/Os.
Figure 20. Standard I/O input characteristics - CMOS port
Figure 21. Standard I/O input characteristics - TTL port
MS52673V1
2.0 3.62.7 3.0
CMOS standard requirement V
IH
= 0.65 V
DD
3.3
1.25
1.96
1.71
1.71
1.59
1.0 1.08 1.08
Tested in production
V
IH
= 0.41 (V
DD
- 2) + 1.3 V
Based on simulations
Tested in production CMOS standard requirement VIL = 0.35 VDD
Area not determined
VIH / VIL (V)
VIH min 1.3
VIL max 0.8
0.7
V
IL
= 0.28 (V
DD
- 2) + 0.8 V
VDD (V)
MS52674V1
2.0 3.6
2.16
TTL requirement VIH = 2.0 V
1.25
1.96
V
IH
= 0.41 (V
DD
- 2) + 1.3 V
Based on simulations
TTL requirement VIL = 0.8 V
Area not determined
VIH / VIL (V)
VIH min
2.0
VIL max
0.8
V
IL
= 0.28 (V
DD
- 2) + 0.8 V
VDD (V)
1.3
Electrical characteristics STM32F102x4, STM32F102x6
52/79 DS5934 Rev 6
Figure 22. 5 V tolerant I/O input characteristics - CMOS port
Figure 23. 5 V tolerant I/O input characteristics - TTL port
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to ± 8 mA, and sink or
source up to ± 20 mA (with a relaxed VOL/VOH) except PC13, PC14 and PC15, which can
sink or source up to ±3 mA. When using the GPIOs PC13 to PC15 in output mode, the
speed should not exceed 2 MHz with a maximum load of 30 pF.
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum ratings specified in Section 5.2.
The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD cannot exceed the absolute maximum rating
IVDD (see Table 6).
The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
IVSS (see Table 6).
Output voltage levels
Unless otherwise specified, the parameters given in Table 35 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 8. All I/Os are CMOS and TTL compliant.
MS52672V1
2.0 3.62.7 3.0
CMOS standard requirement V
IH
= 0.65 V
DD
3.3
1.25
1.67
1.55
1.42
1.295
0.975 1.07 1.16
Tested in production
V
IH
= 0.42 (V
DD
- 2) + 1.0 V
Based on simulations
Tested in production CMOS standard requirement VIL = 0.35 VDD
Area not determined
VIH / VIL (V)
VIH min 1.3
VIL max 0.7
V
IL
= 0.32 (V
DD
- 2) + 0.75 V
VDD (V)
1.00
0.75
MS52675V1
2.0 3.6
2.16
TTL requirement VIH = 2.0 V
1.00
1.67
V
IH
= 0.42 (V
DD
- 2) + 1.0 V
Based on simulations
TTL requirement VIL = 0.8 V
Area not determined
VIH / VIL (V)
VIH min
2.0
VIL max
0.80
V
IL
= 0.32 (V
DD
- 2) + 0.75 V
VDD (V)
0.75
DS5934 Rev 6 53/79
STM32F102x4, STM32F102x6 Electrical characteristics
67
Table 35. Output voltage characteristics
Symbol Parameter Conditions Min Max Unit
VOL(1)
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 6
and the sum of IIO (I/O ports and control pins) must not exceed IVSS.
Output Low level voltage for an I/O pin
when 8 pins are sunk at the same time CMOS port(2).
IIO = +8 mA.
2.7 V < VDD < 3.6 V
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
-0.4
V
VOH(3)
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 6 and the sum of IIO (I/O ports and control pins) must not exceed IVDD.
Output High level voltage for an I/O pin
when 8 pins are sourced at the same time VDD–0.4 -
VOL(1) Output low level voltage for an I/O pin
when 8 pins are sunk at the same time TTL port(2)
IIO = +8 mA
2.7 V < VDD < 3.6 V
-0.4
V
VOH(3) Output high level voltage for an I/O pin
when 8 pins are sourced at the same time 2.4 -
VOL(1) Output low level voltage for an I/O pin
when 8 pins are sunk at the same time IIO = +20 mA(4)
2.7 V < VDD < 3.6 V
4. Based on characterization data, not tested in production.
-1.3
V
VOH (3) Output high level voltage for an I/O pin
when 8 pins are sourced at the same time VDD–1.3 -
VOL(1) Output low level voltage for an I/O pin
when 8 pins are sunk at the same time IIO = +6 mA(4)
2.0 V < VDD < 2.7 V
-0.4
V
VOH(3) Output high level voltage for an I/O pin
when 8 pins are sourced at the same time VDD–0.4 -
Electrical characteristics STM32F102x4, STM32F102x6
54/79 DS5934 Rev 6
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 24 and
Table 36, respectively.
Unless otherwise specified, the parameters given in Table 36 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 8.
Table 36. I/O AC characteristics(1)
1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a
description of GPIO Port configuration register.
MODEx
[1:0] bit
value(1)
Symbol Parameter Conditions Max Unit
10
fmax(IO)out Maximum frequency(2)
2. The maximum frequency is defined in Figure 24.
CL = 50 pF, VDD = 2 V to 3.6 V 2 MHz
tf(IO)out
Output high to low level fall
time
CL = 50 pF, VDD = 2 V to 3.6 V
125(3)
3. Guaranteed by design, not tested in production.
ns
tr(IO)out
Output low to high level rise
time 125(3)
01
fmax(IO)out Maximum frequency(2) CL= 50 pF, VDD = 2 V to 3.6 V 10 MHz
tf(IO)out
Output high to low level fall
time
CL= 50 pF, VDD = 2 V to 3.6 V
25(3)
ns
tr(IO)out
Output low to high level rise
time 25(3)
11
Fmax(IO)out Maximum Frequency(2)
CL= 30 pF, VDD = 2.7 V to 3.6 V 50 MHz
CL = 50 pF, VDD = 2.7 V to 3.6 V 30 MHz
CL = 50 pF, VDD = 2 V to 2.7 V 20 MHz
tf(IO)out
Output high to low level fall
time
CL = 30 pF, VDD = 2.7 V to 3.6 V 5(3)
ns
CL = 50 pF, VDD = 2.7 V to 3.6 V 8(3)
CL = 50 pF, VDD = 2 V to 2.7 V 12(3)
tr(IO)out
Output low to high level rise
time
CL = 30 pF, VDD = 2.7 V to 3.6 V 5(3)
CL = 50 pF, VDD = 2.7 V to 3.6 V 8(3)
CL = 50 pF, VDD = 2 V to 2.7 V 12(3)
-t
EXTIpw
Pulse width of external
signals detected by the EXTI
controller
-10ns
DS5934 Rev 6 55/79
STM32F102x4, STM32F102x6 Electrical characteristics
67
Figure 24. I/O AC characteristics definition
5.3.14 NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 34).
Unless otherwise specified, the parameters given in Table 37 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 8.
ai14131c
10%
90%
50%
tr(IO)out
OUTPUT
EXTERNAL
ON 50pF
Maximum frequency is achieved if (tr + tf) ≤ 2/3)T and if the duty cycle is (45-55%)
10%
50%
90%
when loaded by 50pF
T
tf(IO)out
Table 37. NRST pin characteristics
Symbol Parameter Conditions Min Typ Max Unit
VIL(NRST)(1)
1. Guaranteed by design, not tested in production.
NRST Input low level voltage - –0.5 - 0.8
V
VIH(NRST)(1) NRST Input high level voltage - 2 - VDD+0.5
Vhys(NRST)
NRST Schmitt trigger voltage
hysteresis - - 200 - mV
RPU Weak pull-up equivalent resistor(2)
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution
to the series resistance must be minimum (~10%).
VIN = VSS 30 40 50 kΩ
VF(NRST)(1) NRST Input filtered pulse - - - 100 ns
VNF(NRST)(1) NRST Input not filtered pulse - 300 - - ns
DD
Electrical characteristics STM32F102x4, STM32F102x6
56/79 DS5934 Rev 6
Figure 25. Recommended NRST pin protection
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 39. Otherwise the reset will not be taken into account by the device.
ai14132c
STM32F
RPU
NRST
(2)
VDD
Filter
Internal Reset
0.1 μF
External
reset circuit (1)
DS5934 Rev 6 57/79
STM32F102x4, STM32F102x6 Electrical characteristics
67
5.3.15 TIM timer characteristics
The parameters given in Table 38 are guaranteed by design.
Refer to Section 5.3.13 for details on the input/output alternate function characteristics
(output compare, input capture, external clock, PWM output).
5.3.16 Communications interfaces
I2C interface characteristics
The STM32F102xx medium-density USB access line I2C interface meets the requirements
of the standard I2C communication protocol with the following restrictions: the I/O pins SDA
and SCL are mapped to are not “true” open-drain. When configured as open-drain, the
PMOS connected between the I/O pin and VDD is disabled, but is still present.
The I2C characteristics are described in Table 39. Refer also to Section 5.3.13 for more
details on the input/output alternate function characteristics (SDA and SCL).
Table 38. TIMx(1) characteristics
1. TIMx is used as a general term to refer to the TIM2, TIM3 and TIM4 timers.
Symbol Parameter Conditions Min Max Unit
tres(TIM) Timer resolution time
-1-t
TIMxCLK
fTIMxCLK = 48 MHz 20.84 - ns
fEXT
Timer external clock
frequency on CH1 to CH4
-0f
TIMxCLK/2 MHz
fTIMxCLK = 48 MHz 0 24 MHz
ResTIM Timer resolution - - 16 bit
tCOUNTER
16-bit counter clock period
when internal clock is
selected
- 1 65536 tTIMxCLK
fTIMxCLK = 48 MHz 0.0208 1365 µs
tMAX_COUNT Maximum possible count
- - 65536 × 65536 tTIMxCLK
fTIMxCLK = 48 MHz - 89.48 s
Electrical characteristics STM32F102x4, STM32F102x6
58/79 DS5934 Rev 6
Table 39. I2C characteristics
Symbol Parameter
Standard mode I2C(1)(2)
1. Values guaranteed by design, not tested in production.
Fast mode I2C(1)(2)
2. fPCLK1 must be at least 2 MHz to achieve standard mode I2C frequencies. It must be at least 4 MHz to
achieve fast mode I2C frequencies. It must be a multiple of 10 MHz to reach the 400 kHz maximum I2C fast
mode clock.
Unit
Min Max Min Max
tw(SCLL) SCL clock low time 4.7 - 1.3 -
µs
tw(SCLH) SCL clock high time 4.0 - 0.6 -
tsu(SDA) SDA setup time 250 - 100 -
ns
th(SDA) SDA data hold time - 3450(3)
3. The maximum Data hold time has only to be met if the interface does not stretch the low period of the SCL
signal.
-900
(3)
tr(SDA)
tr(SCL)
SDA and SCL rise time - 1000 - 300
tf(SDA)
tf(SCL)
SDA and SCL fall time - 300 - 300
th(STA) Start condition hold time 4.0 - 0.6 -
µs
tsu(STA)
Repeated Start condition setup
time 4.7 - 0.6 -
tsu(STO) Stop condition setup time 4.0 - 0.6 - µs
tw(STO:STA)
Stop to Start condition time (bus
free) 4.7 - 1.3 - µs
tSP
Pulse width of spikes that are
suppressed by the analog filter 050
(4)
4. The analog filter minimum filtered spikes is above tSP(max) to ensure that spikes width up to tSP(max) are
filtered.
050
(4) ns
CbCapacitive load for each bus line - 400 - 400 pF
D ‘20 DD I2 I'd—n— !4—>: 3—H} u +g—V+ . (fPCLK1
DS5934 Rev 6 59/79
STM32F102x4, STM32F102x6 Electrical characteristics
67
Figure 26. I2C bus AC waveforms and measurement circuit(1)
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
Table 40. SCL frequency (fPCLK1= 36 MHz, VDD_I2C = 3.3 V)(1)(2)
1. RP = External pull-up resistance, fSCL = I2C speed.
2. For speeds around 200 kHz, the tolerance on the achieved speed is of ±5%. For other speed ranges, the
tolerance on the achieved speed ±2%. These variations depend on the accuracy of the external
components used to design the application.
fSCL (kHz)
I2C_CCR value
RP = 4.7 kΩ
400 0x801E
300 0x8028
200 0x803C
100 0x00B4
50 0x0168
20 0x0384
ai14133e
Start
SD A
I²C bus
VDD_I2C
VDD_I2C
STM32F10x
SDA
SCL
tf(SDA) tr(SDA)
SCL
th(STA)
tw(SCLH)
tw(SCLL)
tsu(SDA)
tr(SCL) tf(SCL)
th(SDA)
Start repeated
Start
tsu(STA)
tsu(STO)
Stop tsu(STO:STA)
Rp Rp Rs
Rs
Electrical characteristics STM32F102x4, STM32F102x6
60/79 DS5934 Rev 6
SPI interface characteristics
Unless otherwise specified, the parameters given in Table 41 are derived from tests
performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions
summarized in Table 8.
Refer to Section 5.3.13 for more details on the input/output alternate function characteristics
(NSS, SCK, MOSI, MISO).
Table 41. SPI characteristics
Symbol Parameter Conditions Min Max Unit
fSCK
1/tc(SCK)
SPI clock frequency
Master mode - 18
MHz
Slave mode - 18
tr(SCK)
tf(SCK)
SPI clock rise and fall
time Capacitive load: C = 30 pF - 8 ns
DuCy(SCK) SPI slave input clock
duty cycle Slave mode 30 70 %
tsu(NSS)(1)
1. Based on characterization, not tested in production.
NSS setup time Slave mode 4tPCLK -
ns
th(NSS)(1) NSS hold time Slave mode 2tPCLK -
tw(SCKH)(1)
tw(SCKL)(1) SCK high and low time Master mode, fPCLK = 36 MHz,
presc = 4 50 60
tsu(MI) (1)
tsu(SI)(1) Data input setup time
Master mode 5 -
Slave mode 5 -
th(MI) (1)
Data input hold time
Master mode 5 -
th(SI)(1) Slave mode 4 -
ta(SO)(1)(2)
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
Data output access time Slave mode, fPCLK = 20 MHz 0 3tPCLK
tdis(SO)(1)(3)
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z
Data output disable time Slave mode 2 10
tv(SO) (1) Data output valid time Slave mode (after enable edge) - 25
tv(MO)(1) Data output valid time Master mode (after enable edge) - 5
th(SO)(1)
Data output hold time
Slave mode (after enable edge) 15 -
th(MO)(1) Master mode (after enable edge) 2 -
NSS mpul —\ ‘7‘quK ’su NSS) Mass.) 5 CPHA:0 " \ g CPOL=0 ‘ 7 w(SCKH) x CFHA=0 ‘ 8 spam wrscm ‘a(so) M30) tmso) ‘ ‘r(SCK) M1550) -<—> MISO |f(SCK) OUTPUT MSB our awe__om LSB OUT ‘su(S\) MOSI -- INPUT MSB w 3ij IN LSB IN X tmsl) ammo
DS5934 Rev 6 61/79
STM32F102x4, STM32F102x6 Electrical characteristics
67
Figure 27. SPI timing diagram - slave mode and CPHA=0
Figure 28. SPI timing diagram - slave mode and CPHA=1(1)
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
ai14135b
NSS input
tSU(NSS) tc(SCK) th(NSS)
SCK input
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tw(SCKH)
tw(SCKL)
ta(SO) tv(SO) th(SO) tr(SCK)
tf(SCK) tdis(SO)
MISO
OUTPUT
MOSI
INPUT
tsu(SI) th(SI)
MSB OUT
MSB IN
BIT6 OUT LSB OUT
LSB IN
BIT 1 IN
Electrical characteristics STM32F102x4, STM32F102x6
62/79 DS5934 Rev 6
Figure 29. SPI timing diagram - master mode(1)
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
USB characteristics
The USB interface is USB-IF certified (full speed).
ai14136c
CPHA= 0
MOSI
OUTPUT
MISO
INP UT
CPHA= 0
LSB OUT
LSB IN
CPOL=0
CPOL=1
B IT1 OUT
NSS input
tc(SCK)
tw(SCKH)
tw(SCKL)
tr(SCK)
tf(SCK)
th(MI)
High
CPHA=1
CPHA=1
CPOL=0
CPOL=1
tsu(MI)
tv(MO) th(MO)
MSB IN BIT6 IN
MSB OUT
Table 42. USB startup time
Symbol Parameter Max Unit
tSTARTUP USB transceiver startup time 1 µs
:2? X X K
DS5934 Rev 6 63/79
STM32F102x4, STM32F102x6 Electrical characteristics
67
Figure 30. USB timings: definition of data signal rise and fall time
5.3.17 12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 45 are derived from tests
performed under ambient temperature, fPCLK2 frequency and VDDA supply voltage
conditions summarized in Table 8.
Note: It is recommended to perform a calibration after each power-up.
Table 43. USB DC electrical characteristics
Symbol Parameter Conditions Min.(1)
1. All the voltages are measured from the local ground potential.
Max.(1) Unit
Input
levels
VDD USB operating voltage(2)
2. To be compliant with the USB 2.0 full-speed electrical specification, the USB_DP (D+) pin should be pulled
up with a 1.5 kΩ resistor to a 3.0-to-3.6 V voltage range.
-3.0
(3)
3. The STM32F102xx USB functionality is ensured down to 2.7 V but not the full USB electrical
characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range.
3.6 V
VDI(4)
4. Guaranteed by design, not tested in production.
Differential input sensitivity I(USB_DP, USB_DM) 0.2 -
VVCM(4) Differential common mode range Includes VDI range 0.8 2.5
VSE(4) Single ended receiver threshold - 1.3 2.0
Output
levels
VOL Static output level low RL of 1.5 kΩ to 3.6 V(5)
5. RL is the load connected on the USB drivers
-0.3
V
VOH Static output level high RL of 15 kΩ to VSS(5) 2.8 3.6
Table 44. USB: Full speed electrical characteristics of the driver(1)
1. Guaranteed by design, not tested in production.
Symbol Parameter Conditions Min Max Unit
trRise time(2)
2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0).
CL = 50 pF 420ns
tfFall time(2) CL = 50 pF 4 20 ns
trfm Rise/ fall time matching tr / tf90 110 %
VCRS Output signal crossover voltage - 1.3 2.0 V
ai14137b
Cross over
points
Differential
data lines
VCRS
VSS
tftr
Electrical characteristics STM32F102x4, STM32F102x6
64/79 DS5934 Rev 6
Equation 1: RAIN max formula:
The formula above (Equation 1) is used to determine the maximum external impedance
allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
Table 45. ADC characteristics
Symbol Parameter Conditions Min Typ Max Unit
VDDA Power supply - 2.4 - 3.6 V
fADC ADC clock frequency - 0.6 - 12 MHz
fS(1)
1. Guaranteed by design, not tested in production.
Sampling rate - 0.05 - 0.85 Msps
fTRIG(1) External trigger frequency
fADC = 12 MHz - - 823 kHz
---171/f
ADC
VAIN Conversion voltage range(2)
2. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA.
-
0 (VSSA or
VREF- tied to
ground)
-V
REF+ V
RAIN(1) External input impedance
See Equation 1
and Table 46
for details
--50κΩ
RADC(1) Sampling switch resistance - - - 1 κΩ
CADC(1) Internal sample and hold
capacitor ---8pF
tCAL(1) Calibration time
fADC = 12 MHz 5.9 µs
-831/f
ADC
tlat(1) Injection trigger conversion
latency
fADC = 12 MHz - - 0.214 µs
---3
(3)
3. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 46.
1/fADC
tlatr(1) Regular trigger conversion
latency
fADC = 12 MHz - - 0.143 µs
---2
(3) 1/fADC
tS(1) Sampling time
fADC = 12 MHz 0.125 - 19.95 µs
- 1.5 - 239.5 1/fADC
tSTAB(1) Power-up time - 0 0 1 µs
tCONV(1) Total conversion time
(including sampling time)
fADC = 12 MHz 1.2 - 21 µs
-14 to 252 (tS for sampling +12.5
for successive approximation) 1/fADC
RAIN
TS
fADC CADC 2N2+
()ln××
--------------------------------------------------------------- R ADC
<
AIN ADC
DS5934 Rev 6 65/79
STM32F102x4, STM32F102x6 Electrical characteristics
67
Table 46. RAIN max for fADC = 12 MHz(1)
1. Data guaranteed by design, not tested in production.
Ts (cycles) tS (µs) RAIN max (kΩ)
1.5 0.13 0.4
7.5 0.63 5.9
13.5 1.13 11.4
28.5 2.38 25.2
41.5 3.46 37.2
55.5 4.63 50
71.5 5.96 NA
239.5 19.96 NA
Table 47. ADC accuracy - limited test conditions(1)
1. ADC DC accuracy values are measured after internal calibration.
Symbol Parameter Test conditions Typ Max(2)
2. Based on characterization, not tested in production.
Unit
ET Total unadjusted error fPCLK2 = 48 MHz.
fADC = 12 MHz, RAIN < 10 kΩ.
VDDA = 3 V to 3.6 V
TA = 25 °C
Measurements made after
ADC calibration
±1.3 ±2
LSB
EO Offset error ±1 ±1.5
EG Gain error ±0.5 ±1.5
ED Differential linearity error ±0.7 ±1
EL Integral linearity error ±0.8 ±1.5
Table 48. ADC accuracy(1) (2) (3)
1. ADC DC accuracy values are measured after internal calibration.
2. Better performance could be achieved in restricted VDD, frequency and temperature ranges.
3. ADC accuracy vs. negative injection current: Injecting a negative current on any analog input pins should
be avoided as this significantly reduces the accuracy of the conversion being performed on another analog
input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially
inject negative currents.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 5.3.13 does not
affect the ADC accuracy.
Symbol Parameter Test conditions Typ Max(4)
4. Based on characterization, not tested in production.
Unit
ET Total unadjusted error
fPCLK2 = 48 MHz.
fADC = 12 MHz, RAIN < 10 kΩ.
VDDA = 2.4 V to 3.6 V
Measurements made after
ADC calibration
±2 ±5
LSB
EO Offset error ±1.5 ±2.5
EG Gain error ±1.5 ±3
ED Differential linearity error ±1 ±2
EL Integral linearity error ±1.5 ±3
Electrical characteristics STM32F102x4, STM32F102x6
66/79 DS5934 Rev 6
Figure 31. ADC accuracy characteristics
Figure 32. Typical connection diagram using the ADC
1. Refer to Table 46 for the values of RAIN, RADC and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.
EO
EG
1LSB
IDEAL
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
ET=Total u nadjusted error: maximum deviation
between the actual and the ideal transfer curves.
EO=Offset error: deviation between the first actual
transition and the first ideal one.
EG=Gain error: deviation between the last ideal
transition and the last actual one.
ED=Differential linearity error: maximum deviation
between actual steps and the ideal one.
EL=Integral linearity error: maximum deviation
between any actual transition and the end point
correlation line.
4095
4094
4093
5
4
3
2
1
0
7
6
1234567 4093 4094 4095 4096
(1)
(2)
ET
ED
EL
(3)
VDDA
VSSA
ai15497
VDDA
4096
[1LSBIDEAL =
ai14974b
STM32F102
VDD
AINx
IL±1 µA
0.6 V
VT
RAIN(1)
Cparasitic
VAIN
0.6 V
VT
RADC(1) 12-bit
converter
CADC(1)
Sample and hold ADC
converter
H
DS5934 Rev 6 67/79
STM32F102x4, STM32F102x6 Electrical characteristics
67
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 33. The 10 nF capacitors
should be ceramic (good quality). They should be placed as close as possible to the chip.
Figure 33. Power supply and reference decoupling
5.3.18 Temperature sensor characteristics
VDDA
STM32F102xx
1 µF // 10 nF
VSSA
ai14980
b
Table 49. TS characteristics
Symbol Parameter Min Typ Max Unit
TL(1)
1. Guaranteed by characterization, not tested in production.
VSENSE linearity with temperature - ±1.5 - °C
Avg_Slope(1) Average slope - 4.35 - mV/°C
V25(1) Voltage at 25°C - 1.42 - V
tSTART(2)
2. Data guaranteed by design, not tested in production.
Startup time 4 - 10 µs
TS_temp(3)(2)
3. Shortest sampling time can be determined in the application by multiple iterations.
ADC sampling time when reading the
temperature - - 17.1 µs
aNe “7 a mmmmmmm m WWWW mmmmmimmwmw i,i+i,i 7 WWWWW
Package characteristics STM32F102x4, STM32F102x6
68/79 DS5934 Rev 6
6 Package characteristics
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
6.1 LQFP48 package information
Figure 34. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline
1. Drawing is not to scale.
5B_ME_V2
PIN 1
IDENTIFICATION
ccc C
C
D3
0.25 mm
GAUGE PLANE
b
A1
A
A2
c
A1
L1
L
D
D1
E3
E1
E
e
12
1
13
24
25
36
37
48
SEATING
PLANE
K
DS5934 Rev 6 69/79
STM32F102x4, STM32F102x6 Package characteristics
76
Table 50. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package
mechanical data
Symbol
millimeters inches(1)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Min Typ Max Min Typ Max
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D 8.800 9.000 9.200 0.3465 0.3543 0.3622
D1 6.800 7.000 7.200 0.2677 0.2756 0.2835
D3 - 5.500 - - 0.2165 -
E 8.800 9.000 9.200 0.3465 0.3543 0.3622
E1 6.800 7.000 7.200 0.2677 0.2756 0.2835
E3 - 5.500 - - 0.2165 -
e - 0.500 - - 0.0197 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0°3.5°7° 0°3.5°7°
ccc - - 0.080 - - 0.0031
# mymmnnmnnfl //
Package characteristics STM32F102x4, STM32F102x6
70/79 DS5934 Rev 6
Figure 35. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package
recommended footprint
1. Dimensions are expressed in millimeters.
Device marking for LQFP48
Figure 36 gives an example of topside marking orientation versus pin 1 identifier location.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.
The printed markings may differ depending upon the supply chain.
Figure 36. LQFP48 marking example (package top view)
1. Samples marked “ES” are to be considered as “Engineering Samples”: i.e. they are intended to be sent to
customer for electrical compatibility evaluation and may be used to start customer qualification where
specifically authorized by ST in writing. In no event ST will be liable for any customer usage in production.
Only if ST has authorized in writing the customer qualification Engineering Samples can be used for
9.70 5.80 7.30
12
24
0.20
7.30
1
37
36
1.20
5.80
9.70
0.30
25
1.20
0.50
ai14911d
1348
A
MS38213V1
STM32F
102C4T6A R
Pin 1
identifier
Revision
code
Product identification (1)
Y WW
Date code
(year + week)
HHMMMMMWM E i g E 1 :
DS5934 Rev 6 71/79
STM32F102x4, STM32F102x6 Package characteristics
76
reliability qualification trials.
6.2 LQFP64 package information
Figure 37. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline
1. Drawing is not to scale.
Table 51. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat
package mechanical data
Symbol
millimeters inches(1)
Min Typ Max Min Typ Max
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D - 12.000 - - 0.4724 -
D1 - 10.000 - - 0.3937 -
D3 - 7.500 - - 0.2953 -
E - 12.000 - - 0.4724 -
5W_ME_V3
A1
A2
A
SEATING PLANE
ccc C
b
C
c
A1
L
L1
K
IDENTIFICATION
PIN 1
D
D1
D3
e
116
17
32
33
48
49
64
E3
E1
E
GAUGE PLANE
0.25 mm
IEEEEEEE EEEEJE flflflflfl HHHHDHHHHPPEFHHH Hflflflflflflflflfl L7 EEEEEEEE =5=5¥E=
Package characteristics STM32F102x4, STM32F102x6
72/79 DS5934 Rev 6
Figure 38. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package
recommended footprint
1. Dimensions are expressed in millimeters.
Device marking for LQFP64
Figure 39 is an example of topside marking orientation versus pin 1 identifier location.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.
The printed markings may differ depending upon the supply chain.
E1 - 10.000 - - 0.3937 -
E3 - 7.500 - - 0.2953 -
e - 0.500 - - 0.0197 -
K 0°3.5°7° 0°3.5°7°
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
ccc - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Table 51. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat
package mechanical data (continued)
Symbol
millimeters inches(1)
Min Typ Max Min Typ Max
48
32
49
64 17
116
1.2
0.3
33
10.3
12.7
10.3
0.5
7.8
12.7
ai14909c
//
DS5934 Rev 6 73/79
STM32F102x4, STM32F102x6 Package characteristics
76
Figure 39. LQFP64 marking example (package top view)
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
MS38214V1
STM32F102
R6T6A R
Pin 1
identifier
Revision
code
Product identification (1)
Y WW
Date code
(year + week)
Package characteristics STM32F102x4, STM32F102x6
74/79 DS5934 Rev 6
6.3 Thermal characteristics
The maximum chip junction temperature (TJmax) must never exceed the values given in
Table 8: General operating conditions.
The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max × Θ
JA)
Where:
TA max is the maximum ambient temperature in °C,
•Θ
JA is the package junction-to-ambient thermal resistance, in °C/W,
PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.
6.4 Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
Table 52. Package thermal characteristics
Symbol Parameter Value Unit
Θ
JA
Thermal resistance junction-ambient
LQFP48 - 7 × 7 mm / 0.5 mm pitch 55
°C/W
Thermal resistance junction-ambient
LQFP64 - 10 × 10 mm / 0.5 mm pitch 45
DS5934 Rev 6 75/79
STM32F102x4, STM32F102x6 Package characteristics
76
6.4.1 Evaluating the maximum junction temperature for an application
When ordering the microcontroller, the temperature range is specified in Section 7: Ordering
information scheme.
Each temperature range suffix corresponds to a specific guaranteed ambient temperature at
maximum dissipation and, to a specific maximum junction temperature. Here, only
temperature range 6 is available (–40 to 85 °C).
The following example shows how to calculate the temperature range needed for a given
application, making it possible to check whether the required temperature range is
compatible with the STM32F102xx junction temperature range.
Example: High-performance application
Assuming the following application conditions:
Maximum ambient temperature TAmax = 82 °C (measured according to JESD51-2),
IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output
mode at low level with IOL = 20 mA, VOL= 1.3 V
PINTmax = 50 mA × 3.5 V= 175 mW
PIOmax = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW
This gives: PINTmax = 175 mW and PIOmax = 272 mW
PDmax = 175 + 272 = 447 mW
Thus: PDmax = 447 mW
Using the values obtained in Table 5 2 TJmax is calculated as follows:
For LQFP64, 45 °C/W
TJmax = 82 °C + (45 °C/W × 447 mW) = 82 °C + 20.1 °C = 102.1 °C
This is within the junction temperature range of the STM32F102xx (–40 < TJ < 105 °C).
Figure 40. LQFP64 PD max vs. TA
0
100
200
300
400
500
600
700
65 75 85 95 105 115
TAC)
PD (mW)
Suffix 6
Ordering information scheme STM32F102x4, STM32F102x6
76/79 DS5934 Rev 6
7 Ordering information scheme
Example: STM32 F 102 C 6 T 6 A xxx
Device family
STM32 = Arm®-based 32-bit microcontroller
Product type
F = general-purpose
Device subfamily
102 = USB access line, USB 2.0 full-speed interface
Pin count
C = 48 pins
R = 64 pins
Flash memory size
4 = 16 Kbytes of Flash memory
6 = 32 Kbytes of Flash memory
Package
T = LQFP
Temperature range
6 = Industrial temperature range, –40 to 85 °C.
Internal code
“A” or blank(1)
1. For STM32F102x6 devices with a blank Internal code, please refer to the STM32F103x8/B datasheet
available from the ST website: www.st.com.
Options
xxx = programmed parts
TR = tape and reel
DS5934 Rev 6 77/79
STM32F102x4, STM32F102x6 Revision history
78
8 Revision history
Table 53. Document revision history
Date Revision Changes
23-Sep-2008 1 Initial release.
09-Apr-2009 2
I/O information clarified on page 1. Figure 1: STM32F102T8 medium-
density USB access line block diagram and Figure 5: Memory map
modified.
In Table 4: low-density STM32F102xx pin definitions: PB4, PB13, PB14,
PB15, PB3/TRACESWO moved from Default column to Remap column,
Note 4. added.
PD value added for LQFP64 package in Table 8: General operating
conditions.
Note modified in Table 13: Maximum current consumption in Run mode,
code with data processing running from Flash and Table 15: Maximum
current consumption in Sleep mode, code running from Flash or RAM.
Figure 13, Figure 14 and Figure 15 show typical curves.
Figure 31: ADC accuracy characteristics modified.
Figure 33: Power supply and reference decoupling modified. Small text
changes.
Table 20: High-speed external user clock characteristics and Table 21:
Low-speed external user clock characteristics modified.
ACCHSI max values modified in Table 24: HSI oscillator characteristics.
24-Sep-2009 3
Note 5. updated and Note 4. added in Table 4: low-density STM32F102xx
pin definitions. Typical IDD_VBAT value added in Table 16: Typical and
maximum current consumptions in Stop and Standby modes. Figure 12:
Typical current consumption on VBAT with RTC on versus temperature at
different VBAT values added.
fHSE_ext min modified in Table 20: High-speed external user clock
characteristics.
CL1 and CL2 replaced by C in Table 22: HSE 4-16 MHz oscillator
characteristics and Table 23: LSE oscillator characteristics (fLSE = 32.768
kHz), notes modified and moved below the tables. Table 24: HSI oscillator
characteristics modified. Conditions removed from Table 26: Low-power
mode wakeup timings.
Note 1. modified below Figure 18: Typical application with an 8 MHz
crystal.
Figure 25: Recommended NRST pin protection modified.
IEC 1000 standard updated to IEC 61000 and SAE J1752/3 updated to
IEC 61967-2 in Section 5.3.10: EMC characteristics on page 46.
Jitter added to Table 27: PLL characteristics.
CADC and RAIN parameters modified in Table 47: ADC characteristics.
RAIN max values modified in Table 48: RAIN max for fADC = 12 MHz.
Revision history STM32F102x4, STM32F102x6
78/79 DS5934 Rev 6
02-Aug-2013 4
Figure 2: Clock tree: added FLITFCLK and Note 3., and modified Note 1..
Removed sentence in “Unless otherwise specified the parameters ...” in
I2C interface characteristics section.
Added VIN in Table 8: General operating conditions.
Added note 5 in Table 23: HSI oscillator characteristics
Added DuCy(HSI) in Table 23: HSI oscillator characteristics
Table 24: LSI oscillator characteristics: removed note 2 related to
oscillator selection, updated Note 2., and tSU(LSE) specified for various
ambient temperature values.
Modified charge device model in Table 33: I/O current injection
susceptibility.
Updated ‘VIL’ and ‘VIH’ in Table 34: I/O static characteristics.
Added notes to Figure 20: Standard I/O input characteristics - CMOS port,
Figure 21: Standard I/O input characteristics - TTL port, Figure 22: 5 V
tolerant I/O input characteristics - CMOS port and Figure 23: 5 V tolerant
I/O input characteristics - TTL port
Table 37: Output voltage characteristics: updated VOL and VOH conditions
for TTL and CMOS outputs and added Note 2.
Updated Figure 24: I/O AC characteristics definition
Updated Figure 25: Recommended NRST pin protection
Updated footnotes 2 and 3 in Table 39: I2C characteristics
Updated Figure 26: I2C bus AC waveforms and measurement circuit(1)
Updated title of Table 40: SCL frequency (fPCLK1= 36 MHz, VDD_I2C = 3.3
V)
In Table 43: SPI characteristics, removed note 1 related to SPI1
remapped characteristics.
Updated Table 47: ADC characteristics
Updated Section 6.1: Package mechanical data
14-May-2015 5
Updated Table 18: Peripheral current consumption and Tabl e 39 : I2C
characteristics.
Updated Section 6: Package characteristics.
Updated Section 6.2: LQFP64 package information with addition of
Device marking for LQFP64 and Figure 39.
Updated Section 6.1: LQFP48 package information with addition of
Device marking for LQFP48 and Figure 36.
Updated Disclaimer.
06-Aug-2019 6
Updated Section 1: Introduction, Section 5.2: Absolute maximum ratings,
Device marking for LQFP48 and Device marking for LQFP64.
Updated Figure 19: Typical application with a 32.768 kHz crystal,
Figure 20: Standard I/O input characteristics - CMOS port, Figure 21:
Standard I/O input characteristics - TTL port, Figure 22: 5 V tolerant I/O
input characteristics - CMOS port and Figure 23: 5 V tolerant I/O input
characteristics - TTL port.
Minor text edits across the whole document.
Table 53. Document revision history (continued)
Date Revision Changes
DS5934 Rev 6 79/79
STM32F102x4, STM32F102x6
79
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